WO2016169475A1 - 大功率led芯片及其制造方法 - Google Patents

大功率led芯片及其制造方法 Download PDF

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WO2016169475A1
WO2016169475A1 PCT/CN2016/079729 CN2016079729W WO2016169475A1 WO 2016169475 A1 WO2016169475 A1 WO 2016169475A1 CN 2016079729 W CN2016079729 W CN 2016079729W WO 2016169475 A1 WO2016169475 A1 WO 2016169475A1
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layer
mirror
gallium nitride
type gallium
electrode
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PCT/CN2016/079729
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English (en)
French (fr)
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吕孟岩
张宇
李起鸣
徐慧文
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映瑞光电科技(上海)有限公司
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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    • H01L33/0093—Wafer bonding; Removal of the growth substrate
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    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
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    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
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    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
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    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a high power LED chip and a method of fabricating the same.
  • LED has been widely used in lighting, backlighting, display, and indication fields as a new generation of green light sources.
  • each LED company aims to improve the light efficiency of the chip and reduce the production cost, and gradually improve the production competitiveness.
  • the traditional dressing LED chip is the earliest LED chip structure, and is also commonly used in low power chips.
  • the electrode is on top, and includes a P-type gallium nitride layer, a quantum well layer, an N-type gallium nitride layer, and a substrate from top to bottom.
  • the conventional LED chip of the dressing structure has congenital defects such as uneven current distribution and poor heat dissipation due to the non-conductivity of the sapphire substrate and poor thermal conductivity, which makes it difficult to manufacture high-power chips.
  • the sapphire has poor thermal conductivity, and the heat dissipation problem of the high-power chip is difficult to solve;
  • the sapphire is not conductive, and the P-type gallium nitride layer has poor lateral conductivity.
  • a transparent conductive layer (such as ITO) is needed to help lateral current expansion. The thicker the ITO, the stronger the current spreading capability, but the more the light absorption will increase.
  • the traditional face-loading chip has a P-plane, and the P-type gallium nitride layer is thin, which is difficult to implement.
  • the surface is roughened to increase the light extraction efficiency.
  • An object of the present invention is to provide a high-power LED chip excellent in heat dissipation and uniform in current distribution, and a method of manufacturing the same.
  • the present invention provides a method for manufacturing a high-power LED chip, including:
  • the front end structure comprising a first substrate, an N-type gallium nitride layer, a quantum well layer and a P-type gallium nitride layer formed on the first substrate;
  • first mirror on the P-type gallium nitride layer, forming an extending end and a connecting end of the second mirror in the trench, and extending the second end of the second mirror through the second
  • connection ends of the mirrors are connected on the surface of the N-type gallium nitride layer, and an inner isolation band is left between the sidewalls of the trench and the second mirror, between the sidewalls of the trench and the first mirror Leave the outer isolation belt;
  • a P electrode electrically connected to the first mirror is formed in the P through hole, and an N electrode electrically connecting the connection end of the second mirror is formed in the N through hole.
  • the internal isolation is 1-10 ⁇ m, and the width of the outer separator is 1-10 ⁇ m.
  • the material of the insulating layer comprises silicon oxide, aluminum nitride or aluminum oxide.
  • the forming process of the first mirror and the second mirror includes:
  • the photoresist is removed.
  • the N electrode and the P electrode are located on two sides of the second mirror.
  • the present invention also provides a high-power LED chip produced by the method for manufacturing the high-power LED chip, comprising:
  • the quantum well layer is connected to the surface of the N-type gallium nitride layer through the connection end of the second mirror, and the insulating layer is disposed between the second mirror and the P-type gallium nitride layer, the quantum well layer, the first mirror and the barrier layer isolation;
  • the P electrode Passing through the P-electrode of the P-type gallium nitride layer, the quantum well layer and the N-type gallium nitride layer, the P electrode is electrically connected to the first mirror, and passes through the N-type gallium nitride layer N electrode The N electrode is electrically connected to the connection end of the second mirror.
  • the invention provides a method for manufacturing a high power LED chip, comprising:
  • the front end structure comprising a first substrate, an N-type gallium nitride layer, a quantum well layer and a P-type gallium nitride layer formed on the first substrate;
  • first mirror on the P-type gallium nitride layer, forming a second mirror on the exposed N-type gallium nitride layer, the sidewall of the trench and the second mirror
  • the inner isolation strip is left, and an outer isolation strip is left between the sidewall of the trench and the first mirror
  • a P electrode electrically connected to the first mirror is formed in the P through hole, and an N electrode electrically connecting the connection end of the second mirror is formed in the N through hole.
  • the plurality of trenches are not connected to each other, and the plurality of trenches are circular or rectangular in shape.
  • the method further includes: forming a P interconnect layer and an N interconnect layer on the insulating layer after forming the insulating layer and before forming the barrier layer, wherein the P interconnect a layer connected to the first mirror, the N interconnect layer being connected to the second mirror; and after forming the P electrode and the N electrode, the P electrode is connected to the P interconnect layer, The N electrode is connected to the N interconnect layer.
  • forming the P interconnect layer and the N interconnect layer includes:
  • the patterned photoresist being located between the P interconnect layer and the N interconnect layer to be formed;
  • the bonding layer is an insulating glue bonding layer.
  • the bonding layer is a metal bonding layer.
  • the material of the metal bonding layer comprises one or more of gold, tin, indium, gold indium alloy, gold tin alloy, nickel tin alloy.
  • the method further includes forming a layer of insulating material between the barrier layer and the metal bonding layer.
  • the bonded substrate has a thermal conductivity greater than or equal to 100 W/(m ⁇ K).
  • the bonded substrate comprises two or more sub-layers, and one of the sub-layers is a layer of insulating material.
  • the material of the bonding substrate comprises one or more of silicon, ceramic, aluminum nitride, copper, tungsten, and molybdenum.
  • the present invention also provides a high power LED chip, comprising:
  • a P-type gallium nitride layer, a quantum well layer, and a roughened N-type gallium nitride layer on the first mirror the second mirror passing through the P-type gallium nitride a layer and a quantum well layer are connected to the N-type gallium nitride layer, and the second mirror is separated from the P-type gallium nitride layer, the quantum well layer and the first mirror by an insulating layer;
  • the P electrode Passing through the P-electrode of the P-type gallium nitride layer, the quantum well layer and the N-type gallium nitride layer, the P electrode is electrically connected to the first mirror, and passes through the N-type gallium nitride layer N electrode The N electrode is electrically connected to the connection end of the second mirror.
  • the number of the first mirrors is multiple and not connected to each other, and the shapes of the plurality of first mirrors are circular or rectangular.
  • the LED chip further includes a P interconnect layer and an N interconnect layer on the barrier layer, and the P electrode is electrically connected to the first mirror through the P interconnect layer, An N electrode is electrically connected to the second mirror through the N interconnect layer.
  • a P-electrode is formed on the P-type gallium nitride layer.
  • a mirror forms a second mirror connected to the N electrode in the trench to ensure uniform current distribution, and uses a non-conductive, well-conducting bonded substrate to solve the problem of poor heat dissipation of the high-power chip.
  • the N-side light is used, and the surface micro-roughening treatment greatly improves the light-emitting efficiency, and the N-electrode and the P-electrode are both on the surface of the N-GaN layer, which makes the packaging process simpler.
  • FIG. 1 is a flow chart of a method for manufacturing a high power LED chip according to an embodiment of the present invention
  • FIG. 2 to FIG. 11 are schematic diagrams showing the structure of a device in a process of manufacturing a high-power LED chip according to an embodiment of the present invention.
  • the core idea of the present invention is to provide a method for manufacturing a high-power LED chip, including:
  • Step S101 providing a front end structure, the front end structure comprising a first substrate, an N-type gallium nitride layer, a quantum well layer and a P-type gallium nitride layer formed on the first substrate;
  • Step S102 etching the front end structure to form a plurality of trenches, exposing an N-type gallium nitride layer;
  • Step S103 forming a first mirror on the P-type gallium nitride layer, forming an extending end and a connecting end of the second mirror in the trench, and the extending end of the second mirror passes through
  • the connection ends of the second mirror are connected on the surface of the N-type gallium nitride layer, and an inner isolation band is left between the sidewall of the trench and the second mirror, and the sidewall of the trench and the first reflection
  • An outer isolation strip is left between the mirrors;
  • Step S104 forming an insulating layer on the inner isolation strip, the outer isolation strip and the second mirror, forming a barrier layer and a bonding layer on the entire front end structure;
  • Step S105 providing a bonding substrate to be bonded to the bonding layer, removing the first substrate, exposing the N-type gallium nitride layer;
  • Step S106 performing surface roughening treatment on the N-type gallium nitride layer, and etching the front end structure to form a P through hole and an N through hole;
  • Step S107 forming a P electrode electrically connected to the first mirror in the P through hole, and forming an N electrode electrically connecting the connection end of the second mirror in the N through hole.
  • FIG. 1 is a flowchart of a method for manufacturing a high-power LED chip according to an embodiment of the present invention
  • FIG. 2 to FIG. 11 are diagrams for manufacturing a high-power LED chip according to an embodiment of the present invention
  • the manufacturing method of the high power LED chip includes:
  • step S101 is performed to provide a front end structure including a first substrate 10, an N-type gallium nitride layer (N-GaN) 11 formed on the first substrate, and a quantum Well layer (MQW) 12 and P-type gallium nitride layer (P-GaN) 13.
  • the first substrate 10 can be selected from a sapphire substrate, a silicon substrate, a silicon carbon substrate or a patterned substrate.
  • a sapphire substrate is used.
  • the N-type gallium nitride layer 11, the quantum well layer 12, and the P-type gallium nitride layer 13 may be sequentially formed by a growth method such as MOCVD/MBE molecular beam epitaxy.
  • step S102 is performed to etch the front end structure to form a plurality of trenches 14 to expose the N-type gallium nitride layer 11.
  • the grooves 14 are arranged in a "mountain" shape, and the grooves 14 formed are not limited to the structure as shown in FIG. 3b, but may be any other shape, and any other Arrangement.
  • the arrangement of the grooves 14 may also be of the "M” type, the "n” type, the "T” type, the "X” type, and the like.
  • the plurality of trenches 14 shown in FIG. 3b are connected to each other. However, in other embodiments, the plurality of trenches 14 may be independent of each other. through.
  • the plurality of trenches 14 in Figure 3c are not in communication with one another.
  • the trench 14 has a circular shape in plan view.
  • the shape of the trench 14 may also be a rectangular shape, which will not be enumerated here.
  • step S103 is performed to form a first mirror 16 on the P-type gallium nitride layer 13, and a protrusion of the second mirror 17 is formed in the trench 14.
  • the end 171 and the connecting end 172, the extending end 171 of the second mirror is connected to the surface of the N-type gallium nitride layer 11 through the connecting end 172 of the second mirror, and the sidewall of the trench 14
  • An inner spacer 152 is left between the second mirror 17 and an outer spacer 151 is left between the sidewall of the trench 14 and the first mirror 16.
  • a patterned photoresist 15 is first obtained on the front end structure by a photolithography process, and a first mirror pattern formed on the P-type gallium nitride layer 13 is obtained and located.
  • the second mirror 17 includes an extending end 171 of the second mirror that penetrates into the trench 14 and a connecting end 172 of the second mirror.
  • the top mirror has a pattern of the second mirror as viewed from a plan view.
  • the "mountain" shape of course, varies depending on the groove 14, and the pattern of the second mirror also changes.
  • the photoresist is covered by the entire front end structure and filled with the trenches 14, and then developed to remove the photoresist in the middle of the trenches 14, exposing the N-type gallium nitride layer 11, that is, forming the pattern of the second mirror, the trench
  • the sidewalls of 14 are still protected by photoresist and the photoresist at the first mirror is removed accordingly.
  • the pattern of the first mirror and the pattern of the second mirror thus obtained are separated by the remaining photoresist.
  • the first mirror 16 and the second mirror 17 are formed in the photoresist pattern by an evaporation process.
  • the metal silver may be vapor-deposited by using a sputtering machine.
  • other materials such as metal aluminum, may be used to form the metal in the trench 14 and electrically connected to the N-type gallium nitride layer 11.
  • the connection is formed in a photoresist pattern on the P-type gallium nitride layer 13.
  • the extending end 171 of the second mirror fills the trench 14 (there is still a photoresist on the sidewall of the trench) and exceeds the upper end of the trench 14, and the connecting end 172 of the second mirror can be a thinner one.
  • connection end 172 of the second mirror 17 is also It may be the same thickness as the projecting end 171. It should be noted that the division of the extending end 171 and the connecting end 172 of the second mirror 17 is not absolute, and since the plurality of grooves 14 can have a plurality of different layouts or shapes, The second mirror 17 formed by the portion in which the plurality of grooves are connected may be referred to as a connection end 172.
  • the inner spacer 152 has a width of 1-10 ⁇ m
  • the outer spacer 151 has a width of 1-10 ⁇ m.
  • FIG. 5b corresponds to the case where the plurality of grooves 14 shown in FIG. 3b are circular in shape and are not connected to each other.
  • the structure shown in Figure 5b can be formed using steps similar to those shown in Figure 5a, except that the second mirror 17 is located within the plurality of circular grooves 14, due to the plurality of When the grooves 14 are not connected to each other, the plurality of second mirrors 17 are also not connected to each other.
  • the number of the first mirrors 16 is also plural, and the shape is circular, and is staggered with the plurality of second mirrors 17. It should be noted that, for the sake of clarity in FIG. 5b, the inner isolation band left between the sidewall of the trench 14 and the second mirror 17 is not indicated, and the sidewall of the trench 14 is An outer spacer left between the mirrors 16.
  • the trenches 14 may be smaller in size, forming the first mirror 16 and the second mirror After the 17th, the first mirror 16 and the second mirror 17 occupy a smaller area of the entire LED chip, which increases the light emitting area of the LED chip and improves the luminous efficiency.
  • FIG. 6a, FIG. 6b and FIG. 7a wherein FIG. 6b is a cross-sectional view taken along line XX of FIG. 6a, and step S104 is performed to form on the inner isolation strip 152, the outer isolation strip 151 and the second mirror 17.
  • the insulating layer 18 forms a barrier layer 19 and a bonding layer 20 over the entire front end structure.
  • the material of the insulating layer 18 may be, for example, a non-conductive material such as silicon oxide (SiO 2 ), aluminum nitride (AlN), or aluminum oxide (Al 2 O 3 ), completely covering the second mirror 17 .
  • the bonding layer 20 may be an insulating glue bonding layer or a metal bonding layer.
  • the subsequently used bonding substrate may be an insulating material or a metal material.
  • an insulating material layer is also formed between the barrier layer and the metal bonding layer for electrically shielding the functional layer of the device from the outside.
  • the subsequently provided spacer substrate may comprise two or more sub-layers, and one of the sub-layers is a layer of insulating material for electrically isolating the device functional layer from the outside.
  • the material of the metal bonding layer may be, for example, one or more of gold (Au), tin (Sn), gold-tin alloy, gold-indium alloy, and nickel-tin alloy.
  • Figures 6c-6e corresponding to the case where the plurality of grooves 14 shown in Figures 3b and 5b are circular in shape and not connected to each other.
  • the plurality of first mirrors 16 or the plurality of second mirrors 17 are isolated from each other, the plurality of first mirrors 16 and the plurality of second mirrors 17 are also required to be separated.
  • the P interconnect layer 31 and the N interconnect layer 32 are electrically connected together, respectively.
  • an insulating layer 18 may be evaporated on the entire surface of the front end structure; an imaged photoresist (not shown) is formed on the insulating layer 18, and the patterned photoresist Positioned between the P interconnect layer 31 and the N interconnect layer 32 to be formed, exposing the insulating layer 18 corresponding to the positions of the plurality of first mirrors 16 and second mirrors 17; The photoresist layer is a mask, and the insulating layer 18 is etched until the plurality of first mirrors 16 and second mirrors 17 are exposed.
  • an interconnect metal layer is deposited, the interconnect metal layer is located on the plurality of first mirrors 16, the plurality of second mirrors 17, and the patterned photoresist layer; Removing the imaged photoresist layer and the interconnect metal layer on the patterned photoresist layer by a lift-off process, and remaining portions electrically connected to the first mirror 16 are mutually
  • the metal layer constitutes a P interconnect layer 31, and a portion of the interconnect metal layer electrically connected to the second mirror 17 constitutes an N interconnect layer 32; then, on the P interconnect layer 31 and the N interconnect layer 32
  • the barrier layer 19 and the bonding layer 20 are formed. For a detailed description of the barrier layer 19 and the bonding layer 20, reference may be made to the previous embodiments, and details are not described herein again.
  • FIG. 6e is a top view of the P interconnect layer 31 and the N interconnect layer 32 in an embodiment of the invention.
  • the position of the first mirror 16 under the P interconnect layer 31 and the position of the second mirror 17 under the N interconnect layer 32 are also shown in dashed lines.
  • the P interconnect layer 31 and the N interconnect layer may have other shapes as long as the P interconnect layer 31 functions to connect the plurality of first mirrors 16, the N The interconnect layer functions to connect the plurality of second mirrors 17.
  • step S105 is performed to provide a bonding substrate 21 to be bonded to the bonding layer 20, to remove the first substrate 10, and to expose the N-type gallium nitride layer 11.
  • the bonded substrate 21 is an insulating substrate, and may be, for example, a material that does not conduct electricity such as silicon, ceramics, or aluminum nitride, but has good thermal conductivity.
  • the peeling of the first substrate 10 can be performed by a conventional means, and the description is omitted here.
  • the bonding substrate 21 may be an insulating material, a metal material, or a composite structure of the two, which is not limited in the present invention.
  • the material of the bonded substrate may include one or more of silicon, ceramic, aluminum nitride, copper, tungsten, and molybdenum.
  • the bonded substrate 21 is made of a material having a thermal conductivity greater than 100 W/(m ⁇ K).
  • the bonding layer 20 is a metal bonding layer, and an insulating material layer is formed between the barrier layer 19 and the metal bonding layer, the bonding substrate 21
  • an insulating material, a metal material or a composite structure of the two which is not limited in the present invention. As long as the insulating material or the metal material has better thermal conductivity, refer to the description of the above embodiments.
  • the bonding liner The bottom 21 includes two or more sub-layers, and one of the sub-layers is an insulating material layer for electrically isolating the functional layer of the LED chip from the outside, and the remaining sub-layers may be made of an insulating material having better thermal conductivity. Metal material or a composite structure of the two.
  • An insulating material sub-layer in the bonding substrate 21 may be located on a surface of the bonding substrate 21, Bonding with the metal bonding layer; may also be located between the plurality of sub-layers of the bonding substrate 21, and bonding with the bonding layer 20 through other sub-layers.
  • step S106 is performed to perform surface roughening treatment on the N-type gallium nitride layer 11, and etching the front end structure to form a P through hole 22 and an N through hole 23.
  • the surface roughening treatment for the N-type gallium nitride layer 11 can be wet-etched using a potassium hydroxide (KOH) solution, a sulfuric acid (H 2 SO 4 ) solution or the like to obtain a rough surface 111 to improve the light extraction rate.
  • KOH potassium hydroxide
  • H 2 SO 4 sulfuric acid
  • U-GaN undoped gallium nitride layer
  • the via holes 22 are formed by a photolithography etching process, wherein the etching of the via holes 22 is performed in the Y-Y line direction as shown in FIG. 6a, that is, on both sides of the second mirror 17. Specifically, the etched N-type gallium nitride layer 11, the quantum well layer 12, and the P-type gallium nitride layer 13 form a P-via 22 to expose the first mirror 16; and the etched N-type gallium nitride layer is formed.
  • the N through hole 23 exposes the connection end 172 of the second mirror.
  • step S107 is performed to form a P electrode 24 electrically connected to the first mirror 16 in the P through hole 22, and a connection end electrically connecting the second mirror is formed in the N through hole 23 N electrode 25 of 172.
  • the material of the electrode may be, for example, nickel (Ni)/gold (Au), aluminum (Al)/titanium (Ti)/platinum (Pt)/gold (Au), chromium (Cr)/platinum (Pt)/gold (Au). Wait.
  • the P electrode 24 and the N electrode 25 prepared in the present invention are all on the surface of the N-type gallium nitride layer 11, that is, on the N side, and are respectively located on both sides of the second mirror 17, respectively, which optimizes the packaging process.
  • the passivation layer 26 may be further evaporated, the N-type gallium nitride layer 11 having a roughened surface may be covered, and the electrodes 24, 25 and the sidewalls of the via holes may be isolated, and the material of the passivation layer 26 is, for example, It may be a material having high light transmittance such as silicon oxide or aluminum oxide and having a refractive index between gallium nitride and air.
  • the groove 14 is arranged in a “mountain” shape structure, and the high power LED chip forming method in the embodiment of the present invention is bonded, Surface roughening and electrode formation processes are described.
  • the above process is also applicable to the case where the plurality of grooves 14 shown in Fig. 3c are circular or rectangular and are not in communication with each other.
  • the P through hole and the N through hole expose the P interconnect layer 31 and the N interconnect layer, respectively.
  • the P electrode 24 is electrically connected to the plurality of first mirrors 16 through the P interconnect layer 31
  • the N electrode 25 is electrically connected to the plurality of second mirrors 17 through the N interconnect layer 32.
  • the high power LED chip obtained by the present invention comprises: a bonding substrate 21; a bonding layer 20 and a barrier layer 19 sequentially located on the bonding substrate 21. a first mirror 16 and a second mirror 17 on the barrier layer 19; a P-type gallium nitride layer 13 on the first mirror 16, a quantum well layer 12, and a surface-rough N-type a gallium nitride layer 11, a projecting end 171 of the second mirror passes through the P-type gallium nitride layer 13 and the quantum well layer 12 through the connection end 172 of the second mirror on the surface of the N-type gallium nitride layer 11 Connecting, the second mirror 17 is separated from the P-type gallium nitride layer 13, the quantum well layer 12, the first mirror 16 and the barrier layer 19 by an insulating layer 18; through the P-type gallium nitride layer 13, a quantum well layer 12 and a P electrode 24 of the N-
  • the number of the first mirrors 16 of the first mirror is multiple and not connected to each other.
  • the planar shape of the plurality of first mirrors 16 in the direction perpendicular to the surface of the substrate is circular or rectangular. Since the plurality of first mirrors 16 are not connected to each other, in these embodiments, as shown in FIG. 11b, the LED chip further includes a P interconnection layer 31 and an N mutual on the barrier layer 19. a layer 32 for electrically connecting the plurality of first mirrors 16 for electrically connecting a plurality of second mirrors 17, the P electrodes 24 passing through The P interconnect layer 31 is electrically connected to the first mirror 16, and the N electrode 25 passes through the N interconnect layer and the first The two mirrors are electrically connected. It should be noted that, for the sake of simplicity, all the components of the LED chip are not shown in FIG. 11b. Thus, the high-power LED chip of the present invention is completed, and the present invention has the following advantages over the prior art:
  • the N electrode and the P electrode are on the same side, and the bonding substrate with good non-conductivity and good thermal conductivity is used to make the packaging process simpler;
  • the N-GaN surface is a light-emitting surface, and the surface can be roughened on the thick N-GaN surface to increase the light output.

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Abstract

本发明揭示了一种大功率LED芯片及其制造方法。通过在氮化镓外延层中形成规则的沟槽，在P型氮化镓层上形成与P电极相连接的第一反射镜，在沟槽中形成与N电极相连接的第二反射镜，保证电流分布均匀，采用不导电、导热良好的键合衬底，解决了大功率芯片散热不良的问题。采用N面出光，利用表面微粗化处理大大提高了出光效率，且使得N电极和P电极都在N氮化镓层的表面，使封装工艺更加简单。

Description

大功率LED芯片及其制造方法
本申请要求2015年4月20日提交中国专利局、申请号为201510192220.3、发明名称为“大功率LED芯片及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，特别是涉及一种大功率LED芯片及其制造方法。
背景技术
近年来，LED作为新一代绿色光源，广泛应用于照明、背光、显示、指示等领域。随着市场的竞争，各个LED企业以提高芯片光效，降低生产成本为目标，逐步提高生产竞争力。
传统的正装LED芯片是最早出现的LED芯片结构，也是小功率芯片中普遍使用的结构。一般而言，电极在上方，自上而下包括P型氮化镓层，量子阱层，N型氮化镓层，衬底。
但是，传统的正装结构LED芯片由于蓝宝石衬底不导电、导热率差的制约性，存在电流分布不均匀、散热性差等先天缺陷，导致难以实现大功率芯片的制作。
其制约性主要体现在：
1.蓝宝石导热性差，大功率芯片散热问题难以解决；
2.蓝宝石不导电，P型氮化镓层的横向导电能力差，需要透明导电层(例如ITO)来帮助做横向电流扩展，ITO越厚电流扩展能力越强，但其吸光会增多。
3.传统正装芯片由于结构特性，始终存在电流分布不均匀问题。
4.传统正装芯片出光面为P面，由于P型氮化镓层较薄，难以实 现表面粗化处理以增加出光效率。
因此，能否改善现有的LED芯片结构，获得一种大功率LED芯片，是业内关注的一个焦点。
发明内容
本发明的目的在于，提供一种散热优秀、电流分布均匀的大功率LED芯片及其制造方法。
为解决上述技术问题，本发明提供一种大功率LED芯片的制造方法，包括：
提供前端结构，所述前端结构包括第一衬底，形成于所述第一衬底上的N型氮化镓层、量子阱层和P型氮化镓层；
刻蚀所述前端结构形成多个沟槽，暴露出N型氮化镓层；
在所述P型氮化镓层上形成第一反射镜，在所述沟槽中形成第二反射镜的伸入端及连接端，所述第二反射镜的伸入端通过所述第二反射镜的连接端在N型氮化镓层表面相连接，所述沟槽的侧壁与第二反射镜之间留出内隔离带，所述沟槽的侧壁与第一反射镜之间留出外隔离带；
在所述内隔离带、外隔离带和第二反射镜上形成绝缘层，在整个前端结构上形成阻挡层和键合层；
提供键合衬底与所述键合层相键合，去除第一衬底，暴露出N型氮化镓层；
对所述N型氮化镓层进行表面粗化处理，刻蚀所述前端结构形成P通孔和N通孔；
在所述P通孔中形成电连接第一反射镜的P电极，在所述N通孔中形成电连接第二反射镜的连接端的N电极。
可选的，对于所述的大功率LED芯片的制造方法，所述内隔离 带的宽度为1-10μm，所述外隔离带的宽度为1-10μm。
可选的，对于所述的大功率LED芯片的制造方法，所述绝缘层的材料包括氧化硅、氮化铝或氧化铝。
可选的，对于所述的大功率LED芯片的制造方法，所述第一反射镜和第二反射镜的形成过程包括：
通过光刻工艺在所述前端结构上获得图案化的光阻，获得形成位于P型氮化镓层上的第一反射镜图案和位于沟槽中的第二反射镜图案；
通过蒸镀工艺在光阻图案中形成第一反射镜和第二反射镜；
去除所述光阻。
可选的，对于所述的大功率LED芯片的制造方法，所述N电极与P电极位于第二反射镜两侧。
相应的，本发明还提供一种由所述的大功率LED芯片的制造方法制得的大功率LED芯片，包括：
键合衬底；
依次位于所述键合衬底上的键合层、阻挡层；
位于所述阻挡层上的第一反射镜和第二反射镜；
依次位于所述第一反射镜上的P型氮化镓层、量子阱层和表面粗糙的N型氮化镓层，第二反射镜的伸入端穿过所述P型氮化镓层和量子阱层通过第二反射镜的连接端在N型氮化镓层表面相连接，第二反射镜与P型氮化镓层、量子阱层、第一反射镜及阻挡层之间由绝缘层隔离；
穿过所述P型氮化镓层、量子阱层和N型氮化镓层的P电极，所述P电极电连接第一反射镜，穿过所述N型氮化镓层N电极，所述N电极电连接所述第二反射镜的连接端。
本发明提供一种大功率LED芯片的制造方法，包括：
提供前端结构，所述前端结构包括第一衬底，形成于所述第一衬底上的N型氮化镓层、量子阱层和P型氮化镓层；
刻蚀所述前端结构形成多个沟槽，暴露出N型氮化镓层；
在所述P型氮化镓层上形成第一反射镜，在所述沟槽暴露出的N型氮化镓层上形成第二反射镜，所述沟槽的侧壁与第二反射镜之间留出内隔离带，所述沟槽的侧壁与第一反射镜之间留出外隔离带；
在所述内隔离带和外隔离带上形成绝缘层，在所述绝缘层上形成阻挡层和键合层；
提供键合衬底与所述键合层相键合，去除第一衬底，暴露出N型氮化镓层；
对所述N型氮化镓层进行表面粗化处理，刻蚀所述前端结构形成P通孔和N通孔；
在所述P通孔中形成电连接第一反射镜的P电极，在所述N通孔中形成电连接第二反射镜的连接端的N电极。
可选地，所述多个沟槽互不连通，所述多个沟槽的形状为圆形或者矩形。
可选地，所述方法还包括：在形成所述绝缘层后以及在形成所述阻挡层前，在所述绝缘层上形成P互连层和N互连层，其中，所述P互连层与所述第一反射镜连接，所述N互连层与所述第二反射镜连接；并且在形成所述P电极和N电极后，所述P电极与所述P互连层连接，N电极与N互连层连接。
可选地，形成所述P互连层和N互连层包括：
在所述绝缘层上形成图形化的光刻胶，所述图形化的光刻胶位于待形成的P互连层和N互连层之间；
以所述图像化的光刻胶为掩膜，刻蚀所述绝缘层，暴露出所述第一反射镜和第二反射镜；
沉积互连金属层，所述互连金属层位于所述第一反射镜、第二反射镜和所述图形化的光刻胶上；
剥离所述图形化的光刻胶及位于所述图形化的光刻胶上的互连金属层，剩余的与所述第一反射镜连接的部分互连金属层构成P互连层，与所述第二反射镜连接的部分互连金属层构成N互连层。
可选地，所述键合层为绝缘胶键合层。
可选地，所述键合层为金属键合层。
可选地，所述金属键合层的材料包括金、锡、铟、金铟合金、金锡合金、镍锡合金中的一种或多种。
可选地，所述方法还包括：在所述阻挡层和所述金属键合层之间形成绝缘材料层。
可选地，所述键合衬底的热导率大于等于100W/(m·K)。
可选地，所述键合衬底包括两个或者两个以上的子层，并且其中一个子层为绝缘材料层。
可选地，所述键合衬底的材料包括硅、陶瓷、氮化铝、铜、钨、钼中的一种或多种。
对应地，本发明还提供一种大功率LED芯片，包括：
键合衬底；
依次位于所述键合衬底上的键合层和阻挡层；
位于所述阻挡层上的第一反射镜和第二反射镜；
依次位于所述第一反射镜上的P型氮化镓层、量子阱层和表面经过粗化处理的N型氮化镓层，所述第二反射镜穿过所述P型氮化镓 层和量子阱层与所述N型氮化镓层相连接，所述第二反射镜与所述P型氮化镓层、量子阱层和第一反射镜之间由绝缘层隔离；
穿过所述P型氮化镓层、量子阱层和N型氮化镓层的P电极，所述P电极电连接第一反射镜，穿过所述N型氮化镓层N电极，所述N电极电连接所述第二反射镜的连接端。
可选地，所述第一反射镜的数量为多个，且互不相连，所述多个第一反射镜的形状为为圆形或者矩形。
可选地，所述LED芯片还包括位于所述阻挡层上的P互连层和N互连层，所述P电极通过所述P互连层与所述第一反射镜电连接，所述N电极通过所述N互连层与所述第二反射镜电连接。
相比现有技术，本发明提供的大功率LED芯片及其制造方法中，通过在氮化镓外延层中形成规则的沟槽，在P型氮化镓层上形成与P电极相连接的第一反射镜，在沟槽中形成与N电极相连接的第二反射镜，保证电流分布均匀，采用不导电、导热良好的键合衬底，解决了大功率芯片散热不良的问题。采用N面出光，利用表面微粗化处理大大提高了出光效率，且使得N电极和P电极都在N氮化镓层的表面，使封装工艺更加简单。
附图说明
图1为本发明实施例中大功率LED芯片的制造方法的流程图；
图2-图11为本发明实施例中大功率LED芯片的制造方法的过程中器件结构的示意图。
具体实施方式
下面将结合示意图对本发明的大功率LED芯片及其制造方法进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道， 而并不作为对本发明的限制。
为了清楚，不描述实际实施例的全部特征。在下列描述中，不详细描述公知的功能和结构，因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中，必须做出大量实施细节以实现开发者的特定目标，例如按照有关系统或有关商业的限制，由一个实施例改变为另一个实施例。另外，应当认为这种开发工作可能是复杂和耗费时间的，但是对于本领域技术人员来说仅仅是常规工作。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明的核心思想在于，提供一种大功率LED芯片的制造方法，包括：
步骤S101，提供前端结构，所述前端结构包括第一衬底，形成于所述第一衬底上的N型氮化镓层、量子阱层和P型氮化镓层；
步骤S102，刻蚀所述前端结构形成多个沟槽，暴露出N型氮化镓层；
步骤S103，在所述P型氮化镓层上形成第一反射镜，在所述沟槽中形成第二反射镜的伸入端及连接端，所述第二反射镜的伸入端通过所述第二反射镜的连接端在N型氮化镓层表面相连接，所述沟槽的侧壁与第二反射镜之间留出内隔离带，所述沟槽的侧壁与第一反射镜之间留出外隔离带；
步骤S104，在所述内隔离带、外隔离带和第二反射镜上形成绝缘层，在整个前端结构上形成阻挡层和键合层；
步骤S105，提供键合衬底与所述键合层相键合，去除第一衬底，暴露出N型氮化镓层；
步骤S106，对所述N型氮化镓层进行表面粗化处理，刻蚀所述前端结构形成P通孔和N通孔；
步骤S107，在所述P通孔中形成电连接第一反射镜的P电极，在所述N通孔中形成电连接第二反射镜的连接端的N电极。
以下列举所述大功率LED芯片及其制造方法的较优实施例，以清楚说明本发明的内容，应当明确的是，本发明的内容并不限制于以下实施例，其他通过本领域普通技术人员的常规技术手段的改进亦在本发明的思想范围之内。
请参考图1，并结合图2-图11，其中图1为本发明实施例中大功率LED芯片的制造方法的流程图；图2～图11为本发明实施例中大功率LED芯片的制造方法的过程中器件结构的示意图。
如图1所示，所述大功率LED芯片的制造方法包括：
首先，请参考图2，执行步骤S101，提供前端结构，所述前端结构包括第一衬底10，形成于所述第一衬底上的N型氮化镓层(N-GaN)11、量子阱层(MQW)12和P型氮化镓层(P-GaN)13。较佳的，第一衬底10的可以选择为蓝宝石衬底，硅衬底、硅碳衬底或者图形化的衬底，本实施例中采用蓝宝石衬底。具体的，N型氮化镓层11、量子阱层12和P型氮化镓层13可以采用MOCVD/MBE分子束外延等生长方法依次形成。
接着，请参考图3a和图3b，执行步骤S102，刻蚀所述前端结构形成多个沟槽14，暴露出N型氮化镓层11。在本发明的较佳实施例中，沟槽14排布呈“山”字型，所形成的沟槽14并不限于如图3b中所示的结构，还可以是其他任意形状，以及其他任意的排布方式。例如，所述沟槽14的排布还可以呈“M”型、“n”型、“T”型、“X”型等等。
需要说明的是，图3b所示多个沟槽14之间相互连通，但是，在其他一些实施例中，所述多个沟槽14之间也可以相互独立，并不连 通。例如，参考图3c，图3c中的多个沟槽14相互之间并不连通。在图3c中，所述沟槽14的俯视形状为圆形。当然，所述沟槽14的俯视形状还可以为矩形，在此不再一一列举。
接着，请参考图4a、图4b和图5a，执行步骤S103，在所述P型氮化镓层13上形成第一反射镜16，在所述沟槽14中形成第二反射镜17的伸入端171及连接端172，所述第二反射镜的伸入端171通过所述第二反射镜的连接端172在N型氮化镓层11表面相连接，所述沟槽14的侧壁与第二反射镜17之间留出内隔离带152，所述沟槽14的侧壁与第一反射镜16之间留出外隔离带151。
具体的，如图4a和图4b所示，首先通过光刻工艺在所述前端结构上获得图案化的光阻15，获得形成位于P型氮化镓层13上的第一反射镜图案和位于沟槽14中的第二反射镜图案。例如在本实施例中，第二反射镜17包括深入沟槽14中的第二反射镜的伸入端171以及第二反射镜的连接端172，从俯视图上看，第二反射镜的图案为“山”字型，当然，依据沟槽14的不同，第二反射镜的图案也会变动。那么首先使得光阻覆盖整个前端结构，并填充满沟槽14，之后显影去掉沟槽14中间的光阻，暴露出N型氮化镓层11，也即形成第二反射镜的图案，沟槽14的侧壁依旧被光阻保护，并相应的去掉形成第一反射镜处的光阻。如此获得的第一反射镜的图案和第二反射镜的图案被剩余光阻所分离。
然后，如图5a所示，通过蒸镀工艺在光阻图案中形成第一反射镜16和第二反射镜17。具体的，可以是采用溅镀机进行金属银的蒸镀，当然，还可以是其他材质，例如金属铝等，从而实现将金属形成在沟槽14中，并与N型氮化镓层11电连接，以及形成在P型氮化镓层13上的光阻图案中。其中第二反射镜的伸入端171是填满沟槽14(此时沟槽侧壁尚存在光阻)并超过沟槽14上端，而第二反射镜的连接端172则可以是较薄一层，连接第二反射镜的伸入端171并与N型氮化镓层11电连接。当然，所述第二反射镜17的连接端172也 可以与伸入端171的厚度相同。需要说明的是，所述第二反射镜17的伸入端171和连接端172的划分并不是绝对的，由于所述多个沟槽14可以具有多种不同的布局或者形状，因此在将所述多个沟槽连通起来的部分所形成的第二反射镜17都可称为连接端172。
之后，去除剩余的光阻。那么沟槽14的侧壁与第二反射镜的伸入端171之间存在间隙，作为了内隔离带152，沟槽14与第一反射镜16之间则是外隔离带151。所述内隔离带152的宽度为1-10μm，所述外隔离带151的宽度为1-10μm。
在其他一些实施例中，如图5b所示，图5b对应于图3b所示的所述多个沟槽14的形状为圆形且互不相连的情况。图5b中所示的结构可以采用与形成图5a所示结构类似的步骤形成，不同的是，所述第二反射镜17位于所述多个圆形的沟槽14内，由于所述多个沟槽14互不连接，则多个第二反射镜17也互不连接。此外，在图5b中，所述第一反射镜16的数量也为多个，形状为圆形，与所述多个第二反射镜17交错分布。需要说明的是，图5b中为了清楚起见，并未标示出所述沟槽14的侧壁与第二反射镜17之间留出的内隔离带，和所述沟槽14的侧壁与第一反射镜16之间留出的外隔离带。
当采用如图3c所示的圆形结构的、且相互之间不连通的多个沟槽14时，所述沟槽14的尺寸可以更小，在形成第一反射镜16和第二反射镜17后，所述第一反射镜16和第二反射镜17占用整个LED芯片的面积也更小，增加了所述LED芯片的发光面积，提高了发光效率。
之后，请参考图6a、图6b和图7a，其中图6b为图6a中沿X-X线的剖视图，执行步骤S104，在所述内隔离带152、外隔离带151和第二反射镜17上形成绝缘层18，在整个前端结构上形成阻挡层19和键合层20。所述绝缘层18的材料例如可以是氧化硅(SiO2)、氮化铝(AlN)、氧化铝(Al2O3)等不导电的材料，完全覆盖第二反射镜17。在绝缘层18形成后，形成阻挡层(barrier layer)19，阻挡层 19完全包裹第一反射镜16和绝缘层18，然后在阻挡层19上蒸镀键合层20。所述键合层20可以为绝缘胶键合层或者金属键合层。当所述键合层20为绝缘胶键合层时，后续采用的键合衬底可以为绝缘材料或者金属材料。当所述键合层20为金属键合层时，在一些实施例中，还在所述阻挡层和所述金属键合层之间形成了绝缘材料层，用于将器件功能层与外界电隔离；在另外一些实施例中，后续提供的间隔衬底可以包括两个或者两个以上的子层，并且其中一个子层为绝缘材料层，用于将器件功能层与外界电隔离。所述金属键合层的材料例如可以是金(Au)、锡(Sn)、金锡合金、金铟合金、镍锡合金中的一种或多种。
在其他一些实施例中，参考图6c-6e，对应于图3b和图5b所示的所述多个沟槽14的形状为圆形且互不相连的情况。在这些实施例中，由于所述多个第一反射镜16或者多个第二反射镜17相互之间隔离，因此还需要将所述多个第一反射镜16和多个第二反射镜17分别通过P互连层31和N互连层32电连接在一起。
具体地，参考图6c，可以在所述前端结构的整个表面蒸镀绝缘层18；在所述绝缘层18上形成图像化的光刻胶(未图示)，所述图形化的光刻胶位于待形成的P互连层31和N互连层32之间的位置，暴露出与所述多个第一反射镜16和第二反射镜17位置对应的绝缘层18；以所述图像化的光刻胶层为掩膜，刻蚀所述绝缘层18，直至暴露出所述多个第一反射镜16和第二反射镜17。接着，参考图6d和6e，沉积互连金属层，所述互连金属层位于所述多个第一反射镜16、多个第二反射镜17以及所述图像化的光刻胶层上；采用剥离(lift-off)工艺去除所述图像化的光刻胶层以及位于所述图像化的光刻胶层上互连金属层，剩余的与所述第一反射镜16电连接的部分互连金属层构成P互连层31，与所述第二反射镜17电连接的部分互连金属层构成N互连层32；接着，在所述P互连层31和N互连层32上形成阻挡层19和键合层20。关于所述阻挡层19和键合层20的详细描述可以参考前面的实施例，此处不再赘述。
需要说明的，图6e为本发明实施例一具体实施例中所述P互连层31和N互连层32的俯视图。在图6e中，还采用虚线示出了位于所述P互连层31下的第一反射镜16的位置，和位于所述N互连层32下的第二反射镜17的位置。在其他实施例中，所述P互连层31和N互连层还可以具有其他的形状，只要使得所述P互连层31起到连接多个第一反射镜16的作用、所述N互连层起到连接多个第二反射镜17的作用即可。
然后，请参考图8，执行步骤S105，提供键合衬底21与所述键合层20相键合，去除第一衬底10，暴露出N型氮化镓层11。在本发明中，所述键合衬底21为绝缘衬底，例如可以是硅、陶瓷、氮化铝等不导电，却具备良好导热性的材料。第一衬底10的剥离可以采用常规手段进行，在此省略描述。
在另一些实施例中，当所述键合层20为绝缘胶键合层时，所述键合衬底21可以采用绝缘材料、金属材料或者两者的复合结构，本发明对此不作限制。例如，所述键合衬底的材料可以包括硅、陶瓷、氮化铝、铜、钨、钼中的一种或多种。较佳地，所述键合衬底21采用的材料的热导率大于100W/(m·K)。
在另一些实施例中，当所述键合层20为金属键合层，且在所述阻挡层19和所述金属键合层之间形成有绝缘材料层时，所述键合衬底21也可以采用绝缘材料、金属材料或者两者的复合结构，本发明对此不作限制。只要所述绝缘材料或者金属材料具有较佳的导热性能即可，具体可参考上面实施例的描述。
在另一些实施例中，当所述键合层20为金属键合层，但在所述阻挡层19和所述金属键合层之间没有形成有绝缘材料层时，则所述键合衬底21包括了两个或者两个以上的子层，并且其中一个子层为绝缘材料层，用于将LED芯片的功能层与外界电隔离，其余子层可以采用导热性能较佳的绝缘材料、金属材料或者两者的复合结构。所述键合衬底21中的绝缘材料子层可以位于所述键合衬底21的表面， 与所述金属键合层相键合；也可以位于所述键合衬底21的多个子层中间，通过其他子层与所述键合层20键合。
本发明的上述实施例中，无论采用何种结构，均是为了在对大功率LED芯片功能层进行电隔离的同时，提高芯片散热性能，具体采用哪一种，可以根据具体应用和产品性能需求来确定。
然后，请参考图9和图10，执行步骤S106，对所述N型氮化镓层11进行表面粗化处理，刻蚀所述前端结构形成P通孔22和N通孔23。其中对N型氮化镓层11进行的表面粗化处理可以采用氢氧化钾(KOH)溶液、硫酸(H2SO4)溶液等进行湿法刻蚀，获得粗糙表面111，以提高出光率。对于存在无掺杂氮化镓层(U-GaN)的结构，则还需先进行无掺杂氮化镓层的整体刻蚀或者图形化刻蚀。在粗糙表面111形成后，通过光刻刻蚀工艺，形成通孔22，其中，通孔22的刻蚀按照如图6a中的Y-Y线方向进行，即在第二反射镜17两侧。具体的，包括刻蚀N型氮化镓层11、量子阱层12及P型氮化镓层13形成P通孔22，暴露出第一反射镜16；以及刻蚀N型氮化镓层形成N通孔23，暴露出第二反射镜的连接端172。
最后，请参考图11a，执行步骤S107，在所述P通孔22中形成电连接第一反射镜16的P电极24，在所述N通孔23中形成电连接第二反射镜的连接端172的N电极25。电极的材质例如可以是镍(Ni)/金(Au)，铝(Al)/钛(Ti)/铂(Pt)/金(Au)，铬(Cr)/铂(Pt)/金(Au)等。由此可见，本发明中制得的P电极24和N电极25皆在N型氮化镓层11表面，即都在N侧，且分别位于第二反射镜17两侧，优化了封装过程。在电极形成后，还可以继续蒸镀钝化层26，覆盖表面粗化后的N型氮化镓层11，并隔离电极24、25与通孔侧壁，所述钝化层26的材料例如可以是氧化硅、氧化铝等透光性高，且折射率介于氮化镓和空气之间的材料。
需要说明的是，在图8-图11a中，以所述沟槽14排布呈“山”字型结构为例，对本发明实施例的大功率LED芯片形成方法中键合、 表面粗化和电极形成的工艺进行了描述。上述工艺也同样也适用于图3c所示的多个沟槽14呈圆形或矩形、且相互之间并不连通的情形。只不过，如图11b所示，在刻蚀所述前端结构形成P通孔和N通孔后，所述P通孔和N通孔分别暴露出所述P互连层31和N互连层32；在所述P通孔和N通孔中分别形成P电极24和N电极25后，所述P电极24通过所述P互连层31与多个第一反射镜16电连接，所述N电极25通过所述N互连层32与多个第二反射镜17电连接。其具体工艺此处不再赘述，可以参考上述对所述沟槽14排布呈“山”字型结构的实施例的描述。
请继续参考图11a，并结合图1-图10，本发明获得的大功率LED芯片，包括：键合衬底21；依次位于所述键合衬底21上的键合层20、阻挡层19；位于所述阻挡层19上的第一反射镜16和第二反射镜17；依次位于所述第一反射镜16上的P型氮化镓层13、量子阱层12和表面粗糙的N型氮化镓层11，第二反射镜的伸入端171穿过所述P型氮化镓层13和量子阱层12通过第二反射镜的连接端172在N型氮化镓层11表面相连接，第二反射镜17与P型氮化镓层13、量子阱层12、第一反射镜16及阻挡层19之间由绝缘层18隔离；穿过所述P型氮化镓层13、量子阱层12和N型氮化镓层11的P电极24，所述P电极24电连接第一反射镜16，穿过所述N型氮化镓层11的N电极25，所述N电极25电连接所述第二反射镜的连接端172，从而实现与N型氮化镓层11的欧姆接触。
在另外一些实施例中，所述第一反射镜所述第一反射镜16的数量为多个，且互不连通。所述多个第一反射镜16沿垂直键合衬底表面方向的俯视形状为圆形或者矩形。由于所述多个第一反射镜16互不连通，因此，在这些实施例中，如图11b所示，所述LED芯片还包括位于所述阻挡层19上的P互连层31和N互连层32，所述P互连层31用于电连接所述多个第一反射镜16，所述N互连层用于电连接多个第二反射镜17，所述P电极24通过所述P互连层31与所述第一反射镜16电连接，所述N电极25通过所述N互连层与所述第 二反射镜电连接。需要说明的是，为了简单明了起见，图11b中并没有示出所述LED芯片的所有部件。由此，本发明的大功率LED芯片制造完成，相比现有技术，本发明具备如下优点：
1、通过形成规则的沟槽，并形成与N电极相连接的第二反射镜，解决了电流分布不均匀问题；
2、使得N电极和P电极在同一侧，同时采用不导电、导热良好的键合衬底，使封装工艺更加简单；
3、通过在P-GaN表面蒸镀具有高反射率的Ag镜，Ag与P-GaN形成良好欧姆接触，既保证了优秀的电流扩展，又避免了传统工艺中的透明导电层的吸光，提高了出光效率；
4、通过衬底转移技术，将氮化镓外延层(N-GaN、MQW、P-GaN)从导热性差的蓝宝石衬底转移至导热性良好的键合衬底上面，解决散热问题；
5、衬底转移后，N-GaN面为出光面，可在较厚的N-GaN面进行表面粗化处理，增加出光。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (20)

  1. 一种大功率LED芯片的制造方法，包括：
    提供前端结构，所述前端结构包括第一衬底，形成于所述第一衬底上的N型氮化镓层、量子阱层和P型氮化镓层；
    刻蚀所述前端结构形成多个沟槽，暴露出N型氮化镓层；
    在所述P型氮化镓层上形成第一反射镜，在所述沟槽中形成第二反射镜的伸入端及连接端，所述第二反射镜的伸入端通过所述第二反射镜的连接端在N型氮化镓层表面相连接，所述沟槽的侧壁与第二反射镜之间留出内隔离带，所述沟槽的侧壁与第一反射镜之间留出外隔离带；
    在所述内隔离带、外隔离带和第二反射镜上形成绝缘层，在整个前端结构上形成阻挡层和键合层；
    提供键合衬底与所述键合层相键合，去除第一衬底，暴露出N型氮化镓层；
    对所述N型氮化镓层进行表面粗化处理，刻蚀所述前端结构形成P通孔和N通孔；
    在所述P通孔中形成电连接第一反射镜的P电极，在所述N通孔中形成电连接第二反射镜的连接端的N电极。
  2. 如权利要求1所述的大功率LED芯片的制造方法，其特征在于，所述内隔离带的宽度为1-10μm，所述外隔离带的宽度为1-10μm。
  3. 如权利要求1所述的大功率LED芯片的制造方法，其特征在于，所述绝缘层的材料包括氧化硅、氮化铝或氧化铝。
  4. 如权利要求1所述的大功率LED芯片的制造方法，其特征在于，所述第一反射镜和第二反射镜的形成过程包括：
    通过光刻工艺在所述前端结构上获得图案化的光阻，获得形成位 于P型氮化镓层上的第一反射镜图案和位于沟槽中的第二反射镜图案；
    通过蒸镀工艺在光阻图案中形成第一反射镜和第二反射镜；
    去除所述光阻。
  5. 如权利要求1所述的大功率LED芯片的制造方法，其特征在于，所述N电极与P电极位于第二反射镜两侧。
  6. 一种由权利要求1-5中任意一项所述的大功率LED芯片的制造方法制得的大功率LED芯片，其特征在于，包括：
    键合衬底；
    依次位于所述键合衬底上的键合层、阻挡层；
    位于所述阻挡层上的第一反射镜和第二反射镜；
    依次位于所述第一反射镜上的P型氮化镓层、量子阱层和表面粗糙的N型氮化镓层，第二反射镜的伸入端穿过所述P型氮化镓层和量子阱层通过第二反射镜的连接端在N型氮化镓层表面相连接，第二反射镜与P型氮化镓层、量子阱层、第一反射镜及阻挡层之间由绝缘层隔离；
    穿过所述P型氮化镓层、量子阱层和N型氮化镓层的P电极，所述P电极电连接第一反射镜，穿过所述N型氮化镓层N电极，所述N电极电连接所述第二反射镜的连接端。
  7. 一种大功率LED芯片的制造方法，包括：
    提供前端结构，所述前端结构包括第一衬底，形成于所述第一衬底上的N型氮化镓层、量子阱层和P型氮化镓层；
    刻蚀所述前端结构形成多个沟槽，暴露出N型氮化镓层；
    在所述P型氮化镓层上形成第一反射镜，在所述沟槽暴露出的N型氮化镓层上形成第二反射镜，所述沟槽的侧壁与第二反射镜之间留 出内隔离带，所述沟槽的侧壁与第一反射镜之间留出外隔离带；
    在所述内隔离带和外隔离带上形成绝缘层，在所述绝缘层上形成阻挡层和键合层；
    提供键合衬底与所述键合层相键合，去除第一衬底，暴露出N型氮化镓层；
    对所述N型氮化镓层进行表面粗化处理，刻蚀所述前端结构形成P通孔和N通孔；
    在所述P通孔中形成电连接第一反射镜的P电极，在所述N通孔中形成电连接第二反射镜的连接端的N电极。
  8. 如权利要求7所述的大功率LED芯片的制造方法，其特征在于，所述多个沟槽互不连通，所述多个沟槽的形状为圆形或者矩形。
  9. 如权利要求8所述的大功率LED芯片的制造方法，其特征在于，还包括：在形成所述绝缘层后以及在形成所述阻挡层前，在所述绝缘层上形成P互连层和N互连层，其中，所述P互连层与所述第一反射镜连接，所述N互连层与所述第二反射镜连接；并且在形成所述P电极和N电极后，所述P电极与所述P互连层连接，N电极与N互连层连接。
  10. 如权利要求9所述的大功率LED芯片的制造方法，其特征在于，形成所述P互连层和N互连层包括：
    在所述绝缘层上形成图形化的光刻胶，所述图形化的光刻胶位于待形成的P互连层和N互连层之间；
    以所述图像化的光刻胶为掩膜，刻蚀所述绝缘层，暴露出所述第一反射镜和第二反射镜；
    沉积互连金属层，所述互连金属层位于所述第一反射镜、第二反射镜和所述图形化的光刻胶上；
    剥离所述图形化的光刻胶及位于所述图形化的光刻胶上的互连金属层，剩余的与所述第一反射镜连接的部分互连金属层构成P互连层，与所述第二反射镜连接的部分互连金属层构成N互连层。
  11. 如权利要求7所述的大功率LED芯片的制造方法，其特征在于，所述键合层为绝缘胶键合层。
  12. 如权利要求7所述的大功率LED芯片的制造方法，其特征在于，所述键合层为金属键合层。
  13. 如权利要求12所述的大功率LED芯片的制造方法，其特征在于，所述金属键合层的材料包括金、锡、铟、金铟合金、金锡合金、镍锡合金中的一种或多种。
  14. 如权利要求12所述的大功率LED芯片的制造方法，其特征在于，还包括：在所述阻挡层和所述金属键合层之间形成绝缘材料层。
  15. 如权利要求11或14所述的大功率LED芯片的制造方法，其特征在于，所述键合衬底的热导率大于等于100W/(m·K)。
  16. 如权利要求12所述的大功率LED芯片的制造方法，其特征在于，所述键合衬底包括两个或者两个以上的子层，并且其中一个子层为绝缘材料层。
  17. 如权利要求7所述的大功率LED芯片的制造方法，其特征在于，所述键合衬底的材料包括硅、陶瓷、氮化铝、铜、钨、钼中的一种或多种。
  18. 一种大功率LED芯片，其特征在于，包括：
    键合衬底；
    依次位于所述键合衬底上的键合层和阻挡层；
    位于所述阻挡层上的第一反射镜和第二反射镜；
    依次位于所述第一反射镜上的P型氮化镓层、量子阱层和表面经 过粗化处理的N型氮化镓层，所述第二反射镜穿过所述P型氮化镓层和量子阱层与所述N型氮化镓层相连接，所述第二反射镜与所述P型氮化镓层、量子阱层和第一反射镜之间由绝缘层隔离；
    穿过所述P型氮化镓层、量子阱层和N型氮化镓层的P电极，所述P电极电连接第一反射镜，穿过所述N型氮化镓层N电极，所述N电极电连接所述第二反射镜的连接端。
  19. 如权利要求18所述的大功率LED芯片，其特征在于，所述第一反射镜的数量为多个，且互不相连，所述多个第一反射镜的形状为圆形或者矩形。
  20. 如权利要求19所述的大功率LED芯片，其特征在于，还包括位于所述阻挡层上的P互连层和N互连层，所述P电极通过所述P互连层与所述第一反射镜电连接，所述N电极通过所述N互连层与所述第二反射镜电连接。
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