WO2016169162A1 - 一种制作阵列基板的方法及其阵列基板和显示装置 - Google Patents

一种制作阵列基板的方法及其阵列基板和显示装置 Download PDF

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WO2016169162A1
WO2016169162A1 PCT/CN2015/087208 CN2015087208W WO2016169162A1 WO 2016169162 A1 WO2016169162 A1 WO 2016169162A1 CN 2015087208 W CN2015087208 W CN 2015087208W WO 2016169162 A1 WO2016169162 A1 WO 2016169162A1
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layer
thin film
film layer
array substrate
metal
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PCT/CN2015/087208
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French (fr)
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刘圣烈
崔承镇
宋泳锡
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京东方科技集团股份有限公司
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Priority to US15/022,288 priority Critical patent/US9905434B2/en
Publication of WO2016169162A1 publication Critical patent/WO2016169162A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display, and in particular, to a method for fabricating an array substrate, an array substrate fabricated using the method for fabricating the array substrate, and a display device including the array substrate.
  • an electrode such as a gate, a source, a drain
  • an electrode lead such as a gate line or a data line
  • a low-resistance metal such as Cu
  • the present invention provides a method of fabricating an array substrate, an array substrate fabricated using the method of fabricating the array substrate, and a display device including the array substrate, which can solve or at least alleviate at least a portion of the prior art. defect.
  • a method of fabricating an array substrate comprising the steps of: forming a metal thin film layer as a source drain and a data line; forming an amorphous semiconductor film on the metal thin film layer a layer; annealing to convert at least a portion of the amorphous semiconductor film layer into a metal semiconductor compound.
  • the formed metal semiconductor compound can prevent oxidation of the surface of the metal thin film layer such as the low-resistance metal Cu layer in a subsequent process. corrosion.
  • the method of fabricating the array substrate of the present invention makes it possible to prevent oxidation of the surface of the Cu at the source and the drain in the manufacturing process using an oxide thin film transistor such as a low-resistance metal Cu, and to manufacture, for example, indium gallium zinc oxide InGaZnO (IGZO), oxidation.
  • IGZO indium gallium zinc oxide
  • a metal oxide thin film transistor such as indium tin zinc InSnZnO (ITZO) or nitrogen-doped zinc oxide ZnON.
  • the method of fabricating the array substrate may further include the following a step of: forming a photoresist layer, removing the photoresist outside the source drain and the data line region by exposure and development; and dry etching the metal semiconductor compound outside the source drain and the data line region; The metal thin film layer outside the source drain and data line regions is wet etched away; then the remaining photoresist is removed.
  • the method of fabricating the array substrate may further include the steps of: forming a gate and a gate line on the substrate, overlying the metal thin film layer as the source drain and the data line, overlying a gate insulating layer on the gate and gate lines, and an active layer on the gate insulating layer corresponding to the gate region.
  • the method of fabricating the array substrate may further include the steps of: forming a passivation layer, and etching the passivation layer at a position corresponding to the drain, the gate line, and the data line to form a corresponding Through hole.
  • the method of fabricating the array substrate may further include the step of forming a gate insulating layer via hole corresponding to the gate line position on the gate insulating layer.
  • the method of fabricating the array substrate may further include the steps of: forming a transparent conductive film, forming a pixel electrode, a gate line connection on the passivation layer formed with the via hole by a patterning process a pattern of a line and a data line connection line, wherein the metal semiconductor compound on the drain is electrically connected to the pixel electrode through a via formed by the position of the corresponding drain.
  • the metal thin film layer may comprise a copper layer or a titanium layer.
  • the amorphous semiconductor thin film layer may include ⁇ -silicon, ⁇ -germanium, ⁇ -GaAs, ⁇ -arsenic sulfide or ⁇ -selenium layer.
  • the metal semiconductor compound comprises copper silicide, copper telluride, copper and alpha-arsenide compound, copper and alpha-arsenic sulfide compound, copper and alpha-selenium.
  • the metal thin film layer comprises a copper layer.
  • the amorphous semiconductor thin film layer includes an ⁇ -silicon layer.
  • the metal semiconductor compound comprises a silicide of copper.
  • the annealing temperature is between 200 °C and 280 °C.
  • the active layer is a metal oxide layer.
  • the metal oxide layer may comprise an InGaZnO, InSnZnO or ZnON semiconductor layer.
  • an array substrate produced by the above method of fabricating an array substrate is provided.
  • the array substrate fabricated by the method for fabricating the array substrate described above By using the array substrate fabricated by the method for fabricating the array substrate described above, at least a portion of the amorphous semiconductor thin film layer is converted into a metal semiconductor compound, and the formed metal semiconductor compound can prevent the surface of the metal thin film layer such as the low-resistance metal Cu layer from being in a subsequent process. Oxidation corrosion.
  • the array substrate produced by the method for fabricating the array substrate described above can prevent oxidation of the surface of the low-resistance metal Cu at the source and the drain in the manufacturing process of the metal oxide thin film transistor using the low-resistance metal Cu, and can also produce, for example, indium oxide.
  • a metal oxide thin film transistor such as gallium zinc InGaZnO (IGZO), indium tin zinc oxide InSnZnO (ITZO), or nitrogen-doped zinc oxide ZnON.
  • a display device comprising the above array substrate.
  • FIG. 1 schematically illustrates one of the steps of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • FIG. 2 schematically illustrates one of the steps of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • FIG. 3 schematically illustrates one of the steps of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • FIG. 4 schematically illustrates one of the steps of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • FIG. 5 schematically illustrates one of the steps of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • FIG. 6 is a view schematically showing a method of fabricating an array substrate according to an embodiment of the present invention. One of the steps.
  • FIG. 7 schematically illustrates one of the steps of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • FIG. 8 schematically illustrates one of the steps of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • Figure 9 is a schematic illustration of one of the steps of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • FIG. 10 schematically illustrates one of the steps of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • Figure 11 is a schematic illustration of one of the steps of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • forming shall include broadly understood, and may be carried out, for example, by chemical vapor deposition, molecular beam epitaxy, or the like, which is conventionally used in the art. Since there are many ways to form a film, there is a relatively more suitable forming process for different materials, so the process of forming each film is not specifically pointed out here, because these methods are not the invention of the present invention. .
  • step 1 schematically illustrates step 1 of a method of fabricating an array substrate in which a gate electrode 14 and a gate line 16 are first formed on a substrate 12 such as a silicon substrate, in accordance with one embodiment of the present invention.
  • the gate lines 16 are used to connect the gates 14 of the respective transistors in a subsequent process. That is, the gate electrode 14 and the gate line 16 are formed on the substrate 12 before the metal thin film layer as the source drain and the data line is formed.
  • the metal thin film layer as the source drain and the data line it will be described in detail later.
  • a gate insulating layer 18 is formed on the gate electrode 14, the gate line 16, and the remaining portion of the substrate 12 not covered by the gate electrode 14 and the gate line 16, that is, overlying the gate is formed.
  • the gate insulating layer 18 on the gate 14 and the gate line 16.
  • an active layer 20 is formed on the gate insulating layer 18, that is, an active layer 20 covering the region of the gate electrode 14 overlying the gate insulating layer 18 is formed.
  • the active layer 20 may be a metal oxide layer such as indium gallium zinc oxide InGaZnO (IGZO), indium tin zinc tin oxide InSnZnO (ITZO), or nitrogen-doped zinc oxide ZnON, or amorphous silicon ( ⁇ -silicon) semiconductor Floor.
  • IGZO indium gallium zinc oxide InGaZnO
  • ITZO indium tin zinc tin oxide
  • ZnON nitrogen-doped zinc oxide ZnON
  • ⁇ -silicon amorphous silicon
  • a metal thin film layer 22 as a source drain and a data line may be formed on the active layer 20 and the gate insulating layer 18 not covered by the active layer 20, as shown in FIG.
  • the metal thin film layer 22 may be a copper layer or a titanium layer.
  • the amorphous semiconductor thin film layer 24 may be an ⁇ -silicon, ⁇ - ⁇ , ⁇ -GaAs, ⁇ -arsenic sulfide or ⁇ -selenium layer. It is known to those skilled in the art that the term a refers to an amorphous.
  • the thickness of the amorphous semiconductor film layer 24 is
  • the metal semiconductor compound 26 comprises copper silicide, copper telluride, copper and alpha-arsenide compound, copper and alpha-arsenic sulfide compound, copper and alpha-selenium compound, titanium silicide a titanium telluride, a compound of titanium and ⁇ -arsenide, a compound of titanium and ⁇ -arsenic sulfide, a compound of titanium and ⁇ -selenium.
  • the metal thin film layer 22 is in contact with the amorphous semiconductor thin film layer 24, and it is preferable to perform annealing at a temperature between about 200 ° C and 280 ° C.
  • Cu atoms in the metal thin film layer 22 such as the Cu layer will diffuse into the amorphous semiconductor thin film layer 24 such as the ⁇ -silicon layer, so that the Cu atoms are combined with the Si atoms to form a copper silicide, for example.
  • Cu 5 Si There is a strong bonding force between Cu and Si, and the adhesion of Cu 5 Si is so strong that the combination of Cu and oxygen can be prevented, thereby solving the problem of oxidative corrosion of Cu.
  • the annealing step is carried out under a nitrogen atmosphere.
  • the metal thin film layer 22 may also be a titanium Ti layer.
  • Ti atoms in the Ti layer will diffuse into the amorphous semiconductor thin film layer 24 such as the ⁇ -silicon layer during the annealing process.
  • the Ti atoms are combined with Si atoms to form a silicide of titanium, such as titanium silicide TiSi 2 .
  • Ti has a strong bonding force with Si, and TiSi 2 has a strong adhesion, so that the combination of Ti and oxygen can be prevented, thereby solving the problem of oxidative corrosion of Ti.
  • the annealing step is carried out under a nitrogen atmosphere.
  • the metal thin film layer 22 may be a copper layer or a titanium layer
  • the amorphous semiconductor thin film layer 24 may be ⁇ -silicon, ⁇ - ⁇ , ⁇ -GaAs, ⁇ -arsenic sulfide or ⁇ -selenium layer.
  • the metal semiconductor compound 26 formed after the corresponding annealing may be copper silicide, copper telluride, copper and alpha-arsenide compound, copper and alpha-arsenic sulfide compound, copper and alpha-selenium compound, titanium a silicide, a titanium telluride, a compound of titanium and alpha-arsenide, a compound of titanium and alpha-arsenic sulfide, or a compound of titanium and alpha-selenium, as already mentioned above, this technology People are not difficult to understand.
  • a photoresist layer is formed, and the photoresist outside the source drain and data line regions is removed by exposure, development, as shown in FIG.
  • a photoresist 28a corresponding to the source, corresponding to the photoresist 28b on the drain, corresponding to Photoresist 28c in the data line region is removed by exposure, development, as shown in FIG.
  • the metal semiconductor compound 26 outside the source drain and data line regions is dry etched away, as shown in FIG.
  • the metal semiconductor compound 26 formed by annealing is a silicide of copper such as Cu 5 Si.
  • the copper silicide such as Cu 5 Si has strong resistance to an etchant, and has a strong bonding force between Cu and Si, and is unlikely to cause oxidation of Cu.
  • the source thin film and the metal thin film layer 22 other than the data line region are wet-etched, as shown in FIG.
  • the source 22a, the drain 22b, and the data line 22c formed of the metal thin film layer 22 are formed, and are respectively formed at the source. 22a, the drain 22b, the gate metal semiconductor compound layer 26a, the drain metal semiconductor compound layer 26b, and the metal semiconductor compound layer of the data line region above the data line 22c and the source 22a, the drain 22b, and the data line 22c, respectively 26c.
  • the remaining photoresist is removed, as shown in FIG. 9, in which the metal semiconductor compound layer 26c located in the gate metal semiconductor compound layer 26a, the drain metal semiconductor compound layer 26b, and the data line region, respectively, is removed.
  • the photoresist 28a, the photoresist 28b, and the photoresist 28c expose the gate metal semiconductor compound layer 26a, the drain metal semiconductor compound layer 26b, and the metal semiconductor compound layer 26c in the data line region.
  • the passivation layer 30 is formed, and the passivation layer 30 is etched at a position corresponding to the drain, the gate line, and the data line to form corresponding via holes, for example, corresponding to the drain, the gate line, and the data line, respectively. Positioned through holes 32a, 32b, 32c. As shown in Figure 10.
  • a gate insulating layer via is formed on the gate insulating layer 18 corresponding to the gate line position. As in the drawing shown in FIG. 10, it can be seen that the gate line 16 is directly exposed by the through hole 32b formed at the gate line position penetrating the passivation layer 30 and the gate insulating layer 18.
  • a transparent conductive film is formed, which is formed on the passivation layer on which the via holes are formed by a patterning process.
  • the method of fabricating an array substrate of the present invention by converting at least a portion of the amorphous semiconductor thin film layer into a metal semiconductor compound, the formed metal semiconductor compound can prevent oxidative corrosion of a metal thin film layer such as a Cu or Ti layer in a subsequent process.
  • the method of fabricating the array substrate of the present invention makes it possible to prevent oxidation of Cu or Ti at the source and drain and to manufacture a metal oxide thin film transistor in the manufacturing process of an oxide thin film transistor using Cu or Ti.
  • the method of fabricating an array substrate of the present invention is employed, this problem can be easily solved while at the same time contributing to the fabrication of a back channel etched oxide thin film transistor structure using Cu or Ti.
  • an array substrate produced by the above method of fabricating an array substrate is provided.
  • the array substrate fabricated by the method for fabricating the array substrate described above at least a portion of the amorphous semiconductor thin film layer is converted into a metal semiconductor compound, and the formed metal semiconductor compound can prevent the surface of the metal thin film layer such as the low-resistance metal Cu or Ti layer from being subsequently Oxidation corrosion in the process.
  • the array substrate of the present invention is employed, this problem can be easily solved while at the same time contributing to the fabrication of a metal oxide thin film transistor structure using Cu or Ti.
  • a display device comprising the above array substrate.

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Abstract

一种制作阵列基板的方法及其阵列基板和显示装置，其中制作阵列基板的方法可以包括：形成作为源漏极（22a，22b）和数据线（22c）的金属薄膜层（22）；在所述金属薄膜层（22）上形成非晶半导体薄膜层（24）；退火，以便将至少部分所述非晶半导体薄膜层转换成金属半导体化合物（26）。通过将至少部分所述非晶半导体薄膜层（24）转换成金属半导体化合物（26），形成的金属半导体化合物可以防止金属薄膜层例如低电阻金属Cu或Ti层在后续工艺中的氧化腐蚀，有助于制造使用Cu或Ti的金属氧化物薄膜晶体管结构。

Description

一种制作阵列基板的方法及其阵列基板和显示装置 技术领域
本发明涉及显示领域，特别涉及一种制作阵列基板的方法、使用该制作阵列基板的方法制作的阵列基板、和包括该阵列基板的显示装置。
背景技术
在现有的制作用于显示装置的薄膜晶体管的过程中，其中的电极(如栅极、源极、漏极)或电极引线(如栅线、数据线)通常需要使用低电阻金属(如Cu等)。但在使用这种金属的情况下，存在金属表面因氧化腐蚀而在诸多工序中受到制约的问题。换句话说，由于金属表面出现氧化腐蚀现象，而在诸多工序中限制了该金属的使用。
因此，在现有技术中迫切需要一种新的技术，来防止在制作包括薄膜晶体管的显示装置的过程中出现的金属电极表面氧化腐蚀。
发明内容
有鉴于此，本发明提供一种制作阵列基板的方法、使用该制作阵列基板的方法制作的阵列基板、和包括该阵列基板的显示装置，其能够解决或者至少缓解现有技术中存在的至少一部分缺陷。
根据本发明的第一个方面，提供一种制作阵列基板的方法，该方法可以包括下面的步骤：形成作为源漏极和数据线的金属薄膜层；在该金属薄膜层上形成非晶半导体薄膜层；退火，以便将至少部分该非晶半导体薄膜层转换成金属半导体化合物。
借助于本发明的制作阵列基板的方法，通过将至少部分该非晶半导体薄膜层转换成金属半导体化合物，形成的金属半导体化合物可以防止金属薄膜层例如低电阻金属Cu层表面在后续工艺中的氧化腐蚀。本发明的制作阵列基板的方法使得在使用例如低电阻金属Cu的氧化物薄膜晶体管的制造工序中既可以防止源漏处Cu表面的氧化，又可以制造例如氧化铟镓锌InGaZnO(IGZO)、氧化铟锡锌InSnZnO(ITZO)、氮掺杂的氧化锌ZnON等的金属氧化物薄膜晶体管。
在本发明的一个实施例中，制作阵列基板的方法还可以包括下面 的步骤：形成光刻胶层，通过曝光、显影将源漏极和数据线区域之外的光刻胶去除；将该源漏极和数据线区域之外的金属半导体化合物干法刻蚀去除；将该源漏极和数据线区域之外的金属薄膜层湿法刻蚀去除；然后将剩余的光刻胶去除。
在本发明的另一个实施例中，制作阵列基板的方法还可以包括下面的步骤：在形成作为源漏极和数据线的金属薄膜层之前，在衬底上形成栅极和栅线、覆盖在该栅极和栅线上的栅绝缘层、以及覆盖在该栅绝缘层上的对应于该栅极区域的有源层。
在本发明的再一个实施例中，制作阵列基板的方法还可以包括下面的步骤：形成钝化层，并且在与漏极、栅线和数据线对应的位置刻蚀该钝化层以形成对应的通孔。
在本发明的又一个实施例中，制作阵列基板的方法还可以包括下面的步骤：在该栅绝缘层上对应该栅线位置，形成栅绝缘层过孔。
在本发明的再一个实施例中，制作阵列基板的方法还可以包括下面的步骤：形成透明导电薄膜，通过构图工艺，在该形成有通孔的钝化层上形成包括像素电极、栅线连接线以及数据线连接线的图形，其中该漏极上的金属半导体化合物通过该对应漏极的位置形成的通孔与该像素电极电连接。
在本发明的一个实施例中，其中该金属薄膜层可以包括铜层或钛层。
在本发明的另一个实施例中，其中该非晶半导体薄膜层可以包括α-硅、α-锗、α-砷化镓、α-硫化砷或α-硒层。
在本发明的再一个实施例中，其中该金属半导体化合物包括铜的硅化物、铜的锗化物、铜与α-砷化镓的化合物、铜与α-硫化砷的化合物、铜与α-硒的化合物、钛的硅化物、钛的锗化物、钛与α-砷化镓的化合物、钛与α-硫化砷的化合物、钛与α-硒的化合物。可选的，其中该金属薄膜层包括铜层。
在本发明的又一个实施例中，其中该非晶半导体薄膜层包括α-硅层。
在本发明的一个实施例中，其中该金属半导体化合物包括铜的硅化物。
在本发明的另一个实施例中，其中该非晶半导体薄膜层的厚度为
Figure PCTCN2015087208-appb-000001
在本发明的再一个实施例中，其中该退火温度在200℃-280℃之间。
在本发明的又一个实施例中，其中该退火步骤是在氮气气氛下进行的。
在本发明的一个实施例中，其中该有源层为金属氧化物层。可选的，该金属氧化物层可以包括InGaZnO、InSnZnO或ZnON半导体层。
根据本发明的第二个方面，提供一种使用上述的制作阵列基板的方法制作的阵列基板。
通过使用上述的制作阵列基板的方法制作的阵列基板，将至少部分该非晶半导体薄膜层转换成金属半导体化合物，形成的金属半导体化合物可以防止金属薄膜层例如低电阻金属Cu层表面在后续工艺中的氧化腐蚀。使用上述的制作阵列基板的方法制作的阵列基板，使得在使用低电阻金属Cu的金属氧化物薄膜晶体管的制造工序中既可以防止源漏处低电阻金属Cu表面的氧化，又可以制造例如氧化铟镓锌InGaZnO(IGZO)、氧化铟锡锌InSnZnO(ITZO)、氮掺杂的氧化锌ZnON等的金属氧化物薄膜晶体管。
根据本发明的第三个方面，提供一种显示装置，包括上述的阵列基板。
附图说明
图1示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图2示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图3示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图4示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图5示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图6示意性示出了根据本发明一个实施例的制作阵列基板的方法 的其中一个步骤。
图7示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图8示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图9示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图10示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图11示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
附图标记说明
12-衬底；14-栅极；16-栅线；18-栅绝缘层；20-有源层；22-金属薄膜层；24-非晶半导体薄膜层；26-金属半导体化合物层；28a-对应于源极上的光刻胶；28b-对应于漏极上的光刻胶；28c-对应于数据线区域的光刻胶；22a-源极；22b-漏极；22c-数据线；26a-栅极金属半导体化合物层；26b-漏极金属半导体化合物层；26c-数据线区域的金属半导体化合物层；30-钝化层；32a-位于漏极对应位置的通孔；32b-位于栅线对应位置的通孔；32c-位于数据线对应位置的通孔；30-平坦化的钝化层；34-像素电极；36-栅线连接线；38-数据线连接线。
具体实施方式
下面结合本发明的附图1-11详细地描述本发明的各个实施例。
在本发明中提到的术语“形成”，应当包括广义地理解，例如可以采用化学气相沉积、分子束外延等本领域常用的方式进行。由于这些形成薄膜的方式有很多种，针对于不同的材料，有相对更加适合的形成工艺，因此在这里不再具体指出形成每种薄膜的工艺方法，因为这些方法并不是本发明的发明点所在。
图1示意性示出了根据本发明一个实施例的制作阵列基板的方法的步骤1，在例如硅衬底的衬底12上首先形成栅极14、栅线16。栅线16在后续的工艺中用于连接各个晶体管的栅极14。即，在形成作为源漏极和数据线的金属薄膜层之前，在衬底12上形成栅极14和栅线16。 至于作为源漏极和数据线的金属薄膜层，后面还将详细描述。
接着，如在图2中示出的，在栅极14、栅线16和未被栅极14、栅线16覆盖的衬底12的其余部分上形成栅绝缘层18，即形成了覆盖在栅极14和栅线16上的栅绝缘层18。在对应于栅极14区域的上方，在栅绝缘层18上形成有源层20，即形成了覆盖在栅绝缘层18上的对应于栅极14区域的有源层20。有源层20可以为金属氧化物层，例如氧化铟镓锌InGaZnO(IGZO)、氧化铟锡锌InSnZnO(ITZO)、或氮掺杂的氧化锌ZnON、或者非晶硅(α-硅)等半导体层。
然后，可以在有源层20和未被有源层20覆盖的栅绝缘层18上形成作为源漏极和数据线的金属薄膜层22，如在图3中示出的。金属薄膜层22可以是铜层或钛层。
接着，在该金属薄膜层22上形成非晶半导体薄膜层24，如在图4中示出的。非晶半导体薄膜层24可以是α-硅、α-锗、α-砷化镓、α-硫化砷或α-硒层。本领域技术人员知晓的是，术语α指的是非晶态(amorphous)。优选的，非晶半导体薄膜层24的厚度为
Figure PCTCN2015087208-appb-000002
然后进行退火，以便将至少部分该非晶半导体薄膜层24转换成金属半导体化合物26，如在图5中示出的。优选的，该金属半导体化合物26包括铜的硅化物、铜的锗化物、铜与α-砷化镓的化合物、铜与α-硫化砷的化合物、铜与α-硒的化合物、钛的硅化物、钛的锗化物、钛与α-砷化镓的化合物、钛与α-硫化砷的化合物、钛与α-硒的化合物。在这个工序中，金属薄膜层22是与非晶半导体薄膜层24相接触的，优选的是在大约200℃-280℃之间的温度下进行退火。在上述温度的退火过程中，金属薄膜层22例如Cu层中的Cu原子将会扩散到非晶半导体薄膜层24例如α-硅层中，使得Cu原子与Si原子结合形成铜的硅化物，例如Cu5Si。Cu与Si之间具有较强的结合力，Cu5Si的粘合性很强，以致能够防止Cu与氧的结合，从而能够解决Cu的氧化腐蚀问题。为了形成更厚一些的铜的硅化物，例如Cu5Si，优选的，退火步骤是在氮气气氛下进行。
需要指出的是，金属薄膜层22也可以是钛Ti层，在这样的情况下，在退火过程中，Ti层中的Ti原子将会扩散到非晶半导体薄膜层24例如α-硅层中，使得Ti原子与Si原子结合形成钛的硅化物，例如硅化钛TiSi2。同样，Ti与Si之间具有较强的结合力，TiSi2的粘合性很强， 以致能够防止Ti与氧的结合，从而能够解决Ti的氧化腐蚀问题。为了形成更厚一些的钛的硅化物，例如TiSi2，优选的，退火步骤是在氮气气氛下进行。
还需要指出的是，由于金属薄膜层22可以是铜层或钛层，非晶半导体薄膜层24可以是α-硅、α-锗、α-砷化镓、α-硫化砷或α-硒层，相应退火后形成的金属半导体化合物26可以是铜的硅化物、铜的锗化物、铜与α-砷化镓的化合物、铜与α-硫化砷的化合物、铜与α-硒的化合物、钛的硅化物、钛的锗化物、钛与α-砷化镓的化合物、钛与α-硫化砷的化合物、或者钛与α-硒的化合物，如在上面已经提到的，这一点本领域技术人员是不难理解的。
备选的，形成光刻胶层，通过曝光、显影将源漏极和数据线区域之外的光刻胶去除，如在图6中示出的。在图6中，在将源漏极和数据线区域之外的光刻胶去除之后，剩下了对应于源极上的光刻胶28a、对应于漏极上的光刻胶28b、对应于数据线区域的光刻胶28c。
然后，将该源漏极和数据线区域之外的金属半导体化合物26干法刻蚀去除，如在图7中示出的。如在上面提到的，在例如金属薄膜层22是铜层，非晶半导体薄膜层24是α-硅层的情况下，退火形成的金属半导体化合物26是铜的硅化物，例如Cu5Si。该铜的硅化物例如Cu5Si对刻蚀剂的抗耐性强，Cu与Si之间具有较强的结合力，不易发生Cu的氧化现象。
接着，将该源漏极和数据线区域之外的金属薄膜层22例如Cu层湿法刻蚀去除，如在图8中示出的。在图8中，去除了该源漏极和数据线区域之外的金属薄膜层22之后，形成由金属薄膜层22形成的源极22a、漏极22b、数据线22c，并且形成分别位于源极22a、漏极22b、数据线22c上方且分别与源极22a、漏极22b、数据线22c接触的栅极金属半导体化合物层26a、漏极金属半导体化合物层26b、数据线区域的金属半导体化合物层26c。
然后将剩余的光刻胶去除，如在图9中示出了，其中去除了分别位于栅极金属半导体化合物层26a、漏极金属半导体化合物层26b、数据线区域的金属半导体化合物层26c上方的光刻胶28a、光刻胶28b、光刻胶28c，暴露了栅极金属半导体化合物层26a、漏极金属半导体化合物层26b、数据线区域的金属半导体化合物层26c。
备选的，形成钝化层30，并且在与漏极、栅线和数据线对应的位置刻蚀该钝化层30以形成对应的通孔，例如分别位于漏极、栅线和数据线对应位置的通孔32a、32b、32c。如在图10中示出的。在本发明的一个实施例中，在栅绝缘层18上对应栅线位置，形成栅绝缘层过孔。如在图10所示的附图中，可以看到对应于在栅线位置形成的通孔32b贯穿了钝化层30和栅绝缘层18，直接将栅线16暴露。
在将钝化层30平坦化之后，即钝化层30变成了平坦化的钝化层30′之后，形成透明导电薄膜，通过构图工艺，在该形成有通孔的钝化层上形成包括像素电极34、栅线连接线36以及数据线连接线38的图形，其中该漏极上的金属半导体化合物层26b通过该对应漏极的位置形成的通孔与该像素电极34电连接。
借助于本发明的制作阵列基板的方法，通过将至少部分该非晶半导体薄膜层转换成金属半导体化合物，形成的金属半导体化合物可以防止金属薄膜层例如Cu或Ti层在后续工艺中的氧化腐蚀。本发明的制作阵列基板的方法使得在使用Cu或Ti的氧化物薄膜晶体管的制造工序中既可以防止源漏处Cu或Ti的氧化，又可以制造金属氧化物薄膜晶体管。在现有技术中无论是在薄膜晶体管源漏处Cu或Ti的氧化问题带来的热处理工序，还是等离子体处理工序均有其局限性。然而如果采用本发明的制作阵列基板的方法，则既可以轻易解决这个问题，同时又可以有助于制造使用Cu或Ti的背沟道刻蚀氧化物薄膜晶体管结构。
根据本发明的第二个方面，提供一种使用上述的制作阵列基板的方法制作的阵列基板。
通过使用上述的制作阵列基板的方法制作的阵列基板，将至少部分该非晶半导体薄膜层转换成金属半导体化合物，形成的金属半导体化合物可以防止金属薄膜层例如低电阻金属Cu或Ti层表面在后续工艺中的氧化腐蚀。然而如果采用本发明的阵列基板，则既可以轻易解决这个问题，同时又可以有助于制造使用Cu或Ti的金属氧化物薄膜晶体管结构。
根据本发明的第三个方面，提供一种显示装置，其包括上述的阵列基板。
虽然已经参考目前考虑到的实施例描述了本发明，但是应该理解 本发明不限于所公开的实施例。相反，本发明旨在涵盖所附权利要求的精神和范围之内所包括的各种修改和等同布置。以下权利要求的范围符合最广泛解释，以便包含每个这样的修改及等同结构和功能。

Claims (19)

  1. 一种制作阵列基板的方法，包括：
    形成作为源漏极和数据线的金属薄膜层；
    在所述金属薄膜层上形成非晶半导体薄膜层；
    退火，以便将至少部分所述非晶半导体薄膜层转换成金属半导体化合物。
  2. 根据权利要求1所述的方法，还包括：
    形成光刻胶层，通过曝光、显影将源漏极和数据线区域之外的光刻胶去除；将所述源漏极和数据线区域之外的金属半导体化合物干法刻蚀去除；将所述源漏极和数据线区域之外的金属薄膜层湿法刻蚀去除；然后将剩余的光刻胶去除。
  3. 根据权利要求2所述的方法，还包括：
    在形成作为源漏极和数据线的金属薄膜层之前，在衬底上形成栅极和栅线、覆盖在所述栅极和栅线上的栅绝缘层、以及覆盖在所述栅绝缘层上的对应于所述栅极区域的有源层。
  4. 根据权利要求3所述的方法，还包括：
    形成钝化层，并且在与漏极、栅线和数据线对应的位置刻蚀所述钝化层以形成对应的通孔。
  5. 根据权利要求4所述的方法，还包括：
    在所述栅绝缘层上对应所述栅线位置，形成栅绝缘层过孔。
  6. 根据权利要求5所述的方法，还包括：
    形成透明导电薄膜，通过构图工艺，在所述形成有通孔的钝化层上形成包括像素电极、栅线连接线以及数据线连接线的图形，其中所述漏极上的金属半导体化合物通过所述对应漏极的位置形成的通孔与所述像素电极电连接。
  7. 根据权利要求1-6中任一项所述的方法，其中所述金属薄膜层包括铜层或钛层。
  8. 根据权利要求1-6中任一项所述的方法，其中所述非晶半导体薄膜层包括α-硅、α-锗、α-砷化镓、α-硫化砷或α-硒层。
  9. 根据权利要求1-6中任一项所述的方法，其中所述金属半导体化合物包括铜的硅化物、铜的锗化物、铜与α-砷化镓的化合物、铜与 α-硫化砷的化合物、铜与α-硒的化合物、钛的硅化物、钛的锗化物、钛与α-砷化镓的化合物、钛与α-硫化砷的化合物、钛与α-硒的化合物。
  10. 根据权利要求7所述的方法，其中所述金属薄膜层包括铜层。
  11. 根据权利要求8所述的方法，其中所述非晶半导体薄膜层包括α-硅层。
  12. 根据权利要求9所述的方法，其中所述金属半导体化合物包括铜的硅化物。
  13. 根据权利要求1-6中任一项所述的方法，其中所述非晶半导体薄膜层的厚度为
    Figure PCTCN2015087208-appb-100001
  14. 根据权利要求1-6中任一项所述的方法，其中所述退火温度在200℃-280℃之间。
  15. 根据权利要求1-6中任一项所述的方法，其中所述退火步骤是在氮气气氛下进行的。
  16. 根据权利要求2-6中任一项所述的方法，其中所述有源层为金属氧化物层。
  17. 根据权利要求16所述的方法，其中所述金属氧化物层包括InGaZnO、InSnZnO或ZnON半导体层。
  18. 使用根据权利要求1-17中任一项所述的制作阵列基板的方法制作的阵列基板。
  19. 一种显示装置，包括根据权利要求18所述的阵列基板。
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