WO2016165361A1 - 集成传感器的封装结构和封装方法 - Google Patents

集成传感器的封装结构和封装方法 Download PDF

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WO2016165361A1
WO2016165361A1 PCT/CN2015/096911 CN2015096911W WO2016165361A1 WO 2016165361 A1 WO2016165361 A1 WO 2016165361A1 CN 2015096911 W CN2015096911 W CN 2015096911W WO 2016165361 A1 WO2016165361 A1 WO 2016165361A1
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Prior art keywords
sensor
substrate
asic chip
chip
asic
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English (en)
French (fr)
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端木鲁玉
张俊德
宋青林
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Goertek Inc
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Goertek Inc
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Priority to US15/559,780 priority Critical patent/US10177055B2/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60Seals
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems ; Auxiliary parts of microstructural devices or systems
    • B81B7/0032Packages or encapsulation
    • B81B7/0064Packages or encapsulation for protecting against electromagnetic or electrostatic interferences
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems ; Auxiliary parts of microstructural devices or systems
    • B81B7/02Microstructural systems ; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00Arrangements for protection of devices
    • H10W42/20Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00Arrangements for protection of devices
    • H10W42/20Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/281Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their materials
    • H10W42/284Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their materials shielding resins
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00Specific applications of microelectromechanical systems
    • B81B2201/02Sensors
    • B81B2201/0257Microphones or microspeakers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00Specific applications of microelectromechanical systems
    • B81B2201/02Sensors
    • B81B2201/0264Pressure sensors
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00Microstructural systems or auxiliary parts thereof
    • B81B2207/01Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
    • B81B2207/012Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being separate parts in the same package
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/01Packaging MEMS
    • B81C2203/0109Bonding an individual cap on the substrate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the invention relates to a package structure of an integrated sensor and a packaging method of an integrated sensor.
  • the integrated sensor is a sensor chip that integrates multiple sensor units (such as an integrated sensor integrated by a pressure sensor unit and a temperature sensor unit) and is used as a stand-alone chip capable of simultaneously implementing multiple sensing functions.
  • the package of the integrated sensor is generally mounted on the substrate with the MEMS sensor chip and the ASIC chip of each sensor unit, and finally packaged in a cavity for integration, for example, as shown in FIG. 1 and FIG. 2: the outer cover 2 covers the first substrate 1 is surrounded by a large cavity, and two sensor units mounted on the first substrate 1 are disposed in the cavity.
  • One of the sensor units includes a MEMS sensor chip 3 and an ASIC chip 5, which are electrically connected by a lead 4, and the AISC chip 5 is connected to the first substrate 1 by wires.
  • the other sensor unit includes a MEMS sensor chip 8 and an ASIC chip 7, which are also electrically connected by wires, and the AISC chip 7 is connected to the first substrate 1 by wires.
  • the outer casing 2 is provided with an opening 6 required for sensor unit sensing, and the back surface of the first substrate 1 is provided with a pad 9, and the sensor unit is electrically connected to an external circuit through the pad 9.
  • the existing integrated sensor is packaged in a cavity in which all sensor units of the integrated sensor are packaged.
  • other sensor units may cause electrical, magnetic, thermal, and optical interference. , seriously affecting the performance of the sensor unit and the overall performance of the integrated sensor.
  • a package structure of an integrated sensor comprising: a first substrate and a first outer casing, the first outer casing and the first substrate enclosing a first package cavity; a plurality of sensors disposed in the first package cavity, each of the sensors including a MEMS sensor And an ASIC chip electrically connected to the MEMS sensor chip; inside the first package cavity, at least one of the ASIC chips of the sensor is provided with a shielding structure.
  • the shielding structure comprises an insulating glue covering the electrical connection portion of the ASIC chip and a conductive adhesive shielding cover completely covering the ASIC chip.
  • the ASIC chip provided with the shielding structure is electrically connected at its bottom to the circuit on the first substrate, and is electrically connected to its corresponding MEMS sensor chip and external circuit through the circuits on the first substrate, respectively.
  • the shielding structure comprises a second outer casing disposed outside the ASIC chip, and the second outer casing and the first substrate enclose a second packaging cavity to encapsulate the ASIC chip in the second packaging cavity. Inside the body.
  • the shielding structure is provided outside the ASIC chip of the sensitive sensor of the plurality of sensors, or the shielding structure is provided outside the ASIC chip of the sensor of the interference source.
  • the plurality of sensors comprise a pressure sensor, a microphone, and a humidity sensor; wherein an outer surface of the ASIC chip of the microphone and the ASIC chip of the humidity sensor are respectively provided with the shielding structure or the pressure sensor
  • the shield structure is provided outside the ASIC chip.
  • the senor is disposed directly on the first substrate or on the first substrate through a second substrate.
  • a method for packaging an integrated sensor comprising the steps of: S1, providing a plurality of sensors and a substrate, each of the sensors comprising a MEMS sensor chip and an ASIC chip; S2, to be shielded ASIC chip and its corresponding MEMS sensor chip are mounted on the substrate and complete corresponding electrical connection; S3, the electrical connection portion of the ASIC chip to be shielded is wrapped with insulating glue, and then completely covered with conductive adhesive from above The ASIC chip to be shielded; or, enclosing the second package cavity with the second housing and the substrate to encapsulate the ASIC chip to be shielded inside the second package cavity; S4, Other sensors are mounted on the substrate and complete corresponding electrical connections; S5, using the first housing and the housing The substrate encloses the first package cavity to encapsulate all of the sensors.
  • the step S4 is located before the step S2 or before the step S3.
  • the ASIC chip to be shielded is electrically connected to the circuit on the substrate at the bottom thereof, and electrically connected to the corresponding MEMS sensor chip and the external circuit through the circuit on the substrate.
  • the invention provides a shield structure outside the ASIC chip which is easily interfered in the integrated sensor, and isolates the package from other sensor units, thereby avoiding interference of other sensor units in the integrated sensor, thereby effectively improving the performance of the sensor unit. And the overall performance of the integrated sensor.
  • 1 and 2 are schematic structural views of a conventional integrated sensor package structure.
  • 3 and 4 are schematic structural views of a first embodiment of a package structure of the integrated sensor of the present invention.
  • FIG. 5 is a schematic structural view of a second embodiment of a package structure of the integrated sensor of the present invention.
  • FIG. 6 is a schematic structural view of a third embodiment of a package structure of an integrated sensor of the present invention.
  • FIG. 7 is a schematic flow chart of a packaging method of the integrated sensor of the present invention.
  • the integrated sensor includes multiple sensor units, some of which are relatively more sensitive, ie more susceptible to interference from other sensor units in the integrated sensor. These sensor units that are susceptible to interference from other sensor units are “sensitive sensors”. A sensor unit that interferes with sensitive sensors is a “sensor that is an interference source”.
  • the present invention can provide a shielding structure for the ASIC chips of these sensitive sensors, and can also provide a shielding structure for the ASIC chips of the sensors that are interference sources. For example, in an integrated sensor including a pressure sensor, a microphone, and a humidity sensor, the pressure sensor releases electromagnetic signals and heat energy as a source of interference, and the ASIC chip of the microphone is easily interfered by the electromagnetic signal emitted by the pressure sensor.
  • the ASIC of the humidity sensor may be easily interfered by the thermal energy released by the pressure sensor, so the present invention may separately provide a shielding structure outside the ASIC chip of the microphone and the ASIC chip of the humidity sensor; or, in another embodiment, may also be an interference source.
  • the external structure of the ASIC chip of the pressure sensor is provided with a shielding structure, so that the technical effect of shielding the pressure sensor from interference with other sensors can also be achieved. Based on the disclosure of the present invention, those skilled in the art can determine other sensitive ASIC chips that need to be shielded according to actual application products and environments, and these should also fall within the protection scope of the present invention.
  • a first embodiment of an integrated sensor package structure includes a first substrate 1 and a first housing 2, and the first housing 2 and the first substrate 1 enclose a first package cavity.
  • the first sensor unit includes a MEMS sensor chip 3 and an ASIC chip 5, and the AISC chip 5 is electrically connected to a circuit on the first substrate 1 at the bottom of the AISC chip 5 by soldering or metal wire bonding, and the MEMS sensor chip 3 is also passed through the lead 4 Connected to the circuit on the first substrate 1, so that the ASIC chip 5 can be electrically connected to the corresponding MEMS sensor chip 3 and the external circuit through the circuits on the first substrate 1, respectively. Such a connection is advantageous for the subsequent pair of ASIC chips 5. Perform shielding processing.
  • the shielding of the ASIC chip 5 is realized by the insulating glue 11 and the conductive adhesive shield 10, and only the insulating adhesive 11 is injected at the bottom of the ASIC chip 5 to wrap the electrical connection portion of the ASIC chip 5, and then the conductive material is injected from above.
  • the conductive adhesive shield 10 of the shield ASIC chip 5 can be formed by completely covering the ASIC chip 5 with the glue.
  • the first housing 2 is provided with an opening 6 required for sensor unit sensing, and the back surface of the first substrate 1 is provided with pads 9, and the two sensor units are electrically connected to an external circuit through the pads 9.
  • a second embodiment of the integrated sensor package structure is different from the first embodiment shown in FIG. 3 in that shielding of the ASIC chip 5 is achieved by the second housing 14, and the second housing 14 is implemented. And encapsulating the first substrate 1 as a second package cavity to isolate the ASIC chip 5 from inside the second package cavity.
  • a third embodiment of the integrated sensor package structure is different from the first embodiment shown in FIG. 3 in that the second sensor unit is not disposed directly on the first substrate 1 but through the second
  • the substrate 15 is indirectly disposed on the first substrate 1.
  • the sensor unit is mounted on the second substrate 15 and electrically connected to the external circuit through the pads 9 on the back surface of the first substrate 1.
  • external stress is transmitted to the first substrate 1 and then buffered by the second substrate 15, which protects the sensor unit and makes the sensor unit more stable.
  • the second substrate 15 is designed as a buffer portion, which avoids the influence of external stress on the pressure sensor and causes pressure sensor data error, thereby improving the sensitivity of the pressure sensor unit.
  • first outer casing 2 and the second outer casing 14 may be a metal outer casing or an outer casing composed of a substrate.
  • each chip needs to be separately mounted and electrically connected, the process is low in efficiency, the hidden dangers are sharply increased, and the assembled safety space needs to be left between the chips, thereby wasting the overall space of the product.
  • the invention can also integrate the sensor unit to reduce space waste, optimize the processing procedure, and improve packaging efficiency and product yield.
  • the present invention provides the following three integration methods: 1. Integrating a MEMS sensor chip and an ASIC chip of one sensor unit. 2. Integrate the ASIC chips of the sensor units that do not interfere with each other. 3. Integrate the MEMS sensor chips of the sensor units that do not interfere with each other.
  • FIG. 7 is a schematic flow chart of a method for packaging an integrated sensor according to the present invention, including the following steps:
  • each of the sensors comprising a MEMS sensor chip and an ASIC chip;
  • the step S4 may also be before step S2 or before step S3.
  • step S2 the ASIC chip to be shielded is electrically connected to the circuit on the substrate at the bottom thereof, and electrically connected to the corresponding MEMS sensor chip and the external circuit through the circuits on the substrate.
  • the sensor may be directly disposed on the first substrate or disposed on the first substrate through the second substrate.
  • first outer casing and the second outer casing may be a metal outer casing or an outer casing composed of a substrate.
  • the invention provides a shield structure outside the ASIC chip which is easily interfered in the integrated sensor, and isolates the package from other sensor units, thereby avoiding interference of other sensor units in the integrated sensor, thereby effectively improving the performance of the sensor unit. And the overall performance of the integrated sensor.
  • the shield of the shield ASIC chip can be formed by the conductive paste, which is easy to implement in the process and has a good shielding effect.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Pressure Sensors (AREA)
  • Micromachines (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)

Abstract

一种集成传感器的封装结构和封装方法。封装结构包括:第一基板(1)和第一外壳(2),第一外壳与第一基板围成第一封装腔体;设置在第一封装腔体内的多个传感器,每个传感器均包括MEMS传感器芯片(3,8)和与MEMS传感器芯片电连接的ASIC芯片(5,7);在第一封装腔体的内部,至少一个传感器的ASIC芯片的外部设有屏蔽结构。通过对集成传感器中的容易受到干扰的ASIC芯片的外部设置屏蔽结构,使其与其它传感器单元隔离封装,避免集成传感器中的其它传感器单元对其影响干扰,有效提升了该传感器单元的性能和集成传感器的整体性能。

Description

集成传感器的封装结构和封装方法 技术领域
本发明涉及一种集成传感器的封装结构和一种集成传感器的封装方法。
背景技术
集成传感器是一种内部集成了多个传感器单元的传感器芯片(例如由压力传感器单元和温度传感器单元集成的集成传感器),并且作为一个能够同时实现多种传感功能的独立的芯片进行使用。目前集成传感器的封装一般是将其各个传感器单元的MEMS传感器芯片和ASIC芯片贴装于基板上,最终封装在一个腔体内进行集成,例如图1和图2所示:外壳2覆盖在第一基板1上围成一个大的腔体,腔体内设置有贴装在第一基板1上的两个传感器单元。其中一个传感器单元包括MEMS传感器芯片3和ASIC芯片5,两者之间通过引线4电连接,AISC芯片5通过引线连接至第一基板1。另一个传感器单元包括MEMS传感器芯片8和ASIC芯片7,两者之间同样通过引线电连接,AISC芯片7通过引线连接至第一基板1。外壳2设有传感器单元传感所需的开口6,第一基板1的背面设有焊盘9,传感器单元通过焊盘9与外部电路电连接。
现有集成传感器的这种封装方式是将集成传感器的全部传感器单元封装在一个腔体内,对于其中某些容易受到干扰的ASIC芯片,其它传感器单元会对其造成电、磁、热、光的干扰,严重影响该传感器单元的性能和集成传感器的整体性能。
发明内容
本发明的目的是提供一种在集成传感器中屏蔽某些ASIC芯片以防止其受到其它传感器单元的干扰的新的技术方案。
根据本发明的第一方面,提出了一种集成传感器的封装结构,包括: 第一基板和第一外壳,所述第一外壳与所述第一基板围成第一封装腔体;设置在所述第一封装腔体内的多个传感器,每个所述传感器均包括MEMS传感器芯片和与所述MEMS传感器芯片电连接的ASIC芯片;在所述第一封装腔体的内部,至少一个所述传感器的ASIC芯片的外部设有屏蔽结构。
优选的,所述屏蔽结构包括包裹ASIC芯片电连接部分的绝缘胶和完全覆盖ASIC芯片的导电胶屏蔽罩。
优选的,设有屏蔽结构的ASIC芯片在其底部与所述第一基板上的电路电连接,并且通过所述第一基板上的电路分别与其对应的MEMS传感器芯片和外部电路电连接。
优选的,所述屏蔽结构包括设置于ASIC芯片外部的第二外壳,所述第二外壳和所述第一基板围成第二封装腔体以将ASIC芯片隔离的封装在所述第二封装腔体内部。
优选的,多个所述传感器中的敏感传感器的ASIC芯片的外部设有所述屏蔽结构,或者为干扰源的传感器的ASIC芯片的外部设有所述屏蔽结构。
优选的,多个所述传感器包括压力传感器、麦克风、以及湿度传感器;其中,所述麦克风的ASIC芯片和所述湿度传感器的ASIC芯片的外部分别设有所述屏蔽结构,或者所述压力传感器的ASIC芯片的外部设有所述屏蔽结构。
优选的,所述传感器直接设置于所述第一基板上或者通过第二基板设置于所述第一基板上。
根据本发明的第二方面,提出了一种集成传感器的封装方法,包括以下步骤:S1、提供多个传感器和基板,每个所述传感器均包括MEMS传感器芯片和ASIC芯片;S2、将待屏蔽的ASIC芯片和其对应的MEMS传感器芯片贴装在所述基板上并且完成相应的电连接;S3、用绝缘胶包裹所述待屏蔽的ASIC芯片的电连接部分,然后用导电胶从上方完全覆盖所述待屏蔽的ASIC芯片;或者,用第二外壳和所述基板围成第二封装腔体以将所述待屏蔽的ASIC芯片隔离的封装在所述第二封装腔体内部;S4、将其它传感器贴装在所述基板上并且完成相应的电连接;S5、用第一外壳和所 述基板围成第一封装腔体将全部传感器封装在内。
可选的,所述步骤S4位于所述步骤S2之前或位于所述步骤S3之前。
优选的,在所述步骤S2中,令所述待屏蔽的ASIC芯片在其底部与基板上的电路电连接,并且通过所述基板上的电路分别与其对应的MEMS传感器芯片和外部电路电连接。
本发明通过对集成传感器中的容易受到干扰的ASIC芯片的外部设置屏蔽结构,使其与其它传感器单元隔离封装,避免集成传感器中的其它传感器单元对其影响干扰,有效提升了该传感器单元的性能和集成传感器的整体性能。
附图说明
被结合在说明书中并构成说明书的一部分的附图示出了本发明的实施例,并且连同其说明一起用于解释本发明的原理。
图1、2是现有集成传感器封装结构的结构示意图。
图3、4是本发明集成传感器的封装结构的第一实施例的结构示意图。
图5是本发明集成传感器的封装结构的第二实施例的结构示意图。
图6是本发明集成传感器的封装结构的第三实施例的结构示意图。
图7是本发明集成传感器的封装方法的流程示意图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到:除非另外具体说明,否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的,决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论,但在适当情况下,所述技术、方法和设备应当被视为说明书的一部分。
在这里示出和讨论的所有例子中,任何具体值应被解释为仅仅是示例性的,而不是作为限制。因此,示例性实施例的其它例子可以具有不同的 值。
应注意到:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步讨论。
集成传感器中包括多个传感器单元,其中某些传感器单元相对更为敏感,即更容易受到集成传感器中的其它传感器单元的干扰,这些容易受到其它传感器单元干扰的传感器单元为“敏感传感器”,会对敏感传感器造成干扰的传感器单元为“为干扰源的传感器”。本发明可以对这些敏感传感器的ASIC芯片设置屏蔽结构,也可以对为干扰源的传感器的ASIC芯片设置屏蔽结构。例如在一个包括压力传感器、麦克风、以及湿度传感器的集成传感器中,压力传感器会释放电磁信号和热能成为干扰源,麦克风的ASIC芯片会容易被压力传感器释放出的电磁信号所干扰,湿度传感器的ASIC芯片会容易被压力传感器释放出的热能所干扰,所以本发明会分别在麦克风的ASIC芯片和湿度传感器的ASIC芯片的外部设置屏蔽结构;或者,在另一实施例中也可以在为干扰源的压力传感器的ASIC芯片的外部设置屏蔽结构,这样也能够达到屏蔽压力传感器对其它传感器的干扰的技术效果。在本发明公开的基础上,本领域技术人员可以根据实际应用产品和环境确定其它敏感的需要屏蔽的ASIC芯片,这些也应当属于本发明的保护范围内。
参考图3和图4所示为集成传感器封装结构的第一实施例,包括:第一基板1和第一外壳2,第一外壳2与第一基板1围成第一封装腔体。设置在第一封装腔体内的两个传感器单元,第二传感器单元包括MEMS传感器芯片8和ASIC芯片7,两者之间通过一引线电连接,AISC芯片7同样通过一引线连接至第一基板1。第一传感器单元包括MEMS传感器芯片3和ASIC芯片5,AISC芯片5通过焊接或者金属打线等方式在AISC芯片5的底部与第一基板1上的电路电连接,MEMS传感器芯片3通过引线4同样连接至第一基板1上的电路,这样ASIC芯片5就可以分别通过第一基板1上的电路分别与其对应的MEMS传感器芯片3以及外部电路电连接,这样的连接方式有利于后续对ASIC芯片5进行屏蔽处理。在第一实施例 中,对于ASIC芯片5的屏蔽是通过绝缘胶11和导电胶屏蔽罩10实现,只需要先在ASIC芯片5的底部的注入绝缘胶11以包裹ASIC芯片5的电连接部分,再从上方注入导电胶完全覆盖ASIC芯片5就可以形成屏蔽ASIC芯片5的导电胶屏蔽罩10。第一外壳2设有传感器单元传感所需的开口6,第一基板1的背面设有焊盘9,两个传感器单元通过焊盘9与外部电路电连接。
参考图5所示为集成传感器封装结构的第二实施例,和图3所示的第一实施例的不同之处在于,对于ASIC芯片5的屏蔽是通过第二外壳14实现,第二外壳14和第一基板1围成第二封装腔体以将ASIC芯片5隔离的封装在第二封装腔体内部。
参考图6所示为集成传感器封装结构的第三实施例,和图3所示的第一实施例的不同之处在于,第二传感器单元不是直接设置于第一基板1上而是通过第二基板15间接设置于第一基板1上,该传感器单元贴装于第二基板15上,通过第一基板1背面的焊盘9与外部电路电连接。在该传感器单元的装配、工作过程中,外部应力传递至第一基板1然后由第二基板15缓冲卸掉,保护了该传感器单元,使该传感器单元性能更稳定。特别对于压力传感器单元,第二基板15作为缓冲部的结构设计,避免了外部应力对压力传感器产生影响而导致压力传感器数据误差,提高了压力传感器单元的灵敏度。
其中,第一外壳2和第二外壳14可以为金属外壳或者由基板组成的外壳。
上述实施例中,各个芯片需要单独贴装和电连接,工序多效率低,不良隐患剧增,并且各个芯片之间需要留出组装安全空间,浪费产品总体空间。为了能够更好的实现腔体的分立,本发明还可以将传感器单元进行集成设计,以减少空间浪费,优化加工工序,提升封装效率和产品良率。本发明提供了以下三种集成方式:1.将一个传感器单元的MEMS传感器芯片和ASIC芯片集成在一起。2.将互不干扰的传感器单元的ASIC芯片集成在一起。3.将互不干扰的传感器单元的MEMS传感器芯片集成在一起。
图7是本发明集成传感器的封装方法的流程示意图,包括以下步骤:
S1、提供多个传感器和基板,每个传感器均包括MEMS传感器芯片和ASIC芯片;
S2、将待屏蔽的ASIC芯片和其对应的MEMS传感器芯片贴装在基板上并且完成相应的电连接;
S3、用绝缘胶包裹待屏蔽的ASIC芯片的电连接部分,然后用导电胶从上方完全覆盖待屏蔽的ASIC芯片;或者,用第二外壳和基板围成第二封装腔体以将待屏蔽的ASIC芯片隔离的封装在第二封装腔体内部。
S4、将其它传感器贴装在基板上并且完成相应的电连接;
S5、用第一外壳和基板围成第一封装腔体将全部传感器封装在内。
其中,步骤S4还可以位于步骤S2之前或位于步骤S3之前。
其中,在步骤S2中,令待屏蔽的ASIC芯片在其底部与基板上的电路电连接,并且通过基板上的电路分别与其对应的MEMS传感器芯片和外部电路电连接。
其中,传感器可以直接设置于第一基板上或者通过第二基板设置于第一基板上。
其中,第一外壳和第二外壳可以为金属外壳或者由基板组成的外壳。
本发明通过对集成传感器中的容易受到干扰的ASIC芯片的外部设置屏蔽结构,使其与其它传感器单元隔离封装,避免集成传感器中的其它传感器单元对其影响干扰,有效提升了该传感器单元的性能和集成传感器的整体性能。特别是可以通过导电胶形成屏蔽ASIC芯片的屏蔽罩,工艺上容易实施并且屏蔽效果好。
虽然已经通过例子对本发明的一些特定实施例进行了详细说明,但是本领域的技术人员应该理解,以上例子仅是为了进行说明,而不是为了限制本发明的范围。本领域的技术人员应该理解,可在不脱离本发明的范围和精神的情况下,对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (10)

  1. 一种集成传感器的封装结构,其特征在于,包括:
    第一基板和第一外壳,所述第一外壳与所述第一基板围成第一封装腔体;
    设置在所述第一封装腔体内的多个传感器,每个所述传感器均包括MEMS传感器芯片和与所述MEMS传感器芯片电连接的ASIC芯片;
    在所述第一封装腔体的内部,至少一个所述传感器的ASIC芯片的外部设有屏蔽结构。
  2. 根据权利要求1所述的结构,其特征在于,所述屏蔽结构包括包裹ASIC芯片电连接部分的绝缘胶和完全覆盖ASIC芯片的导电胶屏蔽罩。
  3. 根据权利要求2所述的结构,其特征在于,设有屏蔽结构的ASIC芯片在其底部与所述第一基板上的电路电连接,并且通过所述第一基板上的电路分别与其对应的MEMS传感器芯片和外部电路电连接。
  4. 根据权利要求1所述的结构,其特征在于,所述屏蔽结构包括设置于ASIC芯片外部的第二外壳,所述第二外壳和所述第一基板围成第二封装腔体以将ASIC芯片隔离的封装在所述第二封装腔体内部。
  5. 根据权利要求1-4任一项所述的结构,其特征在于,多个所述传感器中的敏感传感器的ASIC芯片的外部设有所述屏蔽结构,或者为干扰源的传感器的ASIC芯片的外部设有所述屏蔽结构。
  6. 根据权利要求1-4任一项所述的结构,其特征在于,多个所述传感器包括压力传感器、麦克风、以及湿度传感器;其中,所述麦克风的ASIC芯片和所述湿度传感器的ASIC芯片的外部分别设有所述屏蔽结构,或者所述压力传感器的ASIC芯片的外部设有所述屏蔽结构。
  7. 根据权利要求1-4任一项所述的结构,其特征在于,所述传感器直接设置于所述第一基板上或者通过第二基板设置于所述第一基板上。
  8. 一种集成传感器的封装方法,其特征在于,包括以下步骤:
    S1、提供多个传感器和基板,每个所述传感器均包括MEMS传感器芯片和ASIC芯片;
    S2、将待屏蔽的ASIC芯片和其对应的MEMS传感器芯片贴装在所述基板上并且完成相应的电连接;
    S3、用绝缘胶包裹所述待屏蔽的ASIC芯片的电连接部分,然后用导电胶从上方完全覆盖所述待屏蔽的ASIC芯片;或者,用第二外壳和所述基板围成第二封装腔体以将所述待屏蔽的ASIC芯片隔离的封装在所述第二封装腔体内部;
    S4、将其它传感器贴装在所述基板上并且完成相应的电连接;
    S5、用第一外壳和所述基板围成第一封装腔体将全部传感器封装在内。
  9. 根据权利要求8所述的方法,其特征在于:所述步骤S4位于所述步骤S2之前或位于所述步骤S3之前。
  10. 根据权利要求8或9所述的方法,其特征在于,在所述步骤S2中,令所述待屏蔽的ASIC芯片在其底部与基板上的电路电连接,并且通过所述基板上的电路分别与其对应的MEMS传感器芯片和外部电路电连接。
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