WO2016155429A1 - 显示基板及其制造方法、显示装置 - Google Patents

显示基板及其制造方法、显示装置 Download PDF

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Publication number
WO2016155429A1
WO2016155429A1 PCT/CN2016/074125 CN2016074125W WO2016155429A1 WO 2016155429 A1 WO2016155429 A1 WO 2016155429A1 CN 2016074125 W CN2016074125 W CN 2016074125W WO 2016155429 A1 WO2016155429 A1 WO 2016155429A1
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Prior art keywords
substrate
drain
top surface
pad
vertical distance
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Ceased
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PCT/CN2016/074125
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English (en)
French (fr)
Inventor
冯博
苗青
马禹
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/514,328 priority Critical patent/US10256260B2/en
Publication of WO2016155429A1 publication Critical patent/WO2016155429A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to a display substrate, a method for manufacturing the same, and a display device.
  • the liquid crystal display device includes an array substrate. As shown in FIG. 1, each pixel in the array substrate includes a thin film transistor 2' and a plate-shaped pixel electrode 3' which are sequentially disposed on the base substrate 1'; the thin film transistor 2' includes a gate electrode 21' and a gate insulating layer. 22', active layer 23' and source 24' and drain 25' in the same layer, wherein the gate insulating layer 22' extends to the region where the pixel electrode 3' is located; the pixel electrode 3' is formed at the gate insulating The layer 22' is over and extends from the gate insulating layer 22' to the top surface of the drain 25' to overlap the drain 25'.
  • the array substrate In the manufacturing process of the array substrate, in order to reduce the number of masks, the array substrate is usually exposed by a gray scale mask.
  • the drain region of the drain 25' and the active layer 23' corresponds to a completely opaque region of the grayscale reticle such that the outer edge of the drain 25' is aligned with the edge of the active layer 23'.
  • the drop between the drain 25' and the gate insulating layer 22' is equal to the sum of the thickness of the drain 25' and the thickness of the active layer 23', typically, the drain 25'
  • the thickness is 0.4 ⁇ m
  • the thickness of the active layer 23' is 0.25 ⁇ m
  • the drop is 0.65 ⁇ m, which is large with respect to the thickness of 0.05 ⁇ m of the pixel electrode 3', resulting in the pixel electrode 3' being insulated by the gate.
  • the layer 22' climbs to the top surface of the drain 25' when it breaks, thereby affecting the display effect of the display device.
  • a display substrate includes a base substrate and a thin film transistor formed on the base substrate, the thin film transistor including a drain, and an outer side of the drain is provided with at least one pad a high structure; a vertical distance between a top surface of each of the pad structure and the substrate substrate is less than a vertical distance between a top surface of the drain and the substrate, and greater than a substrate A vertical distance between the top surface of the high structure side away from the drain and the substrate substrate.
  • a display device comprising the display substrate as described above.
  • a method of manufacturing a display substrate comprising: forming a thin film transistor and at least one pad structure on a base substrate; wherein the pad structure is located in the thin film transistor The outer side of the drain; the vertical distance between the top surface of the pad structure and the substrate is less than the vertical distance between the top surface of the drain and the substrate, and is larger than the substrate a vertical distance between a top surface of the side of the pad structure that is away from the drain and the substrate.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a schematic structural diagram of a first display substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a second display substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a third display substrate according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a fourth display substrate according to an embodiment of the present invention.
  • the display substrate includes a base substrate 1 and a thin film transistor 2 formed on the base substrate 1.
  • the thin film transistor 2 includes a drain 21 and an outer side of the drain 21.
  • a pad structure 3 is provided; a vertical distance H between the top surface of the pad structure 3 and the substrate 1 is smaller than a vertical distance H d between the top surface of the drain 21 and the substrate 1 and greater than the vertical distance H 0 between the top surface of the base substrate 1 side of the substrate is positioned away from the drain 21 of the padding layer 3.
  • substrate herein includes a substrate substrate and a functional layer disposed on the substrate substrate, such as gate insulating layer 22. In contrast, the term “substrate substrate” does not include functional layers thereon.
  • the pad structure 6 is disposed, for example, on the base substrate 1.
  • the display substrate in the embodiment of the present invention may be an array substrate of a liquid crystal display device, and may of course be another display substrate having a thin film transistor.
  • the drain of the thin film transistor on the display substrate is connected to the pixel electrode to realize a display function.
  • the pixel electrode since at least one pad structure is disposed on the outer side of the drain, when the pixel electrode is subsequently formed, the pixel electrode firstly has a substrate top surface with a minimum vertical distance from the substrate substrate. Climping to the top surface of the padding structure centered at a vertical distance from the substrate substrate, and then climbing to the top surface of the drain having the largest vertical distance from the substrate substrate, so that the pixel electrode is gradually climbed at least twice Up to the top surface of the drain, the height of each climb is small, thereby avoiding the phenomenon that the pixel electrode has a large climb height at a time in the prior art, thereby avoiding the problem that the pixel electrode is broken when climbing to the top surface of the drain.
  • the display substrate includes a plurality of padding structures.
  • the display substrate is described in detail by taking two pad structures 31 and 32 as an example. As shown in FIG. 2 and FIG. 3, the pad is raised away from the drain 21. Structure 3 in turn includes a first padding structure 31 and a second padding structure 32.
  • the vertical distance H 2 between the top surface of the second pad structure 32 and the base substrate 1 is smaller than the vertical distance H 1 between the top surface of the first pad structure 31 and the substrate substrate 1 , thereby making the drain
  • the vertical distance between the top surface of 21, the top surface of the first pad structure 31, the top surface of the second pad structure 32, and the top surface of the substrate away from the drain 21 is sequentially decreased from the substrate substrate 1, That is, H d >H 1 >H 2 >H 0 , thereby further avoiding the problem that the pixel electrode is broken during the climbing process.
  • the above two pad-high structures 31, 32 are formed by different functional layers formed on the base substrate 1.
  • the at least one padding structure includes the spacer 4 to form a padding structure having a different vertical distance between the top surface and the substrate substrate 1.
  • the embodiments of the present invention also provide the following two examples of the padding structure, the difference being that the first padding structure 31 includes the pad 4:
  • the first type of padding structure is as shown in FIG. 2.
  • the pad 4 includes a first pad 41 and a second pad 42 connected to each other;
  • the thin film transistor 2 includes a gate insulating layer 22 sequentially formed on the base substrate 1.
  • Active a layer 23, a source 24 and a drain 21 in the same layer;
  • the first pad structure 31 includes a first pad 41, a gate insulating layer 22 and an active layer 23 at a position where the first pad structure 31 is located;
  • the two pad high structure 32 includes a second pad 42 and a gate insulating layer 22 at a location where the second padding structure 32 is located.
  • the second pad structure is as shown in FIG. 3.
  • the thin film transistor 2 includes a gate insulating layer 22 sequentially formed on the base substrate 1, an active layer 23, a source electrode 24 and a drain electrode 21 located in the same layer;
  • the padding structure 31 includes a gate insulating layer 22 and an active layer 23 at a position where the first padding structure 31 is located;
  • the second padding structure 32 includes a pad 4 and a gate insulating layer at a position where the second padding structure 32 is located Layer 22.
  • the first padding structure 31 does not include the spacer 4.
  • the spacer 4 may be located over the gate insulating layer 22.
  • the spacer 4 is located between the gate insulating layer 22 and the base substrate 1.
  • the thin film transistor 2 further includes a gate 25 between the gate insulating layer 22 and the substrate 1 , the spacer 4 and the gate 25 are in the same layer, and the material of the spacer 4 and the gate 25 The materials are the same, so that the spacer 4 and the gate electrode 25 are simultaneously formed by one patterning process, thereby simplifying the manufacturing method of the display substrate.
  • the thickness of the spacer 4 is less than or equal to the thickness of the gate 25.
  • the mask used in the patterning process may be a normal mask, and the gray scale mask is not required, thereby reducing the manufacturing difficulty of the display substrate.
  • the thickness of the spacer 4 may be adjusted according to actual needs, so that the top surface of the drain 21, the top surface of the first pad structure 31, and the second pad structure 32 The vertical distance between the top surface and the top surface of the second pad structure 32 away from the drain 21 and the substrate substrate 1 are sequentially reduced by a magnitude close to or the same, thereby further preventing the pixel electrode from breaking during the climbing process. There was a problem.
  • the thickness of the spacer 4 may also be thick.
  • the thickness of the gate 25 is 0.4 ⁇ m
  • the thickness of the spacer 4 is also 0.4 ⁇ m
  • the thickness of the gate insulating layer 22 is 0.4 ⁇ m
  • the active layer 23 The thickness of the second pad structure 32 is 0.25 ⁇ m
  • the vertical distance between the top surface of the second pad structure 32 and the substrate 1 is 0.8 ⁇ m
  • the vertical distance between the top surface of the first pad structure 31 and the substrate 1 is 0.65 ⁇ m
  • the thickness of the spacer 4 is smaller than the thickness of the active layer 23 such that the vertical distance between the top surface of the second pad structure 32 and the substrate 1 is smaller than the top surface of the first pad structure 31 and the substrate. The vertical distance between the substrates 1.
  • the embodiment of the invention further provides a display device comprising the above display substrate.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display substrate can avoid the problem that the pixel electrode in the display device climbs to the top surface of the drain
  • the display device including the display substrate can also prevent the pixel electrode from climbing to the drain in the display device.
  • the problem of cracking occurs at the top surface of the pole.
  • the embodiment of the present invention further provides a method for manufacturing the above display substrate, comprising: forming a thin film transistor 2 and at least one pad structure 3 on the base substrate 1; wherein the pad structure 3 is located in the thin film transistor 2
  • the outer side of the drain 21; the vertical distance between the top surface of the pad structure 3 and the substrate 1 is smaller than the vertical distance H d between the top surface of the drain 21 and the substrate 1 and larger than the substrate
  • the vertical distance H 0 between the top surface of the side of the high structure 3 remote from the drain 21 and the base substrate 1.
  • a thin film transistor is formed on the substrate, and at least one pad structure is formed on the outer side of the drain, so that when the pixel electrode is subsequently formed, the pixel electrode is first and the substrate
  • the top surface of the substrate having the smallest vertical distance between the substrates climbs to the top surface of the padding structure centered at a vertical distance from the substrate substrate, and then climbs to the top of the drain having the largest vertical distance from the substrate substrate.
  • the surface is such that the pixel electrode is gradually climbed to the top surface of the drain at least twice, and the height of each climb is small, thereby avoiding a large increase in the height of the pixel electrode in the prior art, thereby preventing the pixel electrode from climbing to The problem of cracking occurs when the top surface of the drain is used.
  • the embodiment of the present invention describes the manufacturing process of the display substrate by taking the display substrate including the first pad structure 31 and the second pad structure 32 as an example.
  • the thin film transistor 2 and the at least one pad structure 3 are formed on the base substrate 1, and include:
  • a gate metal layer is formed on the base substrate 1, and a pattern including the gate electrode 25 and the spacer 4 is formed by one patterning process.
  • the spacer 4 may be located only at the position of the second padding structure 32, or the pad 4 may include the first pad 41 and the second pad 42 connected to each other, wherein the first pad 41 is located at the first pad height
  • the structure of the structure 31 is located, and the second spacer 42 is located at the position of the second pad structure 32.
  • the patterning process described in all the embodiments of the present invention includes: coating a photoresist, masking with a mask, exposing, developing, etching, and finally stripping the photoresist.
  • the thickness of the spacer 4 is less than or equal to the thickness of the gate 25.
  • the structure in which the thickness of the spacer 4 is smaller than the thickness of the gate electrode 25 it is necessary to expose the substrate 1 by using a gray scale mask, and the position of the corresponding gate 25 on the gray scale mask is completely opaque, corresponding to The position of the spacer 4 is a semi-transmissive region, and the other portions are completely transparent regions. After exposure and development, the photoresist in the completely transparent region is removed, and the photoresist in the semi-transmissive region is semi-retained, completely impenetrable.
  • the photoresist in the optical region is completely preserved, and after a single etching, the gate metal layer covered by the photoresist is completely removed, and then the ashing process is performed to remove the semi-retained photoresist, and then the newly exposed gate is removed.
  • the metal layer is etched, and by controlling etching conditions, such as etching time, to etch away a portion of the thickness of the gate metal layer, thereby forming a spacer 4 including the gate electrode 25 and a thickness smaller than the thickness of the gate electrode 25.
  • a gate insulating layer 22 is formed on the base substrate 1 on which the gate electrode 25 and the spacer 4 are formed, thereby forming the second padding structure 32.
  • the second pad structure 32 includes a pad 4 and a gate insulating layer 22 at a location where the second pad structure 32 is located.
  • a gray scale mask a gray scale mask
  • a gray scale mask a gray scale mask
  • the position corresponding to the source electrode 24 and the drain electrode 21 is a completely opaque region
  • the position corresponding to the active layer 23 is a semi-transmissive region
  • the other portions are completely transparent regions
  • the fully transparent region is The photoresist is removed, the photoresist in the semi-transmissive region is semi-retained, and the photoresist in the completely opaque region is completely retained.
  • the source/drain metal layer and the active layer material layer which are not covered by the photoresist are completely removed, and then the ashing process is performed to remove the semi-retained photoresist, and then the newly exposed source and drain metal are removed.
  • the layer is etched, and finally the photoresist is stripped to form a pattern including the active layer 23, the source electrode 24, and the drain electrode 21.
  • the completely opaque region of the gray scale mask simultaneously corresponds to the drain regions of the drain 21 and the active layer 23 such that the outer edge of the drain 21 is aligned with the edge of the active layer 23, but after exposure
  • the source/drain metal layer on the outer side of the drain 21 is first etched away, and then the active layer material layer on the outer side of the drain 21 is also etched away to etch the active layer material layer.
  • the drain 21 is also etched away, so that the drain 21 is retracted, and the active layer 23 extends beyond the outer edge of the drain 21 to form the first pad structure 31.
  • the first padding structure 31 includes a first pad 41, a gate insulating layer 22, and an active layer 23 at a location where the first padding structure 31 is located, and the second padding structure 32 includes a second padding structure 32.
  • the second pad 42 and the gate insulating layer 22 at the position form a display substrate as shown in FIG. 2.
  • the first padding structure 31 includes a gate insulating layer 22 and an active layer 23 at a position where the first padding structure 31 is located
  • the second padding structure 32 includes a pad 4 at a position where the second padding structure 32 is located.
  • a display substrate as shown in FIG. 3 or FIG. 4 is formed.
  • the vertical distance between the top surface of the second pad structure 32 and the substrate 1 is smaller than the vertical distance between the top surface of the first pad structure 31 and the substrate 1 to form a space as shown in FIG.
  • the display substrate for example, when the vertical distance between the top surface of the second pad structure 32 and the substrate 1 is greater than the vertical distance between the top surface of the first pad structure 31 and the substrate 1
  • the display substrate is shown.
  • a thin film transistor is formed on the substrate, and at least one pad structure is formed on the outer side of the drain, so that when the pixel electrode is subsequently formed, the pixel electrode is first and the substrate
  • the top surface of the substrate having the smallest vertical distance between the substrates climbs to the top surface of the padding structure centered at a vertical distance from the substrate substrate, and then climbs to the top of the drain having the largest vertical distance from the substrate substrate.
  • the surface is such that the pixel electrode is gradually climbed to the top surface of the drain at least twice, and the height of each climb is small, thereby avoiding a large increase in the height of the pixel electrode in the prior art, thereby preventing the pixel electrode from climbing to The problem of cracking occurs when the top surface of the drain is used.

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  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
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Abstract

提供了一种显示基板。该显示基板包括衬底基板(1)和形成在衬底基板(1)上的薄膜晶体管(2)，薄膜晶体管(2)包括漏极(21)，漏极(21)的外侧设置有至少一个垫高结构(3)；垫高结构(3)的顶部表面与衬底基板(1)之间的垂直距离，小于漏极(21)的顶部表面与衬底基板(1)之间的垂直距离，且大于基板位于垫高结构(3)的远离漏极(21)的一侧的顶部表面与衬底基板(1)之间的垂直距离。该显示基板能够改善像素电极爬升至漏极的顶部表面时产生断裂的问题。还提供了一种显示基板的制造方法及显示装置。

Description

显示基板及其制造方法、显示装置 技术领域
本发明实施例涉及显示技术领域，尤其涉及一种显示基板及其制造方法、显示装置。
背景技术
液晶显示装置包括阵列基板。如图1所示，阵列基板中每个像素包括依次设置在衬底基板1'上的薄膜晶体管2'和板状的像素电极3'；薄膜晶体管2'包括栅极21'、栅极绝缘层22'、有源层23'以及位于同一层的源极24'和漏极25'，其中，栅极绝缘层22'延伸至像素电极3'所在的区域；像素电极3'形成在栅极绝缘层22'上，并由栅极绝缘层22'延伸至漏极25'的顶部表面，从而与漏极25'搭接。
在阵列基板的制造过程中，为了减少掩模的数量，通常利用灰度掩模板对阵列基板进行曝光。漏极25'及有源层23'的漏极区对应灰度掩模板的完全不透光区，使得漏极25'的外侧边缘与有源层23'的边缘对齐。在漏极25'的外侧边缘处，漏极25'与栅极绝缘层22'之间的落差等于漏极25'的厚度与有源层23'的厚度之和，通常，漏极25'的厚度为0.4μm，有源层23'的厚度为0.25μm，因此，该落差为0.65μm，相对于像素电极3'的0.05μm的厚度，该落差较大，导致像素电极3'由栅极绝缘层22'爬升至漏极25'的顶部表面时产生断裂，从而影响了显示装置的显示效果。
发明内容
根据本发明第一方面，提供一种显示基板，该显示基板包括衬底基板和形成在衬底基板上的薄膜晶体管，所述薄膜晶体管包括漏极，所述漏极的外侧设置有至少一个垫高结构；每个所述垫高结构的顶部表面与所述衬底基板之间的垂直距离，小于所述漏极的顶部表面与所述衬底基板之间的垂直距离，且大于基板位于所述垫高结构的远离所述漏极的一侧的顶部表面与所述衬底基板之间的垂直距离。
根据本发明第二方面，还提供了一种显示装置，该显示装置包括如上所述的显示基板。
根据本发明第三方面，还提供了一种显示基板的制造方法，该制造方法包括：在衬底基板上形成薄膜晶体管和至少一个垫高结构；其中，所述垫高结构位于所述薄膜晶体管的漏极的外侧；所述垫高结构的顶部表面与所述衬底基板之间的垂直距离，小于所述漏极的顶部表面与所述衬底基板之间的垂直距离，且大于基板位于所述垫高结构的远离所述漏极的一侧的顶部表面与所述衬底基板之间的垂直距离。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，而非对本发明的限制。
图1为现有技术中的一种阵列基板的结构示意图；
图2为本发明实施例提供的第一种显示基板的结构示意图；
图3为本发明实施例提供的第二种显示基板的结构示意图；
图4为本发明实施例提供的第三种显示基板的结构示意图；
图5为本发明实施例提供的显示基板的制造方法流程图；
图6本发明实施例提供的第四种显示基板的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种显示基板，如图6所示，该显示基板包括衬底基板1和形成在衬底基板1上的薄膜晶体管2，薄膜晶体管2包括漏极21，漏极21的外侧设置有一个垫高结构3；该垫高结构3的顶部表面与衬底基板1之间的垂直距离H，小于漏极21的顶部表面与衬底基板1之间的垂直距离 Hd，且大于基板位于垫高结构3的远离漏极21的一侧的顶部表面与衬底基板1之间的垂直距离H0。本文中术语“基板”包括衬底基板及设置在衬底基板上的功能层，例如栅极绝缘层22。相反，术语“衬底基板”则不包括其上的功能层。如图所示，该垫高结构6例如设置在衬底基板1上。
需要说明的是，本发明实施例中的显示基板可以为液晶显示装置的阵列基板，当然也可以为具有薄膜晶体管的其它显示基板。该显示基板上的薄膜晶体管的漏极与像素电极连接，从而实现显示功能。
本发明实施例提供的显示基板中，由于在漏极的外侧设置有至少一个垫高结构，使得在后续形成像素电极时，像素电极首先由与衬底基板之间的垂直距离最小的基板顶部表面爬升至与衬底基板之间的垂直距离居中的垫高结构的顶部表面，然后再爬升至与衬底基板之间的垂直距离最大的漏极的顶部表面，使得像素电极分至少两次逐步爬升至漏极的顶部表面，每次爬升的高度较小，从而避免出现现有技术中像素电极一次爬升高度较大情况，进而能够避免出现像素电极爬升至漏极的顶部表面时产生断裂的问题。
为了进一步改善像素电极在爬升时产生断裂的问题，在一个实施例中，显示基板包括多个垫高结构。为了便于本领域技术人员理解，本发明实施例以两个垫高结构31、32为例对该显示基板进行详细说明，如图2和图3所示，向远离漏极21的方向，垫高结构3依次包括第一垫高结构31和第二垫高结构32。例如，第二垫高结构32的顶部表面与衬底基板1之间的垂直距离H2小于第一垫高结构31的顶部表面与衬底基板1之间的垂直距离H1，从而使得漏极21的顶部表面、第一垫高结构31的顶部表面、第二垫高结构32的顶部表面和基板的远离漏极21一侧的顶部表面与衬底基板1之间的垂直距离依次减小，即Hd>H1>H2>H0，从而进一步避免像素电极在爬升过程中断裂的问题出现。
上述两个垫高结构31、32由形成在衬底基板1上的不同的功能层来形成。至少一个垫高结构包括垫块4，从而形成顶部表面与衬底基板1之间的垂直距离不同的垫高结构。为了便于本领域技术人员理解，本发明实施例还提供了以下两种垫高结构的示例，二者区别在于第一垫高结构31是否包括垫块4：
第一种垫高结构如图2所示，垫块4包括相互连接的第一垫块41和第二垫块42；薄膜晶体管2包括依次形成在衬底基板1上的栅极绝缘层22、有源 层23、位于同一层的源极24及漏极21；第一垫高结构31包括位于第一垫高结构31所在位置的第一垫块41、栅极绝缘层22和有源层23；第二垫高结构32包括位于第二垫高结构32所在位置的第二垫块42和栅极绝缘层22。
第二种垫高结构如图3所示，薄膜晶体管2包括依次形成在衬底基板1上的栅极绝缘层22、有源层23、位于同一层的源极24及漏极21；第一垫高结构31包括位于第一垫高结构31所在位置的栅极绝缘层22和有源层23；第二垫高结构32包括位于第二垫高结构32所在位置的垫块4和栅极绝缘层22。在此示例中，第一垫高结构31不包括垫块4。
需要说明地是，本领域技术人员在基于上述两种垫高结构的基础上，在不付出创造性劳动的前提下还可以获得其他可能的具体实施方式，本发明实施例不再一一赘述。
在本发明其他实施例中，垫块4可以位于栅极绝缘层22之上。在以上实施例中，垫块4位于栅极绝缘层22与衬底基板1之间。在一个示例中，薄膜晶体管2还包括位于栅极绝缘层22和衬底基板1之间的栅极25，垫块4与栅极25位于同一层，且垫块4的材质与栅极25的材质相同，使得垫块4与栅极25通过一次构图工艺同时形成，从而简化了显示基板的制造方法。
在一个示例中，垫块4的厚度小于等于栅极25的厚度。当垫块4的厚度等于栅极25的厚度时，构图工艺中所应用的掩模板为普通掩模板即可，不需要使用灰阶掩模板，从而降低了显示基板的制造难度。当垫块4的厚度小于栅极25的厚度时，可以根据实际需要调整垫块4的厚度，从而使得漏极21的顶部表面、第一垫高结构31的顶部表面、第二垫高结构32的顶部表面和第二垫高结构32远离漏极21的一侧的顶部表面与衬底基板1之间的垂直距离依次减小的幅度接近或相同，从而进一步避免像素电极在爬升过程中断裂的问题出现。
需要说明的是，如图4所示，在第一垫高结构31包括位于第一垫高结构31所在位置的栅极绝缘层22和有源层23的情况下，当栅极25的厚度较大时，垫块4的厚度也可能较厚，例如，当栅极25的厚度为0.4μm，垫块4的厚度也为0.4μm，栅极绝缘层22的厚度为0.4μm，有源层23的厚度为0.25μm，则第二垫高结构32的顶部表面与衬底基板1之间的垂直距离为0.8μm，第一垫高结构31的顶部表面与衬底基板1之间的垂直距离为0.65μm， 此时，虽然第二垫高结构32的顶部表面与衬底基板1之间的垂直距离大于第一垫高结构31的顶部表面与衬底基板1之间的垂直距离，但是，由于第二垫高结构32的顶部表面与衬底基板1之间的垂直距离仍然小于漏极21的顶部表面与衬底基板1之间的垂直距离，因此，也可以避免像素电极在爬升过程中断裂的问题出现。优选地，垫块4的厚度小于有源层23的厚度，从而使得第二垫高结构32的顶部表面与衬底基板1之间的垂直距离小于第一垫高结构31的顶部表面与衬底基板1之间的垂直距离。
本发明实施例还提供一种显示装置，该显示装置包括上述的显示基板。该显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明实施例中，由于显示基板能够避免显示装置中像素电极爬升至漏极的顶部表面时产生断裂的问题出现，因此，包括该显示基板的显示装置也能够避免显示装置中像素电极爬升至漏极的顶部表面时产生断裂的问题出现。
本发明实施例还提供了一种上述显示基板的制造方法，该制造方法包括：在衬底基板1上形成薄膜晶体管2和至少一个垫高结构3；其中，垫高结构3位于薄膜晶体管2的漏极21的外侧；该垫高结构3的顶部表面与衬底基板1之间的垂直距离，小于漏极21的顶部表面与衬底基板1之间的垂直距离Hd，且大于基板位于垫高结构3的远离漏极21的一侧的顶部表面与衬底基板1之间的垂直距离H0。
本发明实施例提供的显示基板的制造方法中，在衬底基板上形成薄膜晶体管，并在漏极的外侧形成至少一个垫高结构，使得在后续形成像素电极时，像素电极首先由与衬底基板之间的垂直距离最小的基板顶部表面爬升至与衬底基板之间的垂直距离居中的垫高结构的顶部表面，然后再爬升至与衬底基板之间的垂直距离最大的漏极的顶部表面，使得像素电极分至少两次逐步爬升至漏极的顶部表面，每次爬升的高度较小，从而避免出现现有技术中像素电极一次爬升高度较大情况，进而能够避免出现像素电极爬升至漏极的顶部表面时产生断裂的问题。
为了便于本领域技术人员理解，本发明实施例以显示基板包括第一垫高结构31和第二垫高结构32为例对显示基板的制造过程进行详细说明。例如， 如图5所示，在衬底基板1上形成薄膜晶体管2和至少一个垫高结构3，包括：
S1、在衬底基板1上形成栅极金属层，通过一次构图工艺形成包括栅极25和垫块4的图形。
例如，垫块4可以只位于第二垫高结构32所在位置，或者，垫块4包括相互连接的第一垫块41和第二垫块42，其中，第一垫块41位于第一垫高结构31所在位置，第二垫块42位于第二垫高结构32所在位置。
需要说明的是，本发明所有实施例中描述的构图工艺包括：涂敷光刻胶，使用掩模板遮盖，曝光、显影之后，进行刻蚀，最后剥离光刻胶。
该步骤S1所形成的结构中，垫块4的厚度小于或等于栅极25的厚度。当形成垫块4的厚度小于栅极25的厚度的结构时，需要应用灰阶掩模板对衬底基板1曝光，灰阶掩模板上对应栅极25的位置处为完全不透光区，对应垫块4的位置处为半透光区，其他位置处为完全透光区，曝光显影后，完全透光区的光刻胶被去除，半透光区的光刻胶半保留，完全不透光区的光刻胶完全保留，经过一次刻蚀后将无光刻胶遮盖的栅极金属层完全去除，再经过灰化工艺，将半保留的光刻胶去除，再对新暴露的栅极金属层进行刻蚀，并且通过控制刻蚀条件，例如刻蚀时间，从而至刻蚀掉部分厚度的栅极金属层，从而形成包括栅极25和厚度小于栅极25的厚度的垫块4的图形。
S2、在形成有栅极25和垫块4的衬底基板1上形成栅极绝缘层22，从而形成第二垫高结构32。
例如，第二垫高结构32包括位于第二垫高结构32所在位置的垫块4和栅极绝缘层22。
S3、在形成有栅极绝缘层22的衬底基板1上形成有源层材料层和源漏极金属层，通过一次构图工艺形成包括有源层23、源极24和漏极21的图形，从而形成第一垫高结构31和薄膜晶体管2。
在该步骤S3中，由于要同时在有源层材料层和源漏极金属层两层上形成不同的图形，因此，在该次构图工艺中，需要应用灰阶掩模板，灰阶掩模板上对应源极24和漏极21的位置处为完全不透光区，对应有源层23的位置处为半透光区，其他位置处为完全透光区，曝光显影后，完全透光区的光刻胶被去除，半透光区的光刻胶半保留，完全不透光区的光刻胶完全保留，经 过一次刻蚀后将无光刻胶遮盖的源漏极金属层和有源层材料层完全去除，再经过灰化工艺，将半保留的光刻胶去除，再对新暴露的源漏极金属层进行刻蚀，最后剥离光刻胶，从而形成包括有源层23、源极24和漏极21的图形。
该过程中，灰度掩模板的完全不透光区同时对应漏极21及有源层23的漏极区，使得漏极21的外侧边缘与有源层23的边缘对齐，但在曝光之后的刻蚀过程中，位于漏极21的外侧的源漏极金属层首先被刻蚀掉，之后位于漏极21的外侧的有源层材料层也被刻蚀掉，在刻蚀有源层材料层的同时，漏极21也会被刻蚀掉一部分，使得漏极21内缩，有源层23超出漏极21的外侧边缘而形成第一垫高结构31。
例如，第一垫高结构31包括位于第一垫高结构31所在位置的第一垫块41、栅极绝缘层22和有源层23，第二垫高结构32包括位于第二垫高结构32所在位置的第二垫块42和栅极绝缘层22，形成如图2所示的显示基板。
例如，第一垫高结构31包括位于第一垫高结构31所在位置的栅极绝缘层22和有源层23，第二垫高结构32包括位于第二垫高结构32所在位置的垫块4和栅极绝缘层22时，形成如图3或图4所示的显示基板。进一步地，例如第二垫高结构32的顶部表面与衬底基板1之间的垂直距离小于第一垫高结构31的顶部表面与衬底基板1之间的垂直距离，形成如图3所示的显示基板；例如第二垫高结构32的顶部表面与衬底基板1之间的垂直距离大于第一垫高结构31的顶部表面与衬底基板1之间的垂直距离时，形成如图4所示的显示基板。
本发明实施例提供的显示基板的制造方法中，在衬底基板上形成薄膜晶体管，并在漏极的外侧形成至少一个垫高结构，使得在后续形成像素电极时，像素电极首先由与衬底基板之间的垂直距离最小的基板顶部表面爬升至与衬底基板之间的垂直距离居中的垫高结构的顶部表面，然后再爬升至与衬底基板之间的垂直距离最大的漏极的顶部表面，使得像素电极分至少两次逐步爬升至漏极的顶部表面，每次爬升的高度较小，从而避免出现现有技术中像素电极一次爬升高度较大情况，进而能够避免出现像素电极爬升至漏极的顶部表面时产生断裂的问题。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请基于并且要求于2015年3月27日递交的中国专利申请第201510141487.X号的优先权，在此全文引用上述中国专利申请公开的内容。

Claims (11)

  1. 一种显示基板，包括衬底基板和形成在衬底基板上的薄膜晶体管，所述薄膜晶体管包括漏极；
    其中所述漏极的外侧设置有至少一个垫高结构；所述垫高结构的顶部表面与所述衬底基板之间的垂直距离，小于所述漏极的顶部表面与所述衬底基板之间的垂直距离，且大于基板位于所述垫高结构的远离所述漏极的一侧的顶部表面与所述衬底基板之间的垂直距离。
  2. 根据权利要求1所述的显示基板，其中所述垫高结构包括向远离所述漏极的方向依次设置的第一垫高结构和第二垫高结构，所述第二垫高结构的顶部表面与所述衬底基板之间的垂直距离小于所述第一垫高结构的顶部表面与所述衬底基板之间的垂直距离。
  3. 根据权利要求2所述的显示基板，其中至少一个所述垫高结构包括垫块。
  4. 根据权利要求3所述的显示基板，其中所述垫块包括相互连接的第一垫块和第二垫块；
    所述薄膜晶体管包括依次形成在所述衬底基板上的栅极绝缘层、有源层、位于同一层的源极及漏极；
    所述第一垫高结构包括位于所述第一垫高结构所在位置的所述第一垫块、所述栅极绝缘层和所述有源层；
    所述第二垫高结构包括位于所述第二垫高结构所在位置的所述第二垫块和所述栅极绝缘层。
  5. 根据权利要求3所述的显示基板，其中所述薄膜晶体管包括依次形成在所述衬底基板上的栅极绝缘层、有源层、位于同一层的源极及漏极；
    所述第一垫高结构包括位于所述第一垫高结构所在位置的所述栅极绝缘层和所述有源层；
    所述第二垫高结构包括位于所述第二垫高结构所在位置的所述垫块和所述栅极绝缘层。
  6. 根据权利要求4或5所述的显示基板，其中所述薄膜晶体管还包括位于所述栅极绝缘层和所述衬底基板之间的栅极；
    所述垫块与所述栅极位于同一层，且所述垫块的材质与所述栅极的材质相同。
  7. 根据权利要求6所述的显示基板，其中所述垫块的厚度小于或等于所述栅极的厚度。
  8. 根据权利要求6所述的显示基板，其中所述垫高结构设置在衬底基板上。
  9. 一种显示装置，包括权利要求1-8任一项所述的显示基板。
  10. 一种显示基板的制造方法，包括：
    在衬底基板上形成薄膜晶体管和至少一个垫高结构；
    其中，所述垫高结构位于所述薄膜晶体管的漏极的外侧；所述垫高结构的顶部表面与所述衬底基板之间的垂直距离，小于所述漏极的顶部表面与所述衬底基板之间的垂直距离，且大于基板位于所述垫高结构的远离所述漏极的一侧的顶部表面与所述衬底基板之间的垂直距离。
  11. 根据权利要求10所述的显示基板的制造方法，其中所述在衬底基板上形成薄膜晶体管和至少一个垫高结构的步骤，包括：
    在所述衬底基板上形成栅极金属层，通过一次构图工艺形成包括栅极和垫块的图形；
    在形成有所述栅极和所述垫块的所述衬底基板上形成栅极绝缘层，从而形成第二垫高结构；
    在形成有栅极绝缘层的衬底基板上形成有源层材料层和源漏极金属层，通过一次构图工艺形成包括有源层、源极和漏极的图形，从而形成第一垫高结构和薄膜晶体管。
PCT/CN2016/074125 2015-03-27 2016-02-19 显示基板及其制造方法、显示装置 Ceased WO2016155429A1 (zh)

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