WO2016155322A1 - 一种rram电压产生系统 - Google Patents

一种rram电压产生系统 Download PDF

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Publication number
WO2016155322A1
WO2016155322A1 PCT/CN2015/094865 CN2015094865W WO2016155322A1 WO 2016155322 A1 WO2016155322 A1 WO 2016155322A1 CN 2015094865 W CN2015094865 W CN 2015094865W WO 2016155322 A1 WO2016155322 A1 WO 2016155322A1
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voltage
regulator
output
charge pump
source
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PCT/CN2015/094865
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English (en)
French (fr)
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谢永宜
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山东华芯半导体有限公司
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Publication of WO2016155322A1 publication Critical patent/WO2016155322A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00

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  • the present invention relates to the field of memory, and more particularly to an RRAM voltage generating system.
  • Resistive Random Access Memory is a new type of non-volatile information storage technology with simple structure, compatible with standard CMOS technology, low operating voltage, low power consumption and high-speed read and write.
  • the memory information unit is realized by a variable resistor exhibiting a bipolar memory characteristic of a high resistance state (for example, 100 Kohm) and a low resistance state (for example, 10 Kohm).
  • variable resistor In order to convert the variable resistor between the low resistance state and the high resistance state, the variable resistor needs to be configured under different voltage or current operating conditions.
  • Figure 1 shows a typical 1T1R (1 transistor and 1 variable resistor) memory cell voltage configuration diagram, where the 1T1R is configured under SET conditions, and the variable resistor will change from a high-impedance state to a low-impedance state. That is, the write "1" function is realized; on the contrary, under the condition of RESET, the variable resistor will change from the low resistance state to the high resistance state, that is, the write "0" function is realized.
  • Figure 2 shows a typical memory cell SET process timing diagram (similar to the RESET process).
  • the SET process takes multiple SET (up to 16) operations on the memory cell, ie the voltage of the bit line BL starts from the lowest, SET once. Read again, if the SET is successful, switch to the next memory cell operation; if the SET fails, the voltage on the bit line BL increases by 100mV, then the second SET, and so on, until the SET succeeds. If the 16th SET operation fails, that is, the voltage on the bit line BL reaches the highest level, the memory cell is considered to be disabled, and then switched to the next memory cell to operate in the same manner.
  • the voltage supplied to the word line WL is constant, and the voltage supplied to the bit line BL and the source line SL is increased by 100 mV per pulse level,
  • the voltage supplied to the BL/SL drops rapidly (for example, 100nS) to the lowest voltage (maximum drop of 1.5V);
  • the auxiliary circuit such as the row and column decoder and the sense amplifier is also provided with an external system.
  • the power supply and reference voltage are not available, and all of these voltage generators form the RRAM voltage generation system, which assists the RRAM in its normal operation.
  • the bandgap reference provides process and temperature independent reference voltages for other circuits, including voltage control signals, charge pump output reference voltage, and low voltage LDO output reference voltages;
  • the low voltage LDO provides an output voltage lower than that of the external power supply, and provides a driving voltage sufficient for driving the memory cell to read and write;
  • the Dickson charge pump generates a voltage that is not provided by the external system and is higher than the external power supply, and provides a driving voltage for the memory cell to write 0 or write 1 to provide sufficient driving capability;
  • the present invention provides a RRAM voltage generating system capable of supporting simultaneous operation of multiple bytes, fast data reading and writing speed, and fast and accurate output.
  • An RRAM voltage generating system includes a charge pump for boosting an external power supply voltage and supplying power to other sub-circuits; a square wave oscillator for providing a clock signal; and an output of the square wave oscillator connected to the charge pump clock a signal input terminal; a linear regulator for supplying a driving voltage for the operation of the memory cell, the output of the linear regulator is sequentially connected to the row and column decoder and the memory cell array; the linear regulator is simultaneously connected to the external power source VCC and the charge pump Output power supply VPP power supply; power-on reset circuit for providing power-on reset signal to the system while controlling charge pump, square wave oscillator and linear regulator; used for charge pump, square wave oscillator, linear
  • the voltage regulator and power-up control circuit provide a reference source of voltage and current for the reference voltage and reference current.
  • the voltage and current reference source is composed of a bandgap reference voltage source and a temperature compensation current source, and the output voltage VREF is connected to the reference voltage input terminals of the charge pump, the square wave oscillator and the linear regulator; the output current IREF is respectively connected to The bias current input of the charge pump, square wave oscillator, and linear regulator.
  • the charge pump adopts a double-branched structure, and the charge pump input voltage source is connected to the external power source VCC.
  • the voltage VPP is connected to the linear regulator; the reference voltage VREF input terminal and the bias current IREF input terminal are connected to the output end of the voltage current reference source; the enable signal EN_CP input terminal is connected to the output end of the power-on control circuit;
  • the clock signal CLK input is connected to the output clock terminal of the square wave oscillator.
  • the reference voltage VREF input terminal and the bias current IREF input terminal of the square wave oscillator are connected to the output end of the voltage current reference source; the enable signal EN_OSC input terminal is connected to the output end of the power-on control circuit.
  • the power-on control circuit is composed of logic and delay circuits, and the timing output logic control signals EN_OSC, EN_CP, EN_GEN are respectively connected to the enable inputs of the square wave oscillator, the charge pump and the linear regulator.
  • the linear regulator reference voltage input terminal VREF and the bias current input terminal IREF are connected to the voltage current reference source
  • the enable signal EN_GEN input terminal is connected to the power-on control circuit
  • the output signals VWL_SET, VWL_RESET, VBL_SET, VSL_RESET, and VCLAMP are respectively Connect to the rank decoder.
  • the linear regulator consists of a reference voltage regulator, a SET mode word line WL regulator, a RESET mode word line WL regulator, and a SET mode bit line BL/RESET mode source line SL regulator and a first multi-channel a selector, a second multiplexer, and a third multiplexer;
  • Reference voltage regulator, RESET mode word line WL regulator and SET mode bit line BL/RESET mode source line SL regulator power supply is powered by charge pump output boosted voltage VPP, SET mode word line WL regulator Connect external power supply VCC power supply;
  • the reference voltage regulator outputs a series of reference voltage bus signals VREF_BUS connected to the SET mode word line WL regulator and the RESET mode word line through the first multiplexer, the second multiplexer, and the third multiplexer, respectively.
  • the reference voltage regulator is composed of a first amplifier and a first resistor string and a second resistor string connected in series; the first resistor string and the second resistor connected in series are connected between the output end of the first amplifier and the ground, For dividing the output of the first amplifier, generating a series of reference voltage bus signals VREF_BUS; the first amplifier inverting input is connected to the series common end of the first resistor string and the second resistor string.
  • the SET mode word line WL regulator is composed of a second amplifier, a first resistor and a second resistor; the first resistor and the second resistor connected in series are connected between the amplifier output VWL_SET and the ground; and the second amplifier is inverted.
  • the input terminates a series common terminal of the first resistor and the second resistor.
  • RESET mode word line WL regulator and the SET mode bit line BL/RESET mode source line SL regulator are respectively composed of an amplifier whose output terminal is connected to the inverting input terminal.
  • the present invention has the following beneficial technical effects:
  • bit line BL or the source line SL regulator is implemented by a rail-to-rail input class AB output amplifier, and the output quickly and accurately follows the input change, eliminating the "leakage path" control signal and avoiding the "leakage path” resulting in storage.
  • Figure 1 is a set of typical 1T1R memory cell voltage configuration diagrams
  • FIG. 2 is a timing diagram of a typical memory cell SET process
  • Figure 3 is a schematic diagram of a conventional voltage generating system
  • FIG. 4 is a schematic diagram of a general system diagram of a RRAM of the present invention and a schematic diagram of a voltage generating system;
  • Figure 5 is a schematic diagram of a linear regulator of the present invention.
  • Figure 6a is an amplifier circuit of a class A output
  • Figure 6b is an amplifier of a rail-to-rail input class AB output
  • Fig. 7 is a charge pump circuit of a double branch structure.
  • voltage generation system 1 row and column decoder 2, memory cell array 3, voltage and current reference source 11, charge pump 12, square wave oscillator 13, linear regulator 14, power-on control circuit 15, stable reference voltage Voltage regulator 141, first multiplexer 142, SET mode word line WL regulator 143, second multiplexer 144, RESET mode word line WL regulator 145, third multiplexer 146, SET mode
  • the RRAM voltage generating system of the present invention is a schematic diagram of the overall system diagram and voltage generating system of the RRAM of the present invention, wherein the thick dotted line is circled as the voltage generating system 1, and the row and column decoder 2 and the memory cell array 3 Provide the required voltage.
  • the voltage generating system 1 is composed of a voltage and current reference source 11, a charge pump 12, a square wave oscillator 13, a linear regulator 14, and a power-on control circuit 15.
  • the logic control circuit provides a clock signal; the linear regulator 14 provides an operating voltage with sufficient driving capability for the operation of the memory unit;
  • the circuit 15 provides a power-on reset signal for the system, and controls the other modules to be sequentially turned on.
  • VCC is the external voltage source
  • VPP is the power supply after the charge pump boosts VCC
  • VREF and IREF are the reference voltage signal and the reference current signal output by the voltage and current reference source 11
  • EN_OSC, EN_CP, EN_GEN are square wave oscillators respectively 13.
  • the enable signals of the charge pump 12 and the linear regulator 14 are active high, and are all controlled by the power-on control circuit 15
  • VWL_SET, VWL_RESET, VBL_SET, and VSL_RESET are the word lines WL generated by the linear regulator 14 at SET.
  • RESET the voltage signal when the bit line BL is at SET, and the source line SL is at RESET
  • VCLAMP is the reference voltage of the sense amplifier when the memory unit reads data.
  • the voltage and current reference source 11 is selected from the following reference sources, and is composed of a bandgap reference voltage source and a temperature compensation current source.
  • the output voltage VREF is connected to the reference of the charge pump 12, the square wave oscillator 13, and the linear regulator 14.
  • the voltage input terminal; the output current IREF (several current branches) are respectively connected to the charge current input terminal of the charge pump 12, the square wave oscillator 13, and the linear regulator 14.
  • the charge pump 12 adopts a dual-branch voltage doubler with good process compatibility, high efficiency and low cost, and the input voltage source is connected to the external power source VCC, and the output boosted power supply VPP is connected to the linear regulator 14 and The other circuit; the reference voltage VREF input terminal and the bias current IREF input terminal are connected to the output of the voltage current reference source 11; the enable signal EN_CP is connected to the output of the power-on control circuit 15; and the clock signal CLK is connected to the output of the square wave oscillator 13. Clock side.
  • the square wave oscillator 13 selects an oscillator of a common structure, and its reference voltage VREF input terminal and bias current IREF input terminal are connected to the output of the voltage current reference source 11; the enable signal EN_OSC is connected to the output of the power-on control circuit 15; The signal is coupled to the clock signal input of charge pump 12 and also provides a clock signal to other logic control circuits.
  • the power-on control circuit 15 is composed of a logic and a delay circuit. After the system is powered on, the logic control signals EN_OSC, EN_CP, and EN_GEN are respectively connected to the square wave oscillator 13 and the charge pump according to a certain timing. 12 and the enable input of the linear regulator 14, sequentially open each module.
  • the linear regulator 14 is simultaneously powered by the external power supply VCC and the charge pump output VPP, and the reference voltage input terminal VREF, the bias current input terminal IREF is connected to the voltage current reference source 11, and the enable signal EN_GEN is connected to the power-on control circuit 15, and the output is
  • the signals VWL_SET, VWL_RESET, VBL_SET, VSL_RESET, and VCLAMP are connected to the row and column decoder 2, respectively.
  • the schematic diagram of the linear regulator 14 is composed of a reference voltage regulator 141, a SET mode word line WL regulator 143, a RESET mode word line WL regulator 145, and a SET mode bit line BL/RESET.
  • the mode source line SL regulator 147 is composed of a first multiplexer 142, a second multiplexer 144, and a third multiplexer 146. From the typical 1T1R memory cell voltage configuration diagram shown in FIG. 1, it can be seen that the reference voltage regulator 141, the RESET mode word line WL regulator 145, in order to generate the correct voltage while taking into account factors of high power conversion efficiency. And SET mode bit line BL / RESET mode source line SL regulator 147 selects VPP as the power supply, SET mode word line WL regulator 143 selects VCC as the power supply.
  • the reference voltage regulator 141 is composed of a first amplifier 1411 and a first resistor string 1412 and a second resistor string 1413. Wherein, the first resistor string 1412 and the second resistor string 1413 are connected in series, connected between the output end of the first amplifier 1411 and the ground, and the resistor strings divide the output of the first amplifier 1411 to generate a series of reference voltage buses.
  • the signal VREF_BUS; the non-inverting input terminal of the first amplifier 1411 is connected to the reference voltage VREF, and the inverting input terminal is connected to the series common terminal of the first resistor string 1412 and the second resistor string 1413.
  • the SET mode word line WL regulator 143 is composed of a second amplifier 1431, a first resistor 1432, and a second resistor 1433.
  • the first resistor 1432 and the second resistor 1433 are connected in series, and are connected between the amplifier output VWL_SET and the ground; the non-inverting input terminal of the second amplifier 1431 is connected to the output of the multiplexer 142, and the inverting input terminal is connected.
  • RESET mode word line WL regulator 145 is connected by the output and the inverting input amplifier Now, its non-inverting input is connected to the output of the second multiplexer 144.
  • the SET mode bit line BL/RESET mode source line SL regulator 147 is implemented by an amplifier whose output terminal is connected to the inverting input terminal, and whose non-inverting input terminal is connected to the output terminal of the third multiplexer 146.
  • the first multiplexer 142 is connected to the reference voltage bus signal VREF_BUS, controlled by the trimming control signal TRM_VWL_SET ⁇ 3:0>, and selects one voltage as a reference voltage, and is connected to the non-inverting input terminal of the SET mode word line WL regulator 143.
  • the second multiplexer 144 is connected to the reference voltage bus signal VREF_BUS, controlled by the trimming control signal TRM_VWL_RESET ⁇ 3:0>, and selects one voltage as a reference voltage, and is connected to the non-inverting input terminal of the RESET mode word line WL regulator 145.
  • the third multiplexer 146 is connected to the reference voltage bus signal VREF_BUS, controlled by the configuration control signal CFG_VBSL ⁇ 3:0>, and selects one voltage as the reference voltage, and is connected to the SET mode bit line BL/RESET mode source line SL regulator 147. Non-inverting input.
  • FIG. 5 shows the detailed and complete circuit schematic of the linear regulator.
  • the types of each regulator are described in detail:
  • the reference voltage of the word line WL/bit line BL/source line SL regulator is provided by the reference voltage regulator 141, and has characteristics that it does not change with temperature and power supply voltage; its output is a capacitive load, so the first amplifier
  • the 1411 is implemented with an amplifier of Class A output;
  • the SET mode word line WL regulator 143 outputs are both lower than the outputs of the external power supply VCC and RESET mode word line WL regulator 145; at the same time, their loads are capacitive and the output voltage is fixed;
  • RESET mode word line WL regulator 145 When the RESET mode word line WL regulator 145 output is higher than VCC, RESET mode
  • This regulator has a wide voltage output range, resistive load, and the output voltage constantly changes rapidly (for example, each time the SET/RESET process is increased by 100mV, and the voltage changes rapidly from high to low during mode switching or address switching). ), so the rail-to-rail input amplifier of class AB output is selected.
  • the present invention further provides an implementation example of a typical amplifier circuit and a dual-branched charge pump circuit, as shown in FIG. 6a, FIG. 6b, and FIG. 7; Conducive to or easy to implement the design of the program.

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Abstract

一种RRAM电压产生系统，包括用于将外部电源电压升高并为其他子电路提供电源的电荷泵（12）；用于提供时钟信号的方波振荡器（13）；方波振荡器（13）的输出端连接电荷泵（12）的时钟信号输入端；用于为存储单元的操作提供驱动电压的线性稳压器（14），线性稳压器（14）的输出端依次连接行列译码器（2）和存储单元阵列（3）；线性稳压器（14）同时连接外部电源VCC和电荷泵（12）输出电源VPP；用于为系统提供上电复位信号，同时控制电荷泵（12）、方波振荡器（13）和线性稳压器（14）有序开启的上电控制电路（15）；用于为电荷泵（12）、方波振荡器（13）、线性稳压器（14）和上电控制电路（15）提供参考电压和参考电流的电压电流基准源（11）。通过同时采用外部电源和工艺兼容性好的双分支结构的电荷泵（12）输出电源为线性稳压器（14）分别供电，实现支持多字节。

Description

一种RRAM电压产生系统 技术领域
本发明涉及存储器领域，具体为一种RRAM电压产生系统。
背景技术
阻变型随机存储器(RRAM)是一种新型的非易失性信息存储技术，具有结构简单、兼容标准CMOS工艺、低操作电压、低功耗及高速读写等特点。其存储信息单元是由表现出高阻态(例如：100Kohm)和低阻态(例如：10Kohm)的双极记忆特性的可变电阻实现。
为了使可变电阻在低阻态和高阻态之间转化，则需要将可变电阻配置在不同的电压或电流工作条件下。
图1所示为一组典型的1T1R(1个晶体管和1个可变电阻)存储单元电压配置图，其中将1T1R配置在SET条件下，可变电阻将从高阻态变为低阻态，即实现写“1”功能；与之相反，配置在RESET条件下，可变电阻将从低阻态变为高阻态，即实现写“0”功能。
图2所示为一种典型的存储单元SET过程时序图(RESET过程类似)，SET过程采取对存储单元多次SET(最多16次)的操作方式，即位线BL的电压从最低开始，SET一次后读一次，如果本次SET成功，则切换到下一个存储单元的操作；如果本次SET失败，则位线BL上的电压增加100mV，再进行第二次SET，以此类推，直到SET成功；如果第16次SET操作失败，即位线BL上的电压达到最高，则认为此存储单元失效，然后切换到下一个存储单元以相同的方式操作。
从以上相关背景介绍可知，为了改变1T1R存储单元的存储状态，必须为其 提供输出正确、具有足够驱动能力且时序满足要求的驱动电压：提供给字线WL上的电压恒定不变，而提供给位线BL和源线SL上的电压每个脉冲电平升高100mV，但当地址切换时，提供给BL/SL上的电压迅速下降(例如100nS)至最低电压(最大下降幅度1.5V)；同时，也要给辅助电路如行列译码器、灵敏放大器提供外部系统所不能提供的电源及参考电压，而所有这些电压产生器则组成了RRAM电压产生系统，辅助RRAM正常工作。
现有的一种RRAM电压解决方案，如学术论文：《新型阻变存储器内的电压解决方案》；廖启宏等；集成电路设计与应用(半导体技术)，2011年6月，第36卷，第6期，如图3为其电压产生系统原理图，包括带隙基准源、低压输出LDO(低压差线性稳压器)和Dickson电荷泵，其中Dickson电荷泵由压控振荡器、时钟分频和电荷泵核组成。
带隙基准源为其他电路提供与工艺和温度无关的参考电压，包括压控信号，电荷泵输出参考电压和低压LDO输出参考电压；
低压LDO提供低于外部电源的输出电压，为存储单元读写提供足够驱动能力的驱动电压；
Dickson电荷泵产生外部系统所不能提供的且高于外部电源的电压，为存储单元写0或写1提供足够驱动能力的驱动电压；
虽然上述现有方案能够为RRAM提供所需的所有电压，但是还存在以下缺点：1)此方案不支持多字节Bytes存储单元同时操作；原文中提到：电荷泵采用Dickson电荷泵，其负载最大为1mA；由此可以推测，此方案仅用来支持驱动小于1个字节(8bits)存储单元同时进行SET/RESET操作；若要支持多个字节(例16Bytes＝128bits)存储单元同时进行SET/RESET操作，即电荷泵的负载电流便会很大(>16mA)；2)采用3级Dickson电荷泵，电压损失大，负载驱动 能力低，功率效能低；若要达到足够的驱动能力和输出电压，此方案的版图面积变大，芯片的成本提高；3)存储单元切换或SET/RESET模式切换(即提供给存储单元的电压迅速下降)采用“漏电路径”的方式：需要额外的脉宽信号控制漏电路径，同时切换后的电压不能快速准确稳定到目标值(即切换后的实际值与目标值存在一定的偏差)，影响后续存储单元的正常操作；4)此方案并没有对字线WL、位线BL和源线SL的LDO类型做出详细阐述，不利于高效方案的实现。
发明内容
针对现有技术中存在的问题，本发明提供一种能够支持多字节同时操作，数据读写速度快，输出快速准确的RRAM电压产生系统。
本发明是通过以下技术方案来实现：
一种RRAM电压产生系统，包括用于将外部电源电压升高并为其他子电路提供电源的电荷泵；用于提供时钟信号的方波振荡器；方波振荡器的输出端连接电荷泵的时钟信号输入端；用于为存储单元的操作提供驱动电压的线性稳压器，线性稳压器的输出端依次连接行列译码器和存储单元阵列；线性稳压器同时连接外部电源VCC和电荷泵输出电源VPP供电；用于为系统提供上电复位信号，同时控制电荷泵、方波振荡器和线性稳压器有序开启的上电控制电路；用于为电荷泵、方波振荡器、线性稳压器和上电控制电路提供参考电压和参考电流的电压电流基准源。
优选的，电压电流基准源由带隙基准电压源和温度补偿电流源组成，其输出电压VREF接至电荷泵、方波振荡器和线性稳压器的参考电压输入端；输出电流IREF分别接至电荷泵、方波振荡器和线性稳压器的偏置电流输入端。
优选的，电荷泵采用双分支结构，电荷泵输入电压源接外部电源VCC，输 出升压后电压VPP接至线性稳压器；参考电压VREF输入端和偏置电流IREF输入端接至电压电流基准源的输出端；使能信号EN_CP输入端接至上电控制电路的输出端；时钟信号CLK输入端接至方波振荡器的输出时钟端。
优选的，方波振荡器的参考电压VREF输入端和偏置电流IREF输入端接至电压电流基准源的输出端；使能信号EN_OSC输入端接至上电控制电路的输出端。
优选的，上电控制电路由逻辑及延时电路组成，按时序输出逻辑控制信号EN_OSC、EN_CP、EN_GEN分别接至方波振荡器、电荷泵及线性稳压器的使能输入端。
优选的，线性稳压器参考电压输入端VREF和偏置电流输入端IREF接至电压电流基准源，使能信号EN_GEN输入端接至上电控制电路，输出信号VWL_SET、VWL_RESET、VBL_SET、VSL_RESET和VCLAMP分别接至行列译码器。
进一步，线性稳压器由参考电压稳压器、SET模式字线WL稳压器、RESET模式字线WL稳压器和SET模式位线BL/RESET模式源线SL稳压器及第一多路选择器、第二多路选择器、第三多路选择器组成；
参考电压稳压器、RESET模式字线WL稳压器和SET模式位线BL/RESET模式源线SL稳压器的电源由电荷泵输出升压后电压VPP供电，SET模式字线WL稳压器连接外部电源VCC供电；
参考电压稳压器输出一系列参考电压总线信号VREF_BUS分别通过第一多路选择器、第二多路选择器、第三多路选择器连接到SET模式字线WL稳压器、RESET模式字线WL稳压器和SET模式位线BL/RESET模式源线SL稳压器的同相输入端。
优选的，参考电压稳压器由第一放大器和串联的第一电阻串、第二电阻串组成；串联的第一电阻串、第二电阻串接于第一放大器的输出端和地之间，用于对第一放大器的输出分压，产生一系列参考电压总线信号VREF_BUS；第一放大器反相输入端接第一电阻串和第二电阻串的串联公共端。
进一步，SET模式字线WL稳压器由第二放大器、第一电阻和第二电阻组成；串联的第一电阻、第二电阻接于放大器输出VWL_SET和地端之间；第二放大器的反相输入端接第一电阻和第二电阻的串联公共端。
进一步，RESET模式字线WL稳压器和SET模式位线BL/RESET模式源线SL稳压器分别由输出端与反相输入端相连的放大器组成。
与现有技术相比，本发明具有以下有益的技术效果：
本发明所述RRAM电压产生系统，通过同时采用外部电源和工艺兼容性好的高效双分支结构的电荷泵输出电源为线性稳压器分别供电，能够支持多字节，包括单字节存储单元的同时操作，例16Bytes＝128bits，提高了RRAM数据读写的速度；同时，也降低了芯片成本。
进一步的，位线BL或源线SL稳压器采用轨到轨输入AB类输出放大器实现的，输出快速准确跟随输入变化，省去了“漏电路径”控制信号，避免了“漏电路径”导致存储单元切换或SET/RESET模式切换后实际值与目标值偏差的问题；同时，由于其结构清晰，更利于或易于方案的设计实现。
附图说明
图1为一组典型的1T1R存储单元电压配置图；
图2为一种典型的存储单元SET过程时序图；
图3为传统电压产生系统原理图；
图4为本发明RRAM总体系统原理图和电压产生系统原理图；
图5为本发明线性稳压器原理图；
图6a为一种A类输出的放大器电路；
图6b为一种轨到轨输入AB类输出的放大器；
图7为双分支结构的电荷泵电路。
图中：电压产生系统1，行列译码器2，存储单元阵列3，电压电流基准源11，电荷泵12，方波振荡器13，线性稳压器14，上电控制电路15，参考电压稳压器141，第一多路选择器142，SET模式字线WL稳压器143，第二多路选择器144，RESET模式字线WL稳压器145，第三多路选择器146，SET模式位线BL/RESET模式源线SL稳压器147，第一放大器1411，第一电阻串1412，第二电阻串1413，第二放大器1431，第一电阻1432，第二电阻1433。
具体实施方式
下面结合具体的实施例对本发明做进一步的详细说明，所述是对本发明的解释而不是限定。
本发明RRAM电压产生系统，如图4所示，为本发明RRAM总体系统原理图和电压产生系统原理图，其中粗虚线所圈为电压产生系统1，为行列译码器2和存储单元阵列3提供所需的电压。
其中，电压产生系统1由电压电流基准源11、电荷泵12、方波振荡器13、线性稳压器14和上电控制电路15五部分组成。电压电流基准源11为其他电路(方波振荡器、电荷泵、线性稳压器、灵敏放大器等)提供经过温度补偿和微调后的参考电压和参考电流；电荷泵12将外部电源(VCC＝3.3V)升高系统所不能提供的较高的电压(如VPP＝5V)，为其他模块(线性稳压器、行/列译码器等)提供电源；方波振荡器13为电荷泵及其他逻辑控制电路提供时钟信号；线性稳压器14为存储单元的操作提供具有足够驱动能力的工作电压；上电控制电 路15为系统提供上电复位信号，同时控制其他各个模块有序开启。
其中：VCC为外部电压源，VPP为电荷泵将VCC升压后的电源；VREF和IREF为电压电流基准源11输出的基准电压信号和基准电流信号；EN_OSC、EN_CP、EN_GEN分别是方波振荡器13、电荷泵12及线性稳压器14的使能信号，高电平有效，均由上电控制电路15控制；VWL_SET、VWL_RESET、VBL_SET、VSL_RESET为线性稳压器14产生的字线WL在SET或RESET时、位线BL在SET时、源线SL在RESET时的电压信号；VCLAMP是存储单元读取数据时灵敏放大器的参考电压。
电压电流基准源11选用如下结构的基准源，由带隙基准电压源和温度补偿电流源两部分构成，其输出电压VREF接至电荷泵12、方波振荡器13、线性稳压器14的参考电压输入端；输出电流IREF(多条电流支路)分别接至电荷泵12、方波振荡器13、线性稳压器14的偏置电流输入端。
电荷泵12选用工艺兼容性好、效率高且成本低的双分支结构(Dual-branch Voltage Doubler)，其输入电压源接外部电源VCC，输出升压后的电源VPP接至线性稳压器14及其他电路；参考电压VREF输入端和偏置电流IREF输入端接至电压电流基准源11的输出；使能信号EN_CP接至上电控制电路15的输出；时钟信号CLK接至方波振荡器13的输出时钟端。
方波振荡器13选用普通结构的振荡器，其参考电压VREF输入端和偏置电流IREF输入端接至电压电流基准源11的输出；使能信号EN_OSC接至上电控制电路15的输出；输出时钟信号接至电荷泵12的时钟信号输入端，同时也为其他逻辑控制电路提供时钟信号。
上电控制电路15由逻辑及延时电路构成，在系统上电后，按一定的时序输出逻辑控制信号EN_OSC、EN_CP、EN_GEN分别接至方波振荡器13、电荷泵 12及线性稳压器14的使能输入端，有序开启各个模块。
线性稳压器14由外部电源VCC和电荷泵输出VPP同时供电，其参考电压输入端VREF、偏置电流输入端IREF接至电压电流基准源11，使能信号EN_GEN接至上电控制电路15，输出信号VWL_SET、VWL_RESET、VBL_SET、VSL_RESET和VCLAMP分别接至行列译码器2。
如图5所示为线性稳压器14的原理图，由参考电压稳压器141、SET模式字线WL稳压器143、RESET模式字线WL稳压器145和SET模式位线BL/RESET模式源线SL稳压器147及第一多路选择器142、第二多路选择器144、第三多路选择器146组成。由图1所示的一组典型的1T1R存储单元电压配置图可知，为了产生正确的电压，同时考虑到电源转换效率高的因素，参考电压稳压器141、RESET模式字线WL稳压器145和SET模式位线BL/RESET模式源线SL稳压器147选用VPP作电源，SET模式字线WL稳压器143选用VCC做电源。
参考电压稳压器141由第一放大器1411和第一电阻串1412、第二电阻串1413组成。其中，第一电阻串1412和第二电阻串1413串联而成，接于第一放大器1411的输出端和地之间，这些电阻串对第一放大器1411的输出分压，产生一系列参考电压总线信号VREF_BUS；第一放大器1411的同相输入端接参考电压VREF，反相输入端接第一电阻串1412和第二电阻串1413的串联公共端。
SET模式字线WL稳压器143由第二放大器1431、第一电阻1432和第二电阻1433组成。其中，第一电阻1432和第二电阻1433串联而成，接于放大器输出VWL_SET和地端之间；第二放大器1431的同相输入端接多路选择器142的输出端，反相输入端接第一电阻1432和第二电阻1433的串联公共端。
RESET模式字线WL稳压器145则由输出端与反相输入端相连的放大器实 现，其同相输入端接第二多路选择器144的输出端。
SET模式位线BL/RESET模式源线SL稳压器147同样输出端与反相输入端相连的放大器实现，其同相输入端接第三多路选择器146的输出端。
第一多路选择器142输入接参考电压总线信号VREF_BUS，由微调控制信号TRM_VWL_SET<3：0>控制，选择一路电压作为参考电压，接SET模式字线WL稳压器143的同相输入端。
第二多路选择器144输入接参考电压总线信号VREF_BUS，由微调控制信号TRM_VWL_RESET<3：0>控制，选择一路电压作为参考电压，接RESET模式字线WL稳压器145的同相输入端。
第三多路选择器146输入接参考电压总线信号VREF_BUS，由配置控制信号CFG_VBSL<3：0>控制，选择一路电压作为参考电压，接SET模式位线BL/RESET模式源线SL稳压器147同相输入端。
图5所示给出了线性稳压器详细完整的电路原理图，为了更利于或易于方案的设计实现，分别就各个稳压器的类型作以详细的说明：
1)参考电压稳压器141：
字线WL/位线BL/源线SL稳压器的参考电压均由参考电压稳压器141提供，具有不随温度、电源电压变化而变化的特点；其输出为容性负载，故第一放大器1411选用A类输出的放大器实现；
2)SET模式字线WL稳压器143和RESET模式字线WL稳压器145：
通常，SET模式字线WL稳压器143输出均低于外部电源VCC和RESET模式字线WL稳压器145的输出；同时，它们的负载是容性的，且输出电压固定不变；
(1)当RESET模式字线WL稳压器145输出高于VCC时，RESET模式 字线WL稳压器145可选用A类输出的放大器实现，但需要选用VPP为电源，保证输出电压正确；而SET模式字线WL稳压器143的第二放大器1431也选用A类输出的放大器实现，同时选用VCC＝3.3V为电源，节省功耗。
(2)当RESET模式字线WL稳压器145输出也低于外部电源VCC时，由于SET模式和RESET模式工作在不同时段，所以可共用一个运放，以节省功耗；又由于它们的电压输出范围宽，故可选用轨对轨(Rail-to-Rail)输入AB类输出的放大器实现。
3)SET模式位线BL/RESET模式源线SL稳压器147：
(1)由于SET模式和RESET模式工作在不同时段，所以用一个运算放大器产生VBL_SET和VSL_RESET电压，以节省功耗；
(2)此稳压器电压输出范围宽，阻性负载，且输出电压不断地迅速变化(例SET/RESET过程中每次升高100mV，及模式切换或地址切换时电压迅速从高变到低)，故选用轨到轨输入AB类输出的放大器。
参考图4和图5，本发明再给出一组典型的放大器电路和双分支结构的电荷泵电路的实现实例，如图6a、图6b、图7所示；相比较现有技术，其更利于或易于方案的设计实现。

Claims (10)

  1. 一种RRAM电压产生系统，其特征在于，包括：
    用于将外部电源电压升高并为其他子电路提供电源的电荷泵(12)；
    用于提供时钟信号的方波振荡器(13)；方波振荡器(13)的输出端连接电荷泵(12)的时钟信号输入端；
    用于为存储单元的操作提供驱动电压的线性稳压器(14)，线性稳压器(14)的输出端依次连接行列译码器(2)和存储单元阵列(3)；线性稳压器(14)同时连接外部电源VCC和电荷泵输出电源VPP供电；
    用于为系统提供上电复位信号，同时控制电荷泵(12)、方波振荡器(13)和线性稳压器(14)有序开启的上电控制电路(15)；
    用于为电荷泵(12)、方波振荡器(13)、线性稳压器(14)和上电控制电路(15)提供参考电压和参考电流的电压电流基准源(11)。
  2. 根据权利要求1所述的一种RRAM电压产生系统，其特征在于，所述的电压电流基准源(11)由带隙基准电压源和温度补偿电流源组成，其输出电压VREF接至电荷泵(12)、方波振荡器(13)和线性稳压器(14)的参考电压输入端；输出电流IREF分别接至电荷泵(12)、方波振荡器(13)和线性稳压器(14)的偏置电流输入端。
  3. 根据权利要求1所述的一种RRAM电压产生系统，其特征在于，所述的电荷泵(12)采用双分支结构，电荷泵(12)输入电压源接外部电源VCC，输出升压后电压VPP接至线性稳压器(14)；参考电压VREF输入端和偏置电流IREF输入端接至电压电流基准源(11)的输出端；使能信号EN_CP输入端接至上电控制电路(15)的输出端；时钟信号CLK输入端接至方波振荡器(13)的输出时钟端。
  4. 根据权利要求1所述的一种RRAM电压产生系统，其特征在于，所述的方波振荡器(13)的参考电压VREF输入端和偏置电流IREF输入端接至电压电流基准源(11)的输出端；使能信号EN_OSC输入端接至上电控制电路(15)的输出端。
  5. 根据权利要求1所述的一种RRAM电压产生系统，其特征在于，所述的上电控制电路(15)由逻辑及延时电路组成，按时序输出逻辑控制信号EN_OSC、EN_CP、EN_GEN分别接至方波振荡器(13)、电荷泵(12)及线性稳压器(14)的使能输入端。
  6. 根据权利要求1所述的一种RRAM电压产生系统，其特征在于，所述的线性稳压器(14)参考电压输入端VREF和偏置电流输入端IREF接至电压电流基准源(11)，使能信号EN_GEN输入端接至上电控制电路(15)，输出信号VWL_SET、VWL_RESET、VBL_SET、VSL_RESET和VCLAMP分别接至行列译码器(2)。
  7. 根据权利要求6所述的一种RRAM电压产生系统，其特征在于，所述的线性稳压器(14)由参考电压稳压器(141)、SET模式字线WL稳压器(143)、RESET模式字线WL稳压器(145)和SET模式位线BL/RESET模式源线SL稳压器(147)及第一多路选择器(142)、第二多路选择器(144)、第三多路选择器(146)组成；
    参考电压稳压器(141)、RESET模式字线WL稳压器(145)和SET模式位线BL/RESET模式源线SL稳压器(147)的电源由电荷泵输出升压后电压VPP供电，SET模式字线WL稳压器(143)连接外部电源VCC供电；
    参考电压稳压器(141)输出一系列参考电压总线信号VREF_BUS分别通过第一多路选择器(142)、第二多路选择器(144)、第三多路选择器(146)连 接到SET模式字线WL稳压器(143)、RESET模式字线WL稳压器(145)和SET模式位线BL/RESET模式源线SL稳压器(147)的同相输入端。
  8. 根据权利要求7所述的一种RRAM电压产生系统，其特征在于，所述的参考电压稳压器(141)由第一放大器(1411)和串联的第一电阻串(1412)、第二电阻串(1413)组成；串联的第一电阻串(1412)、第二电阻串(1413)接于第一放大器(1411)的输出端和地之间，用于对第一放大器(1411)的输出分压，产生一系列参考电压总线信号VREF_BUS；第一放大器(1411)反相输入端接第一电阻串(1412)和第二电阻串(1413)的串联公共端。
  9. 根据权利要求7所述的一种RRAM电压产生系统，其特征在于，所述的SET模式字线WL稳压器(143)由第二放大器(1431)、第一电阻(1432)和第二电阻(1433)组成；串联的第一电阻(1432)、第二电阻(1433)接于放大器输出VWL_SET和地端之间；第二放大器(1431)的反相输入端接第一电阻(1432)和第二电阻(1433)的串联公共端。
  10. 根据权利要求7所述的一种RRAM电压产生系统，其特征在于，所述的RESET模式字线WL稳压器(145)和SET模式位线BL/RESET模式源线SL稳压器(147)分别由输出端与反相输入端相连的放大器组成。
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CN104778968B (zh) * 2015-04-01 2017-10-03 西安紫光国芯半导体有限公司 一种rram电压产生系统
CN105719691A (zh) * 2016-01-22 2016-06-29 清华大学 阻变存储器的操作方法及阻变存储器装置
CN108646841A (zh) * 2018-07-12 2018-10-12 上海艾为电子技术股份有限公司 一种线性稳压电路

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1538453A (zh) * 2003-04-17 2004-10-20 ���µ�����ҵ��ʽ���� 升压电源电路
US20050174162A1 (en) * 2004-02-09 2005-08-11 Taiwan Semiconductor Manufacturing Company Configurable voltage generator
US20120243319A1 (en) * 2011-03-23 2012-09-27 Kabushiki Kaisha Toshiba Nonvolatile semicondcutor memory device, ic card and portable apparatus
CN103346779A (zh) * 2013-06-26 2013-10-09 成都鸿芯纪元科技有限公司 一种fpga片上低功耗系统
CN103413567A (zh) * 2013-08-22 2013-11-27 上海宏力半导体制造有限公司 参考电压提供电路
CN104112473A (zh) * 2014-04-28 2014-10-22 北京时代民芯科技有限公司 一种低功耗快速升压flash电荷泵控制电路
CN104778968A (zh) * 2015-04-01 2015-07-15 山东华芯半导体有限公司 一种rram电压产生系统
CN204680386U (zh) * 2015-04-01 2015-09-30 山东华芯半导体有限公司 一种rram电压产生系统

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100589207C (zh) * 2006-10-12 2010-02-10 中兴通讯股份有限公司 一种电荷泵输出高压的控制装置
KR20130069029A (ko) * 2011-12-16 2013-06-26 에스케이하이닉스 주식회사 저항성 메모리 장치
CN103839588B (zh) * 2014-03-17 2018-02-09 上海华虹宏力半导体制造有限公司 稳压器及其控制方法、存储器

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1538453A (zh) * 2003-04-17 2004-10-20 ���µ�����ҵ��ʽ���� 升压电源电路
US20050174162A1 (en) * 2004-02-09 2005-08-11 Taiwan Semiconductor Manufacturing Company Configurable voltage generator
US20120243319A1 (en) * 2011-03-23 2012-09-27 Kabushiki Kaisha Toshiba Nonvolatile semicondcutor memory device, ic card and portable apparatus
CN103346779A (zh) * 2013-06-26 2013-10-09 成都鸿芯纪元科技有限公司 一种fpga片上低功耗系统
CN103413567A (zh) * 2013-08-22 2013-11-27 上海宏力半导体制造有限公司 参考电压提供电路
CN104112473A (zh) * 2014-04-28 2014-10-22 北京时代民芯科技有限公司 一种低功耗快速升压flash电荷泵控制电路
CN104778968A (zh) * 2015-04-01 2015-07-15 山东华芯半导体有限公司 一种rram电压产生系统
CN204680386U (zh) * 2015-04-01 2015-09-30 山东华芯半导体有限公司 一种rram电压产生系统

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