WO2016152857A1 - 光電変換装置 - Google Patents

光電変換装置 Download PDF

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WO2016152857A1
WO2016152857A1 PCT/JP2016/058991 JP2016058991W WO2016152857A1 WO 2016152857 A1 WO2016152857 A1 WO 2016152857A1 JP 2016058991 W JP2016058991 W JP 2016058991W WO 2016152857 A1 WO2016152857 A1 WO 2016152857A1
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layer
semiconductor layer
photoelectric conversion
semiconductor
conversion device
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PCT/JP2016/058991
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English (en)
French (fr)
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順次 荒浪
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京セラ株式会社
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Priority to US15/558,678 priority Critical patent/US20180114874A1/en
Priority to JP2017508359A priority patent/JPWO2016152857A1/ja
Publication of WO2016152857A1 publication Critical patent/WO2016152857A1/ja

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    • H01L31/0322—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312 comprising only AIBIIICVI chalcopyrite compounds, e.g. Cu In Se2, Cu Ga Se2, Cu In Ga Se2
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    • H10K85/50—Organic perovskites; Hybrid organic-inorganic perovskites [HOIP], e.g. CH3NH3PbI3
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    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L2031/0344—Organic materials
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    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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    • H10K30/80—Constructional details
    • H10K30/81—Electrodes
    • H10K30/82—Transparent electrodes, e.g. indium tin oxide [ITO] electrodes
    • H10K30/83—Transparent electrodes, e.g. indium tin oxide [ITO] electrodes comprising arrangements for extracting the current from the cell, e.g. metal finger grid systems to reduce the serial resistance of transparent electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/541—CuInSe2 material PV cells
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present invention relates to a photoelectric conversion device including a compound semiconductor layer.
  • Such a photoelectric conversion device has a configuration in which a plurality of photoelectric conversion cells are arranged side by side in a plane.
  • Each photoelectric conversion cell includes a lower electrode such as a metal electrode on a substrate such as glass, a light absorption layer including a metal chalcogenide such as CIGS, and a buffer layer including indium sulfide heterojunction to the light absorption layer.
  • the upper electrode such as a transparent electrode or a metal electrode is laminated in this order.
  • the plurality of photoelectric conversion cells are electrically connected in series by electrically connecting the upper electrode of one adjacent photoelectric conversion cell and the lower electrode of the other photoelectric conversion cell by a connecting conductor. (See JP 2003-282909 A).
  • the photoelectric conversion device includes an electrode layer, a first semiconductor layer, a second semiconductor layer, and an intermediate layer.
  • the first semiconductor layer is located on the electrode layer.
  • the first semiconductor layer is p-type or i-type and mainly contains a chalcopyrite compound or a perovskite compound.
  • the second semiconductor layer is n-type and is located on the first semiconductor layer.
  • the intermediate layer is located at the interface between the electrode layer and the first semiconductor layer.
  • the intermediate layer mainly includes a p-type semiconductor having a crystal structure different from that of the first semiconductor layer. Furthermore, the intermediate layer has a higher carrier density than the first semiconductor layer.
  • FIG. 1 is a perspective view showing the photoelectric conversion device according to the first embodiment, and FIG. 2 is a sectional view thereof.
  • the photoelectric conversion device 11 includes a plurality of photoelectric conversion cells 10 on a substrate 1. These photoelectric conversion cells 10 are arranged with a space P3 therebetween, and the adjacent photoelectric conversion cells 10 are electrically connected to each other. In FIG. 1, only two photoelectric conversion cells 10 are shown for convenience of illustration. However, in an actual photoelectric conversion device 11, a large number of photoelectric conversion cells are arranged in the horizontal direction of the drawing or in a direction perpendicular thereto. The cells 10 may be arranged in a plane (two-dimensionally).
  • a plurality of electrode layers 2 are arranged in a plane on a substrate 1.
  • the electrode layer 2 connected to the first semiconductor layer 3 side will be described as the lower electrode layer 2 in order to distinguish it from the upper electrode layer 5 described later.
  • the lower electrode layer 2 does not necessarily have to be positioned below the upper electrode layer 4 and may be on the upper side.
  • the plurality of lower electrode layers 2 are provided with lower electrode layers 2a to 2c arranged at intervals P1 in one direction.
  • a first semiconductor layer 3, a buffer layer 4, and an upper electrode layer 5 are sequentially stacked from the lower electrode layer 2 a through the substrate 1 to the lower electrode layer 2 b.
  • the connection conductor 7 is provided along or through the side surfaces of the first semiconductor layer 3 and the buffer layer 4. The connection conductor 7 electrically connects the upper electrode layer 5 and the lower electrode layer 2b.
  • an intermediate layer 3 a is interposed at the interface between the lower electrode layer 2 and the first semiconductor layer 3.
  • the lower electrode layer 2, the intermediate layer 3 a, the first semiconductor layer 3, the buffer layer 4, and the upper electrode layer 5 constitute one photoelectric conversion cell 10, and the adjacent photoelectric conversion cells 10 are connected to each other via the connection conductor 7. By connecting them in series, the high-power photoelectric conversion device 11 is obtained.
  • the photoelectric conversion apparatus 11 in this embodiment assumes what light injects into the 1st semiconductor layer 3 from the upper electrode layer 5 side, it is not limited to this, From the lower electrode layer 2 side The light may be incident on the first semiconductor layer 3.
  • the substrate 1 is for supporting the photoelectric conversion cell 10.
  • Examples of the material used for the substrate 1 include glass, ceramics, resin, and metal.
  • the lower electrode layer 2 (lower electrode layers 2a, 2b, 2c) is a conductor such as Mo, Al, Ti, or Au provided on the substrate 1.
  • the lower electrode layer 2 is formed to a thickness of about 0.2 ⁇ m to 1 ⁇ m using a known thin film forming method such as sputtering or vapor deposition.
  • the first semiconductor layer 3 is a semiconductor layer that functions to absorb light and generate carriers (electrons and holes), and is a so-called light absorption layer.
  • the first semiconductor layer 3 is a p-type or i-type semiconductor layer having a thickness of about 1 ⁇ m to 3 ⁇ m, for example.
  • the first semiconductor layer 3 mainly contains a chalcopyrite compound or mainly contains a perovskite compound. “Containing mainly chalcopyrite compounds” means containing at least 70 mol% of chalcopyrite compounds.
  • the phrase “mainly containing a perovskite compound” means containing 70 mol% or more of a perovskite compound.
  • the chalcopyrite compound is a compound having a chalcopyrite structure, and examples thereof include I-III-VI group compounds.
  • the group I-III-VI compound is a compound of a group 11 element (also referred to as a group IB element), a group 13 element (also referred to as a group III-B element), and a group 16 element.
  • Examples of the I-III-VI group compounds include CuInSe 2 (also referred to as copper indium diselenide, CIS), Cu (In, Ga) Se 2 (also referred to as copper indium diselenide / gallium, CIGS), Cu ( In, Ga) (Se, S) 2 (also referred to as diselene / copper indium / gallium / CIGSS).
  • the first semiconductor layer 3 may be composed of a multi-component compound semiconductor thin film such as copper indium selenide / gallium having a thin film of selenite / copper indium sulfide / gallium layer as a surface layer.
  • a multi-component compound semiconductor thin film such as copper indium selenide / gallium having a thin film of selenite / copper indium sulfide / gallium layer as a surface layer.
  • the perovskite compound is a compound having a perovskite structure, and examples thereof include organic-inorganic composite materials such as CH 3 NH 3 PbX 3 (X is a halogen element).
  • the organic-inorganic composite material is a material in which an organic component and an inorganic component are combined at the molecular level.
  • a structure containing no organic substance such as APbX 3 (A is an alkali metal element such as Cs and X is a halogen element) is also included in the perovskite compound.
  • a perovskite compound containing Pb and having X composed of a halogen element is preferably used.
  • the halogen element represented by X may include two or more elements, and an organic substance such as CH 3 NH 3 and an alkali metal such as Cs may also include two or more elements. .
  • an organic substance such as CH 3 NH 3 and an alkali metal such as Cs may also include two or more elements.
  • the first semiconductor layer 3 can be formed by a so-called vacuum process such as a sputtering method or an evaporation method, or can be formed by a process called a coating method or a printing method.
  • a process referred to as a coating method or a printing method is a process in which a complex solution of constituent elements of the first semiconductor layer 3 is applied on the intermediate layer 3a or the lower electrode layer 2 and then dried and heat-treated.
  • the intermediate layer 3 a is located at the interface between the lower electrode layer 2 and the first semiconductor layer 3. That is, the first semiconductor layer 3 is electrically connected to the lower electrode layer 2 through the intermediate layer 3a.
  • the intermediate layer 3 a is made of a p-type semiconductor having a crystal structure different from that of the first semiconductor layer 3, and has a carrier density higher than that of the first semiconductor layer 3.
  • the intermediate layer 3a has a thickness of about 30 to 2000 nm.
  • the carrier density of the first semiconductor layer 3 may be, for example, about 1 ⁇ 10 10 to 9 ⁇ 10 17 cm ⁇ 3 or less so as not to reveal recombination due to defects.
  • the intermediate layer 3 a has a carrier density higher than that of the first semiconductor layer 3, for example, 1 ⁇ 10 18 to 9 ⁇ 10 18 cm ⁇ 3. It can be easily pulled out.
  • a p-type semiconductor having a crystal structure different from that of the first semiconductor layer 3 is used from the viewpoint of easy control of the dopant with few defects.
  • the intermediate layer 3a examples include a semiconductor mainly containing silicon (Si) doped with other elements such as boron (B). Note that “mainly containing Si” means containing 70 mol% or more of Si. Further, as the other intermediate layer 3 a, a compound semiconductor such as zinc selenide that can be easily bonded to the first semiconductor layer 3 may be used.
  • the intermediate layer 3a is produced by using a deposition method such as a vapor deposition method, a sputtering method, a sol-gel method, a screen printing method, a coating method, a plating method, a spray coating method, an inkjet coating method, a CVD method, a plasma CVD method, or a PVD method. can do. If necessary, the intermediate layer 3a may be formed into a desired pattern shape by combining a photolithography method, a lift-off method, a coating method using a dispenser, and a pattern forming method such as laser scribing.
  • a deposition method such as a vapor deposition method, a sputtering method, a sol-gel method, a screen printing method, a coating method, a plating method, a spray coating method, an inkjet coating method, a CVD method, a plasma CVD method, or a PVD method. can do.
  • the intermediate layer 3a may be formed into a desired pattern shape
  • the second semiconductor layer is a semiconductor layer having an n-type conductivity different from that of the first semiconductor layer 3, and forms a pn junction with the first semiconductor layer 3.
  • the second semiconductor layer is a stacked body of the buffer layer 4 and the upper electrode layer 5 is shown.
  • the above laminated body may be sufficient.
  • the second semiconductor layer includes a plurality of layers, at least one of the plurality of layers may be n-type. That is, the second semiconductor layer may be a stacked body of an n-type semiconductor layer and an i-type semiconductor layer, or may be a stacked body of an n-type semiconductor layer.
  • the buffer layer 4 is an n-type or i-type semiconductor layer that is heterojunction with the first semiconductor layer 3.
  • the buffer layer 4 has a thickness of 5 to 200 nm, for example.
  • a metal sulfide such as CdS, ZnS, In 2 S 3 is used.
  • the buffer layer 4 may be a mixed crystal containing at least one of a metal oxide and a metal hydroxide in addition to such a metal sulfide.
  • the buffer layer 4 is formed by, for example, a solution deposition method (CBD method), an ALD method, an MOCVD method, or the like.
  • an n-type organic semiconductor may be used as the buffer layer 4.
  • an organic semiconductor include fullerene derivatives such as phenyl-C 61 -butyric acid methyl ester (PCBM) and fullerene C60.
  • PCBM phenyl-C 61 -butyric acid methyl ester
  • the buffer layer 4 can be formed by dissolving PCBM or the like in an organic solvent, applying this solution onto the first semiconductor layer 3, and then drying.
  • the buffer layer 4 may be formed by evaporating fullerene C60 or the like on the first semiconductor layer 3.
  • a protective buffer layer is further laminated on the buffer layer 4. You may do it.
  • the protective buffer layer include molybdenum oxide and tungsten oxide.
  • Such a protective buffer layer can be formed by sputtering or vapor deposition.
  • the upper electrode layer 5 is an n-type semiconductor layer and is a conductive film having a thickness of about 0.05 to 3.0 ⁇ m.
  • the upper electrode layer 5 is used to satisfactorily extract carriers generated in the first semiconductor layer 3.
  • the upper electrode layer 5 has an electrical resistivity of 1 ⁇ ⁇ cm or less and a sheet resistance of 50 ⁇ / ⁇ . It may be the following.
  • the upper electrode layer 5 includes, for example, a metal oxide such as ZnO, In 2 O 3 , or SnO 2 , and any one of Al, B, Ga, In, Sn, F, etc. in order to reduce the electrical resistivity. These elements may be included. Specific examples of the metal oxide semiconductor containing such an element include, for example, AZO (Aluminum Zinc Oxide), BZO (Boron Zinc Oxide), GZO (Gallium Zinc Oxide), IZO (Indium Zinc Oxide), ITO ( Indium Tin Oxide) and FTO (Fluorine tin Oxide).
  • the upper electrode layer 5 is formed by sputtering, vapor deposition, CVD, or the like.
  • a metal such as gold, silver or copper may be used as the upper electrode layer 5.
  • the upper electrode layer 5 is made thin enough to transmit light, or a light-transmitting material is used as the lower electrode layer 2 and light can be incident on the first semiconductor layer 3 from the substrate 1 side. You may make it become.
  • a metal is used as the upper electrode layer 5 so that light can be incident from the substrate 1 side, the optical path length is extended by light reflection by the upper electrode layer 5, light absorption is improved, and conversion efficiency is improved. To do.
  • a collecting electrode 8 may be further formed on the upper electrode layer 5.
  • the collecting electrode 8 is for taking out the carriers generated in the first semiconductor layer 3 more satisfactorily.
  • the collector electrode 8 is formed in a linear shape from one end of the photoelectric conversion cell 10 to the connection conductor 7. As a result, the current generated in the first semiconductor layer 3 is collected by the current collecting electrode 8 via the upper electrode layer 5, and the adjacent photoelectric conversion cell 10 is successfully energized via the connection conductor 7.
  • the collecting electrode 8 may have a width of 50 to 400 ⁇ m from the viewpoint of increasing the light transmittance to the first semiconductor layer 3 and having good conductivity.
  • the current collecting electrode 8 may have a plurality of branched portions.
  • the current collecting electrode 8 is formed, for example, by printing a metal paste in which a metal powder such as Ag is dispersed in a resin binder or the like in a pattern and curing it.
  • connection conductor 7 is a conductor provided in the groove P2 that divides the first semiconductor layer 3, the buffer layer 4, and the upper electrode layer 5.
  • the connection conductor 7 can be made of metal, conductive paste, or the like.
  • the collector electrode 8 is extended to form the connection conductor 7, but the present invention is not limited to this.
  • the upper electrode layer 5 may be stretched.
  • FIG. 3 is a perspective view of the photoelectric conversion layer 21 of the second embodiment
  • FIG. 4 is a cross-sectional view thereof
  • FIG. 5 is a plan view of the photoelectric conversion device 21 in a state in which the first semiconductor layer 23 and the upper portion thereof are removed in order to make the planar structure of the intermediate layer 23a and the insulating layer 26 easier to see.
  • the same components as those of the photoelectric conversion device 11 of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the intermediate layer 23a partially covers the lower electrode layer 2 and is insulated on a portion of the lower electrode layer 2 that is not covered by the intermediate layer 23a.
  • Layer 26 is located.
  • the first semiconductor layer 23 is bonded to the intermediate layer 23 a and the insulating layer 26.
  • the insulating layer 26 functions as a passivation film, and field recombination on the surface of the first semiconductor layer 23 can be reduced by generating an electric field effect due to band bending. Further, in the portion where the lower electrode layer 2 and the first semiconductor layer 23 are joined via the intermediate layer 23 a, the intermediate layer 23 a can take out carriers from the first semiconductor layer 3 satisfactorily. As a result, the photoelectric conversion efficiency of the photoelectric conversion device 21 can be further improved.
  • the insulating layers 26 are dotted with a plurality of them in a plan view.
  • the insulating layer 26 is not limited to such a configuration.
  • a plurality of linear layers may be arranged at intervals.
  • the insulating layer 26 may have an electrical resistivity of 1 ⁇ ⁇ m or more.
  • Examples of the insulating layer 26 include metal oxides such as Al 2 O 3 , SiO 2 , ZrO 2 , MgO, and TiO 2 or heat resistant resins such as polyimide resins.
  • the adhesion between the lower electrode layer 2 and the first semiconductor layer 23 can be improved.
  • Al 2 O 3 in the insulating layer 6, SiO 2, ZrO 2, the content of MgO and TiO 2 is, Al 2 O 3, SiO 2 , ZrO 2, total mass of MgO and TiO 2 is an insulator layer 6 It is preferable to be 50% or more of the total mass.
  • the total mass of Al 2 O 3 , SiO 2 , ZrO 2 , MgO and TiO 2 is insulated. It is preferable to be 70% or more of the total mass of the layer 6.
  • the insulating layer 26 includes a polyimide resin
  • the flexibility of the insulating layer 26 is improved, and it becomes possible to reduce insulation failure (deterioration of the passivation function) due to cracks or the like of the insulating layer 26.
  • the insulating layer 26 functions as a stress relaxation layer between the first semiconductor layer 23 and the lower electrode 2, and also serves to reduce cracks and peeling of the first semiconductor layer 23.
  • the insulating layer 26 contains a polyimide resin
  • the total mass of the polyimide resin is 50% or more of the total mass of the insulating layer 26. From the viewpoint of further improving the flexibility and heat resistance of the insulating layer 26, it is preferable that the total mass of the polyimide resin is 70% or more of the total mass of the insulating layer 26.
  • the thickness of the insulating layer 26 may be about 15 to 200 nm. Further, from the viewpoint of further improving the photoelectric conversion efficiency by satisfactorily performing the passivation function and carrier extraction by the insulating layer 26, the junction area between the intermediate layer 23a and the first semiconductor layer 23 is the same as that of the insulating layer 26 and the first semiconductor layer 23. It may be 0.01 to 2 times the bonding area with one semiconductor layer 23.
  • the insulating layer 26 can be produced by using a deposition method such as a vapor deposition method, a sputtering method, a sol-gel method, a screen printing method, a coating method, a plating method, a spray coating method, an inkjet coating method, or an ALD method. If necessary, the insulating layer 26 can be formed into a desired pattern shape by combining a photolithography method, a lift-off method, a coating method using a dispenser, and a pattern forming method such as laser scribing.
  • a deposition method such as a vapor deposition method, a sputtering method, a sol-gel method, a screen printing method, a coating method, a plating method, a spray coating method, an inkjet coating method, or an ALD method. If necessary, the insulating layer 26 can be formed into a desired pattern shape by combining a photolithography method, a lift-off method, a coating method using a dispenser, and a
  • the quantity or size of the insulating layer 26 may be changed depending on the location. By doing so, the conversion efficiency of the photoelectric conversion device 21 can be increased by further increasing the effect of suppressing recombination corresponding to the composition of the first semiconductor layer 23 and the film thickness unevenness, or by reducing the resistance component as much as possible. Can be increased.
  • FIG. 6 is a perspective view of the photoelectric conversion layer 31 of the third embodiment
  • FIG. 7 is a sectional view thereof.
  • the same components as those of the photoelectric conversion device 11 of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • an insulating layer 36 that partially covers the intermediate layer 33 a is located at the interface between the intermediate layer 33 a and the first semiconductor layer 33.
  • the first semiconductor layer 33 is bonded to the intermediate layer 33 a and the insulating layer 36.
  • the insulating layer 36 functions as a passivation film, and it is possible to reduce carrier recombination on the surface of the first semiconductor layer 33 by generating an electric field effect due to band bending.
  • the intermediate layer 33 a can take out carriers from the first semiconductor layer 33 satisfactorily. As a result, the photoelectric conversion efficiency of the photoelectric conversion device 31 can be further improved.
  • the insulating layer 36 may be formed without performing pattern processing such as removal of the intermediate layer 33a. Therefore, the manufacturing process can be simplified.
  • the insulating layer 36 can have the same structure and the same material as the insulating layer 26 in the photoelectric conversion device 21 of the second embodiment.

Abstract

　本発明の一態様に係る光電変換装置は、電極層と、第１の半導体層と、第２の半導体層と、中間層とを具備する。第１の半導体層は、電極層上に位置している。第１の半導体層は、ｐ型またはｉ型であり、カルコパイライト系化合物またはペロブスカイト系化合物を主として含んでいる。第２の半導体層は、ｎ型であり、第１の半導体層上に位置している。中間層は、電極層および第１の半導体層の界面に位置している。中間層は、第１の半導体層とは異なる結晶構造のｐ型の半導体を主として含んでいる。さらに、中間層は、第１の半導体層よりもキャリア密度が高い。

Description

光電変換装置
　本発明は、化合物半導体層を具備する光電変換装置に関する。
　太陽光発電等に使用される光電変換装置として、カルコパイライト系化合物等から成る化合物半導体層を光吸収層として用いたものがある（例えば特許文献１参照）。このような光電変換装置は、複数の光電変換セルが平面的に並設された構成を有する。各光電変換セルは、ガラス等の基板の上に、金属電極等の下部電極と、ＣＩＧＳなどの金属カルコゲナイドを含む光吸収層と、この光吸収層にヘテロ接合した、硫化インジウムを含むバッファ層と、透明電極や金属電極等の上部電極とが、この順に積層されて構成されている。また、複数の光電変換セルは、隣り合う一方の光電変換セルの上部電極と他方の光電変換セルの下部電極とが接続導体によって電気的に接続されることで、電気的に直列に接続されている（特開２００３－２８２９０９号公報参照）。
　本発明の一態様に係る光電変換装置は、電極層と、第１の半導体層と、第２の半導体層と、中間層とを具備する。第１の半導体層は、電極層上に位置している。第１の半導体層は、ｐ型またはｉ型であり、カルコパイライト系化合物またはペロブスカイト系化合物を主として含んでいる。第２の半導体層は、ｎ型であり、第１の半導体層上に位置している。中間層は、電極層および第１の半導体層の界面に位置している。中間層は、第１の半導体層とは異なる結晶構造のｐ型の半導体を主として含んでいる。さらに、中間層は、第１の半導体層よりもキャリア密度が高い。
第１実施形態の光電変換装置を示す斜視図である。 図１の光電変換装置の断面図である。 第２実施形態の光電変換装置を示す斜視図である。 図３の光電変換装置の断面図である。 図３の光電変換装置の第１の半導体層およびそれよりも上側の部分を除いた平面図である。 第３実施形態の光電変換装置を示す斜視図である。 図６の光電変換装置の断面図である。
　以下に本開示の光電変換装置の実施形態について、図面を参照しながら詳細に説明する。
　＜第１実施形態の光電変換装置＞
　図１は、第１実施形態に係る光電変換装置を示す斜視図であり、図２はその断面図である。光電変換装置１１は、基板１上に複数の光電変換セル１０を具備している。これらの光電変換セル１０は、互いに間隔Ｐ３をあけて並んでおり、隣接する光電変換セル１０同士が互いに電気的に接続されている。なお、図１においては図示の都合上、２つの光電変換セル１０のみを示しているが、実際の光電変換装置１１においては、図面左右方向、あるいはさらにこれに垂直な方向に、多数の光電変換セル１０が平面的に（二次元的に）配設されていてもよい。
　図１、図２において、基板１上に複数の電極層２が平面配置されている。なお、以下の説明においては、第１の半導体層３側に接続された電極層２を、後述する上部電極層５と区別するため、下部電極層２として説明する。しかし、下部電極層２が、必ずしも上部電極層４よりも下側に位置している必要はなく、上側であってもよい。
　図１、図２において、複数の下部電極層２は、一方向に間隔Ｐ１をあけて並べられた下部電極層２ａ～２ｃを具備している。この下部電極層２ａ上から基板１上を経て下部電極層２ｂ上にかけて、第１の半導体層３、バッファ層４および上部電極層５が順に積層されている。さらに、下部電極層２ｂ上において、接続導体７が、第１の半導体層３およびバッファ層４側面に沿って、またはこれらを貫通して設けられている。この接続導体７は、上部電極層５と下部電極層２ｂとを電気的に接続している。また、下部電極層２と第１の半導体層３との界面には中間層３ａが介在している。これら下部電極層２、中間層３ａ、第１の半導体層３、バッファ層４および上部電極層５によって、１つの光電変換セル１０が構成され、隣接する光電変換セル１０同士が接続導体７を介して直列接続されることによって、高出力の光電変換装置１１となる。なお、本実施形態における光電変換装置１１は、上部電極層５側から第１の半導体層３へ光が入射されるものを想定しているが、これに限定されず、下部電極層２側から第１の半導体層３へ光が入射されるものであってもよい。
　基板１は、光電変換セル１０を支持するためのものである。基板１に用いられる材料としては、例えば、ガラス、セラミックス、樹脂および金属等が挙げられる。基板１としては、例えば、厚さ１～３ｍｍ程度の青板ガラス（ソーダライムガラス）を用いることができる。
　下部電極層２（下部電極層２ａ、２ｂ、２ｃ）は、基板１上に設けられた、Ｍｏ、Ａｌ、ＴｉまたはＡｕ等の導電体である。下部電極層２は、スパッタリング法または蒸着法などの公知の薄膜形成手法を用いて、０．２μｍ～１μｍ程度の厚みに形成される。
　第１の半導体層３は、光を吸収してキャリア（電子および正孔）を発生させる機能をする半導体層であり、いわゆる光吸収層である。第１の半導体層３は、例えば１μｍ～３μｍ程度の厚みのｐ型またはｉ型の半導体層である。また、第１の半導体層３は、カルコパイライト系化合物を主として含んでいるか、あるいはペロブスカイト系化合物を主として含んでいる。カルコパイライト系化合物を主として含むとは、カルコパイライト系化合物を７０ｍｏｌ％以上含むことをいう。また、ペロブスカイト系化合物を主として含むとは、ペロブスカイト系化合物を７０ｍｏｌ％以上含むことをいう。
　カルコパイライト系化合物とは、カルコパイライト構造を有する化合物であり、例えば、Ｉ－III－VI族化合物が挙げられる。Ｉ－III－VI族化合物とは、１１族元素（Ｉ－Ｂ族元素ともいう）と１３族元素（III－Ｂ族元素ともいう）と１６族元素との化合物である。Ｉ－III－VI族化合物としては、例えば、ＣｕＩｎＳｅ２（二セレン化銅インジウム、ＣＩＳともいう）、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ２（二セレン化銅インジウム・ガリウム、ＣＩＧＳともいう）、Ｃｕ（Ｉｎ，Ｇａ）（Ｓｅ，Ｓ）２（二セレン・イオウ化銅インジウム・ガリウム、ＣＩＧＳＳともいう）が挙げられる。あるいは、第１の半導体層３は、薄膜の二セレン・イオウ化銅インジウム・ガリウム層を表面層として有する二セレン化銅インジウム・ガリウム等の多元化合物半導体薄膜にて構成されていてもよい。
　ペロブスカイト系化合物とは、ペロブスカイト構造を有する化合物であり、例えばＣＨ３ＮＨ３ＰｂＸ３（Ｘはハロゲン元素である）等の有機無機複合材料が挙げられる。なお、有機無機複合材料とは、分子レベルで有機成分と無機成分とが複合された材料である。また、ＡＰｂＸ３（ＡはＣｓなどのアルカリ金属元素、Ｘはハロゲン元素である）のような有機物を含まない構造も、ペロブスカイト系化合物には含まれる。本開示に含まれる材料としては、Ｐｂを含み、ハロゲン元素でＸが構成されているペロブスカイト系化合物が好適に用いられる。さらには、Ｘで表したハロゲン元素は、２種類以上の元素が含まれても良く、ＣＨ３ＮＨ３などの有機物や、Ｃｓなどのアルカリ金属も、２種類以上の元素が含まれても良い。このように材料を多く混ぜることで、所望のバンドギャップや、耐熱性、耐電圧性が得られるようになり、タンデム化に適したペロブスカイト系太陽電池や、プロセスの自由度が高い、かつ長期信頼性に優れた太陽電池を得ることができるようになる。
　第１の半導体層３は、スパッタリング法、蒸着法などのいわゆる真空プロセスによって形成可能であるほか、いわゆる塗布法あるいは印刷法と称されるプロセスによって形成することもできる。塗布法あるいは印刷法と称されるプロセスは、第１の半導体層３の構成元素の錯体溶液を中間層３ａまたは下部電極層２の上に塗布し、その後、乾燥・熱処理を行うプロセスである。
　中間層３ａは、下部電極層２と第１の半導体層３との界面に位置している。つまり、第１の半導体層３は中間層３ａを介して下部電極層２と電気的に接続されている。中間層３ａは、第１の半導体層３とは異なる結晶構造を有するｐ型の半導体から成り、第１の半導体層３よりもキャリア密度が高い。また、中間層３ａは３０～２０００ｎｍ程度の厚みを有する。
　このような構成によって、第１の半導体層３の光電変換によって生じたキャリアの再結合を低減し、光電変換装置１１の光電変換効率を向上させることができる。つまり、第１の半導体層３で電荷分離したキャリアに対し、中間層３ａによって強い電界をかけてキャリアを引き抜く効果を強めることができる。その結果、キャリアの再結合を低減して変換効率を高めることができる。
　ここで、カルコパイライト系化合物およびペロブスカイト系化合物はドーパントの制御が難しく、欠陥の少ない状態でキャリア密度を所望の濃度に制御するのが難しい。そのため、第１の半導体層３のキャリア密度は、欠陥による再結合を顕在化させないように例えば１×１０１０～９×１０１７ｃｍ－３程度以下としてもよい。そして、中間層３ａは、第１の半導体層３よりもキャリア密度が例えば１×１０１８～９×１０１８ｃｍ－３と高くなっているので、電荷分離したキャリアを第１の半導体層３から引き抜き易くすることができる。このような中間層３ａとしては、欠陥の少ない状態でドーパントの制御が容易であるという観点から、第１の半導体層３とは異なる結晶構造を有するｐ型の半導体が用いられる。
　このような中間層３ａとしては、ホウ素（Ｂ）等の他の元素をドーピングしたシリコン（Ｓｉ）を主として含む半導体等が挙げられる。なお、Ｓｉを主として含むとは、Ｓｉを７０ｍｏｌ％以上含むことをいう。また、他の中間層３ａとしては、第１の半導体層３と接合し易いセレン化亜鉛等の化合物半導体を用いてもよい。
　中間層３ａは、蒸着法、スパッタリング法、ゾルゲル法、スクリーン印刷法、塗布法、めっき法、スプレー塗布法、インクジェット塗布法、ＣＶＤ法、プラズマＣＶＤ法、ＰＶＤ法等の成膜方法を用いて作製することができる。また、必要に応じて、フォトリソグラフィー法、リフトオフ法、ディスペンサーを用いた塗布法、レーザスクライブ等のパターン形成法を組み合わせることによって、中間層３ａを所望のパターン形状にしてもよい。
　第２の半導体層は、第１の半導体層３と異なるｎ型の導電型を有する半導体層であり、第１の半導体層３とｐｎ接合を形成する。第１実施形態の光電変換装置１１では、第２の半導体層がバッファ層４と上部電極層５との積層体である例を示すが、これに限定されず、１層だけでもよく、３層以上の積層体であってもよい。第２の半導体層が複数層から成る場合、その複数層のうちの少なくとも１層がｎ型であればよい。つまり、第２の半導体層は、ｎ型の半導体層とｉ型の半導体層の積層体であってもよく、ｎ型の半導体層の積層体であってもよい。
　バッファ層４は、第１の半導体層３にヘテロ接合された、ｎ型またはｉ型の半導体層である。バッファ層４は、例えば５～２００ｎｍの厚みを有している。バッファ層４としては、例えば、ＣｄＳ、ＺｎＳ、Ｉｎ２Ｓ３等の金属硫化物が用いられる。なお、バッファ層４は、このような金属硫化物に加えて、金属酸化物および金属水酸化物の少なくとも一方を含む混晶であってもよい。バッファ層４は、例えば溶液析出法（ＣＢＤ法）、ＡＬＤ法、ＭＯＣＶＤ法などで形成される。
　また、第１の半導体層３がペロブスカイト系化合物を主として含む場合には、バッファ層４として、ｎ型の有機半導体を用いてもよい。このような有機半導体としては、フェニル－Ｃ６１－酪酸メチルエステル（ＰＣＢＭ）およびフラーレンＣ６０等のフラーレン誘導体等が挙げられる。バッファ層４として有機半導体を用いる場合、例えば、ＰＣＢＭ等を有機溶剤に溶解させ、この溶液を第１の半導体層３上に塗布した後、乾燥することによってバッファ層４を形成できる。もしくは、フラーレンＣ６０等を第１の半導体層３上に蒸着することによってバッファ層４を形成してもよい。また、第１の半導体層３またはバッファ層４に対して、後述する上部電極層５を形成する際のプロセスの影響を受けにくくするため、バッファ層４の上に、さらに保護用バッファ層を積層しても良い。この保護用バッファ層としては、酸化モリブデンおよび酸化タングステンなどが挙げられる。このような保護用バッファ層はスパッタリング法や蒸着法等で形成することができる。
　上部電極層５は、ｎ型の半導体層であり、０．０５～３．０μｍ程度の厚みの導電膜である。上部電極層５は、第１の半導体層３で生じたキャリアを良好に取り出すためのものであり、例えば、上部電極層５の電気抵抗率は１Ω・ｃｍ以下であり、シート抵抗は５０Ω／□以下であってもよい。
　上部電極層５は、例えば、ＺｎＯやＩｎ２Ｏ３、ＳｎＯ２等の金属酸化物を含み、電気抵抗率を低くするために、Ａｌ、Ｂ、Ｇａ、Ｉｎ、ＳｎおよびＦ等のうちの何れかの元素が含まれても良い。このような元素が含まれた金属酸化物半導体の具体例としては、例えば、ＡＺＯ（Aluminum Zinc Oxide）、ＢＺＯ（Boron Zinc Oxide）、ＧＺＯ（Gallium Zinc Oxide）、ＩＺＯ（Indium Zinc Oxide）、ＩＴＯ（Indium Tin Oxide）、ＦＴＯ（Fluorine tin Oxide）等がある。上部電極層５は、スパッタリング法、蒸着法またはＣＶＤ法等で形成される。
　また、バッファ層４としてｎ型の有機半導体を用いる場合、上部電極層５として、金、銀または銅等の金属を用いても良い。この場合、光が透過する程度に上部電極層５を薄くするか、あるいは、下部電極層２として光透過性の材料を採用するとともに、基板１側から第１の半導体層３に光が入射可能となるようにしてもよい。このように上部電極層５として金属を用い、基板１側から光が入射可能となるようにした場合、上部電極層５による光反射で光路長が延び、光吸収が改善されて変換効率が向上する。
　また、図１、図２に示すように、上部電極層５上にさらに集電電極８が形成されていてもよい。集電電極８は、第１の半導体層３で生じたキャリアをさらに良好に取り出すためのものである。集電電極８は、例えば、図１に示すように、光電変換セル１０の一端から接続導体７にかけて線状に形成されている。これにより、第１の半導体層３で生じた電流が上部電極層５を介して集電電極８に集電され、接続導体７を介して隣接する光電変換セル１０に良好に通電される。
　集電電極８は、第１の半導体層３への光透過率を高めるとともに良好な導電性を有するという観点から、５０～４００μｍの幅を有していてもよい。また、集電電極８は、枝分かれした複数の分岐部を有していてもよい。
　集電電極８は、例えば、Ａｇ等の金属粉を樹脂バインダー等に分散させた金属ペーストがパターン状に印刷され、これが硬化されることによって形成される。
　図１、図２において、接続導体７は、第１の半導体層３、バッファ層４および上部電極層５を分断する溝Ｐ２内に設けられた導体である。接続導体７は、金属や導電ペースト等が用いられ得る。図１、図２においては、集電電極８を延伸して接続導体７が形成されているが、これに限定されない。例えば、上部電極層５が延伸したものであってもよい。
　なお、本発明は上述の実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更、改良などが可能である。以下に種々の変形例を示す。
　＜第２実施形態の光電変換装置＞
　図３は、第２実施形態の光電変換層２１の斜視図であり、図４はその断面図である。また、図５は、中間層２３ａおよび絶縁層２６の平面視構造を見やすくするため、光電変換装置２１における第１の半導体層２３およびそれよりも上側の部分を除いた状態における平面図である。第２実施形態の光電変換装置２１において、第１実施形態の光電変換装置１１と同じ構成のものには同じ符号を付しており、詳細な説明は省略する。
　第２実施形態の光電変換装置２１における各光電変換セル２０は、中間層２３ａが下部電極層２を部分的に覆っており、下部電極層２の中間層２３ａに覆われていない部位上に絶縁層２６が位置している。そして、第１の半導体層２３は、中間層２３ａと絶縁層２６とに接合している。
　このような構成によって、絶縁層２６がパッシベーション膜として機能し、バンドベンディングによる電界効果を生じさせることによって第１の半導体層２３の表面でのキャリアの再結合を低減できる。また、中間層２３ａを介して下部電極層２と第１の半導体層２３とが接合している部分においては、中間層２３ａが第１の半導体層３からキャリアを良好に取り出すことができる。以上の結果、光電変換装置２１の光電変換効率をさらに向上させることができる。
　絶縁層２６は、図５に示すように、平面視において、複数のものが互いに間隔をあけて点在している。絶縁層２６は、このような構成に限定されず、例えば、複数の線状のものが互いに間隔をあけて並んだものであってもよい。
　絶縁層２６は電気抵抗率が１Ω・ｍ以上のものが用いられ得る。このような絶縁層２６としては、Ａｌ２Ｏ３、ＳｉＯ２、ＺｒＯ２、ＭｇＯおよびＴｉＯ２の等の金属酸化物またはポリイミド樹脂等の耐熱性樹脂が挙げられる。
　絶縁層６がＡｌ２Ｏ３、ＳｉＯ２、ＺｒＯ２、ＭｇＯおよびＴｉＯ２の少なくとも一種を含む場合、下部電極層２と第１の半導体層２３との密着性を高めることができる。この場合、絶縁層６におけるＡｌ２Ｏ３、ＳｉＯ２、ＺｒＯ２、ＭｇＯおよびＴｉＯ２の含有量は、Ａｌ２Ｏ３、ＳｉＯ２、ＺｒＯ２、ＭｇＯおよびＴｉＯ２の質量合計が絶縁層６の全質量の５０％以上となるようにするのが好ましい。下部電極層２と第１の半導体層２３との密着性および絶縁層２６の耐熱性をより高めるという観点からは、Ａｌ２Ｏ３、ＳｉＯ２、ＺｒＯ２、ＭｇＯおよびＴｉＯ２の質量合計が絶縁層６の全質量の７０％以上となるようにするのが好ましい。
　また、絶縁層２６がポリイミド樹脂を含む場合、絶縁層２６の柔軟性が向上し、絶縁層２６のクラックなどによる絶縁不良（パッシベーション機能の低下）を低減させることが可能となる。更に、絶縁層２６が第１の半導体層２３と下部電極２との間の応力緩和層として作用し、第１の半導体層２３のクラックや剥離を軽減する役割もする。また、パターン形状の絶縁層２６を形成する際、インクジェット塗布法等で容易に行なうことができ、生産性も向上する。なお、絶縁層２６がポリイミド樹脂を含む場合、ポリイミド樹脂の質量合計が絶縁層２６の全質量の５０％以上となるようにするのが好ましい。絶縁層２６の柔軟性および耐熱性をより高めるという観点からは、ポリイミド樹脂の質量合計が絶縁層２６の全質量の７０％以上となるようにするのが好ましい。
　また、絶縁層２６の厚みは１５～２００ｎｍ程度であればよい。また、絶縁層２６によるパッシベーション機能とキャリアの取り出しとを良好に行なって光電変換効率をさらに高めるという観点からは、中間層２３ａと第１の半導体層２３との接合面積は、絶縁層２６と第１の半導体層２３との接合面積の０．０１～２倍であってもよい。
　絶縁層２６は、蒸着法、スパッタリング法、ゾルゲル法、スクリーン印刷法、塗布法、めっき法、スプレー塗布法、インクジェット塗布法、ＡＬＤ法等の成膜方法を用いて作製することができる。また、必要に応じて、フォトリソグラフィー法、リフトオフ法、ディスペンサーを用いた塗布法、レーザスクライブ等のパターン形成法を組み合わせることによって、絶縁層２６を所望のパターン形状にすることができる。
　絶縁層２６は、数量やサイズなどを場所によって変更しても良い。このようにすることで、第１の半導体層２３の組成や膜厚ムラなどに対応して再結合抑制の効果をさらに高めたり、抵抗成分を極力小さくすることで光電変換装置２１の変換効率を高めることができる。
　＜第３実施形態の光電変換装置＞
　図６は、第３実施形態の光電変換層３１の斜視図であり、図７はその断面図である。第３実施形態の光電変換装置３１において、第１実施形態の光電変換装置１１と同じ構成のものには同じ符号を付しており、詳細な説明は省略する。
　第３実施形態の光電変換装置３１における各光電変換セル３０は、中間層３３ａと第１の半導体層３３との界面に、中間層３３ａを部分的に覆う絶縁層３６が位置している。そして、第１の半導体層３３は中間層３３ａと絶縁層３６とに接合している。
　このような構成によって、絶縁層３６がパッシベーション膜として機能し、バンドベンディングによる電界効果を生じさせることによって第１の半導体層３３の表面でのキャリアの再結合を低減できる。また、絶縁層３６の非形成部においては、中間層３３ａが第１の半導体層３３からキャリアを良好に取り出すことができる。以上の結果、光電変換装置３１の光電変換効率をさらに向上させることができる。
　また、第３実施形態の光電変換装置３１では、中間層３３ａを下部電極層２上の全面に形成した後、中間層３３ａの除去等のパターン加工をすることなく絶縁層３６を形成すればよいので、製造工程が簡略化できる。
　絶縁層３６は、第２実施形態の光電変換装置２１における絶縁層２６と同様の構造および同様の材料とすることができる。
　２、２ａ、２ｂ、２ｃ：下部電極層
　３、２３、３３：第１の半導体層
　３ａ、２３ａ、３３ａ：中間層
　４：バッファ層
　５：上部電極層
　２６、３６：絶縁層
　１１、２１、３１：光電変換装置

Claims (7)

  1. 　電極層と、
    該電極層上に位置するカルコパイライト系化合物またはペロブスカイト系化合物を主として含む、ｐ型またはｉ型の第１の半導体層と、
    該第１の半導体層上に位置するｎ型の第２の半導体層と、
    前記電極層および前記第１の半導体層の界面に位置しており、前記第１の半導体層とは異なる結晶構造のｐ型の半導体を主として含み、前記第１の半導体層よりもキャリア密度の高い中間層と
    を具備する光電変換装置。
  2. 　前記中間層はシリコンを主として含んでいる、請求項２に記載の光電変換装置。
  3. 　前記第１の半導体層のキャリア密度が１×１０１０～９×１０１７ｃｍ－３であり、前記中間層のキャリア密度が１×１０１８～９×１０１８ｃｍ－３である、請求項１または２に記載の光電変換装置。
  4. 　前記中間層は前記電極層を部分的に覆っており、
    前記電極層の前記中間層に覆われていない部位上に位置する絶縁層をさらに具備し、前記第１の半導体層は前記中間層と前記絶縁層とに接合している、請求項１乃至３のいずれかに記載の光電変換装置。
  5. 　前記中間層と前記第１の半導体層との界面に前記中間層を部分的に覆う絶縁層をさらに具備し、
    前記第１の半導体層は前記中間層と前記絶縁層とに接合している、請求項１乃至３のいずれかに記載の光電変換装置。
  6. 　前記絶縁層の電気抵抗率が１Ω・ｍ以上である、請求項４または５に記載の光電変換装置。
  7. 　前記中間層と前記第１の半導体層との接合面積は、前記絶縁層と前記第１の半導体層との接合面積の０．０１～２倍である、請求項４乃至６のいずれかに記載の光電変換装置。
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JPH09219530A (ja) * 1996-02-08 1997-08-19 Matsushita Electric Ind Co Ltd カルコパイライト構造半導体薄膜太陽電池及びその製造方法
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