WO2016150385A1 - 一种基于fpga和dsp的气体超声流量计及其测量方法 - Google Patents

一种基于fpga和dsp的气体超声流量计及其测量方法 Download PDF

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Publication number
WO2016150385A1
WO2016150385A1 PCT/CN2016/077122 CN2016077122W WO2016150385A1 WO 2016150385 A1 WO2016150385 A1 WO 2016150385A1 CN 2016077122 W CN2016077122 W CN 2016077122W WO 2016150385 A1 WO2016150385 A1 WO 2016150385A1
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circuit
signal
module
fpga
chip
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PCT/CN2016/077122
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English (en)
French (fr)
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徐科军
方敏
汪伟
朱文姣
沈子文
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合肥工业大学
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Publication of WO2016150385A1 publication Critical patent/WO2016150385A1/zh
Priority to US15/688,898 priority Critical patent/US10088348B2/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
    • G01F1/66—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by measuring frequency, phase shift or propagation time of electromagnetic or other waves, e.g. using ultrasonic flowmeters
    • G01F1/667—Arrangements of transducers for ultrasonic flowmeters; Circuits for operating ultrasonic flowmeters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
    • G01F1/66—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by measuring frequency, phase shift or propagation time of electromagnetic or other waves, e.g. using ultrasonic flowmeters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
    • G01F1/66—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by measuring frequency, phase shift or propagation time of electromagnetic or other waves, e.g. using ultrasonic flowmeters
    • G01F1/662—Constructional details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
    • G01F1/74—Devices for measuring flow of a fluid or flow of a fluent solid material in suspension in another fluid
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/02—Analysing fluids
    • G01N29/024—Analysing fluids by measuring propagation velocity or propagation time of acoustic waves
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/02—Analysing fluids
    • G01N29/032—Analysing fluids by measuring attenuation of acoustic waves
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/22—Details, e.g. general constructional or apparatus details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/22—Details, e.g. general constructional or apparatus details
    • G01N29/222—Constructional or flow details for analysing fluids
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N2291/00—Indexing codes associated with group G01N29/00
    • G01N2291/02—Indexing codes associated with the analysed material
    • G01N2291/028—Material parameters
    • G01N2291/02836—Flow rate, liquid level
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N2291/00—Indexing codes associated with group G01N29/00
    • G01N2291/10—Number of transducers
    • G01N2291/105—Number of transducers two or more emitters, two or more receivers

Definitions

  • the invention relates to the field of flow measurement, and relates to a gas ultrasonic flowmeter, in particular to a dual core architecture based on an FPGA chip and a DSP chip, which is capable of tracking the highest peak value of an echo signal for an ultrasonic echo signal generated by sinusoidal excitation.
  • a variable-threshold method combined with a gas-ultrasonic flowmeter with a zero-crossing detection method.
  • Gas ultrasonic flowmeters have unique advantages in terms of metering accuracy, reliability, pressure loss, maintenance cost, and manufacturing cost compared to other gas flow meters (such as orifice plates, turbine flow meters, etc.), especially in medium and large calibers.
  • the superiority of pipeline flow measurement is more obvious.
  • the gas-time ultrasonic flowmeter with the propagation time difference is the most widely used.
  • the gas ultrasonic flowmeter consists of two parts, one is the transducer and the sensor part, including one or more pairs of ultrasonic transducers, pressure sensors and temperature sensors; the other is the transmitter, including the generation and conditioning of the drive signal, The conditioning and digital processing part of the echo signal, as well as the human-computer interaction part.
  • the key to the development of gas ultrasonic flowmeter is to select the appropriate ultrasonic drive signal, and overcome the influence of the mixed noise signal in the echo signal, and then obtain the propagation of the ultrasonic downstream and countercurrent according to a certain stable characteristic point of the echo signal. time.
  • the signal applied to the transmitting ultrasonic transducer is defined as the driving signal, and the ultrasonic transducer transmits the ultrasonic wave; the receiving ultrasonic transducer receives the ultrasonic wave, and the signal output by the receiving ultrasonic transducer is the echo signal.
  • the ultrasonic transducer can be used both as a transmitter and as a receiver, and its function is controlled by a transmit/receive signal channel switching circuit.
  • United States Daniel Corporation uses a method for detecting energy mutations to find feature points (William Freund, Winsor Letton, James Mc-Clellan, Baocang Jia, Anni Wey, Wen Chang. Method and apparatus for measuring the time of flight of a signal, US patent NO.5983730, Nov. 16, 1999). Since the energy of the echo signal experiences a process from weak to strong and then from strong to weak, the energy change rate of the echo signal will first increase and then decrease, and the ultrasonic propagation can be determined according to the critical change point of the energy change rate. time. Specifically, this method first obtains the square of the amplitude of each point of the echo signal, and the magnitude of the square of the amplitude characterizes the magnitude of the signal energy.
  • the average energy of each point is obtained, and then the curve of the ratio of the average energy of the two points before and after, that is, the curve of the energy change rate is plotted. Finally, the ultrasonic propagation time is determined by the critical point of the rate of change of energy.
  • the key technologies in the implementation process such as the time interval of the sliding window, and the time interval between the first and last points when the energy change rate is obtained, are not disclosed.
  • the flow measurement is achieved by monitoring the ultrasonic echo signal to phase change in the process from scratch. First, find the maximum amplitude of the echo signal, and obtain the phase information of the signal by Hilbert's change calculation. Take the time corresponding to the maximum amplitude point of the echo signal as the starting point and look forward to the time when the phase stops continuously. Point, the point of phase change. Through this phase abrupt point, the first zero crossing of the echo signal is determined, and the ultrasonic propagation time is obtained.
  • this method is computationally intensive and susceptible to on-site noise, making it inconvenient for industrial sites. Practical application.
  • Instromet of the Netherlands employs a method of shift superposition (Eduard Johannes Botter. Ultrasonic signal processing method and applications thereof, US patent No. 7254494 B2, Aug. 7, 2007).
  • the method firstly transmits the driving signals 8 times in succession according to a certain time interval to obtain corresponding 8 sets of echo signals, and then shifts the 8 sets of echo signals according to a preset time to enhance the echo signals.
  • the noise signals due to their randomness, cancel each other and attenuate during the superposition process.
  • the ultrasonic propagation time is obtained by the method of threshold detection.
  • the method utilizes the time domain characteristics of the echo signal and the noise signal to effectively improve the signal to noise ratio.
  • repeated transmission of the ultrasonic drive signal prolongs the measurement time of the system and affects the dynamic response of the flowmeter. When the flow rate is abrupt, a large measurement error will occur.
  • the cross-correlation and the derivative method can be used to calculate the propagation time difference of the ultrasonic waves.
  • the traditional cross-correlation calculation is as shown in equation (1), in which it is assumed that the echo signal generated in the forward flow is x(t), and the echo generated in the reverse current is y(t), then R xy ( ⁇ ) is obtained.
  • the time shift ⁇ corresponding to the maximum value is the difference between the forward flow and the reverse flow propagation time.
  • the traditional cross-correlation method has a large amount of computation, and it is difficult to realize real-time implementation by using the limited resources of the single chip microcomputer.
  • Keiso Co., Ltd. of Japan adopted a cross-correlation derivative algorithm (Tokio Sugl, Tadao Sasaki. Ultrasonic flow meter, US patent NO. 007299150B1, Nov. 20, 2007), such as Equation (2), where m is the number of shift steps and N is the number of sampling points. Then, the number of shift steps corresponding to the maximum value of S xy (m) represents the difference between the forward and reverse current propagation times. .
  • this cross-correlation derivative algorithm replaces the multiplication operation in the original cross-correlation algorithm with the addition modulo operation, reducing the amount of computation. However, it also brings measurement errors, especially when the noise interference is large, and there is a high possibility of calculation errors.
  • Siemens AG, Germany uses a combination of zero-crossing detection and cross-correlation to calculate the absolute propagation time of ultrasonic downstream and countercurrent (Arthur Freund, Nils Kroemer. Method for measuring the time of flight of electric, electromagnetic or acoustic signals, EP Patent No.0797105A2, Mar.17, 1997), firstly obtain a segment of echo signal without noise by some method, assuming that its starting time is t 0 , and select one of the echo signals Zero point, the time interval of the zero crossing from the starting time t 0 is denoted as t N . Then, the echo signal of the segment is cross-correlated with the echo signal actually collected by the transducer.
  • the propagation time of the echo signal is:
  • t korr is the correction time, which includes the transducer conversion delay and the circuit transmission delay.
  • This method is capable of reliably detecting an echo signal from a received waveform mixed with a noisy signal, and is suitable for a noisy industrial site due to its high amplitude resolution near the zero crossing.
  • the patent does not disclose how to obtain an echo signal without noise, and at the same time, there are problems such as a large amount of cross-correlation calculation.
  • the present invention provides a gas ultrasonic flowmeter based on FPGA and DSP.
  • a gas ultrasonic flowmeter transmitter based on FPGA and DSP consists of gas ultrasonic transducer and sensor unit, transmitting/receiving signal channel switching circuit, driving signal generating and amplifying circuit, echo signal conditioning and collecting circuit, timing control and Signal processing circuit, man-machine interface, serial communication and power management module.
  • the gas ultrasonic transducer and sensor unit are composed of four transducers, a pressure sensor and a temperature sensor, respectively, which are fixed on a pipeline for conveying gas; each transduction
  • the device is both a transmitting transducer and a receiving transducer;
  • the transmitting/receiving signal channel switching circuit is composed of an excitation gating circuit, a transformer amplifying circuit and four echo gate circuit units; four echo gating devices
  • the circuit units are circuit units of the same structure and are respectively connected to four transducers.
  • the driving signal generating and amplifying circuit is composed of a high speed DAC signal generating and output circuit, a driving signal voltage amplifying and a power amplifying circuit.
  • the echo signal conditioning and acquisition circuit is composed of a voltage amplifying circuit, a band pass filter circuit, a self-gain control circuit, a single-ended signal-to-differential signal circuit, a bias circuit, and a high-speed ADC signal acquisition and conversion circuit.
  • the timing control and signal processing circuit is composed of an FPGA circuit system and a DSP circuit system, wherein the FPGA circuit system is mainly composed of an FPGA chip, an FPGA chip serial configurator circuit, and an FPGA chip reset and configuration button circuit; the DSP circuit system is mainly It consists of a DSP chip and a DSP chip boot mode selection circuit.
  • the FPGA chip is used for temporarily storing the converted code value transmitted by the driving signal generating and amplifying circuit, and when the delay time is determined, and transmitted to the DSP chip;
  • the DSP chip is the main control chip, and is responsible for digital signal processing and human-computer interaction. Serial communication, and with the FPGA circuit system to complete the timing control of the whole system;
  • the DSP chip uses digital filtering to eliminate the mixed noise in the signal, and uses the variable threshold zero-crossing detection method to track the maximum peak value of the echo signal to calculate the ultrasonic echo The propagation time, in turn, the gas flow.
  • the control method of the gas ultrasonic flowmeter transmitter based on FPGA and DSP is implemented by a main monitoring program and each program module;
  • the main monitoring program is a total scheduling program, and each program module is an initialization module, a watchdog module, and an iron An electric reading and writing module, a channel switching module, a communication module, an FPGA data transmission module, a pulse output module, an interrupt module, a calculation module and a display module;
  • the main monitoring program implements the gas ultrasonic flowmeter transmitter by mobilizing each program module Various functions.
  • the DSP chip After the circuit system is powered on, the DSP chip completes the initialization of each part: including allocating the GPIO port of the DSP chip, interrupting the initialization of the internal timer 1 of the DSP chip, initializing the liquid crystal display module, and reading the accumulated flow from the FRAM read/write module.
  • the parameters of the meter are initialized, and four queues are established, each queue consisting of 50 data slots for storing the propagation time of the ultrasonic waves received by the four transducers (hereinafter referred to as propagation time); whenever there is one
  • propagation time the propagation time of the ultrasonic waves received by the four transducers
  • the program enters the flow detection loop; first, the DSP chip switches the transducer transmit and receive channels by changing the output state of the corresponding GPIO port.
  • the order of switching channels is: the first transducer 1 emits a third The transducer 3 receives; the second transducer 2 transmits the fourth transducer 4 to receive; the third transducer 3 transmits the first transducer 1 to receive; the fourth transducer 4 transmits the second transducer 2 to receive.
  • the above switching process is continuously cycled; after switching the channel, the FPGA chip is notified to start measurement, and the DSP chip needs to wait for the FPGA chip to complete the signal reception.
  • the DSP chip sends a “start measurement” signal to the FPGA chip, and the FPGA chip immediately enables the internal delay module, and simultaneously calls the waveform data stored in the ROM module inside the FPGA chip, and transmits the waveform data to the driving signal generation and amplification circuit; a controlled transmit/receive signal channel switching circuit that outputs to the first transducer 1 of the direct-channel two-channel structure, or the second transducer 2, or the third transducer 3, or the fourth transducer 4, The ultrasonic wave is emitted by the first transducer 1, the second transducer 2, or the third transducer 3, or the fourth transducer 4; after a period of transit, the ultrasonic wave reaches the corresponding receiving transducer; Receiving ultrasonic waves by the third transducer 3, or the fourth transducer 4, or the first transducer 1, or the second transducer 2, forming an echo signal; transmitting/receiving signal channel switching controlled by the DSP chip The circuit receives the echo signal sent by the transducer and inputs it
  • the data stored in the RAM_2PORT module inside the FPGA chip is copied to the on-chip RAM of the DSP chip for digital signal processing by the DSP chip.
  • DSP chip processes the data and calculates the propagation time of the ultrasonic wave
  • the DSP chip processes the copied data, and calculates the propagation time T of each ultrasonic wave
  • t' is a fixed deviation value, which is calculated in the case of zero flow rate
  • step (2) switching different transmit transducers and receiving transducers in step (2), so that the propagation time of each channel downstream and countercurrent signals can be continuously measured in sequence; thus, the loop is completed four times, and the double sound is completed.
  • the measurement of the downstream and countercurrent propagation time is performed, and the four propagation times are respectively placed in the four queues established in the step (1).
  • Q is the instantaneous flow rate
  • D is the pipe diameter
  • L is the channel length
  • ⁇ is the angle of the channel angle
  • the channel angle is the angle between the ultrasonic propagation path and the pipe axis
  • t s , t n ⁇ t is the downstream propagation time, the countercurrent propagation time, and their time difference, respectively
  • k f is the meter factor.
  • the cumulative flow is calculated by the interrupt service routine of the internal timer 1 of the DSP chip.
  • the quantity is guaranteed to be accumulated once in 1 second, that is, the timer interrupt is generated by the internal timer 1 of the DSP chip, and the period is 1 second;
  • the timer interrupt service program first reads the instantaneous flow result calculated by the main monitoring program, and accumulates the accumulated flow. And then update the parameters of the pulse output module according to the value of the instantaneous flow rate, output a pulse of a certain frequency, indicating the measured instantaneous flow rate; then, set the timer time flag to 1 to update the liquid crystal display in the main monitoring program and perform the upper position Machine communication.
  • the beneficial technical effect of the invention is: based on the dual core of the FPGA chip and the DSP chip, the high-frequency output of the driving signal and the high-speed sampling of the echo signal are realized, and the digital signal processing method is realized in real time, and the calculation precision of the propagation time is improved. It enhances the anti-interference ability of the system and meets the needs of industrial field applications.
  • Figure 1 is a system hardware block diagram
  • Figure 2 is a schematic diagram of a high speed DAC signal generation and output circuit
  • Figure 3 is a schematic diagram of a driving signal voltage amplification and power amplifying circuit
  • Figure 4 is a schematic diagram of the excitation gating and transformer amplifying circuit
  • Figure 5 is a schematic diagram of an echo gate circuit
  • Figure 6 is a schematic diagram of a voltage amplifying circuit
  • Figure 7 is a schematic diagram of a band pass filter circuit
  • Figure 8 is a schematic diagram of a self-gain control circuit
  • Figure 9 is a schematic diagram of a single-ended signal-to-differential signal circuit
  • Figure 10 is a schematic diagram of a bias circuit
  • Figure 11 is a schematic diagram of a high speed ADC signal acquisition and conversion circuit
  • FIG. 12 is a schematic diagram of an I/O interface of an FPGA chip (EP2C8Q208C8N) sub-module;
  • FIG. 13 is a schematic diagram of the I/O voltage and reference voltage of the FPGA chip (EP2C8Q208C8N) sub-module;
  • Figure 14 is a sub-module of the FPGA chip (EP2C8Q208C8N) - core voltage and ground schematic;
  • FIG. 15 is a schematic diagram of the clock input of the FPGA chip (EP2C8Q208C8N) sub-module;
  • Figure 16 is a schematic diagram of the FPGA chip (EP2C8Q208C8N) sub-module - simulation interface;
  • FIG. 17 is a schematic diagram of a FPGA chip serial configurator circuit
  • Figure 18 is a schematic diagram of the FPGA chip reset and configuration button circuit
  • Figure 19 is a schematic diagram of a DSP chip circuit
  • 20 is a schematic diagram of a DSP chip boot mode selection circuit
  • 21 is a schematic diagram of functional modules of a timing control and signal processing circuit
  • Figure 22 is a general block diagram of the software
  • Figure 23 is a flow chart of the main monitoring program
  • Figure 24 is a waveform diagram of an echo signal
  • Figure 25 is a comparison diagram of ultrasonic signal waveforms at different flow rates
  • Figure 26 is a linear interpolation calculation zero crossing
  • Figure 27 is a schematic diagram of the "step" that occurs when an error is calculated
  • Figure 28 is a flow chart of the timer interrupt service routine.
  • the hardware system of the present invention comprises a gas ultrasonic transducer and a sensor unit, a transmitting/receiving signal channel switching circuit, a driving signal generating and amplifying circuit, an echo signal conditioning and collecting circuit, a timing control and a signal processing circuit, and a human
  • the machine interface, serial communication and power management module are composed.
  • the gas ultrasonic transducer and sensor unit are composed of four transducers, a pressure sensor and a temperature sensor, and are respectively fixedly mounted on the pipeline for conveying gas flow; the four transducers are the first transducer 1, and the second transducer
  • the energy converter 2, the third transducer 3 and the fourth transducer 4 are formed as a direct-acting two-channel structure; each transducer is both a transmitting transducer and a receiving transducer.
  • the transmitting/receiving signal channel switching circuit is composed of an excitation gating circuit, a transformer amplifying circuit and an echo gating circuit.
  • the driving signal generating and amplifying circuit is composed of a high speed DAC signal generating and output circuit, a driving signal voltage amplifying and a power amplifying circuit.
  • the echo signal conditioning and acquisition circuit is composed of a voltage amplifying circuit, a band pass filter circuit, a self-gain control circuit, a single-ended signal-to-differential signal circuit, a bias circuit, and a high-speed ADC signal acquisition and conversion circuit.
  • the timing control and signal processing circuit is composed of an FPGA circuit system and a DSP circuit system.
  • the FPGA circuit system is mainly composed of FPGA chip, FPGA chip serial configurator circuit, and FPGA reset and configuration button circuit, wherein the model of FPGA chip is EP2C8Q208C8N;
  • DSP circuit system is mainly composed of DSP chip and DSP chip guiding mode selection circuit.
  • the model of the DSP chip is TMS320F28335.
  • the circuit system of the invention is divided into an analog board and a digital board according to functions, and the analog board comprises a transmitting/receiving signal channel switching circuit, a driving signal voltage amplifying and power amplifying circuit, an echo strobing circuit, a voltage amplifying circuit and a band pass filter circuit.
  • the analog board comprises a transmitting/receiving signal channel switching circuit, a driving signal voltage amplifying and power amplifying circuit, an echo strobing circuit, a voltage amplifying circuit and a band pass filter circuit.
  • self-gain control circuit single-ended signal-to-differential signal circuit, bias circuit, and analog power supply (+12V, -12V, +5V, -5V) conversion circuit in power management module
  • digital board includes high-speed DAC signal generation and Output circuit, high-speed ADC signal acquisition and conversion circuit, FPGA circuit system, DSP circuit system, and digital power supply (+3V3, +1V9, +1V2) conversion circuit in power management module.
  • the working process of the circuit system of the present invention is: after detecting the "start measurement" signal sent by the DSP chip, the FPGA chip immediately enables its internal delay circuit, and simultaneously calls the waveform data stored in the internal ROM module, and at 20MSPS.
  • the rate is transmitted to the drive signal generating and amplifying circuit.
  • the driving signal generated by the high-speed DAC, after voltage amplification and power amplification, is output to the transmitting transducer end via a transmitting signal channel switching circuit controlled by the DSP chip.
  • the transmitting transducer emits ultrasonic waves based on the electrostrictive effect of the piezoelectric crystal.
  • the ultrasonic waves in the pipeline reach the corresponding receiving transducer end after a period of transit time.
  • the receiving transducer outputs an echo electrical signal.
  • the input signal channel switching circuit is input to the echo signal conditioning and acquisition circuit.
  • the high-speed ADC is based on the 5MHz provided by the FPGA chip.
  • the sampling frequency completes the data conversion.
  • the dual-port RAM inside the FPGA chip is used to temporarily store the conversion code value of the high-speed ADC. After the delay time determined by the delay circuit arrives, it is transmitted to the DSP chip through the parallel port line.
  • the DSP chip uses digital filtering to further eliminate the mixed noise in the echo signal.
  • the variable threshold zero-crossing detection method that tracks the maximum peak value of the echo signal is used to calculate the propagation time of the ultrasonic echo.
  • the first transducer 1, the second transducer 2, the third transducer 3, and the fourth transducer 4 are sequentially used as transmitting transducers, and the above process is repeated to synthesize the echo propagation time of four channels, that is, The actual gas flow can be calculated.
  • the transmitter calculates the gas flow under the working condition, it can realize the on-site display through the liquid crystal or remote reading through the serial communication module.
  • Figure 2 shows the high-speed DAC signal generation and output circuit. It consists of two differential line drivers U2, resistors R2, R9, R5, R7, R10, R12, R14, R16, R18, R20, R22, R24, R25, capacitors C11, C12. , C13, C14, C18, C20 and C21.
  • U2 is a high-speed current output type DAC.
  • the DB0 to DB8 pins of U2 are connected to the corresponding data output pins of the FPGA through resistors R5, R7, R10, R12, R14, R16, R18, R20, R22 and R25, respectively.
  • the small string of resistors in the middle helps to suppress the reflection and oscillation of high-speed signals.
  • Resistor R2 is connected to the FSADJ pin of U2 to adjust the full-scale output current value.
  • Capacitors C11, C12, and C13 are decoupling capacitors.
  • Resistor R9 pulls the output of IOUTB of U1 to ground.
  • Capacitors C14 and C18 are compensation capacitors that connect the bandwidth/noise suppression node COMP1 of U2 and the internal bias node COMP2 of the switch drive circuit to the power rail 3.3V and "ground", respectively.
  • C20 and C21 are decoupling capacitors.
  • the CLOCK pin of U2 is connected to the clock output pin of the FPGA through resistor R24. The conversion result of the high-speed DAC OUTPUT is output via the IOUTA pin.
  • Figure 3 is a drive signal voltage amplification and power amplifier circuit, consisting of low noise high speed op amp U1, resistors R13, R14, R15, R16, R17, R22, R27, R28, R29, R30, R31, R32, R33, R35, R44 Capacitor C25 and C26.
  • DAC_OUTPUT is the current signal output by the high speed DAC and is converted to a voltage signal via resistor R16.
  • Capacitor C25 is the filter capacitor
  • capacitor C26 is the DC blocking capacitor
  • resistor R16 provides the DC path for the non-inverting input of U1 to prevent the op amp from output saturation due to the bias current.
  • Resistor R17 is a matching resistor that balances the input impedance of op amp U1. Resistors R13 and R14 are used to set the voltage gain. U2 is a dual differential line driver with current negative feedback, high bandwidth, high drive current and low distortion. Resistor R33 acts as a connection, and resistors R35, R44, R22, and R27 are used to set the amplification gain; the two outputs of U2 are connected in parallel via resistors R31 and R28, further enhancing the power amplification capability. The drive signal that has undergone voltage amplification and power amplification is finally transmitted to the lower stage via the resistor R30.
  • FIG. 4 shows the excitation gating circuit and the transformer amplifying circuit.
  • the excitation gating circuit includes four bipolar operational amplifiers U3A, U3B, U3C and U3D; the transformer A1 is composed of transformers T1, T2, T3 and T4; T1, T2, T3 and T4 are transformers with a ratio of 1:10. Pins 1, 2 correspond to the secondary side of the transformer; pins 3, 4 correspond to the primary side of the transformer.
  • U3 is a bipolar op amp.
  • OUTPUT is the drive signal after the voltage and power amplification of the previous stage.
  • OC1, OC2, OC3, and OC4 transmit the strobe signal to the transducer output of the DSP.
  • the OC1 control logic is taken as an example to illustrate the working principle of the circuit, and the other channels are similar.
  • the U3D output voltage is close to its negative supply rail (about -12V)
  • the N-channel enhancement MOS transistors Q4 and Q8 are not conducting, and the drive signal cannot reach the transducer end;
  • U3D The output voltage is close to its positive power rail (about +12V).
  • Q4 and Q8 are turned on, and the driving signal reaches the primary side of the transformer.
  • the bridge circuit built by several diodes finally reaches the transducer connection terminal W1. .
  • Resistor R34 is a pull-down resistor that provides the circuit with an initial input level.
  • Resistors R21 and R26 are pull-down current limiting resistors.
  • Capacitor C30 and diode D36 together form a MOS transistor Q4 and Q8 protection circuit to prevent accidental breakdown.
  • Resistors R4 and R12 form a voltage dividing circuit that can be adjusted according to different transducer characteristics; resistor R11 acts as a connection.
  • TP4 is the test port.
  • COM1 corresponds to the transducer connected to W1 as an echo signal generated when the transducer is received.
  • Figure 5 shows the echo gate circuit of channel 1, the other three channels are similar.
  • U4 is a dual low-impedance single-pole, single-throw switch that is compatible with 3V logic levels. When powered by 12V, the crosstalk between channels is only -70dB.
  • IC1 and NIC1 are the transducer 1 strobe signal and the shutdown signal of the DSP output. When IC1 is set high, strobe S1 and D1, ie COM1 Access subsequent echo signal conditioning and acquisition circuits.
  • JUMP1 is the debug port.
  • the resistors R48, R49, and R50 are pull-down resistors; the gated echo signals are output to the subsequent circuit via the resistor R47.
  • Figure 6 shows the voltage amplification circuit in the echo signal conditioning and acquisition circuit, which consists of a low-noise high-speed op amp U10, capacitors C98, C100, resistors R59, R63, R64, R77, R81, R78, R83, where resistor R77
  • the R81 and the low-noise high-speed op amp U10 form an inverting amplifying circuit; wherein the resistors R78 and R83 and the low-noise high-speed op amp U10 constitute a non-inverting amplifying circuit.
  • Signal_0 is the echo signal that the front end is gated
  • U10 is the low noise high speed op amp.
  • Capacitors C98 and C100 are DC blocking capacitors and together with resistor R59 form a high pass filter.
  • the soldering resistors R77 and R81 are selected and the resistors R78 and R83 are omitted, they form an inverting amplifying circuit with the feedback resistor of the subsequent stage op amp; when the soldering resistors R78 and R83 are selected, the resistors R77 and R81 are ignored, they are shipped with the post stage.
  • the feedback resistors are configured to form a non-inverting amplifier circuit, and the actual connection manner of the above two resistors needs to be selected according to the characteristics of the echo signals.
  • Figure 7 shows the bandpass filter circuit in the echo signal conditioning and acquisition circuit, consisting of a fourth-order continuous-time active filter U8, resistors R60, R62, R66, R67, R71, R72, R74, and R75.
  • the center frequency, bandwidth, quality factor, and gain parameters of the filter can be changed by changing the peripheral resistors R60, R66, R71, R74, R62, R67, R72, and R75.
  • the echo signal passing through the front end is introduced into the filter through a resistor R65, and the resistor R57 and the capacitor C99 together form a high pass filter.
  • Figure 8 shows the self-gain control circuit in the echo signal conditioning and acquisition circuit, with high gain and wide range adjustable gain amplifier U9, low power wide range op amp U12, low noise high speed op amp U7, resistor R55, R56 , R76 and R68.
  • U7 and its peripheral resistors R55, R56 constitute a non-inverting amplifier.
  • Resistor R76 is a pull-down resistor and resistor R68 is an Oohm connection resistor.
  • the self-gain circuit of the echo signal is mainly realized by the negative feedback structure built by U9 and U10 and its peripheral discrete devices.
  • Signal_2 is the input of the feedback link, and Single_ended Signal is the output. If the input level of pin 9 of U9 is V C , the actual gain G (dB) of U9 is calculated by equation (6).
  • Figure 9 shows the single-ended signal-to-differential signal circuit in the echo signal conditioning and acquisition circuit.
  • the U13's in-phase and inverting input device parameters and PCB layout are as symmetrical as possible, that is, resistors R95, R96, C105, R94, R93 and resistors R100, R98, C111, R102, R104 Symmetrical, where resistors R94 and C105, R102 and C111 form a first order low pass filter, respectively.
  • the differentially amplified double-ended signals are output to the lower stage circuits through resistors R93 and R104, respectively.
  • V ocm is the common mode input voltage.
  • the resistors R99, R101 and U15 form the bias circuit. By changing the ratio of the resistors R99 and R101, V ocm can be configured.
  • U15 is an ordinary low noise op amp.
  • Figure 11 is a high speed ADC signal acquisition and conversion circuit in the echo signal conditioning and acquisition circuit.
  • the high-speed ADC signal acquisition and conversion circuit consists of high-speed ADC chip U1, resistors R1, R27, R28, R29, R35, R37, R48, capacitors C15, C16, C17, C19, C22, C23, C24, C25; U1 is two-way 12-bit pipeline type. Resistor R1 and capacitors C15, C16, C17, C19 and C22, C23, C24, C25 configure the reference voltage of the high speed ADC to 1V.
  • Resistors R27, R29 and capacitors C26, C27 form the first-order low-pass filtering of the differential input signals INPUT- and INPUT+, and are connected to VINB- and VINB+ of U13, respectively; resistors R28, R35 and capacitors C28, C29 also form the differential input signal INPUT - First-order low-pass filtering with INPUT+ and connected to VINA- and VINA+ of U13, respectively.
  • the INPUT- and INPUT+ are connected to the two inputs of the dual channel of the U13, and the redundant design enhances the reliability of the system.
  • DF can be configured by resistors R154, R155, R156, R157, R158, R159, R160 and R161
  • the pin level of the PD that is, the operating mode of the U13 is configured, and the A or B channel is strobed accordingly for conversion.
  • AD_CLK is the clock signal provided by the FPGA to U13, and resistors R37, R48 and C30 form a filter circuit for filtering out clutter in the clock signal.
  • Capacitors C1, C2, C3, C4, C6, C7, and C10 are decoupling capacitors, and resistors R3, R4, R6, R8, R11, R13, R15, R17, R19, R21, R23, and R26 are B-channel output snubber resistors.
  • resistors R30, R31, R32, R33, R34, R36, R38, R39, R40, R41, R42, and R44 are A-channel output snubber resistors.
  • AD_DB0 to AD_DB11 and AD_DA0 to AD_DA11 are respectively connected to the I/O module of the FPGA chip, and the conversion result of U13 is output to the FPGA.
  • the model of the FPGA chip is EP2C8Q208C8N; the FPGA chip serial configurator circuit is composed of a flash type serial configurator U8; the FPGA resets and configures the key circuit. It consists of resistors R111, R112, R113, capacitor C96, diode D2 and buttons.
  • U7A, U7B, U7C, U7D, and U7E in Figures 12-16 together form an FPGA chip.
  • Figure 12 shows the I/O interface sub-module
  • Figure 13 shows the I/O voltage and reference voltage sub-modules
  • Figure 14 shows the core voltage and ground sub-modules
  • Figure 15 shows the clock input sub-module
  • Figure 16 shows the simulation interface sub-module
  • Figure 17 shows the FPGA chip serial configurator circuit
  • Figure 18 shows the FPGA reset and configuration button circuit.
  • the above circuit constitutes the smallest system in which the FPGA chip operates.
  • the pin connection of the FPGA chip is mainly divided into the following five categories:
  • the DA_RSTn connected to the pin IO_VB1N0_8 is used to receive the start measurement command from the DSP chip, and start the high-speed DAC output drive signal;
  • the RAM_RSTn connected to the pin IO_VB1N0_6 is used to receive the reset command issued by the DSP chip, and initialize the FPGA chip on-chip dual Temporary data is stored in the port RAM; when the high-speed ADC conversion code value stored in the dual-port RAM of the FPGA chip reaches a certain amount, the INT2DSP connected to the pin IO_VB1N1_46 will send an accept request signal to the DSP chip; connected to the pin IO_VB1N0_5 READ_EN is used to detect the read command issued by the DSP chip, indicating that the DSP chip is ready to receive data; the READ_CLK connected to the pin CRC_ERROR is used
  • FIG 19 shows the DSP circuit system.
  • the DSP chip model is TMS320F28335;
  • the DSP chip boot mode selection circuit is composed of resistors R49, R50, R51, R52, R53, R54, R55 and R56, as shown in Figure 20;
  • DSP chip pin connections are mainly divided into the following five categories:
  • Pins 80, 78, 87, 79, 76, 77, 85, 86 are connected to respective pins of the DSP chip JTAG port, respectively.
  • NIC0, NIC1, NIC2, and NIC3 connected to pins 75, 73, 90, and 94 correspond to "non" logic signals of IC0, IC1, IC2, and IC3, respectively.
  • the DA_RSTn connected to the pin 152 is used to start the flow measurement, and the FPGA chip is notified to start the output signal of the external DAC module;
  • the RAM_RSTn connected to the pin 153 is used to initialize the temporary data of the dual-port RAM in the FPGA chip;
  • INT2DSP connected to pin 114 used to inform the DSP chip to start receiving the high-speed ADC conversion code value stored in the FPGA chip;
  • READ_EN connected to pin 156 for enabling the reading of the dual-port RAM of the FPGA chip, DSP
  • the chip is ready to receive data;
  • Pins connected to other function modules for example: connected to pins 10, 11, 12, 13 FRAM_SOMI, FRAM_SIMO, FRAM_CLK for data exchange with external ferroelectric memory; KEY0 ⁇ KEY3 connected to pins 65, 64, 63, 62 for receiving external key input signals; connected to pin 66, 67, 68 LCD_CS, LCD_CLK, LCD_DI, used to control the display of the external liquid crystal module; SCITXDB, SCIRXDB connected to pins 18, 20, for serial communication with the host computer.
  • the DSP chip boot mode selection circuit can modify the boot mode of the DSP chip by configuring the resistance ratio between R49 and R50, R51 and R52, R53 and R54, and R55 and R56.
  • FIG. 21 shows the functional block diagram of the timing control and signal processing circuit.
  • the FPGA chip adopts the Top-Down design method to perform functional division and structural design from the top layer.
  • the main functional modules of the FPGA chip include: frequency division module, ADC control module, RAM_2PROT module, DAC control module, ROM module, delay module and SignalTap module.
  • the synchronous design scheme is adopted between each module.
  • the frequency dividing module is used to modulate an external input 20 MHz clock signal into a 5 MHz sampling clock output to a high speed ADC;
  • the ADC control module is used to transfer the high speed ADC conversion code value to the RAM_2PORT module inside the FPGA chip;
  • the RAM_2PROT module is used After storing the high-speed ADC conversion code value, when the conversion code value of the high-speed ADC reaches a certain amount, a "request to read" signal is sent to the DSP chip, and then the stored high-speed ADC conversion code value is transmitted to the DSP chip according to a certain rate;
  • the DAC control module is used to carry the waveform data stored in the ROM module to the high speed DAC to generate a corresponding excitation waveform;
  • the delay module is used to control the RAM_2PORT module to be started after a predetermined delay time after the excitation signal is sent.
  • the conversion code value of the high-speed ADC is stored to save storage space;
  • the SignalTap module is
  • the DSP chip receives the high-speed ADC conversion code value stored in the FPGA chip in parallel through the GPIO module.
  • one GPIO of the DSP chip is connected to the FPGA chip as an address latch signal. After querying the "request to read" instruction issued by the FPGA, the DSP chip enables the address latch signal to read the conversion code value of the high-speed ADC from the inside of the FPGA chip; at the same time, the internal "read pointer" of the FPGA chip moves down 1 Bit, repeat the above operation until the data stored in the FPGA chip is completely read.
  • the DSP chip sends a "reset" instruction to the FPGA chip to clear the internal RAM_2PORT space of the FPGA chip and the data in the delay module, in preparation for the next measurement.
  • the GPIO module of the DSP chip completes the key input and the liquid crystal display; through the PWM module, the pulse output of the flow result is completed, which facilitates the later gas flow calibration; and the serial communication between the host computer and the host computer is completed through the SCI module. It facilitates the storage and analysis of the flow results; the bidirectional read and write between the ferroelectric memory and the FRAM is completed by the SPI module.
  • the DSP chip detects the “power-down reset”, the accumulated flow and instrument parameters are written into the FRAM in time.
  • the system uses an external watchdog to prevent the program from running away.
  • the external watchdog also has functions such as button reset, power-on/power-down reset, and low-voltage monitoring.
  • Figure 22 shows the overall block diagram of the DSP chip software for the circuit system.
  • the software design uses a modular design approach.
  • the main monitoring program and each program module are composed; wherein each program module includes an initialization module, a transmit/receive signal channel switching module, an FPGA data transmission module, an interrupt module, a calculation module, a FRAM read/write module, a serial communication module, and a pulse output. Module, key input module and liquid crystal display module.
  • the main monitoring program is the total scheduling program of the entire system, and the various functions of the system are implemented by mobilizing each program module.
  • Figure 23 is a flow chart of the main monitoring program of the circuit system. After the circuit system is powered on, the main monitoring program runs automatically. The specific steps of the main monitor are as follows:
  • the DSP chip After the circuit system is powered on, the DSP chip completes the initialization of each part: including allocating the GPIO port of the DSP chip, interrupting the initialization of the internal timer 1 of the DSP chip, initializing the liquid crystal display module, and reading the accumulated flow from the FRAM read/write module.
  • the parameters of the meter are initialized, and four queues are established, each queue consisting of 50 data slots for storing the propagation time of the ultrasonic waves received by the four transducers (hereinafter referred to as propagation time); whenever there is one
  • propagation time the propagation time of the ultrasonic waves received by the four transducers
  • the program enters the loop of flow detection.
  • the DSP chip switches the transducer transmit and receive channels by changing the output state of the corresponding GPIO port.
  • the sequence of switching channels is: the first transducer 1 transmits the third transducer 3 to receive; the second transducer 2 transmits the fourth transducer 4 to receive; the transducer 3 transmits the first transducer 1 to receive; The four transducers 4 emit the second transducer 2 for reception. Then continue to cycle the above switching process.
  • the FPGA chip is notified to start measurement, and the DSP chip needs to wait for the FPGA chip to complete the signal reception.
  • FPGA chip controls high-speed DAC and high-speed ADC to complete signal drive and echo signal acquisition
  • the DSP chip After switching channels, the DSP chip sends a "start measurement" signal to the FPGA chip.
  • the FPGA chip immediately enables the internal delay module, simultaneously calls the waveform data stored in the ROM module inside the FPGA chip, and transmits it to the driving signal generation and amplification circuit; and then transmits and receives the signal transmission circuit controlled by the DSP chip to output to
  • the first transducer 1 or the second transducer 2, or the third transducer 3, or the fourth transducer 4 of the direct-channel two-channel structure is replaced by the first transducer 1, or the second transducer
  • the energy sensor 2, or the third transducer 3, or the fourth transducer 4 emits ultrasonic waves; after a period of transit time, the ultrasonic waves reach the corresponding receiving transducer; the third transducer 3, or the fourth exchange
  • the energy sensor 4, or the first transducer 1, or the second transducer 2 receives ultrasonic waves to form an echo signal; the transmit/receive signal channel switching circuit controlled by the DSP chip
  • the data stored in the RAM_2PORT module inside the FPGA chip is copied to the on-chip RAM of the DSP chip for digital signal processing by the DSP chip.
  • the DSP chip There is a wait time of approximately 400 ⁇ s before the DSP chip knows that signal acquisition is complete. This time is mainly the time when the ultrasound propagates in the channel and the time when the FPGA chip receives the acquired signal. During this time, the DSP chip can complete the update of the liquid crystal display and communication with the host computer. It is not necessary to update the liquid crystal display and the communication with the host computer in each acquisition signal, but only once per second, which is controlled by the time stamp of the timer 1 inside the DSP chip. That is, the DSP chip first determines whether the time stamp of the timer 1 is 0. If it is not 0, then Complete both tasks and then set the timer time stamp to zero. If it is 0, it will not be executed. The time stamp of Timer 1 is set to 1 in the 1 second interrupt service routine. Through the time stamp of Timer 1, make full use of this waiting time to improve the real-time performance of the system.
  • DSP chip processes the data and calculates the propagation time of the ultrasonic wave
  • the DSP chip processes the copied data and calculates the propagation time of each ultrasonic wave.
  • the waveform of the received ultrasonic signal is as shown in Fig. 24.
  • the signal waveform is similar to the sine wave whose amplitude is modulated. There are multiple waves, and the peak value of each wave is gradually increased first, and then gradually decreased until the attenuation is zero.
  • the sampled signal is digitally filtered.
  • a fourth-order band-pass IIR digital filter with a cutoff frequency of 200 kHz ⁇ 180 kHz is used.
  • the noise content is reduced.
  • the shapes of the echo signals under these two flows are basically the same, so the ratio of the peak value of each wave in the echo signal to the maximum peak amplitude should be substantially the same.
  • ⁇ is a fixed value and is obtained by statistical calculation in advance. Taking the transducer corresponding to FIG. 25 as an example, a flow point is taken every 100 m 3 /h between 0 and 800 m 3 /h flow range, and 50 echo signals are collected at each flow point, and then MATLAB is used.
  • the ratio of the fifth wave to the sixth wave to the maximum peak is substantially constant at each flow rate.
  • the ratio of the peak of the fifth wave to the maximum peak is maintained at about 0.39, and the ratio of the peak of the sixth wave to the maximum peak is maintained at about 0.53. Therefore, take ⁇ as the mean of the two, which is 0.46.
  • the SW is used to detect the echo signal. When the amplitude of the echo signal reaches this threshold for the first time, the corresponding wave is the characteristic wave to be found. This method of determining the characteristic waves in the echo signal is called a variable threshold method.
  • the required zero crossing can be calculated based on the characteristic wave.
  • 8 zero-crossing points after the characteristic wave are used, and the propagation time is calculated by the average of the 8 points to eliminate some random errors and improve the measurement accuracy.
  • the time corresponding to the eight zero crossings are: ⁇ 1 , ⁇ 2 ... ⁇ 8 .
  • the required zero-crossing point can be calculated based on the characteristic wave.
  • the eight zero crossings after the characteristic wave are used, and the propagation time is calculated by the average of the eight points. This eliminates some random errors and improves measurement accuracy.
  • the time represented by these eight zero crossings is arranged in chronological order: ⁇ 1 , ⁇ 2 ... ⁇ 8 .
  • a linear interpolation method is employed, as shown in FIG.
  • the propagation time T can be calculated by the formula (4):
  • t' is a fixed deviation value, which can be in the case of zero flow. Calculated.
  • the propagation time of the ultrasonic wave can be calculated in real time according to the equations (7) and (4).
  • step (2) different transmit transducers and receive transducers are switched, so that the propagation time of the downstream and reverse current signals of each channel can be continuously measured in sequence.
  • step (3) the measurement of the two-channel forward and reverse current propagation time is completed, and the four propagation times are respectively placed in the four queues established in the step (1).
  • the method of judging the "step” is adopted, that is, when calculating the average flow rate, firstly, 50 data in the propagation time queue corresponding to a certain channel is taken out, It is stored in an otherwise opened array, and then the data representing the propagation time of 50 measurements is sorted from small to large. If there are coarse errors in the 50 measurements, then the sorted propagation time value will have a significant "step” phenomenon, as shown in Figure 27.
  • the data is divided into several segments, and the data with the most points is the correct propagation time data. Taking Figure 27 as an example, the "step” appears at points 5 and 40.
  • the 50 pieces of propagation time data are divided into 3 segments: 1 to 4, 5 to 39, and 40 to 50.
  • the 5 to 39 segments with the largest number of data points measure the correct propagation time.
  • the correct propagation time data is averaged to obtain the average propagation time t of the channel.
  • the measured instantaneous flow rate Q can be calculated according to equation (5).
  • Q is the measured instantaneous flow rate
  • D is the pipe diameter
  • L is the channel length
  • ⁇ is the angle of the channel angle (the angle between the ultrasonic propagation path and the pipe axis)
  • t s , t n is the angle of the channel angle (the angle between the ultrasonic propagation path and the pipe axis)
  • t s , t n is the angle between the ultrasonic propagation path and the pipe axis
  • k f is the meter factor. Visible, traffic Q and In direct proportion.
  • K f was obtained by calibration experiments.
  • the time differences ⁇ t and t s t n are calculated from t 1 , t 2 , t 3 , t 4 as shown in equations (9) and (10), respectively.
  • the initial value of a meter factor is initially given, and a flow point (for example, about 400 m 3 /h) is marked.
  • a flow point for example, about 400 m 3 /h
  • the meter coefficient is corrected to obtain an accurate k f . .
  • the flow can be calculated in real time by equations (7), (4), and (5). Due to factors such as flow field distribution and changes in sound propagation path, actual flow and It has a nonlinear relationship.
  • the error is segmentally linearly corrected according to the actual flow calibration result. Selecting 11 flow points of 30, 60, 80, 100, 200, 300, 400, 500, 600, 700, 800 m 3 /h between 30 and 800 m 3 /h to obtain the error of these flow points. That is, the relationship between flow rate and error is obtained.
  • the error corresponding to any flow point between 30 and 800 m 3 /h can be calculated, and then the measured flow value can be corrected. Assuming that the measured flow value is Q' and the error corresponding to the flow point is e(Q'), then the corrected instantaneous flow rate Q is:
  • the accumulated flow rate is calculated by the interrupt service program of the internal timer 1 of the DSP chip to ensure that the accumulated time is accumulated once in 1 second, that is, the timer interrupt is generated by the internal timer 1 of the DSP chip, and the period is 1 second.
  • FIG. 28 is a flow chart of the interrupt service routine of the internal timer 1 of the DSP chip.
  • the timer interrupt service program first reads the instantaneous flow result calculated by the main monitoring program, and accumulates the accumulated flow rate; then updates the parameters of the pulse output module according to the value of the instantaneous flow rate, and outputs a pulse of a certain frequency to indicate the measured instantaneous flow rate; Set the timer time flag to 1 to update the LCD display and perform host communication in the main monitor.

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Abstract

一种基于FPGA和DSP的气体超声流量计，由气体超声换能器和传感器单元、发射/接收信号通道切换电路、驱动信号生成和放大电路、回波信号调理与采集电路、时序控制与信号处理电路、人机接口、串口通讯和电源管理模块组成，采用跟踪回波信号最大峰值的可变阈值过零检测方法，计算超声回波的传播时间，进而获得气体流量。还提供一种基于FPGA和DSP的气体超声流量计的测量方法。

Description

[根据细则37.2由ISA制定的发明名称]　一种基于FPGA和DSP的气体超声流量计及其测量方法 技术领域
本发明涉及流量测量领域，为一种气体超声流量计，特别是一种基于FPGA芯片和DSP芯片双核心架构，针对利用正弦波激励产生的超声回波信号，采用跟踪回波信号最高峰值的可变阈值法，同时结合过零检测方法的气体超声流量计。
背景技术
气体超声流量计在计量精度、可靠性、压力损失、维护费用以及制造成本等方面相比于其他气体流量计(如孔板、涡轮流量计等)具有独到的优势，尤其是在中、大口径管道流量测量方面，其优越性更加明显。其中，又以传播时间差式气体超声流量计应用最为广泛。气体超声流量计由两部分组成，一是换能器和传感器部分，包括1对或者多对超声波换能器、压力传感器和温度传感器；二是变送器，包括驱动信号的产生和调理部分、回波信号的调理和数字处理部分，以及人机交互部分。气体超声波流量计研制的关键在于选取合适的超声波驱动信号，同时克服回波信号中混杂的噪声信号的影响，然后根据回波信号的某一稳定特征点分别获得超声波顺流和逆流状态下的传播时间。
为了叙述清楚起见，定义加在发射超声波换能器上的信号为驱动信号，由发射超声波换能器发出超声波；由接收超声波换能器接收超声波，接收超声波换能器输出的信号为回波信号。超声波换能器既可以用作发射，也可以用作接收，由发射/接收信号通道切换电路控制其功能的转换。
国外率先将数字信号处理技术应用于气体超声流量计中，归纳起来有以下几种方法。
(1)基于能量突变的方法
美国Daniel公司采用检测能量突变的方法查找特征点的方法(William Freund，Winsor Letton，James Mc-Clellan，Baocang Jia，Anni Wey，Wen Chang.Method and apparatus for measuring the time of flight of a signal，US patent NO.5983730，Nov.16，1999)。由于回波信号的能量经历了从弱到强，再从强到弱的过程，因此回波信号的能量变化率将先增大再减少，依据能量变化率的临界变化点，即可确定超声波传播时间。具体说来，此方法首先求取回波信号各点的幅值平方，幅值平方的大小表征了信号能量的大小。然后，利用滑动平均的方法，求取每一点的平均能量，再绘制出前、后两点平均能量之比的变化曲线，即能量变化率曲线。最后，通过能量变化率的临界点，确定超声波传播时间。但是，该专利中，没有披露实施过程中的关键技术，如滑动窗口的时间间隔，以及求取能量变化率时前、后两点之间的时间间隔等。
(2)基于相位突变的方法
奥地利AVL里斯托有限公司(Mario Kupnik，Andreas Schroder，Michael Wiesinger，Klaus-Christoph Harms.Ultrasonic gas flowmeter as well as device to measure exhaust flows of internal combustion engines and method to determine flow of gases，US Patent NO.2005/0066744A1，Mar.31，2005)采用监测超声回波信号在从无到有的过程中相位的突变来实现流量测量。首先寻找到回波信号的幅值最大点，并且通过希尔伯特变化计算获得信号的相位信息，以回波信号的最大幅值点对应的时刻为起点，向前寻找相位停止持续变化的时间点，即相位突变点。通过这个相位突变点，确定回波信号的第一个过零点，进而获得超声传播时间。可是，这种方法计算量大，并且易受现场噪声的影响，不便于工业现场 的实际应用。
(3)基于移位叠加的方法
为了提高回波信号的信噪比，荷兰的Instromet公司采用了移位叠加的方法(Eduard Johannes Botter.Ultrasonic signal processing method and applications thereof，US patent NO.7254494B2，Aug.7，2007)。此方法首先按照一定的时间间隔连续发送8次驱动信号，获得相应的8组回波信号，然后，将这8组回波信号按照预设的时间进行移位叠加，使回波信号获得增强，而噪声信号由于其随机性，在叠加的过程中会相互抵消而衰减。最后，再通过阈值检测的方法获得超声波传播时间。该方法利用回波信号和噪声信号各自的时域特征，有效地提高了信噪比。但是，重复发射超声驱动信号，延长了系统的测量时间，影响了流量计的动态响应。当流量发生突变时，将会产生较大的测量误差。
(4)基于互相关及其衍生的方法
由于在超声波流量计工作工程中，顺流和逆流时产生的回波信号之间具有相关性，而噪声信号之间不具有相关性，因此可以利用互相关及其衍生方法计算超声波的传播时间差。传统的互相关计算如式(1)所示，其中，假设顺流时产生的回波信号为x(t)，逆流时产生的回波为y(t)，那么，Rxy(τ)取得最大值时所对应的时间位移τ，即为顺流传与逆流传播时间之差。传统的互相关方法运算量大，难以利用单片机的有限资源实时实现。为了减少互相关的运算量，日本东京计装(Keiso)株式会社采用了一种互相关衍生算法(Tokio Sugl，Tadao Sasaki.Ultrasonic flow meter，US patent NO.007299150B1，Nov.20，2007)，如式(2)所示，其中，m为移位步数，N为采样点数，那么，Sxy(m)取得最大值时所对应的移位步数m表征了顺流和逆流传播时间之差。通过对比公式(1)和(2)，不难发现，这种互相关衍生算法利用加法取模运算代替了原互相关算法中的乘法运算，减少了运算量。可是，同时也带了测量的误差，尤其当噪声干扰较大的时候，极有可能出现计算错误。
Figure PCTCN2016077122-appb-000001
Figure PCTCN2016077122-appb-000002
(5)基于互相关和过零检测相结合的方法
德国西门子股份公司采用一种过零检测与互相关相结合的方法计算超声波顺流和逆流的绝对传播时间(Arthur Freund，Nils Kroemer.Method for measuring the time of flight of electric，electromagnetic or acoustic signals，EP Patent NO.0797105A2，Mar.17，1997)，首先通过某种方法获得1段不含噪声的回波信号，假设其起始时刻为t0，同时在该回波信号中选定某1个过零点，该过零点距离起始时刻t0的时间间隔记为tN。然后，将该段回波信号与换能器实际采集的回波信号做互相关运算。如果互相关运算结果的最大值表征的时间间隔为td，同时假设实际回波信号的起始时刻相对于驱动信号发射时刻的时间间隔为t1，那么回波信号的传播时间为：
t＝t1+td+tN-tkorr                  (3)
式中，tkorr为修正时间，它包括换能器转换延时和电路传输延迟。这种方法能够可靠地从混杂有噪声信号的接收波形中检测出回波信号，并且由于过零点附近具有较高的幅值分辨率，所以适合于嘈杂的工业现场。但是，该专利中没有披露如何获取不含噪声的回波信号，同时，也存在互相关运算量大等问题。
发明内容
为了提高传播时间的计算精度，增强系统的抗干扰能力，本发明提供一种基于FPGA和DSP的气体超声流量计。
一种基于FPGA和DSP的气体超声流量计变送器由气体超声换能器和传感器单元、发射/接收信号通道切换电路、驱动信号生成和放大电路、回波信号调理与采集电路、时序控制与信号处理电路、人机接口、串口通讯和电源管理模块组成。所述气体超声换能器和传感器单元由四个换能器、压力传感器和温度传感器组成，所述四个换能器、压力传感器和温度传感器分别固定在输送气体的管道上；每个换能器既为发射换能器，又为接收换能器；所述发射/接收信号通道切换电路由激励选通电路、变压器放大电路和四个回波选通电路单元组成；四个回波选通电路单元为相同结构的电路单元，且分别与四个换能器对应连接。所述驱动信号生成和放大电路由高速DAC信号产生与输出电路，驱动信号电压放大和功率放大电路组成。所述回波信号调理与采集电路由电压放大电路、带通滤波器电路、自增益控制电路、单端信号转差分信号电路、偏置电路和高速ADC信号采集与转换电路组成。所述时序控制与信号处理电路由FPGA电路系统和DSP电路系统组成，其中，FPGA电路系统主要由FPGA芯片、FPGA芯片串行配置器电路，以及FPGA芯片复位和配置按键电路组成；DSP电路系统主要由DSP芯片和DSP芯片引导模式选择电路组成。所述FPGA芯片用于暂存驱动信号生成和放大电路传送来的转换码值，当确定了延迟时间，并传输至DSP芯片；所述DSP芯片为主控芯片，负责数字信号处理以及人机交互、串口通讯，并且与FPGA电路系统配合完成整个系统的时序控制；由DSP芯片采用数字滤波消除信号中混杂的噪声，采用跟踪回波信号最大峰值的可变阈值过零检测方法，计算超声回波的传播时间，进而获得气体流量。
基于FPGA和DSP的气体超声流量计变送器的控制方法由主监控程序和各个程序模块实现；所述主监控程序为总调度程序，所述各个程序模块为初始化模块、看门狗模块、铁电读写模块、通道切换模块、通信模块、与FPGA数据传输模块、脉冲输出模块、中断模块、计算模块和显示模块；主监控程序通过调动各个程序模块实行所述气体超声流量计变送器的各项功能。
主监控程序的具体操作步骤如下：
(1)电路系统初始化
电路系统上电后，DSP芯片完成各个部分的初始化：包括对DSP芯片的GPIO口进行分配，DSP芯片的内部定时器1的中断初始化，液晶显示模块初始化，从FRAM读写模块中读取累计流量、仪表的各项参数初始化，并且建立4个队列，每个队列由50个数据空位组成，用于存放4个换能器接收到的超声波的传播时间(以下简称传播时间)；每当有一个新的传播时间数据进入时，每个队列首位的数据会被抛掉，新的传播时间数据加在队列尾部。在后面的测量过程中，将根据这4个队列的数据，实时计算出双声道超声波流量计顺流和逆流的平均传播时间。
(2)进入流量检测的循环
电路系统初始化后程序就进入流量检测的循环中；首先DSP芯片通过改变对应GPIO口的输出状态，切换换能器发射与接收通道。切换通道的顺序为：第一换能器1发射第三 换能器3接收；第二换能器2发射第四换能器4接收；第三换能器3发射第一换能器1接收；第四换能器4发射第二换能器2接收；然后再不断地循环以上的切换过程；切换通道后通知FPGA芯片开始测量，DSP芯片需要等待FPGA芯片完成信号接收。
(3)等待FPGA芯片控制高速DAC和高速ADC完成信号驱动与回波信号的采集
DSP芯片向FPGA芯片发送“开始测量”信号，FPGA芯片立即使能内部的延时模块，同时调用FPGA芯片内部的ROM模块中存储的波形数据，传输至驱动信号生成和放大电路；再经由DSP芯片控制的发射/接收信号通道切换电路，输出至直射式双声道结构的第一换能器1、或者第二换能器2、或者第三换能器3、或者第四换能器4，由第一换能器1、或者第二换能器2、或者第三换能器3、或者第四换能器4发出超声波；超声波经过一段渡越时间后，到达对应的接收换能器；由第三换能器3、或者第四换能器4、或者第一换能器1、或者第二换能器2接收超声波，形成回波信号；由DSP芯片控制的发射/接收信号通道切换电路接收由换能器发出的回波信号，并输入至回波信号调理和采集电路；由回波信号调理和采集电路中的高速ADC完成数据转换；FPGA芯片内部的RAM_2PORT模块用于暂存高速ADC的转换码值，当延迟电路确定的延迟时间到达以后，通过拉高设定的DSP芯片的GPIO端口告知DSP芯片信号采集完成。
(4)复制数据
DSP芯片检测到设定的端口的高电平后，将存放在FPGA芯片内部的RAM_2PORT模块中的数据复制到DSP芯片的片内RAM中，供DSP芯片对其进行数字信号处理。
(5)DSP芯片对数据进行处理，计算超声波的传播时间
DSP芯片对复制的数据进行处理，计算每次超声波的传播时间T为；
Figure PCTCN2016077122-appb-000003
式中，τi(i＝1，2，3...8)为过零点时间，t′为一个固定的偏差值，该偏差值为零流量的情况下计算得到；
(6)计算瞬时流量
进行一次步骤(2)～(5)的循环，就可以得到一次超声波从一个换能器到另外一个换能器之间的传播时间。
在步骤(2)中切换不同的发射换能器和接收换能器，这样就可以不断地依次测量出每个声道顺流和逆流信号的传播时间；这样循环4次，就完成了双声道顺流和逆流传播时间的测量，并将这4个传播时间分别放入步骤(1)中所建立的4个队列中。
执行5次这样的测量，计算出双声道顺流和逆流的平均传播时间，并根据这个平均传播时间计算出平均流量，并作为瞬时流量显示。
瞬时流量的计算公式为：
Figure PCTCN2016077122-appb-000004
式中，Q为瞬时流量，D为管道直径，L为声道长度，θ为声道角的角度，所述声道角为超声波传播路径与管道轴线之间的夹角；ts、tn、Δt分别为顺流传播时间、逆流传播时间以及它们的时间差，kf是仪表系数。再通过修正操作，得到修正后的瞬时流量。
(7)计算累积流量
在得到修正后的瞬时流量后，由DSP芯片的内部定时器1的中断服务程序计算累积流 量，以保证1秒钟累积一次，即定时器中断由DSP芯片内部定时器1产生，周期为1秒；定时器中断服务程序首先读取主监控程序计算的瞬时流量结果，并累加得到累积流量；再根据瞬时流量的值更新脉冲输出模块的参数，输出一定频率的脉冲，表示测得的瞬时流量；然后，将定时器时间标志置为1，以便在主监控程序中更新液晶显示以及进行上位机通信。
本发明的有益技术效果是：基于FPGA芯片和DSP芯片双核心，既实现了驱动信号的高频输出和回波信号的高速采样，又实时实现了数字信号处理方法，提高了传播时间的计算精度，增强了系统的抗干扰能力，符合工业现场应用的需求。
附图说明
图1是系统硬件框图；
图2是高速DAC信号产生与输出电路原理图；
图3是驱动信号电压放大和功率放大电路原理图；
图4是激励选通和变压器放大电路原理图；
图5是回波选通电路原理图；
图6是电压放大电路原理图；
图7是带通滤波器电路原理图；
图8是自增益控制电路原理图；
图9是单端信号转差分信号电路原理图；
图10是偏置电路原理图；
图11是高速ADC信号采集与转换电路原理图；
图12是FPGA芯片(EP2C8Q208C8N)子模块——I/O接口原理图；
图13是FPGA芯片(EP2C8Q208C8N)子模块——I/O电压和参考电压原理图；
图14是FPGA芯片(EP2C8Q208C8N)子模块——内核电压和地原理图；
图15是FPGA芯片(EP2C8Q208C8N)子模块——时钟输入原理图；
图16是FPGA芯片(EP2C8Q208C8N)子模块——仿真接口原理图；
图17是FPGA芯片串行配置器电路原理图；
图18是FPGA芯片复位和配置按键电路原理图；
图19是DSP芯片电路原理图；
图20是DSP芯片引导模式选择电路原理图；
图21是时序控制与信号处理电路功能模块示意图；
图22是软件总体框图；
图23是主监控程序流程图；
图24是回波信号波形图；
图25是不同流量下的超声波信号波形对比图；
图26是线性插值计算过零点；
图27是计算错误时出现的“台阶”示意图；
图28是定时器中断服务程序流程图。
具体实施方式
参见图1，本发明的硬件系统由气体超声换能器和传感器单元、发射/接收信号通道切换电路、驱动信号生成和放大电路、回波信号调理与采集电路、时序控制与信号处理电路、人机接口、串口通讯和电源管理模块组成。
气体超声换能器和传感器单元由四个换能器、压力传感器和温度传感器组成，且分别固定安装在输送气体流量的管道上；四个换能器为第一换能器1、第二换能器2、第三换能器3和第四换能器4，并且组建为直射式双声道结构；每个换能器既为发射换能器，又为接收换能器。
所述发射/接收信号通道切换电路由激励选通电路、变压器放大电路和回波选通电路组成。
所述驱动信号生成和放大电路由高速DAC信号产生与输出电路，驱动信号电压放大和功率放大电路组成。
所述回波信号调理与采集电路由电压放大电路、带通滤波器电路、自增益控制电路、单端信号转差分信号电路、偏置电路和高速ADC信号采集与转换电路组成。
所述时序控制与信号处理电路由FPGA电路系统和DSP电路系统组成。其中，FPGA电路系统主要由FPGA芯片、FPGA芯片串行配置器电路，以及FPGA复位和配置按键电路组成，其中FPGA芯片的型号为EP2C8Q208C8N；DSP电路系统主要由DSP芯片和DSP芯片引导模式选择电路组成，其中DSP芯片的型号为TMS320F28335。
本发明的电路系统按功能分为模拟板和数字板，模拟板包括发射/接收信号通道切换电路、驱动信号电压放大和功率放大电路、回波选通电路、电压放大电路、带通滤波器电路、自增益控制电路、单端信号转差分信号电路、偏置电路，以及电源管理模块中的模拟电源(+12V、-12V、+5V、-5V)转换电路；数字板包括高速DAC信号产生与输出电路、高速ADC信号采集与转换电路、FPGA电路系统、DSP电路系统，以及电源管理模块中的数字电源(+3V3、+1V9、+1V2)转换电路。
本发明的电路系统的工作过程为：FPGA芯片在检测到DSP芯片发出的“开始测量”信号后，立即使能其内部的延时电路，同时调用内部ROM模块中存储的波形数据，并且以20MSPS的速率传输至驱动信号生成和放大电路。由高速DAC生成的驱动信号，经过电压放大和功率放大之后，经由DSP芯片控制的发射信号通道切换电路，输出至发射换能器端。发射换能器基于压电晶体的电致伸缩效应，发出超声波。管道内的超声波经过一段渡越时间之后，达到相应的接收换能器端。由于压电晶体的压电效应，接收换能器输出回波电信号。回波信号经由DSP芯片控制的接收信号通道切换电路之后，输入至回波信号调理和采集电路，经过放大、带通滤波和自增益电路之后，由高速ADC依据FPGA芯片提供的5MHz 采样频率完成数据转换。FPGA芯片内部的双口RAM用于暂存高速ADC的转换码值，当延迟电路确定的延迟时间到达以后，通过并口线传输至DSP芯片。DSP芯片采用数字滤波进一步消除回波信号中混杂的噪声，采用跟踪回波信号最大峰值的可变阈值过零检测方法，计算超声回波的传播时间。第一换能器1、第二换能器2、第三换能器3和第四换能器4依次作为发射换能器，重复上述过程，综合4个声道的回波传播时间，即可计算出实际气体流量。变送器计算出工况下的气体流量之后，既可以通过液晶实现现场显示，也可以通过串口通讯模块实现远程读取。
图2为高速DAC信号产生与输出电路，由双路差分线路驱动器U2、电阻R2、R9、R5、R7、R10、R12、R14、R16、R18、R20、R22、R24、R25、电容C11、C12、C13、C14、C18、C20和C21组成。U2为高速电流输出型DAC，U2的DB0至DB8引脚分别通过电阻R5、R7、R10、R12、R14、R16、R18、R20、R22和R25连接至FPGA相应的数据输出引脚，在数据传输线中串入小电阻，有利于抑制高速信号的反射和振荡。电阻R2连接至U2的FSADJ引脚，用于调整满量程输出电流值。电容C11、C12和C13为退耦电容。电阻R9将U1的IOUTB的输出下拉到地。电容C14和C18为补偿电容，分别将U2的带宽/噪声抑制节点COMP1和开关驱动电路的内部偏置节点COMP2连接至电源轨3.3V和“地”。C20、C21为退耦电容。U2的CLOCK引脚通过电阻R24连接至FPGA的时钟输出引脚。高速DAC的转换结果OUTPUT经由IOUTA引脚输出。
图3为驱动信号电压放大和功率放大电路，由低噪声高速运放U1、电阻R13、R14、R15、R16、R17、R22、R27、R28、R29、R30、R31、R32、R33、R35、R44、电容C25和C26组成。DAC_OUTPUT为高速DAC输出的电流信号，经由电阻R16转换为电压信号。电容C25为滤波电容，电容C26为隔直电容，电阻R16为U1的同相输入端提供直流路径，防止运放因为偏置电流产生输出饱和。电阻R17为匹配电阻，用于平衡运放U1的输入阻抗。电阻R13和R14用于设置电压增益。U2为双路差分线路驱动器，采用电流负反馈形式，具备高带宽、高驱动电流及低失真特性。电阻R33起连接作用，电阻R35、R44、R22、R27用于设置放大增益；U2的两路输出经由电阻R31和R28实现电流并联，进一步增强了功率放大能力。经过电压放大和功率放大的驱动信号最终经由电阻R30向下级传输。
图4所示为激励选通电路和变压器放大电路。其中激励选通电路包括四个双极性运放U3A、U3B、U3C和U3D；由变压器T1、T2、T3和T4构成变压器放大电路；T1、T2、T3和T4为匝比1∶10的变压器，引脚1、2对应为变压器的副边；引脚3、4对应为变压器的原边。U3为双极性运放。OUTPUT为前级经过电压和功率放大之后的驱动信号。OC1、OC2、OC3和OC4为DSP输出的换能器发射选通信号。为方便起见，先以OC1控制逻辑为例说明电路工作原理，其他通道类似。当OC1置低时，U3D输出电压接近其负电源轨(约-12V)，N沟道增强型MOS管Q4和Q8不导通，驱动信号不能到达换能器端；当OC1置高时，U3D输出电压接近其正电源轨(约+12V)，此时，Q4和Q8导通，驱动信号到达变压器原边，经由变压器放大之后，经由若干二极管搭建的桥式电路最终到达换能器连接端W1。电阻R34为下拉电阻，为该电路提供初始输入电平。电阻R21和R26为下拉限流电阻。电容C30和二极管D36共同构成MOS管Q4和Q8保护电路，防止其被意外击穿。电阻R4和R12构成分压电路，可以根据不同的换能器特性进行调整；电阻R11起连接作用。TP4为测试端口。COM1对应为连接至W1的换能器作为接收换能器时产生的回波信号。
图5所示为通道1的回波选通电路，其他3个通道与其类似。U4为双路低阻抗单刀单掷开关，兼容3V逻辑电平，采用12V供电时，通道间的串扰仅为-70dB。IC1和NIC1为DSP输出的换能器1选通信号和关断信号。当IC1置高时，选通S1和D1，即将COM1 接入后续的回波信号调理和采集电路。JUMP1为调试端口。电阻R48、R49、R50为下拉电阻；被选通的回波信号经由电阻R47输出至后续电路。
图6所示为回波信号调理与采集电路中的电压放大电路，由低噪声高速运放U10、电容C98、C100、电阻R59、R63、R64、R77、R81、R78、R83组成，其中电阻R77、R81和低噪声高速运放U10构成反相放大电路；其中电阻R78、R83和低噪声高速运放U10构成同相放大电路。Signal_0为前端被选通的回波信号，U10为低噪声高速运放。电容C98和C100为隔直电容，并且与电阻R59一起构成高通滤波器。当选择焊接电阻R77和R81，忽略电阻R78和R83时，它们与后级运放的反馈电阻构成反相放大电路；当选择焊接电阻R78和R83，忽略电阻R77和R81时，它们与后级运放的反馈电阻构成同相放大电路，上述两种电阻的实际连接方式需要根据回波信号特征进行选择。
图7所示为回波信号调理与采集电路中的带通滤波器电路，由4阶连续时间有源滤波器U8、电阻R60、R62、R66、R67、R71、R72、R74和R75组成。通过改变外围电阻R60、R66、R71、R74、R62、R67、R72和R75即可改变该滤波器的中心频率、带宽、品质因数和增益等参数。通过电阻R65将经过前端调理的回波信号引入该滤波器，电阻R57和电容C99共同构成高通滤波器。
图8所示为回波信号调理与采集电路中的自增益控制电路，由高增益宽范围可调增益放大器U9、低功耗宽范围运放U12、低噪声高速运放U7、电阻R55、R56、R76和R68组成。其中，U7及其外围电阻R55、R56构成同相放大器。电阻R76为下拉电阻，电阻R68为Oohm连接电阻。回波信号的自增益电路主要通过U9和U10及其外围分立器件搭建的负反馈结构实现，Signal_2为该反馈环节的输入，Single_ended Signal为输出。若U9引脚3的输入电平为VC，则U9的实际增益G(dB)通过式(6)计算获得。
G(dB)＝-40(VC+1)dB            (6)
由式(6)可见，当VC从0V变化到-2V时，增益从-40dB线性的变化到+40dB。U12和三极管Q9构成了峰值检测电路。电阻R85、R91和滑阻R88用于设置峰值参考电压Vref。电阻R79为平衡电阻，电阻R70为Oohm连接电阻。电阻R89和R90构成分压电路，为U9的引脚3提供偏置电压。电阻R86和C101决定了反馈回路的调整频率。反馈电路的工作过程如下：
当Single_ended Signal的峰值大于Vref时，U12输出正向电压，三极管的基射极导通，电容C101充电，U9引脚3的输入电压产生正向变化，增益降低。于是，Single_ended Signal就减小，直到其峰值等于Vref时，自增益电路进入稳态。
当Single_ended Signal的峰值小于Vref时，U12输出负向电压，三极管的基射极截止，此时，由-5V给C101充电，U9引脚3的输入电压产生负向变化，增益提高。于是，Single_ended Signal就增大，直到其峰值等于Vref时，自增益电路进入稳态。
图9所示为回波信号调理与采集电路中的单端信号转差分信号电路，由低失真差分ADC驱动器U13、电阻R95、R96、R94、R93、R100、R98、R102、R104、电容C105、 C111组成。为了获得差分电路的最佳性能，U13的同相与反相输入端的器件参数和PCB布局布线都尽量保持对称，即电阻R95、R96、C105、R94、R93和电阻R100、R98、C111、R102、R104保持对称，其中电阻R94和C105，R102和C111分别构成一阶低通滤波。经过差分放大的双端信号，分别通过电阻R93和R104输出至下级电路。
如图10所示，Vocm为共模输入电压，由电阻R99、R101和U15构成偏置电路，通过改变电阻R99和R101的比值，即可配置Vocm，U15为普通低噪声运放。
图11是回波信号调理与采集电路中的高速ADC信号采集和转换电路。高速ADC信号采集和转换电路由高速ADC芯片U1、电阻R1、R27、R28、R29、R35、R37、R48、电容C15、C16、C17、C19、C22、C23、C24、C25组成；U1为双路12位流水线型。电阻R1和电容C15、C16、C17、C19和C22、C23、C24、C25，将高速ADC的参考电压配置为1V。电阻R27、R29和电容C26、C27构成差分输入信号INPUT-和INPUT+的一阶低通滤波，并且分别连接至U13的VINB-和VINB+；电阻R28、R35和电容C28、C29也构成差分输入信号INPUT-和INPUT+的一阶低通滤波，并且分别连接至U13的VINA-和VINA+。INPUT-和INPUT+连接至U13的双通道的两个输入端，冗余设计增强了系统的可靠性。通过电阻R154、R155、R156、R157、R158、R159、R160和R161可以配置DF、
Figure PCTCN2016077122-appb-000005
PD的引脚电平，即配置U13的工作模式，相应地选通A或者B通道进行转换。AD_CLK为FPGA提供给U13的时钟信号，电阻R37、R48和电容C30构成滤波电路，用于滤除时钟信号中的杂波。电容C1、C2、C3、C4、C6、C7和C10为去耦电容，电阻R3、R4、R6、R8、R11、R13、R15、R17、R19、R21、R23和R26为B通道输出缓冲电阻，防止高频电路产生反射和振铃。同理，电阻R30、R31、R32、R33、R34、R36、R38、R39、R40、R41、R42和R44为A通道输出缓冲电阻。AD_DB0至AD_DB11和AD_DA0至AD_DA11分别连接至FPGA芯片的I/O模块，将U13的转换结果输出至FPGA。
图12、13、14、15、16构成FPGA电路系统，FPGA电路系统中，FPGA芯片的型号为EP2C8Q208C8N；FPGA芯片串行配置器电路由Flash型串行配置器U8构成；FPGA复位和配置按键电路由电阻R111、R112、R113、电容C96、二极管D2和按键组成。图12～16中的U7A、U7B、U7C、U7D、U7E共同构成FPGA芯片。
其中图12所示为I/O接口子模块；图13所示为I/O电压和参考电压子模块；图14所示为内核电压和地子模块；图15所示为时钟输入子模块；图16所示为仿真接口子模块。图17所示为FPGA芯片串行配置器电路，图18所示为FPGA复位和配置按键电路。以上电路构成了FPGA芯片工作的最小系统。FPGA芯片的引脚连线主要分为以下5类：
1、连接至FPGA芯片电源和“地”参考端的引脚，该类引脚主要集中于图13、14所示电路模块。
2、连接至FPGA芯片JTAG端口和串行配置器的引脚，该类引脚主要集中于图16、17所示的电路模块，用于FPGA芯片的功能配置和程序引导。
3、连接至FPGA芯片复位电路和配置按键的引脚，该类引脚主要集中于图18所示的电路模块，用于FPGA芯片的复位与配置。
4、连接至高速ADC和高速DAC的引脚，该类引脚主要集中于图12所示电路模块，其中，DA_DATA0、DA_DATA1、DA_DATA2、DA_DATA3、DA_DATA4、DA_DATA5、DA_DATA6、DA_DATA7、DA_DATA8、DA_DATA9、DA_CLK分别连接至FPGA芯片的 IO_VB4N0_86、IO_VB4N0_87、IO_VB4N0_88、IO_VB4N0_89、IO_VB4N0_90、IO_VB4N0_92、IO_VB4N0_94、IO_VB4N0_95、IO_VB4N0_96、IO_VB4N0_97、IO_VB4N0_99引脚，用于FPGA芯片控制高速DAC产生驱动信号；AD_DA0、AD_DA1、AD_DA2、AD_DA3、AD_DA4、AD_DA5、AD_DA6、AD_DA7、AD_DA8、AD_DA9、AD_DA10、AD_DA11、AD_CLK、AD_DB0、AD_DB1、AD_DB2、AD_DB3、AD_DB4、AD_DB5、AD_DB6、AD_DB7、AD_DB8、AD_DB9、AD_DB10、AD_DB11分别连接至FPGA芯片的IO_VB4N0_82、IO_VB4N0_81、IO_VB4N0_80、IO_VB4N0_77、IO_VB4N0_76、IO_VB4N1_75、IO_VB4N1_74、IO_VB4N1_72、IO_VB4N1_70、IO_VB4N1_69、IO_VB4N1_68、VREFB4N1、IO_VB4N1_64、IO_VB3N1_105、IO_VB3N1_106、IO_VB3N1_108、IO_VB3N1_110、IO_VB3N1_112、IO_VB3N1_113、IO_VB3N1_114、IO_VB3N1_115、IO_VB3N1_116、IO_VB3N1_118、IO_VB3N1_127、IO_VB3N1_128引脚，用于FPGA芯片控制高速ADC以预定采样频率完成回波信号的采集与转换，并且将转换结果上传至FPGA芯片内部的双口RAM模块。
5、连接至DSP芯片的引脚，该类引脚主要集中于图12所示的电路模块。其中，连接至引脚IO_VB1N0_8的DA_RSTn用于接收DSP芯片发出的开始测量指令，启动高速DAC输出驱动信号；连接至引脚IO_VB1N0_6的RAM_RSTn用于接收DSP芯片发出的复位指令，初始化FPGA芯片片内双口RAM中暂存数据；当FPGA芯片片内双口RAM中存储的高速ADC转换码值达到一定数量后，连接至引脚IO_VB1N1_46的INT2DSP将向DSP芯片发送接受请求信号；连接至引脚IO_VB1N0_5的READ_EN用于检测DSP芯片发出的读取指令，表明DSP芯片已经做好接收数据的准备；连接至引脚CRC_ERROR的READ_CLK用于控制FPGA芯片和DSP芯片之间的数据传递速度；连接至IO_VB1N1_45、IO_VB1N1_44、IO_VB1N1_43、IO_VB1N1_41、IO_VB1N1_40、IO_VB1N1_39、VREFB1N1、IO_VB1N1_35、IO_VB1N1_34、IO_VB1N1_33、IO_VB1N1_31、IO_VB1N1_30引脚的DATA2DSP0、DATA2DSP1、DATA2DSP2、DATA2DSP3、DATA2DSP4、DATA2DSP5、DATA2DSP6、DATA2DSP7、DATA2DSP8、DATA2DSP9、DATA2DSP10、DATA2DSP11，用于将FPGA芯片中暂存的采样数据并行传输至DSP芯片。
图19所示为DSP电路系统，DSP电路系统中，DSP芯片的型号为TMS320F28335；DSP芯片引导模式选择电路由电阻R49、R50、R51、R52、R53、R54、R55和R56组成，见图20；
DSP芯片引脚连线主要分为以下5类：
1、连接至DSP芯片电源和“地”参考端的引脚。
2、连接至DSP芯片JTAG端口的引脚。引脚80、78、87、79、76、77、85、86分别连接至DSP芯片JTAG端口的相应引脚。
3、连接至发射/接收信号通道切换电路的引脚。其中，连接至引脚99、74的OC0、IC0，连接至引脚95、72的OC1、IC1，连接至引脚91、98的OC2、IC2，连接至引脚97、96的OC3、IC3分别对应控制换能器1、2、3、4的发射和接收信号的通道切换。如图1所示，当第一换能器1处于发射状态时，第三换能器1处于接收状态，对应的声道记做通道A；当第二换能器2处于发射状态时，第四换能器4处于接收状态，对应的声道记做通道B；当第三换能器3处于发射状态时，第一换能器1处于接收状态，对应的声道记做通道C；当第四换能器4处于发射状态时，第二换能器2处于接收状态，对应的声道记做通道D，如此循环1次，完成1次超声流量计量。连接至引脚75、73、90、94的NIC0、NIC1、NIC2、NIC3分别对应为IC0、IC1、IC2、IC3的“非”逻辑信号。
4、连接至FPGA芯片的控制和数据传输引脚。其中，连接至引脚152的DA_RSTn，用于启动流量测量，通知FPGA芯片启动外部DAC模块输出驱动信号；连接至引脚153的RAM_RSTn，用于初始化FPGA芯片片内双口RAM的暂存数据；连接至引脚114的INT2DSP，用于通知DSP芯片开始接收FPGA芯片内部存储的高速ADC转换码值；连接至引脚156的READ_EN，用于使能FPGA芯片片内双口RAM的读取，DSP芯片已经完成做好接收数据的准备；连接至引脚158的READ_CLK，用于DSP芯片控制数据转移的速度，为数据传递提供时钟信号；连接至引脚115、116、119、122、、23、124、127、128、129、130、131、132的DATA2DSP0～DATA2DSP11，用于并行接收FPGA芯片中暂存的采样数据。
5、连接至其他功能模块的引脚，例如：连接至引脚10、11、12、13的
Figure PCTCN2016077122-appb-000006
FRAM_SOMI、FRAM_SIMO、FRAM_CLK，用于和外部铁电存储器之间的数据交换；连接至引脚65、64、63、62的KEY0～KEY3，用于接收外部的按键输入信号；连接至引脚66、67、68的LCD_CS、LCD_CLK、LCD_DI，用于控制外部液晶模块的显示；连接至引脚18、20的SCITXDB、SCIRXDB，用于和上位机之间的串行通讯。
DSP芯片引导模式选择电路通过配置R49和R50，R51和R52，R53和R54以及R55和R56之间的阻值比，即可修改DSP芯片的引导模式。
图21所示为时序控制与信号处理电路功能模块示意图，FPGA芯片采用Top-Down的设计方法，从顶层进行功能划分和结构设计。FPGA芯片的主要功能模块包括：分频模块、ADC控制模块、RAM_2PROT模块、DAC控制模块、ROM模块、延迟模块以及SignalTap模块，各个模块之间采用同步设计方案。其中，分频模块用于将外部输入的20MHz时钟信号调制为输出至高速ADC的5MHz采样时钟；ADC控制模块用于将高速ADC的转换码值搬运至FPGA芯片内部的RAM_2PORT模块；RAM_2PROT模块则用于存放高速ADC转换码值，当高速ADC的转换码值存储达到一定数量后，向DSP芯片发出“请求读取”信号，然后将存储的高速ADC转换码值按照一定的速率传输至DSP芯片；DAC控制模块用于将ROM模块中存储的波形数据搬运至高速DAC，产生相应的激励波形；延迟模块用于控制在激励信号发出之后，必须经过预先设定的延迟时间，才使能RAM_2PORT模块开始存储高速ADC的转换码值，节约存储空间；SignalTap模块则主要用于在程序下载之后，实时观测高速ADC的转换码值，方便程序修改和调试。
DSP芯片内部集成的以下6大功能模块：GPIO模块、中断模块、PWM模块、SCI模块、SPI模块和时钟模块，见图21。DSP芯片通过GPIO模块，并行接收FPGA芯片存储的高速ADC转换码值。此外，DSP芯片的1路GPIO作为地址锁存信号连接至FPGA芯片。DSP芯片在查询到FPGA发出的“请求读取”指令后，使能地址锁存信号，从FPGA芯片内部读取1次高速ADC的转换码值；同时，FPGA芯片内部“读指针”下移1位，重复上述操作，直至FPGA芯片内部存储的数据被全部读取。读取完成以后，DSP芯片向FPGA芯片发送“复位”指令，清除FPGA芯片内部RAM_2PORT空间和延时模块中数据，为下一次测量做准备。另外，通过DSP芯片的GPIO模块，完成按键输入和液晶显示；通过PWM模块，完成流量结果的脉冲输出，便于后期的气体实流标定；通过SCI模块，完成与上位机之间的串行通讯，便于流量结果的存储和分析；通过SPI模块完成与铁电存储器FRAM之间的双向读写，当DSP芯片检测到“掉电复位”时，及时将累积流量和仪表参数等写入FRAM。系统选用外部看门狗防止程序跑飞。此外，外部看门狗还兼有按键复位、上电/掉电复位和低电压监测等功能。
图22所示为电路系统的DSP芯片软件总体框图，软件设计采用了模块化的设计方法。 由主监控程序和各个程序模块组成；其中，各个程序模块包括初始化模块、发射/接收信号通道切换模块、与FPGA数据传输模块、中断模块、计算模块、FRAM读写模块、串口通讯模块、脉冲输出模块、按键输入模块以及液晶显示模块。主监控程序是整个系统的总调度程序，通过调动各个程序模块实行系统的各项功能。
图23为电路系统的主监控程序流程图，电路系统上电后主监控程序自动运行。主监控程序的具体操作步骤如下：
(1)电路系统初始化
电路系统上电后，DSP芯片完成各个部分的初始化：包括对DSP芯片的GPIO口进行分配，DSP芯片的内部定时器1的中断初始化，液晶显示模块初始化，从FRAM读写模块中读取累计流量、仪表的各项参数初始化，并且建立4个队列，每个队列由50个数据空位组成，用于存放4个换能器接收到的超声波的传播时间(以下简称传播时间)；每当有一个新的传播时间数据进入时，每个队列首位的数据会被抛掉，新的传播时间数据加在队列尾部。在后面的测量过程中，将根据这4个队列的数据，实时计算出双声道超声波流量计顺流和逆流的平均传播时间。
(2)进入流量检测的循环
电路系统初始化后程序就进入流量检测的循环中。首先DSP芯片通过改变对应GPIO口的输出状态，切换换能器发射与接收通道。切换通道的顺序为：第一换能器1发射第三换能器3接收；第二换能器2发射第四换能器4接收；换能器3发射第一换能器1接收；第四换能器4发射第二换能器2接收。然后再不断地循环以上的切换过程。切换通道后通知FPGA芯片开始测量，DSP芯片需要等待FPGA芯片完成信号接收。
(3)FPGA芯片控制高速DAC和高速ADC，完成信号驱动与回波信号的采集
在切换通道后，DSP芯片向FPGA芯片发送“开始测量”信号。FPGA芯片立即使能内部的延时模块，同时调用FPGA芯片内部的ROM模块中存储的波形数据，传输至驱动信号生成和放大电路；再经由DSP芯片控制的发射/接收信号通道切换电路，输出至直射式双声道结构的第一换能器1、或者第二换能器2、或者第三换能器3、或者第四换能器4，由第一换能器1、或者第二换能器2、或者第三换能器3、或者第四换能器4发出超声波；超声波经过一段渡越时间后，到达对应的接收换能器；由第三换能器3、或者第四换能器4、或者第一换能器1、或者第二换能器2接收超声波，形成回波信号；由DSP芯片控制的发射/接收信号通道切换电路接收由换能器发出的回波信号，并输入至回波信号调理和采集电路；由回波信号调理和采集电路中的高速ADC完成数据转换；FPGA芯片内部的RAM_2PORT模块用于暂存高速ADC的转换码值，当延迟电路确定的延迟时间到达以后，通过拉高设定的DSP芯片的GPIO端口告知DSP芯片信号采集完成。
(4)复制数据
DSP芯片检测到设定的端口的高电平后，将存放在FPGA芯片内部的RAM_2PORT模块中的数据复制到DSP芯片的片内RAM中，供DSP芯片对其进行数字信号处理。
在DSP芯片得知信号采集完成之前，有大约400μs的等待时间。这段时间主要是超声波在声道中传播的时间，以及FPGA芯片接收采集信号的时间。在这段时间内，DSP芯片可以完成液晶显示的更新，以及与上位机之间的通信。并非每次采集信号中都进行液晶显示的更新，以及与上位机之间的通信，而是每秒钟只做一次，这由DSP芯片内部的定时器1的时间标志来控制。即DSP芯片先判断定时器1的时间标志是否为0。如果不为0，则 完成这两项任务，然后，将定时器时间标志置为0。如果为0，则不执行。定时器1的时间标志则会在1秒一次的中断服务程序中被置为1。通过定时器1的时间标志，充分利用这段等待时间，提高系统的实时性。
(5)DSP芯片对数据进行处理，计算超声波的传播时间
DSP芯片对复制的数据进行处理，计算每次超声波的传播时间。
接收到的超声波信号波形如图24所示，信号波形类似幅值经过调制的正弦波，有多个波，各个波的峰值先是逐渐增大，然后再逐渐减小，直至衰减为零。首先对采样的信号进行数字滤波，这里采用截止频率为200kHz±180kHz的四阶带通IIR型数字滤波器。回波信号经过滤波后，噪声含量减小。我们将滤波后0流量和640m3/h流量下信号的波形对齐，绘制在同一张图上，如图25所示。可见，这两个流量下的回波信号的形状基本一致，所以，回波信号中每个波的峰值与最大峰幅值的比例也应该基本一致。我们可以利用回波信号的这种特点，准确地找到某一个特征波。首先，在滤波后的回波信号中找到最大峰值Amax，再根据最大峰值设定一个可变的阈值SW(SW＝α·Amax)。其中，α为一个固定值，事先通过统计计算得到。以图25对应的换能器为例，在0～800m3/h流量范围之间，每隔100m3/h取一个流量点，在每个流量点下采集50次回波信号，然后，用MATLAB对其进行分析，计算回波信号中各个峰值与最大峰值的比例。可见，在各个流量下，第5个波与第6个波与最大峰的比值基本上是不变的。第5个波的波峰与最大峰的比值维持在0.39左右，而第6个波的波峰与最大峰的比值则维持在0.53左右。所以，取α为两者的均值，即0.46。用SW去检测回波信号，当回波信号的幅值第一次达到这个阈值时，所对应的波就是要找的特征波。这种确定回波信号中特征波的方法称为可变阈值方法。
通过这种可变阈值方法准确地找到特征波后，就可以以此特征波为依据，来计算所需的过零点。这里采用特征波后的8个过零点，通过这8个点的平均值，计算传播时间，以消除一些随机误差，提高测量精度。按照时间顺序排列，这8个过零点对应的时间分别为：τ1，τ2...τ8。
通过这种可变阈值的过零检测方法准确地找到特征波后，就可以以此特征波为依据来计算所需的过零点。这里采用特征波后的8个过零点，通过这8个点的平均值，计算传播时间。这样可以消除一些随机误差，提高测量精度。这8个过零点代表的时间按照时间顺序排列分别为：τ1，τ2...τ8。在确定过零点时间时，采用线性插值的方法，如图26所示。若第n点的幅值为x(n)，第n+1点的幅值为x(n+1)，且x(n)与x(n+1)数值的极性相反，那么，第n点和第n+1点的之间必有一个过零点，可通过式(7)进行线性插值运算，计算出信号过零点τi(i＝1，2，3...8)：
Figure PCTCN2016077122-appb-000007
式中，Tc为信号采样的周期，因为采样频率是5MHz，这里Tc＝0.2μs，n为第i个过零点对应的点数；x(n)与x(n+1)分别是第n点和第n+1点的幅值。
在超声波气体流量计中，超声波在介质中传播的时间越长，那么，这8个过零点的时间也相应越长。这8个过零点所对应的时间与超声波的传播时间都成线性关系，因此，传播时间T可通过式(4)计算获得：
Figure PCTCN2016077122-appb-000008
式中，τi(i＝1，2，3...8)为由式(7)计算获得的过零点时间，t′为一个固定的偏差值，该偏差值可以在零流量的情况下计算出来。
当管道内气体不流动情况下，首先，依据测量声道的长度以及实际声速计算出超声回波的传播时间T0，然后依据式(7)计算获得此时8个过零点对应的时间τ0i(i＝1，2，3...8)，最后，通过式(8)计算出改固定偏差值t′。
Figure PCTCN2016077122-appb-000009
得到t′后，就可根据式(7)和(4)实时计算出超声波的传播时间。
(6)计算瞬时流量
进行一次步骤(2)～(5)的循环，就可以得到一次超声波从一个换能器到另外一个换能器之间的传播时间。
在步骤(2)中切换不同的发射换能器和接收换能器，这样就可以不断地依次测量出每个声道顺流和逆流信号的传播时间。这样循环4次，就完成了双声道顺流和逆流传播时间的测量，并将这4个传播时间分别放入步骤(1)中所建立的4个队列中。
执行5次这样的测量，计算出双声道顺流和逆流的平均传播时间，并根据这个平均传播时间计算出平均流量，并作为瞬时流量显示。
为了提高系统测量的稳定性，避免极端情况下出现的粗大误差，采用判断“台阶”的方法，即在计算平均流量时，首先将某一个声道对应的传播时间队列里的50个数据取出，存放在另外开辟的数组中，然后，将代表50次测量的传播时间的数据从小到大进行排序。如果这50次测量结果中存在粗大误差，那么，排序后的传播时间值就会出现明显的“台阶”现象，如图27所示。通过判断“台阶”，将数据分成若干段，点数最多的那一段数据即为正确的传播时间数据。以图27为例，“台阶”出现在第5点和第40点，这50个传播时间数据，则被分为3小段：1～4点、5～39点以及40～50点。数据点数最多的5～39段为测量正确的传播时间。然后，将正确的传播时间数据求其均值，即可得到该个通道的平均传播时间t。
计算出4个声道的平均传播时间t1、t2、t3、t4后，就可以根据式(5)计算出测得瞬时流量Q。
Figure PCTCN2016077122-appb-000010
式中，Q为测得瞬时流量，D为管道直径，L为声道长度，θ为声道角(超声波传播路径与管道轴线之间的夹角)的角度，ts、tn、Δt分别为顺流传播时间、逆流传播时间以及它们的时间差，kf是仪表系数。可见，流量Q与
Figure PCTCN2016077122-appb-000011
成正比。通过标定实验得到kf。由t1、t2、t3、t4计算出时间差Δt和tstn，分别如式(9)和(10)所示。
Figure PCTCN2016077122-appb-000012
Figure PCTCN2016077122-appb-000013
在标定开始时，先初步给定一个仪表系数的初值，标一个流量点(例如，400m3/h左右)，根据测量值与标准值之间的关系，修正仪表系数，得到准确的kf。
确定kf后，就可以通过式(7)、(4)、(5)实时计算流量。由于流场分布、声音传播路径变化等因素影响，实际流量与
Figure PCTCN2016077122-appb-000014
呈非线性关系。为了减小非线性误差，根据实流标定结果对误差进行分段线性修正。在流量30～800m3/h之间选择30、60、80、100、200、300、400、500、600、700、800m3/h这11个流量点进行标定，得到这些流量点的误差，即得到了流量与误差之间的关系曲线。对这一关系曲线进行分段线性化，就可以计算出30～800m3/h之间任一流量点对应的误差，那么，就可以修正测量的流量值。假设测量得到的流量值为Q′，该流量点对应的误差为e(Q′)，那么，修正后的瞬时流量Q为：
Q＝Q′-Q′·e(Q′)              (11)
(7)计算累积流量
在得到修正后的瞬时流量后，由DSP芯片的内部定时器1的中断服务程序计算累积流量，以保证1秒钟累积一次，即定时器中断由DSP芯片内部定时器1产生，周期为1秒；图28为DSP芯片的内部定时器1的中断服务程序流程图。定时器中断服务程序首先读取主监控程序计算的瞬时流量结果，并累加得到累积流量；再根据瞬时流量的值更新脉冲输出模块的参数，输出一定频率的脉冲，表示测得的瞬时流量；然后，将定时器时间标志置为1，以便在主监控程序中更新液晶显示以及进行上位机通信。

Claims (11)

  1. 一种基于FPGA和DSP的气体超声流量计变送器，其特征在于：由气体超声换能器和传感器单元、发射/接收信号通道切换电路、驱动信号生成和放大电路、回波信号调理与采集电路、时序控制与信号处理电路、人机接口、串口通讯和电源管理模块组成；
    所述气体超声换能器和传感器单元固定在输送气体的管道上；
    所述驱动信号生成和放大电路由高速DAC信号产生与输出电路、驱动信号电压放大和功率放大电路组成；
    所述回波信号调理与采集电路由电压放大电路、带通滤波器电路、自增益控制电路、单端信号转差分信号电路、偏置电路和高速ADC信号采集与转换电路组成；
    所述时序控制与信号处理电路由FPGA电路系统和DSP电路系统组成，其中，FPGA电路系统主要由FPGA芯片、FPGA芯片串行配置器电路，以及FPGA芯片复位和配置按键电路组成；DSP电路系统主要由DSP芯片和DSP芯片引导模式选择电路组成。
  2. 根据权利要求1所述的一种基于FPGA和DSP的气体超声流量计变送器，其特征在于：所述气体超声换能器和传感器单元由四个换能器、压力传感器和温度传感器组成，每个换能器既为发射换能器，又为接收换能器。
  3. 根据权利要求2所述的一种基于FPGA和DSP的气体超声流量计变送器，其特征在于所述发射/接收信号通道切换电路由激励选通电路、变压器放大电路和四个回波选通电路单元组成；四个回波选通电路单元为相同结构的电路单元，且分别与四个换能器对应连接。
  4. 根据权利要求1所述的一种基于FPGA和DSP的气体超声流量计变送器，其特征在于：所述FPGA芯片用于暂存回波信号调理和采集电路传送来的转换码值，当确定了延迟时间，并传输至DSP芯片；所述DSP芯片为主控芯片，负责数字信号处理以及人机交互、串口通讯，并且与FPGA电路系统配合完成整个系统的时序控制；由DSP芯片采用数字滤波消除信号中混杂的噪声，采用跟踪回波信号最大峰值的可变阈值过零检测方法，计算超声回波的传播时间，进而获得气体流量。
  5. 根据权利要求3或4所述的一种基于FPGA和DSP的气体超声流量计变送器，其特征在于：所述高速DAC信号产生与输出电路由双路差分线路驱动器U2、电阻R2、R9、R5、R7、R10、R12、R14、R16、R18、R20、R22、R24、R25、电容C11、C12、C13、C14、C18、C20和C21组成；高速DAC信号产生与输出电路将输出能够抑制反射和振荡的高速电流信号；
    所述驱动信号电压放大和功率放大电路由低噪声高速运放U1、电阻R13、R14、R15、R16、R17、R22、R27、R28、R29、R30、R31、R32、R33、R35、R44、电容C25和C26组成；
    双路差分线路驱动器U2实现两路输出，进一步增强了功率放大能力；经过电压放大和功率放大的驱动信号最终向下级传输。
  6. 根据权利要求3或4所述的一种基于FPGA和DSP的气体超声流量计变送器，其特征在于：所述激励选通电路包括四个双极性运放U3A、U3B、U3C和U3D；所述变压器放大电路由变压器T1、T2、T3和T4组成，且匝比均为1∶10；所述回波选通电路由四个回波选通电路单元组成；
    每个回波选通电路单元由双路低阻抗单刀单掷开关U4、电阻R47、R48、R49和R50组成，双路低阻抗单刀单掷开关U4的IC1端口和NIC1端口为DSP输出的一个换能器的选通信号和关断信号；当IC1置高时，选通S1和D1，即将COM1接入后续的回波信号调理和采集电路；其中的JUMP1为调试端口；电阻R48、R49、R50为下拉电阻；被选通的 回波信号经由电阻R47输出至后续电路。
  7. 根据权利要求3或4所述的一种基于FPGA和DSP的气体超声流量计变送器，其特征在于：所述回波信号调理与采集电路中，
    所述电压放大电路由低噪声高速运放U10、电容C98、C100、电阻R59、R63、R64、R77、R81、R78、R83组成，其中电阻R77、R81和低噪声高速运放U10构成反相放大电路；其中电阻R78、R83和低噪声高速运放U10构成同相放大电路；
    所述带通滤波器电路由4阶连续时间有源滤波器U8、电阻R60、R62、R66、R67、R71、R72、R74和R75组成；通过改变外围电容C99、电阻R57、R60、R65、R66、R71、R74、R62、R67、R72和R75即可改变该滤波器的中心频率、带宽、品质因数和增益参数；通过电阻R65将经过前端调理的回波信号引入该滤波器，电阻R57和电容C99共同构成高通滤波器；
    所述自增益控制电路由高增益宽范围可调增益放大器U9、低功耗宽范围运放U12、低噪声高速运放U7、电阻R55、R56、R76和R68组成；U7及其外围电阻R55、R56构成同相放大器；电阻R76为下拉电阻，电阻R68为0ohm连接电阻；回波信号的自增益通过U9和U10及其外围分立器件搭建的负反馈结构实现；
    所述单端信号转差分信号电路由低失真差分ADC驱动器U13、电阻R95、R96、R94、R93、R100、R98、R102、R104、电容C105、C111组成，其中电阻R95、R96、C105、R94、R93和电阻R100、R98、C111、R102、R104保持对称，其中电阻R94、C105和R102、C111分别构成一阶低通滤波；Vocm为共模输入电压；
    所述偏置电路由普通低噪声运放U15、电阻R99和R101组成；
    所述高速ADC信号采集和转换电路由高速ADC芯片U1、电阻R1、R27、R28、R29、R35、R37、R48、电容C15、C16、C17、C19、C22、C23、C24、C25组成；
    所述回波信号调理与采集电路将ADC驱动器U13的转换结果输出至所述时序控制与信号处理电路中的FPGA电路系统。
  8. 根据权利要求3或4所述的一种基于FPGA和DSP的气体超声流量计变送器，其特征在于：所述时序控制与信号处理电路中，
    所述FPGA电路系统中，FPGA芯片的型号为EP2C8Q208C8N；FPGA芯片串行配置器电路由Flash型串行配置器U8构成；FPGA复位和配置按键电路由电阻R111、R112、R113、电容C96、二极管D2和按键组成；FPGA芯片由U7A、U7B、U7C、U7D、U7E共同构成；
    所述DSP电路系统中，DSP芯片的型号为TMS320F28335；DSP芯片引导模式选择电路由电阻R49、R50、R51、R52、R53、R54、R55和R56组成；
    工作时，DSP芯片向FPGA芯片发送“开始测量”的信号，FPGA芯片立即使能部的延时电路，同时调用FPGA芯片中存储的波形数据，传输至驱动信号生成和放大电路，再经由DSP芯片控制的发射/接收信号通道切换电路输出至所述四个换能器，形成超声回波信号；由DSP芯片控制的所述发射/接收信号通道切换电路接收由四个换能器发出的超声回波信号，并输入至回波信号调理和采集电路，由回波信号调理和采集电路中的高速ADC完成数据转换。
  9. 基于FPGA和DSP的气体超声流量计变送器的控制方法，其特征在于：由主监控程序和各个程序模块组成；所述主监控程序为总调度程序，所述各个程序模块为初始化模块、铁电读写模块、通道切换模块、通信模块、与FPGA数据传输模块、脉冲输出模块、中断模块、计算模块和显示模块；主监控程序通过调动各个程序模块实行所述气体超声流量计变送器的各项功能；
    主监控程序的具体操作步骤如下：
    (1)电路系统初始化
    电路系统上电后，DSP芯片完成各个部分的初始化：包括对DSP芯片的GPIO口进行分配，DSP芯片的内部定时器1的中断初始化，液晶显示模块初始化，从FRAM读写模块中读取累计流量、仪表的各项参数初始化，并且建立4个队列，每个队列由50个数据空位组成，用于存放4个换能器接收到的超声波的传播时间；每当有一个新的传播时间数据进入时，每个队列首位的数据会被抛掉，新的传播时间数据加在队列尾部，在后面的测量过程中，将根据这4个队列的数据，实时计算出双声道超声波流量计顺流和逆流的平均传播时间；
    (2)进入流量检测的循环
    电路系统初始化后程序就进入流量检测的循环中；首先DSP芯片通过改变对应GPIO口的输出状态，切换换能器发射与接收通道，切换通道的顺序为：第一换能器发射第三换能器接收；第二换能器发射第四换能器接收；第三换能器发射第一换能器接收；第四换能器发射第二换能器接收；然后再不断地循环以上的切换过程；切换通道后通知FPGA芯片开始测量，DSP芯片需要等待FPGA芯片完成信号接收；
    (3)等待FPGA芯片控制高速DAC和高速ADC完成信号驱动与回波信号的采集
    DSP芯片向FPGA芯片发送“开始测量”信号，FPGA芯片立即使能内部的延时模块，同时调用FPGA芯片内部的ROM模块中存储的波形数据，传输至驱动信号生成和放大电路；再经由DSP芯片控制的发射/接收信号通道切换电路，输出至直射式双声道结构的第一换能器、或者第二换能器、或者第三换能器、或者第四换能器，由第一换能器、或者第二换能器、或者第三换能器、或者第四换能器发出超声波；超声波经过一段渡越时间后，到达对应的接收换能器；由第三换能器、或者第四换能器、或者第一换能器或者第二换能器接收超声波，形成回波信号；由DSP芯片控制的发射/接收信号通道切换电路接收由换能器发出的回波信号，并输入至回波信号调理和采集电路；由回波信号调理和采集电路中的高速ADC完成数据转换；FPGA芯片内部的RAM_2PORT模块用于暂存高速ADC的转换码值，当延迟电路确定的延迟时间到达以后，通过拉高设定的DSP芯片的GPIO端口告知DSP芯片信号采集完成；
    (4)复制数据
    DSP芯片检测到设定的端口的高电平后，将存放在FPGA芯片内部的RAM_2PORT模块中的数据复制到DSP芯片的片内RAM中，供DSP芯片对其进行数字信号处理；
    (5)DSP芯片对数据进行处理，计算超声波的传播时间
    DSP芯片对复制的数据进行处理，计算每次超声波的传播时间T为：
    Figure PCTCN2016077122-appb-100001
    式中，τi(i＝1，2，3...8)为过零点时间，t′为一个固定的偏差值，该偏差值为零流量的情况下计算得到；
    (6)计算瞬时流量
    进行一次步骤(2)～(5)的循环，就可以得到一次超声波从一个换能器到另外一个换能器之间的传播时间；
    在步骤(2)中切换不同的发射换能器和接收换能器，这样就可以不断地依次测量出每个声道顺流和逆流信号的传播时间；这样循环4次，就完成了双声道顺流和逆流传播时间的测量，并将这4个传播时间分别放入步骤(1)中所建立的4个队列中；
    执行5次这样的测量，计算出双声道顺流和逆流的平均传播时间，并根据这个平均传播时间计算出平均流量，并作为瞬时流量显示；
    瞬时流量的计算式为：
    Figure PCTCN2016077122-appb-100002
    式中，Q为测得瞬时流量，D为管道直径，L为声道长度，θ为声道角的角度，所述声道角为超声波传播路径与管道轴线之间的夹角；ts、tn、Δt分别为顺流传播时间、逆流传播时间以及它们的时间差，kf是仪表系数；
    再通过修正操作，得到修正后的瞬时流量；
    (7)计算累积流量
    在得到修正后的瞬时流量后，由DSP芯片的内部定时器1的中断服务程序计算累积流量，以保证1秒钟累积一次，即定时器中断由DSP芯片内部定时器1产生，周期为1秒；定时器中断服务程序首先读取主监控程序计算的瞬时流量结果，并累加得到累积流量；再根据瞬时流量的值更新脉冲输出模块的参数，输出一定频率的脉冲，表示测得的瞬时流量；然后，将定时器时间标志置为1，以便在主监控程序中更新液晶显示以及进行上位机通信。
  10. 根据权利要求9所述的基于FPGA和DSP的气体超声流量计变送器的控制方法，其特征在于：
    FPGA芯片的片内逻辑和存储资源设有7大功能模块，分别为分频模块、ADC控制模块、RAM_2PROT模块、DAC控制模块、ROM模块、延迟模块和SignalTap模块；其中，分频模块用于将外部输入的20MHz时钟信号调制为输出至高速ADC的5MHz采样时钟；ADC控制模块用于将高速ADC的转换码值搬运至FPGA芯片内部的RAM_2PORT模块；RAM_2PROT模块则用于存放高速ADC转换码值，当高速ADC的转换码值存储达到一定数量后，向DSP芯片发出“请求读取”信号，然后将存储的高速ADC转换码值按照一定的速率传输至DSP芯片；DAC控制模块用于将ROM模块中存储的波形数据搬运至高速DAC，产生相应的激励波形；延迟模块用于控制在激励信号发出之后，必须经过预先设定的延迟时间，才使能RAM_2PORT模块开始存储高速ADC的转换码值，节约存储空间；SignalTap模块则主要用于在程序下载之后，实时观测高速ADC的转换码值，方便程序修改和调试；
    DSP芯片通过GPIO模块，并行接收FPGA芯片存储的高速ADC转换码值；此外，DSP芯片的1路GPIO作为地址锁存信号连接至FPGA芯片；DSP芯片在查询到FPGA发出的“请求读取”指令后，使能地址锁存信号，从FPGA芯片内部读取1次高速ADC的转换码值；同时，FPGA芯片内部“读指针”下移1位，重复上述操作，直至FPGA芯片内部存储的数据被全部读取；读取完成以后，DSP芯片向FPGA芯片发送“复位”指令，清除FPGA芯片内部RAM_2PORT空间和延时模块中数据，为下一次测量做准备；另外，通过DSP芯片的GPIO模块，完成按键输入和液晶显示；通过PWM模块，完成流量结果的脉冲输出，便于后期的气体实流标定；通过SCI模块，完成与上位机之间的串行通讯，便于流量结果的存储和分析；通过SPI模块完成与铁电存储器FRAM之间的双向读写，当DSP芯片检测到“掉电复位”时，及时将累积流量和仪表参数等写入FRAM。
  11. 根据权利要求9所述的基于FPGA和DSP的气体超声流量计变送器的控制方法，其特征在于：所述各个程序模块还包括看门狗模块，系统选用外部看门狗防止程序跑飞；此外，外部看门狗还兼有按键复位、上电/掉电复位和低电压监测功能。
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