WO2016145694A1 - Coa型液晶面板的制作方法及coa型液晶面板 - Google Patents

Coa型液晶面板的制作方法及coa型液晶面板 Download PDF

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WO2016145694A1
WO2016145694A1 PCT/CN2015/075852 CN2015075852W WO2016145694A1 WO 2016145694 A1 WO2016145694 A1 WO 2016145694A1 CN 2015075852 W CN2015075852 W CN 2015075852W WO 2016145694 A1 WO2016145694 A1 WO 2016145694A1
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Prior art keywords
layer
disposed
insulating layer
liquid crystal
drain
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Ceased
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PCT/CN2015/075852
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English (en)
French (fr)
Inventor
徐洪远
孙博
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/758,563 priority Critical patent/US20170038653A1/en
Publication of WO2016145694A1 publication Critical patent/WO2016145694A1/zh
Anticipated expiration legal-status Critical
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    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/103—Materials and properties semiconductor a-Si
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a COA liquid crystal panel and a COA liquid crystal panel.
  • Liquid crystal display has many advantages such as thin body, power saving, and no radiation, and has been widely used. Such as: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or laptop screen.
  • a liquid crystal display device includes a housing, a liquid crystal panel disposed in the housing, and a backlight module disposed in the housing.
  • the structure of the liquid crystal panel is mainly composed of a Thin Film Transistor Array Substrate (TFT Array Substrate), a color filter substrate (Color Filter, CF), and a liquid crystal layer disposed between the two substrates (Liquid).
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • Color Filter Color Filter
  • the crystal layer is constructed by controlling the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on the two glass substrates, and refracting the light of the backlight module to produce a picture.
  • LTPS TFT technology is a new technology that has the advantage of higher carrier mobility than amorphous silicon (a-si) and oxide type TFTs. Rate, can enhance the display drive capability and reduce power consumption.
  • a-si amorphous silicon
  • oxide type TFTs oxide type TFTs. Rate
  • the mainstream LTPS TFT is a top gate type structure.
  • the method of preventing photocurrent is to deposit a layer of amorphous silicon as a protective layer on the glass substrate to absorb light, or directly deposit a layer of metal to block light.
  • the liquid crystal may be disorderly reversed due to uneven terrain and lack of voltage control, and a large black matrix (Black Matrix, BM) needs to be used on the CF substrate side. ) occlusion.
  • Black Matrix, BM Black Matrix
  • COA Color filter On Array
  • the COA structure reduces the coupling of the pixel electrode and the metal trace, and the delay condition of the signal on the metal line is improved.
  • the COA structure can significantly reduce the size of the parasitic capacitance, increase the panel aperture ratio, and improve the panel display quality.
  • FIG. 1 is a schematic cross-sectional view of a conventional COA type liquid crystal panel, which mainly includes an array substrate 100, a glass substrate 200 disposed opposite to the array substrate 100, and between the array substrate 100 and the glass substrate 200. Liquid crystal layer 300.
  • FIG. 2 is a schematic plan view of the array substrate 100 of the COA liquid crystal panel of FIG. 1. Said The array substrate 100 includes red, green, and blue sub-pixel regions, and each of the sub-pixel regions includes a substrate 110, an amorphous silicon layer 210 disposed on the substrate 110, and the amorphous silicon layer 210 and the substrate 110.
  • a buffer layer 310 a polysilicon layer 400 disposed on the buffer layer 310 above the amorphous silicon layer 210, a gate insulating layer 510 disposed on the polysilicon layer 400 and the buffer layer 310, and the polysilicon layer a gate electrode 500 disposed on the gate insulating layer 510, an interlayer insulating layer 520 disposed on the gate electrode 500 and the gate insulating layer 510, and an interlayer insulating layer 520 disposed on the interlayer insulating layer 520.
  • the polysilicon layer 400 includes a channel 430, two N-type lightly doped regions 410 on both sides of the channel 430, and two N-type heavily doped regions 420 located outside the two N-type lightly doped regions 410, the layers
  • the first insulating via 610 is disposed above the N-type heavily doped region 420, and the color resist layer 540 and the passivation layer 530 correspond to the source/drain.
  • a second via 810 is disposed above the pole 600, and the source/drain 600 is respectively in contact with the N-type heavily doped region 420 via the first via 610, and the pixel electrode layer 800 is The second via 810 is in contact with the source/drain 600.
  • a black matrix 910 is disposed on the glass substrate 200, and a common electrode layer 900 is disposed on the black matrix 910.
  • the color resist layer 540 forms red, green, and blue blocking blocks respectively corresponding to the red, green, and blue sub-pixel regions, and a certain block is generated between adjacent color blocking blocks during the process.
  • the degree of the intersection area 640, the liquid crystal above the intersection area 640 may be reversed due to the difference in terrain, and thus the upper area of the intersection area 640 is blocked by the black matrix 910 on the glass substrate 200, but the black matrix 910 is disposed to lose a large part. Opening ratio.
  • An object of the present invention is to provide a method for fabricating a COA type liquid crystal panel, which does not need to separately fabricate a black matrix, which simplifies the process and improves the aperture ratio, and avoids misalignment between the array substrate and the glass substrate or bending of the panel in the curved display. And the resulting light leakage.
  • Another object of the present invention is to provide a COA type liquid crystal panel which has a simple structure, a high aperture ratio, and low energy consumption.
  • the present invention provides a method for fabricating a COA type liquid crystal panel, comprising the following steps:
  • Step 1 Providing an array substrate and a glass substrate
  • the array substrate includes red, green, and blue sub-pixel regions, and each sub-pixel region includes a base. a plate, an amorphous silicon layer disposed on the substrate, a buffer layer disposed on the amorphous silicon layer and the substrate, and a polysilicon layer disposed on the buffer layer and disposed corresponding to the amorphous silicon layer a gate insulating layer on the polysilicon layer and the buffer layer, a gate electrode disposed on the gate insulating layer and corresponding to the polysilicon layer, and a scan line disposed on the gate insulating layer,
  • the gate, the scan line and the interlayer insulating layer on the gate insulating layer, the source/drain provided on the interlayer insulating layer, and the interlayer insulating layer are disposed on the interlayer insulating layer and horizontally The signal lines vertically intersecting the scan lines;
  • a first via hole is formed on the interlayer insulating layer and the gate insulating layer corresponding to the polysilicon layer, and the source/drain are respectively in contact with the polysilicon layer via the first via hole;
  • Step 2 forming a passivation layer on the source/drain, the signal line, and the interlayer insulating layer;
  • Step 3 forming a color resist layer on the passivation layer
  • the color resist layer forms red, green, and blue blocking blocks corresponding to the red, green, and blue sub-pixel regions, respectively, and a first intersection region is formed between adjacent two color blocking blocks arranged laterally, the first The intersection area is located above the signal line, a second interface area is formed between adjacent two color block blocks arranged longitudinally, and the second interface area is located above the scan line;
  • Step 4 forming a flat layer on the color resist layer, and forming a second via hole on the flat layer, the color resist layer, and the passivation layer corresponding to the source/drain;
  • Step 5 depositing and patterning a pixel electrode layer on the flat layer, forming a common electrode layer on the glass substrate;
  • the pixel electrode layer is in contact with the source/drain via the second via, the pixel electrode layer includes pixel electrode blocks respectively located in each sub-pixel region, and a lateral boundary of the pixel electrode block is located at the Above the scan line, the vertical boundary is above the signal line;
  • Step 6 Align the array substrate with the glass substrate and fill the liquid crystal layer.
  • the polysilicon layer includes a channel, two N-type lightly doped regions on both sides of the channel, and two N-type heavily doped regions respectively located outside the two N-type lightly doped regions, the first vias correspondingly Above the N-type heavily doped region, the source/drain are in contact with the N-type heavily doped region via the first via, respectively.
  • the step 2 forms the passivation layer by chemical vapor deposition.
  • the step 3 forms a color resist layer by a coating process.
  • the step 4 forms a flat layer by a coating process, and the flat layer is a transparent organic material.
  • the pixel electrode layer is formed by physical vapor deposition, and the material of the pixel electrode layer and the common electrode layer are indium tin oxide.
  • the present invention also provides a COA type liquid crystal panel, comprising an array substrate, a glass substrate disposed opposite to the array substrate, and a liquid crystal layer between the array substrate and the glass substrate;
  • the array substrate includes red, green, and blue sub-pixel regions, and each sub-pixel region includes a substrate, an amorphous silicon layer disposed on the substrate, a buffer layer disposed on the amorphous silicon layer and the substrate, a polysilicon layer disposed on the buffer layer and corresponding to the amorphous silicon layer, a gate insulating layer disposed on the polysilicon layer and the buffer layer, disposed on the gate insulating layer and corresponding to the polysilicon a gate electrode disposed on the gate, a scan line disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, the scan line and the gate insulating layer, and the interlayer insulating layer disposed on the interlayer insulating layer a source/drain, a signal line disposed on the interlayer insulating layer and vertically intersecting the scan line in a horizontal direction, and disposed on the source/drain, the signal line, and the interlayer insulating layer a passivation layer, a color resist layer
  • a first via hole is formed on the interlayer insulating layer and the gate insulating layer corresponding to the polysilicon layer, and the flat layer, the color resist layer, and the passivation layer correspond to the source/drain above Forming a second via hole; the source/drain are respectively in contact with the polysilicon layer via the first via hole, and the pixel electrode layer is in contact with the source/drain via the second via hole ;
  • the color resist layer forms red, green, and blue blocking blocks corresponding to the red, green, and blue sub-pixel regions, respectively, and a first intersection region is formed between adjacent two color blocking blocks arranged laterally, the first The intersection area is located above the signal line, and a second interface area is formed between adjacent two color block blocks arranged longitudinally, the second interface area is located above the scan line; and the pixel electrode layer is respectively located in each of the sub-sections a pixel electrode block of a pixel region, a lateral boundary of the pixel electrode block being above the scan line, and a longitudinal boundary being above the signal line.
  • the polysilicon layer includes a channel, two N-type lightly doped regions on both sides of the channel, and two N-type heavily doped regions respectively located outside the two N-type lightly doped regions, the first vias correspondingly Above the N-type heavily doped region, the source/drain are in contact with the N-type heavily doped region via the first via, respectively.
  • the flat layer is a transparent organic material.
  • a common electrode layer is disposed on the glass substrate; the material of the element electrode layer and the common electrode layer is indium tin oxide.
  • the present invention also provides a COA type liquid crystal panel, comprising an array substrate, a glass substrate disposed opposite to the array substrate, and a liquid crystal layer between the array substrate and the glass substrate;
  • the array substrate includes red, green, and blue sub-pixel regions, and each sub-pixel region includes a substrate, an amorphous silicon layer disposed on the substrate, a buffer layer disposed on the amorphous silicon layer and the substrate, a polysilicon layer disposed on the buffer layer and corresponding to the amorphous silicon layer, a gate insulating layer disposed on the polysilicon layer and the buffer layer, disposed on the gate insulating layer and corresponding to the polysilicon a gate electrode disposed on the gate, a scan line disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, the scan line and the gate insulating layer, and the interlayer insulating layer disposed on the interlayer insulating layer Source/drain, provided in the a signal line vertically intersecting the scanning line on the interlayer insulating layer, a passivation layer provided on the source/drain, the signal line, and the interlayer insulating layer, and the blunt layer a color resist layer on the layer,
  • a first via hole is formed on the interlayer insulating layer and the gate insulating layer corresponding to the polysilicon layer, and the flat layer, the color resist layer, and the passivation layer correspond to the source/drain above Forming a second via, the source/drain being in contact with the polysilicon layer via the first via, the pixel electrode layer being in contact with the source/drain via the second via ;
  • the color resist layer forms red, green, and blue blocking blocks corresponding to the red, green, and blue sub-pixel regions, respectively, and a first intersection region is formed between adjacent two color blocking blocks arranged laterally, the first The intersection area is located above the signal line, and a second interface area is formed between adjacent two color block blocks arranged in a longitudinal direction, the second interface area is located above the scan line, and the pixel electrode layer is respectively located in each of the sub-portions a pixel electrode block of a pixel region, a lateral boundary of the pixel electrode block is above the scan line, and a longitudinal boundary is above the signal line;
  • the polysilicon layer includes a channel, two N-type lightly doped regions on both sides of the channel, and two N-type heavily doped regions respectively located outside the two N-type lightly doped regions, the first via Correspondingly disposed above the N-type heavily doped region, the source/drain are respectively in contact with the N-type heavily doped region via the first via;
  • the flat layer is a transparent organic material.
  • the beneficial effects of the present invention the COA type liquid crystal panel of the present invention and the manufacturing method thereof, by forming a flat layer on the color resist layer, eliminating the gap caused by the overlap between adjacent color resist blocks, and in the flat layer Forming a pixel electrode layer such that the pixel electrode layer is located above the scan line at a lateral boundary of the pixel electrode block of each sub-pixel region, and the longitudinal boundary is located above the signal line, so that the array substrate blocks the light leakage by the scan line itself in the lateral direction, in the longitudinal direction.
  • the signal line itself shields the light leakage, and does not need to use the black matrix to block the light leakage, thereby simplifying the process and increasing the aperture ratio, and respectively providing a gate electrode and an amorphous silicon layer on the upper and lower sides of the polysilicon layer to block the light to prevent the trench.
  • Light leakage occurs at the channel to affect the liquid crystal layer, and light leakage caused by alignment of the array substrate and the glass substrate or bending of the panel in the curved display can be avoided.
  • FIG. 1 is a schematic cross-sectional view of a conventional COA type liquid crystal panel
  • FIG. 2 is a top plan view of an array substrate of the COA type liquid crystal panel of FIG. 1;
  • FIG. 3 is a flow chart of a method for fabricating a COA type liquid crystal panel according to the present invention.
  • FIG. 4 is a schematic view showing a step 1 of a method for fabricating a COA liquid crystal panel according to the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a COA type liquid crystal panel according to the present invention
  • FIG. 6 is a schematic diagram of step 3 of a method for fabricating a COA type liquid crystal panel according to the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating a COA liquid crystal panel of the present invention.
  • step 5 is a schematic diagram of step 5 of a method for fabricating a COA liquid crystal panel of the present invention.
  • FIG. 9 is a schematic view showing a step 6 of a method for fabricating a COA liquid crystal panel of the present invention. and a schematic cross-sectional view of the COA liquid crystal panel of the present invention;
  • FIG. 10 is a schematic plan view of an array substrate of a COA liquid crystal panel of the present invention.
  • the present invention provides a method for fabricating a COA type liquid crystal panel, comprising the following steps:
  • Step 1 As shown in FIG. 4, the array substrate 1 and the glass substrate 2 are provided.
  • the array substrate 1 includes red, green, and blue sub-pixel regions, and each sub-pixel region includes a substrate 11 , an amorphous silicon layer 21 disposed on the substrate 11 , and the amorphous silicon layer.
  • a buffer layer 31 on the substrate 11 a polysilicon layer 4 disposed on the buffer layer 31 and corresponding to the amorphous silicon layer 21 , and a gate insulating layer disposed on the polysilicon layer 4 and the buffer layer 31 a gate electrode 5 disposed on the gate insulating layer 51 and corresponding to the polysilicon layer 4, a scan line 35 disposed on the gate insulating layer 51, and the gate electrode 5 and the scan line 35 and the interlayer insulating layer 52 on the gate insulating layer 51, the source/drain electrodes 6 provided on the interlayer insulating layer 52, and the interlayer insulating layer 52 are disposed on the interlayer insulating layer 52 in a horizontal direction
  • the signal lines 7 in which the scanning lines 35 are vertically intersected are described.
  • a first via 61 is formed on the interlayer insulating layer 52 and the gate insulating layer 51 corresponding to the polysilicon layer 4, and the source/drain 6 is respectively connected to the source via the first via 61
  • the polysilicon layer 4 is in contact.
  • the polysilicon layer 4 includes a channel 43 , two N-type lightly doped regions 41 on both sides of the channel 43 , and two N-type heavily doped regions 42 respectively located outside the two N-type lightly doped regions 41 .
  • the first via 61 is correspondingly disposed above the N-type heavily doped region 42, and the source/drain 6 The N-type heavily doped region 42 is in contact via the first via 61, respectively.
  • the material of the signal line 7 and the scanning line 35 is a metal material such as aluminum, molybdenum or copper.
  • Step 2 As shown in FIG. 5, a passivation layer 53 is formed on the source/drain electrodes 6, the signal lines 7, and the interlayer insulating layer 52.
  • the passivation layer 53 is formed by a chemical vapor deposition (CVD) method.
  • Step 3 As shown in FIG. 6, a color resist layer 54 is formed on the passivation layer 53.
  • the color resist layer 54 forms red, green, and blue blocking blocks respectively corresponding to the red, green, and blue sub-pixel regions, and the first intersection region 64 is formed between the adjacent two color blocking blocks arranged laterally.
  • the first interface area 64 is located above the signal line 7, and a second interface area is formed between adjacent two color block blocks arranged longitudinally, and the second interface area is located above the scan line 35, thereby omitting
  • the black matrix of the horizontal and vertical directions realizes self-shading of the scanning line and the signal line.
  • the color resist layer 54 is formed by a coating process.
  • Step 4 as shown in FIG. 7, a flat layer 55 is formed on the color resist layer 54 and corresponds to the source/drain electrodes 6 on the flat layer 55, the color resist layer 54, and the passivation layer 53.
  • a second via 81 is formed above.
  • the flat layer 55 is formed by a coating process, and the flat layer 55 is a transparent organic material.
  • Step 5 as shown in FIG. 8, a pixel electrode layer 8 is deposited and patterned on the flat layer 55, and a common electrode layer 9 is formed on the glass substrate 2.
  • the pixel electrode layer 8 is in contact with the source/drain 6 via the second via 81, and the pixel electrode layer 8 includes pixel electrode blocks respectively located in each sub-pixel region, and the lateral direction of the pixel electrode block The boundary is above the scan line 35 and the longitudinal boundary is above the signal line 7.
  • the pixel electrode layer 8 is formed by a physical vapor deposition (PVD) method, and the material of the pixel electrode layer 8 and the common electrode layer 9 is indium tin oxide (ITO).
  • PVD physical vapor deposition
  • ITO indium tin oxide
  • Step 6 As shown in FIG. 9, the array substrate 1 and the glass substrate 2 are paired and poured into the liquid crystal layer 3.
  • the lateral boundary of the pixel electrode block of the layer located in each sub-pixel region is located above the scan line, and the longitudinal boundary is located above the signal line, so that the array substrate is laterally supported by the scan line itself Blocking the light leakage, blocking the light leakage by the signal line itself in the longitudinal direction, eliminating the need to use the black matrix to block the light leakage, thereby simplifying the process, increasing the aperture ratio, and respectively providing the gate and the amorphous silicon layer on the upper and lower sides of the polysilicon layer to block
  • the light is used to prevent light leakage at the channel to affect the liquid crystal layer, and to avoid light leakage caused by alignment of the array substrate and the glass substrate or bending of the panel in the curved display.
  • the present invention further provides a COA type liquid crystal panel, comprising an array substrate 1 , a glass substrate 2 disposed opposite to the array substrate 1 , and the array substrate 1 and the glass substrate 2 .
  • the liquid crystal layer 3 between.
  • the array substrate 1 includes red, green, and blue sub-pixel regions, and each sub-pixel region includes a substrate 11 , an amorphous silicon layer 21 disposed on the substrate 11 , and the amorphous silicon layer.
  • a buffer layer 31 on the substrate 11 a polysilicon layer 4 disposed on the buffer layer 31 and corresponding to the amorphous silicon layer 21 , and a gate insulating layer disposed on the polysilicon layer 4 and the buffer layer 31 a gate electrode 5 disposed on the gate insulating layer 51 and corresponding to the polysilicon layer 4, a scan line 35 disposed on the gate insulating layer 51, and the gate electrode 5 and the scan line 35 and an interlayer insulating layer 52 on the gate insulating layer 51, a source/drain 6 provided on the interlayer insulating layer 52, on the interlayer insulating layer 52, and in the horizontal direction a signal line 7 vertically aligned with the scanning lines 35, a passivation layer 53 provided on the source/drain electrodes 6, the signal
  • a first via 61 is formed on the interlayer insulating layer 52 and the gate insulating layer 51 corresponding to the polysilicon layer 4, and the flat layer 55, the color resist layer 54, and the passivation layer 53 are correspondingly disposed.
  • a second via 81 is formed above the source/drain 6 , and the source/drain 6 is respectively in contact with the polysilicon layer 4 via the first via 61 , and the pixel electrode layer 8 is via the The second via 81 is in contact with the source/drain 6.
  • the polysilicon layer 4 includes a channel 43, two N-type lightly doped regions 41 on both sides of the channel 43, and two N-type heavily doped regions 42 respectively located outside the two N-type lightly doped regions 41.
  • the first via 61 is correspondingly disposed above the N-type heavily doped region 42 , and the source/drain 6 are respectively in contact with the N-type heavily doped region 42 via the first via 61 .
  • the color resist layer 54 forms red, green, and blue blocking blocks respectively corresponding to the red, green, and blue sub-pixel regions, and a first intersection region 64 is formed between the adjacent two color blocking blocks arranged laterally.
  • the first interface area 64 is located above the signal line 7
  • a second interface area is formed between the adjacent two color block blocks arranged longitudinally.
  • the second interface area is located above the scan line 35
  • the pixel electrode layer 8 includes pixel electrode blocks respectively located in respective sub-pixel regions, a lateral boundary of the pixel electrode block being located above the scan line 35, and a longitudinal boundary being located above the signal line 7.
  • the flat layer 55 is a transparent organic material; the material of the signal line 7 and the scan line 35 is a metal material such as aluminum, molybdenum or copper.
  • the glass substrate 2 is provided with a common electrode layer 9, and the material of the pixel electrode layer 8 and the common electrode layer 9 are indium tin oxide.
  • the pixel electrode layer is formed on the flat layer, so that the pixel electrode layer is located at each The lateral boundary of the pixel electrode block of the sub-pixel area is located above the scan line, and the longitudinal boundary is located above the signal line, so that the array substrate blocks the light leakage by the scan line itself in the lateral direction, and blocks the light leakage by the signal line itself in the longitudinal direction, and does not need to be used again.
  • the black matrix blocks the light leakage, thereby simplifying the process and increasing the aperture ratio, and respectively providing a gate electrode and an amorphous silicon layer on the upper and lower sides of the polysilicon layer to block the light to prevent light leakage at the channel and thereby affecting the liquid crystal layer.
  • the COA type liquid crystal panel of the present invention and the manufacturing method thereof by forming a flat layer on the color resist layer, eliminate the gap caused by the overlap between adjacent color resist blocks, and on the flat layer Forming a pixel electrode layer such that the pixel electrode layer is located above the scan line at a lateral boundary of the pixel electrode block of each sub-pixel region, and the longitudinal boundary is located above the signal line, so that the array substrate blocks the light leakage by the scan line itself in the lateral direction, in the longitudinal direction.
  • the signal line itself blocks the light leakage, and the black matrix is not needed to block the light leakage, thereby simplifying the process and increasing the aperture ratio, and respectively providing a gate electrode and an amorphous silicon layer on the upper and lower sides of the polysilicon layer to block the light to prevent the channel from being blocked.
  • the light leakage occurs to affect the liquid crystal layer, and the light leakage caused by the alignment of the array substrate and the glass substrate or the bending of the panel in the curved display can be avoided.

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Abstract

一种COA型液晶面板的制作方法及COA型液晶面板，该方法通过在色阻层（54）上形成一层平坦层（55），消除了相邻色阻块之间因重叠产生的断差，并在平坦层（55）上形成像素电极层（8），使像素电极层（8）位于各子像素区域的像素电极块的横向边界位于扫描线（35）上方，纵向边界位于信号线（7）上方，从而使阵列基板（1）在横向上靠扫描线（35）自身遮挡漏光，在纵向上靠信号线（7）自身遮挡漏光，不需要再使用黑色矩阵遮挡漏光，从而实现简化制程，提高开口率，并且在多晶硅层（4）的上、下方分别设置栅极（5）和非晶硅层（21）以遮挡光线，以防止沟道处产生光漏电从而对液晶层（3）造成影响，同时可避免阵列基板（1）与玻璃基板（2）对位不准或曲面显示中因面板弯曲而导致的漏光。

Description

COA型液晶面板的制作方法及COA型液晶面板 技术领域
本发明涉及显示技术领域，尤其涉及一种COA型液晶面板的制作方法及COA型液晶面板。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。通常液晶显示装置包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlight module)。其中，液晶面板的结构主要是由一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)、一彩色滤光片基板(Color Filter，CF)、以及配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
低温多晶硅(Low Temperature Poly Silicon，LTPS)TFT技术是一种新型技术，其优点在于，相比于非晶硅(a-si)和氧化物(oxide)型TFT，具有更高的载流子迁移率，能够增强显示器的驱动能力，降低功耗。现在主流的LTPS TFT为顶栅型结构，在用做液晶面板的显示时，由于TFT沟道下方没有遮光层，沟道会产生光漏电。目前防止光电流的方法是在玻璃基板上先沉积一层非晶硅作为保护层将光吸收掉，或者直接沉积一层金属来挡光。但在普通阵列基板结构中，在TFT位置的上方，液晶会因地形不平整及缺乏电压控制而出现杂乱的倒向，需要在CF基板一侧用很大一块面积的黑色矩阵(Black Matrix，BM)遮挡。
COA(Color filter On Array)是一种将CF基板上的色阻层制备于阵列基板上的技术，COA结构因减小了像素电极与金属走线的耦合，金属线上信号的延迟状况得到改善。COA结构可明显减小寄生电容大小，并提高面板开口率，改善面板显示品质。
请参阅图1，为一种现有COA型液晶面板的剖面示意图，主要包括阵列基板100、与所述阵列基板100相对设置的玻璃基板200、及位于所述阵列基板100与玻璃基板200之间的液晶层300。
图2为图1中的COA型液晶面板的阵列基板100的俯视示意图。所述 阵列基板100包括红、绿、蓝色子像素区域，每一子像素区域包括基板110、设于所述基板110上的非晶硅层210、设于所述非晶硅层210与基板110上的缓冲层310、位于所述非晶硅层210上方设于所述缓冲层310上的多晶硅层400、设于所述多晶硅层400与缓冲层310上的栅极绝缘层510、位于所述多晶硅层400上方设于所述栅极绝缘层510上的栅极500、设于所述栅极500与栅极绝缘层510上的层间绝缘层520、设于所述层间绝缘层520上的源/漏极600、设于所述层间绝缘层520上与所述源/漏极600相间隔的信号线700、设于所述源/漏极600、信号线700、及层间绝缘层520上的钝化层530、设于所述钝化层530上的色阻层540、及设于所述色阻层540上的像素电极层800。
所述多晶硅层400包括沟道430、位于沟道430两侧的两N型轻掺杂区域410、及位于两N型轻掺杂区域410外侧的两N型重掺杂区域420，所述层间绝缘层520、及栅极绝缘层510对应所述N型重掺杂区域420的上方设有第一过孔610，所述色阻层540、及钝化层530上对应所述源/漏极600的上方设有第二过孔810，所述源/漏极600分别经由所述第一过孔610与所述N型重掺杂区域420相接触，所述像素电极层800经由所述第二过孔810与所述源/漏极600相接触。所述玻璃基板200上设有黑色矩阵910，所述黑色矩阵910上设有公共电极层900。
该现有COA型液晶面板中，色阻层540对应所述红、绿、蓝色子像素区域分别形成红、绿、蓝色阻块，相邻色阻块之间在制程过程中会产生一定程度的交接区域640，交接区域640上方的液晶会因地形差异而出现倒向错乱，因而交接区域640上方采用玻璃基板200上的黑色矩阵910遮挡，但设置黑色矩阵910会损失掉很大一部分的开口率。
发明内容
本发明的目的在于提供一种COA型液晶面板的制作方法，不需要单独制作黑色矩阵，可简化制程，提高开口率，同时可避免阵列基板与玻璃基板对位不准或曲面显示中因面板弯曲而导致的漏光。
本发明的另一目的在于提供一种COA型液晶面板，结构简单，开口率高，能耗较低。
为实现上述目的，本发明提供一种COA型液晶面板的制作方法，包括如下步骤：
步骤1、提供阵列基板与玻璃基板；
所述阵列基板包括红、绿、蓝色子像素区域，每一子像素区域包括基 板、设于所述基板上的非晶硅层、设于所述非晶硅层与基板上的缓冲层、设于所述缓冲层上且对应所述非晶硅层设置的多晶硅层、设于所述多晶硅层与缓冲层上的栅极绝缘层、设于所述栅极绝缘层上且对应所述多晶硅层设置的栅极、设于所述栅极绝缘层上的扫描线、设于所述栅极、扫描线与栅极绝缘层上的层间绝缘层、设于所述层间绝缘层上的源/漏极、及设于所述层间绝缘层上且在水平方向上与所述扫描线垂直交叉排列的信号线；
所述层间绝缘层、及栅极绝缘层上对应所述多晶硅层的上方形成有第一过孔，所述源/漏极分别经由所述第一过孔与所述多晶硅层相接触；
步骤2、在所述源/漏极、信号线、及层间绝缘层上形成钝化层；
步骤3、在所述钝化层上形成色阻层；
所述色阻层对应所述红、绿、蓝色子像素区域分别形成红、绿、蓝色阻块，横向排列的相邻的两色阻块之间形成第一交接区域，所述第一交接区域位于所述信号线上方，纵向排列的相邻的两色阻块之间形成第二交接区域，所述第二交接区域位于所述扫描线上方；
步骤4、在所述色阻层上形成平坦层，并在所述平坦层、色阻层、及钝化层上对应所述源/漏极的上方形成第二过孔；
步骤5、在所述平坦层上沉积并图案化像素电极层，在所述玻璃基板上形成公共电极层；
所述像素电极层经由所述第二过孔与所述源/漏极相接触，所述像素电极层包括分别位于各子像素区域的像素电极块，所述像素电极块的横向边界位于所述扫描线上方，纵向边界位于所述信号线上方；
步骤6、将所述阵列基板与玻璃基板对组，并灌入液晶层。
所述多晶硅层包括沟道、位于沟道两侧的两N型轻掺杂区域、及分别位于两N型轻掺杂区域外侧的两N型重掺杂区域，所述第一过孔对应设于N型重掺杂区域的上方，所述源/漏极分别经由所述第一过孔与N型重掺杂区域相接触。
所述步骤2采用化学气相沉积法形成所述钝化层。
所述步骤3采用涂布制程形成所述色阻层。
所述步骤4采用涂布制程形成所述平坦层，所述平坦层为透明有机材料。
所述步骤5采用物理气相沉积法形成所述像素电极层，所述像素电极层、及公共电极层的材料均为氧化铟锡。
本发明还提供一种COA型液晶面板，包括阵列基板、与所述阵列基板相对设置的玻璃基板、及位于所述阵列基板与玻璃基板之间的液晶层；
所述阵列基板包括红、绿、蓝色子像素区域，每一子像素区域包括基板、设于所述基板上的非晶硅层、设于所述非晶硅层与基板上的缓冲层、设于所述缓冲层上且对应所述非晶硅层设置的多晶硅层、设于所述多晶硅层与缓冲层上的栅极绝缘层、设于所述栅极绝缘层上且对应所述多晶硅层设置的栅极、设于所述栅极绝缘层上的扫描线、设于所述栅极、扫描线与栅极绝缘层上的层间绝缘层、设于所述层间绝缘层上的源/漏极、设于所述层间绝缘层上且在水平方向上与所述扫描线垂直交叉排列的信号线、设于所述源/漏极、信号线、及层间绝缘层上的钝化层、设于所述钝化层上的色阻层、设于所述色阻层上的平坦层、及设于所述平坦层上的像素电极层；
所述层间绝缘层、及栅极绝缘层上对应所述多晶硅层的上方形成有第一过孔，所述平坦层、色阻层、及钝化层上对应所述源/漏极的上方形成有第二过孔；所述源/漏极分别经由所述第一过孔与所述多晶硅层相接触，所述像素电极层经由所述第二过孔与所述源/漏极相接触；
所述色阻层对应所述红、绿、蓝色子像素区域分别形成红、绿、蓝色阻块，横向排列的相邻的两色阻块之间形成第一交接区域，所述第一交接区域位于所述信号线上方，纵向排列的相邻的两色阻块之间形成第二交接区域，所述第二交接区域位于所述扫描线上方；所述像素电极层包括分别位于各子像素区域的像素电极块，所述像素电极块的横向边界位于所述扫描线上方，纵向边界位于所述信号线上方。
所述多晶硅层包括沟道、位于沟道两侧的两N型轻掺杂区域、及分别位于两N型轻掺杂区域外侧的两N型重掺杂区域，所述第一过孔对应设于N型重掺杂区域的上方，所述源/漏极分别经由所述第一过孔与N型重掺杂区域相接触。
所述平坦层为透明有机材料。
所述玻璃基板上设有公共电极层；所述素电极层、及公共电极层的材料均为氧化铟锡。
本发明还提供一种COA型液晶面板，包括阵列基板、与所述阵列基板相对设置的玻璃基板、及位于所述阵列基板与玻璃基板之间的液晶层；
所述阵列基板包括红、绿、蓝色子像素区域，每一子像素区域包括基板、设于所述基板上的非晶硅层、设于所述非晶硅层与基板上的缓冲层、设于所述缓冲层上且对应所述非晶硅层设置的多晶硅层、设于所述多晶硅层与缓冲层上的栅极绝缘层、设于所述栅极绝缘层上且对应所述多晶硅层设置的栅极、设于所述栅极绝缘层上的扫描线、设于所述栅极、扫描线与栅极绝缘层上的层间绝缘层、设于所述层间绝缘层上的源/漏极、设于所述 层间绝缘层上且在水平方向上与所述扫描线垂直交叉排列的信号线、设于所述源/漏极、信号线、及层间绝缘层上的钝化层、设于所述钝化层上的色阻层、设于所述色阻层上的平坦层、及设于所述平坦层上的像素电极层；
所述层间绝缘层、及栅极绝缘层上对应所述多晶硅层的上方形成有第一过孔，所述平坦层、色阻层、及钝化层上对应所述源/漏极的上方形成有第二过孔，所述源/漏极分别经由所述第一过孔与所述多晶硅层相接触，所述像素电极层经由所述第二过孔与所述源/漏极相接触；
所述色阻层对应所述红、绿、蓝色子像素区域分别形成红、绿、蓝色阻块，横向排列的相邻的两色阻块之间形成第一交接区域，所述第一交接区域位于所述信号线上方，纵向排列的相邻的两色阻块之间形成第二交接区域，所述第二交接区域位于所述扫描线上方，所述像素电极层包括分别位于各子像素区域的像素电极块，所述像素电极块的横向边界位于所述扫描线上方，纵向边界位于所述信号线上方；
其中，所述多晶硅层包括沟道、位于沟道两侧的两N型轻掺杂区域、及分别位于两N型轻掺杂区域外侧的两N型重掺杂区域，所述第一过孔对应设于N型重掺杂区域的上方，所述源/漏极分别经由所述第一过孔与N型重掺杂区域相接触；
其中，所述平坦层为透明有机材料。
本发明的有益效果：本发明的COA型液晶面板及其制作方法，通过在色阻层上形成一层平坦层，消除了相邻色阻块之间因重叠产生的断差，并在平坦层上形成像素电极层，使像素电极层位于各子像素区域的像素电极块的横向边界位于扫描线上方，纵向边界位于信号线上方，从而使阵列基板在横向上靠扫描线自身遮挡漏光，在纵向上靠信号线自身遮挡漏光，不需要再使用黑色矩阵遮挡漏光，从而实现简化制程，提高开口率，并且在多晶硅层的上、下方分别设置栅极和非晶硅层以遮挡光线，以防止沟道处产生光漏电从而对液晶层造成影响，同时可避免阵列基板与玻璃基板对位不准或曲面显示中因面板弯曲而导致的漏光。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为一种现有COA型液晶面板的剖面示意图；
图2为图1中COA型液晶面板的阵列基板的俯视示意图；
图3为本发明COA型液晶面板的制作方法的流程图；
图4为本发明COA型液晶面板的制作方法的步骤1的示意图；
图5为本发明COA型液晶面板的制作方法的步骤2的示意图；
图6为本发明COA型液晶面板的制作方法的步骤3的示意图；
图7为本发明COA型液晶面板的制作方法的步骤4的示意图；
图8为本发明COA型液晶面板的制作方法的步骤5的示意图；
图9为本发明COA型液晶面板的制作方法的步骤6的示意图暨本发明COA型液晶面板的剖面示意图；
图10为本发明COA型液晶面板的阵列基板的俯视示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3，本发明提供一种COA型液晶面板的制作方法，包括如下步骤：
步骤1、如图4所示，提供阵列基板1与玻璃基板2。
具体地，所述阵列基板1包括红、绿、蓝色子像素区域，每一子像素区域包括基板11、设于所述基板11上的非晶硅层21、设于所述非晶硅层21与基板11上的缓冲层31、设于所述缓冲层31上且对应所述非晶硅层21设置的多晶硅层4、设于所述多晶硅层4与缓冲层31上的栅极绝缘层51、设于所述栅极绝缘层51上且对应所述多晶硅层4设置的栅极5、设于所述栅极绝缘层51上的扫描线35、设于所述栅极5、扫描线35与栅极绝缘层51上的层间绝缘层52、设于所述层间绝缘层52上的源/漏极6、及设于所述层间绝缘层52上且在水平方向上与所述扫描线35垂直交叉排列的信号线7。
所述层间绝缘层52、及栅极绝缘层51上对应所述多晶硅层4的上方形成有第一过孔61，所述源/漏极6分别经由所述第一过孔61与所述多晶硅层4相接触。
具体的，所述多晶硅层4包括沟道43、位于沟道43两侧的两N型轻掺杂区域41、及分别位于两N型轻掺杂区域41外侧的两N型重掺杂区域42，所述第一过孔61对应设于N型重掺杂区域42的上方，所述源/漏极6 分别经由所述第一过孔61与N型重掺杂区域42相接触。
具体的，所述信号线7与扫描线35的材料为铝、钼或铜等金属材料。
步骤2、如图5所示，在所述源/漏极6、信号线7、及层间绝缘层52上形成钝化层53。
具体地，采用化学气相沉积(CVD)法形成所述钝化层53。
步骤3、如图6所示，在所述钝化层53上形成色阻层54。
具体地，所述色阻层54对应所述红、绿、蓝色子像素区域分别形成红、绿、蓝色阻块，横向排列的相邻的两色阻块之间形成第一交接区域64，所述第一交接区域64位于所述信号线7上方，纵向排列的相邻的两色阻块之间形成第二交接区域，所述第二交接区域位于所述扫描线35上方，从而省略了横向与纵向的黑色矩阵，实现扫描线与信号线自遮光。
具体地，采用涂布制程形成所述色阻层54。
步骤4、如图7所示，在所述色阻层54上形成平坦层55，并在所述平坦层55、色阻层54、及钝化层53上对应所述源/漏极6的上方形成第二过孔81。
具体地，采用涂布制程形成所述平坦层55，所述平坦层55为透明有机材料。
步骤5、如图8所示，在所述平坦层55上沉积并图案化像素电极层8，在所述玻璃基板2上形成公共电极层9。
所述像素电极层8经由所述第二过孔81与所述源/漏极6相接触，所述像素电极层8包括分别位于各子像素区域的像素电极块，所述像素电极块的横向边界位于所述扫描线35上方，纵向边界位于所述信号线7上方。
具体地，采用物理气相沉积(PVD)法形成所述像素电极层8，所述像素电极层8、及公共电极层9的材料均为氧化铟锡(ITO)。
步骤6、如图9所示，将所述阵列基板1与玻璃基板2对组，并灌入液晶层3。
具体地，在阵列基板1和玻璃基板2对位时，由于玻璃基板2上省去了黑色矩阵，在简化制程的同时，避免了因对位不准确而导致的漏光，同时也避免了在曲面显示器中由于黑色矩阵在面板弯曲时发生偏移而导致的漏光。
上述COA型液晶面板的制作方法，通过在色阻层上形成一层平坦层，消除了相邻色阻块之间因重叠产生的断差，并在平坦层上形成像素电极层，使像素电极层位于各子像素区域的像素电极块的横向边界位于扫描线上方，纵向边界位于信号线上方，从而使阵列基板在横向上靠扫描线自身 遮挡漏光，在纵向上靠信号线自身遮挡漏光，不需要再使用黑色矩阵遮挡漏光，从而实现简化制程，提高开口率，并且在多晶硅层的上、下方分别设置栅极和非晶硅层以遮挡光线，以防止沟道处产生光漏电从而对液晶层造成影响，同时可避免阵列基板与玻璃基板对位不准或曲面显示中因面板弯曲而导致的漏光。
请同时参阅图9、图10，本发明还提供一种COA型液晶面板，包括阵列基板1、与所述阵列基板1相对设置的玻璃基板2、及位于所述阵列基板1与玻璃基板2之间的液晶层3。
具体地，所述阵列基板1包括红、绿、蓝色子像素区域，每一子像素区域包括基板11、设于所述基板11上的非晶硅层21、设于所述非晶硅层21与基板11上的缓冲层31、设于所述缓冲层31上且对应所述非晶硅层21设置的多晶硅层4、设于所述多晶硅层4与缓冲层31上的栅极绝缘层51、设于所述栅极绝缘层51上且对应所述多晶硅层4设置的栅极5、设于所述栅极绝缘层51上的扫描线35、设于所述栅极5、扫描线35与栅极绝缘层51上的层间绝缘层52、设于所述层间绝缘层52上的源/漏极6、设于所述层间绝缘层52上且在水平方向上与所述扫描线35垂直交叉排列的信号线7、设于所述源/漏极6、信号线7、及层间绝缘层52上的钝化层53、设于所述钝化层53上的色阻层54、设于所述色阻层54上的平坦层55、及设于所述平坦层55上的像素电极层8。
所述层间绝缘层52、及栅极绝缘层51上对应所述多晶硅层4的上方形成有第一过孔61，所述平坦层55、色阻层54、及钝化层53上对应所述源/漏极6的上方形成有第二过孔81，所述源/漏极6分别经由所述第一过孔61与所述多晶硅层4相接触，所述像素电极层8经由所述第二过孔81与所述源/漏极6相接触。
具体地，所述多晶硅层4包括沟道43、位于沟道43两侧的两N型轻掺杂区域41、及分别位于两N型轻掺杂区域41外侧的两N型重掺杂区域42，所述第一过孔61对应设于N型重掺杂区域42的上方，所述源/漏极6分别经由所述第一过孔61与N型重掺杂区域42相接触。
所述色阻层54对应所述红、绿、蓝色子像素区域分别形成红、绿、蓝色阻块，横向排列的相邻的两色阻块之间形成第一交接区域64，所述第一交接区域64位于所述信号线7上方，纵向排列的相邻的两色阻块之间形成第二交接区域，所述第二交接区域位于所述扫描线35上方，所述像素电极层8包括分别位于各子像素区域的像素电极块，所述像素电极块的横向边界位于所述扫描线35上方，纵向边界位于所述信号线7上方。
具体地，所述平坦层55为透明有机材料；所述信号线7与扫描线35的材料为铝、钼或铜等金属材料。
具体地，所述玻璃基板2上设有公共电极层9，所述像素电极层8、及公共电极层9的材料均为氧化铟锡。
上述COA型液晶面板，通过在色阻层上形成一层平坦层，消除了相邻色阻块之间因重叠产生的断差，并在平坦层上形成像素电极层，使像素电极层位于各子像素区域的像素电极块的横向边界位于扫描线上方，纵向边界位于信号线上方，从而使阵列基板在横向上靠扫描线自身遮挡漏光，在纵向上靠信号线自身遮挡漏光，不需要再使用黑色矩阵遮挡漏光，从而实现简化制程，提高开口率，并且在多晶硅层的上、下方分别设置栅极和非晶硅层以遮挡光线，以防止沟道处产生光漏电从而对液晶层造成影响，同时可避免阵列基板与玻璃基板对位不准或曲面显示中因面板弯曲而导致的漏光。
综上所述，本发明的COA型液晶面板及其制作方法，通过在色阻层上形成一层平坦层，消除了相邻色阻块之间因重叠产生的断差，并在平坦层上形成像素电极层，使像素电极层位于各子像素区域的像素电极块的横向边界位于扫描线上方，纵向边界位于信号线上方，从而使阵列基板在横向上靠扫描线自身遮挡漏光，在纵向上靠信号线自身遮挡漏光，不需要再使用黑色矩阵遮挡漏光，从而实现简化制程，提高开口率，并且在多晶硅层的上、下方分别设置栅极和非晶硅层以遮挡光线，以防止沟道处产生光漏电从而对液晶层造成影响，同时可避免阵列基板与玻璃基板对位不准或曲面显示中因面板弯曲而导致的漏光。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (12)

  1. 一种COA型液晶面板的制作方法，包括如下步骤：
    步骤1、提供阵列基板与玻璃基板；
    所述阵列基板包括红、绿、蓝色子像素区域，每一子像素区域包括基板、设于所述基板上的非晶硅层、设于所述非晶硅层与基板上的缓冲层、设于所述缓冲层上且对应所述非晶硅层设置的多晶硅层、设于所述多晶硅层与缓冲层上的栅极绝缘层、设于所述栅极绝缘层上且对应所述多晶硅层设置的栅极、设于所述栅极绝缘层上的扫描线、设于所述栅极、扫描线与栅极绝缘层上的层间绝缘层、设于所述层间绝缘层上的源/漏极、及设于所述层间绝缘层上且在水平方向上与所述扫描线垂直交叉排列的信号线；
    所述层间绝缘层、及栅极绝缘层上对应所述多晶硅层的上方形成有第一过孔，所述源/漏极分别经由所述第一过孔与所述多晶硅层相接触；
    步骤2、在所述源/漏极、信号线、及层间绝缘层上形成钝化层；
    步骤3、在所述钝化层上形成色阻层；
    所述色阻层对应所述红、绿、蓝色子像素区域分别形成红、绿、蓝色阻块，横向排列的相邻的两色阻块之间形成第一交接区域，所述第一交接区域位于所述信号线上方，纵向排列的相邻的两色阻块之间形成第二交接区域，所述第二交接区域位于所述扫描线上方；
    步骤4、在所述色阻层上形成平坦层，并在所述平坦层、色阻层、及钝化层上对应所述源/漏极的上方形成第二过孔；
    步骤5、在所述平坦层上沉积并图案化像素电极层，在所述玻璃基板上形成公共电极层；
    所述像素电极层经由所述第二过孔与所述源/漏极相接触，所述像素电极层包括分别位于各子像素区域的像素电极块，所述像素电极块的横向边界位于所述扫描线上方，纵向边界位于所述信号线上方；
    步骤6、将所述阵列基板与玻璃基板对组，并灌入液晶层。
  2. 如权利要求1所述的COA型液晶面板的制作方法，其中，所述多晶硅层包括沟道、位于沟道两侧的两N型轻掺杂区域、及分别位于两N型轻掺杂区域外侧的两N型重掺杂区域，所述第一过孔对应设于N型重掺杂区域的上方，所述源/漏极分别经由所述第一过孔与N型重掺杂区域相接触。
  3. 如权利要求1所述的COA型液晶面板的制作方法，其中，所述步骤2采用化学气相沉积法形成所述钝化层。
  4. 如权利要求1所述的COA型液晶面板的制作方法，其中，所述步骤3采用涂布制程形成所述色阻层。
  5. 如权利要求1所述的COA型液晶面板的制作方法，其中，所述步骤4采用涂布制程形成所述平坦层，所述平坦层为透明有机材料。
  6. 如权利要求1所述的COA型液晶面板的制作方法，其中，所述步骤5采用物理气相沉积法形成所述像素电极层，所述像素电极层、及公共电极层的材料均为氧化铟锡。
  7. 一种COA型液晶面板，包括阵列基板、与所述阵列基板相对设置的玻璃基板、及位于所述阵列基板与玻璃基板之间的液晶层；
    所述阵列基板包括红、绿、蓝色子像素区域，每一子像素区域包括基板、设于所述基板上的非晶硅层、设于所述非晶硅层与基板上的缓冲层、设于所述缓冲层上且对应所述非晶硅层设置的多晶硅层、设于所述多晶硅层与缓冲层上的栅极绝缘层、设于所述栅极绝缘层上且对应所述多晶硅层设置的栅极、设于所述栅极绝缘层上的扫描线、设于所述栅极、扫描线与栅极绝缘层上的层间绝缘层、设于所述层间绝缘层上的源/漏极、设于所述层间绝缘层上且在水平方向上与所述扫描线垂直交叉排列的信号线、设于所述源/漏极、信号线、及层间绝缘层上的钝化层、设于所述钝化层上的色阻层、设于所述色阻层上的平坦层、及设于所述平坦层上的像素电极层；
    所述层间绝缘层、及栅极绝缘层上对应所述多晶硅层的上方形成有第一过孔，所述平坦层、色阻层、及钝化层上对应所述源/漏极的上方形成有第二过孔，所述源/漏极分别经由所述第一过孔与所述多晶硅层相接触，所述像素电极层经由所述第二过孔与所述源/漏极相接触；
    所述色阻层对应所述红、绿、蓝色子像素区域分别形成红、绿、蓝色阻块，横向排列的相邻的两色阻块之间形成第一交接区域，所述第一交接区域位于所述信号线上方，纵向排列的相邻的两色阻块之间形成第二交接区域，所述第二交接区域位于所述扫描线上方，所述像素电极层包括分别位于各子像素区域的像素电极块，所述像素电极块的横向边界位于所述扫描线上方，纵向边界位于所述信号线上方。
  8. 如权利要求7所述的COA型液晶面板，其中，所述多晶硅层包括沟道、位于沟道两侧的两N型轻掺杂区域、及分别位于两N型轻掺杂区域外侧的两N型重掺杂区域，所述第一过孔对应设于N型重掺杂区域的上方，所述源/漏极分别经由所述第一过孔与N型重掺杂区域相接触。
  9. 如权利要求7所述的COA型液晶面板，其中，所述平坦层为透明有机材料。
  10. 如权利要求7所述的COA型液晶面板，其中，所述玻璃基板上设有公共电极层；所述素电极层、及公共电极层的材料均为氧化铟锡。
  11. 一种COA型液晶面板，包括阵列基板、与所述阵列基板相对设置的玻璃基板、及位于所述阵列基板与玻璃基板之间的液晶层；
    所述阵列基板包括红、绿、蓝色子像素区域，每一子像素区域包括基板、设于所述基板上的非晶硅层、设于所述非晶硅层与基板上的缓冲层、设于所述缓冲层上且对应所述非晶硅层设置的多晶硅层、设于所述多晶硅层与缓冲层上的栅极绝缘层、设于所述栅极绝缘层上且对应所述多晶硅层设置的栅极、设于所述栅极绝缘层上的扫描线、设于所述栅极、扫描线与栅极绝缘层上的层间绝缘层、设于所述层间绝缘层上的源/漏极、设于所述层间绝缘层上且在水平方向上与所述扫描线垂直交叉排列的信号线、设于所述源/漏极、信号线、及层间绝缘层上的钝化层、设于所述钝化层上的色阻层、设于所述色阻层上的平坦层、及设于所述平坦层上的像素电极层(8)；
    所述层间绝缘层、及栅极绝缘层上对应所述多晶硅层的上方形成有第一过孔，所述平坦层、色阻层、及钝化层上对应所述源/漏极的上方形成有第二过孔，所述源/漏极分别经由所述第一过孔与所述多晶硅层相接触，所述像素电极层经由所述第二过孔与所述源/漏极相接触；
    所述色阻层对应所述红、绿、蓝色子像素区域分别形成红、绿、蓝色阻块，横向排列的相邻的两色阻块之间形成第一交接区域，所述第一交接区域位于所述信号线上方，纵向排列的相邻的两色阻块之间形成第二交接区域，所述第二交接区域位于所述扫描线上方，所述像素电极层包括分别位于各子像素区域的像素电极块，所述像素电极块的横向边界位于所述扫描线上方，纵向边界位于所述信号线上方；
    其中，所述多晶硅层包括沟道、位于沟道两侧的两N型轻掺杂区域、及分别位于两N型轻掺杂区域外侧的两N型重掺杂区域，所述第一过孔对应设于N型重掺杂区域的上方，所述源/漏极分别经由所述第一过孔与N型重掺杂区域相接触；
    其中，所述平坦层为透明有机材料。
  12. 如权利要求11所述的COA型液晶面板，其中，所述玻璃基板上设有公共电极层；所述素电极层、及公共电极层的材料均为氧化铟锡。
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