WO2016141666A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2016141666A1
WO2016141666A1 PCT/CN2015/085303 CN2015085303W WO2016141666A1 WO 2016141666 A1 WO2016141666 A1 WO 2016141666A1 CN 2015085303 W CN2015085303 W CN 2015085303W WO 2016141666 A1 WO2016141666 A1 WO 2016141666A1
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Prior art keywords
output
shift register
node
module
input
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PCT/CN2015/085303
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English (en)
French (fr)
Inventor
张元波
韩承佑
林允植
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京东方科技集团股份有限公司
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Priority to EP15884347.4A priority Critical patent/EP3270370B1/en
Priority to US14/911,666 priority patent/US9679512B2/en
Publication of WO2016141666A1 publication Critical patent/WO2016141666A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to a shift register, a driving method thereof, a gate driving circuit, and a display device.
  • the display panels adopt GOA (Gate driver On Array) technology.
  • GOA Gate driver On Array
  • the conventional GOA circuit is disposed on both sides of the effective display area, and needs a certain width of the black matrix area to block, so that the display panel itself has a certain width of the border. From the perspective of user comfort and operability, the ultra-narrow bezel or borderless is the current consumer and technology trend.
  • the GOA circuit mainly implements a shift register function, and in a GOA circuit that cannot realize a CMOS (Complementary Metal Oxide Semiconductor) device such as an a-Si (amorphous silicon) or an oxide process, A circuit structure having a pull-up node PU (Pulling up) and a pull-down node PD (Pulling down) is employed.
  • CMOS Complementary Metal Oxide Semiconductor
  • PD pull-down node
  • a shift register and a driving method thereof, a gate driving circuit, and a display device are provided for solving a circuit structure having a pull-up node PU and a pull-down node PD, which limits a frame width of a GOA circuit. Reduced problems.
  • the present disclosure provides a shift register including an input terminal, a reset terminal, and an output terminal, wherein the shift register further includes:
  • a first input module connected to the input end, for pulling up a potential at the first node by a signal received by the input end;
  • An output module connected to the output terminal for pulling up a potential at the output end by a potential at the first node
  • a reset module connected to the reset terminal for pulling down a potential at the first node at a role of a signal connected at the reset terminal;
  • An output pull-down module connected to the output terminal for pulling down a potential of the output terminal under the action of the first clock signal
  • the first input module, the output module, the reset module, and the output pull-down module are all connected to the first node;
  • the shift register further includes a second input module coupled to the input terminal and the first node, the second input module for operating the first input module and the first clock signal
  • the output pull-down module connects the input terminal to the first node during a working time.
  • the second input module includes a first transistor, a gate of the first transistor is connected to the first clock signal, and one of a source and a drain is connected to the input end, and the other is The first node is connected.
  • the output module includes a first capacitor and a third transistor, wherein:
  • One end of the first capacitor is connected to the first node, and the other end is connected to the output end;
  • the gate of the third transistor is connected to the first node, one of the source and the drain is connected to the output, and the other is connected to the second clock signal.
  • the duty cycle of the second clock signal is less than fifty percent.
  • the shift register further includes a fourth transistor, a gate of the fourth transistor is connected to the reset terminal, one of the source and the drain is connected to the output terminal, and the other is low-voltage
  • the flat voltage lines are connected.
  • the shift register further includes a second capacitor, one end of the second capacitor is connected to the first node, and the other end is connected to the first clock signal.
  • the size of the second capacitor is equal to the magnitude of the parasitic capacitance between the second clock signal and the third transistor.
  • the output pull-down module includes a second transistor, a gate of the second transistor is connected to the first clock signal, one of the source and the drain is connected to the output end, and the other is connected to the low level voltage. Lines are connected.
  • the input module includes a fifth transistor, and a gate of the fifth transistor is connected to the At the input end, one of the source and the drain is connected to the input terminal, and the other is connected to the first node.
  • the reset module includes a sixth transistor, a gate of the sixth transistor is connected to the reset end, one of a source and a drain is connected to the first node, and the other is connected to a low-voltage line. .
  • the present disclosure further provides a gate driving circuit including a plurality of shift register units having an input terminal, a reset terminal, and an output terminal, and input terminals of any one of the shift register units except the first stage Both are connected to the output of the shift register unit of the upper stage, and the shift register unit employs a shift register of any of the above.
  • the present disclosure also provides a display device comprising any of the above gate drive circuits.
  • the present disclosure also provides a method for driving any one of the above shift registers, including:
  • a first level is input to the input terminal to cause the first input module to pull up a potential at the first node under a first level
  • the second input module is Turning on the input terminal and the first node by the first clock signal, and causing the output module to pull up the potential at the output end under the action of the potential at the first node
  • a second level is input to the input terminal, and a second level is input to the reset terminal to cause the reset module to pull down a potential at the first node, the output pull-down
  • the module pulls down the potential of the output terminal under the action of the first clock signal, and causes the second input module to turn on the input terminal and the first node under the action of the first clock signal.
  • the output module includes a third transistor, one of a source or a drain of the third transistor is connected to a second clock signal, and the other is connected to the output end, and a duty ratio of the second clock signal Less than fifty percent.
  • the shift register of the present disclosure can be used as the circuit structure of the GOA unit.
  • the second output module can discharge the first node (the first node) while discharging the potential at the output end to the low-level voltage line. That is, the noise voltage at the pull-up node PU) is discharged to the input terminal, so that it can be discharged to the low-level voltage line via the output terminal of the upper-level GOA unit and the output pull-down module in the cascade circuit. Therefore, the present disclosure can also implement the functions of the circuit structure having the pull-up node PU and the pull-down node PD in the prior art.
  • the present disclosure only removes the pull-down node PD, that is, removes a plurality of transistors in the shift register and the gate driving circuit for regulating the potential at the pull-down node, the number of transistors used therein can be reduced, which is advantageous. Reduce the width of the border occupied by the gate drive circuit.
  • 1 is a block diagram showing the circuit structure of a shift register in an embodiment of the present disclosure
  • FIG. 2 is a flow chart showing the steps of a method for driving a shift register in an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram showing the circuit structure of a shift register in an embodiment of the present disclosure
  • FIG. 4 is a circuit operation timing diagram of a circuit structure of the shift register of FIG. 3;
  • FIG. 5 is a schematic diagram of a circuit structure of a shift register according to another embodiment of the present disclosure.
  • FIG. 6 is a circuit timing diagram of a circuit configuration of the shift register of FIG. 5;
  • FIG. 7 is a schematic structural diagram of a gate driving circuit in an embodiment of the present disclosure.
  • the shift register includes an input, a reset, and an output. Moreover, the shift register includes a first input module 11, a second input module 12, an output module 13, an output pull-down module 14, and a reset module 15, both connected to the first node PU.
  • the first input module 11 is further connected to the input terminal for pulling up the potential at the first node PU by the signal received by the input terminal.
  • the output module 13 is also coupled to the output for pulling up the potential at the output at the potential of the first node PU.
  • the reset module 15 is also connected to the reset terminal for pulling down the signal received at the reset terminal.
  • the potential at a node PU exemplarily shown by connecting the low-level voltage line VGL in FIG. 1 acts as a pull-down).
  • the output pull-down module 14 is also connected to the output terminal for pulling down the potential of the low output terminal by the action of the first clock signal CLKB (exemplarily shown by connecting the low-level voltage line VGL as a pull-down in FIG. 1).
  • the second input module 12 is connected to the input terminal for connecting the input terminal to the first node PU during the working hours of the first input module 11 and the output pull-down module 14 under the action of the first clock signal CLKB.
  • clock signal referred to herein may be divided into two or more clock signals having the same frequency and phase shifting.
  • the second input module 12 can connect the input terminal to the first node PU during the working time of the first input module 11. If the signal received by the input terminal is at a high level at the same time, the second input module 12 can function to assist in pulling up the potential at the first node PU, so that the rise time of the potential at the first node is shorter. On the other hand, the second input module 12 can connect the input terminal to the first node PU during the working time of the output pull-down module 14, and the second input module 12 can discharge the potential at the output terminal to the low battery at the output pull-down module 14.
  • the noise voltage at the first node PU is discharged to the input terminal, so that the output of the upper-level GOA unit and the output pull-down module can be discharged to the low-level voltage line VGL in the cascade circuit.
  • the first node PU can be smoothly discharged to a stable low level.
  • each module in the shift register can cooperatively complete the output and reset of the signal (ie, the pull-up and pull-down of the potential at the output). Therefore, the function of the circuit structure having the pull-up node PU and the pull-down node PD can also be implemented in this embodiment of the present disclosure.
  • the pull-down node PD is removed in the embodiment of the present disclosure, that is, the plurality of transistors in the shift register and the gate driving circuit for regulating the potential at the pull-down node are removed, the transistor used therein can be reduced. The number is beneficial to reduce the width of the frame occupied by the gate drive circuit.
  • first input module 11, the second input module 12, the output module 13, the output pull-down module 14, and the reset module 15 have clear functions, and obviously have a switching circuit (conducted under one end control or The characteristics of the other ends are disconnected, and thus those skilled in the art can realize this by a switching element such as a transistor and a relay or a combination of switching elements. And, in maintaining the company In the case that the relationship and the function are unchanged, those skilled in the art can obtain a plurality of different ones for the first input module 11, the second input module 12, the output module 13, the output pull-down module 14, and the reset module 15 described above. The implementation does not limit this disclosure.
  • FIG. 2 is a flow chart showing the steps of a method for driving a shift register in an embodiment of the present disclosure.
  • the method includes the following work processes:
  • step 201 during the first phase, a first level is input to the input terminal, so that the first input module pulls up the potential at the first node PU under the action of the first level,
  • the second input module connects the input end to the first node under the action of the first clock signal, and causes the output module to pull up the potential at the output end under the action of the potential at the first node PU;
  • step 202 during the second phase, a second level is input to the input terminal, and a second level is input to the reset terminal to cause the reset module to pull down the potential at the first node PU, and output
  • the pull-down module pulls down the potential of the low output terminal by the action of the first clock signal, and causes the second input module to connect the input terminal with the first node under the action of the first clock signal.
  • the above method can drive any of the above shift registers to realize the function of shift registering.
  • the first level be a high level and the second level be a low level.
  • the flow of steps of an exemplary alternative driving method can be as follows:
  • the first input module 11 performs a function of pulling up the potential at the first node PU under the high level received by the input terminal.
  • the second input module 12 connects the first node PU with the input terminal under the action of the first clock signal CLKB, so that the high level received by the input terminal can be pulled up by the second input module 12 at the first node PU.
  • the potential of the second input module 12 can assist in performing the pull-up function of the potential at the first node PU.
  • the output module 13 pulls up the potential of the output terminal under the action of the potential at the first node PU, so that the shift register outputs a high level at the output end.
  • the first input module 11 no longer performs the function of pulling up the potential at the first node PU.
  • the reset module 15 performs a function of pulling down the potential at the first node PU (such as causing the first node PU to communicate with the low level voltage line VGL).
  • the output pull-down module 14 pulls down the potential of the low output terminal by the action of the first clock signal CLKB (for example, connecting the output terminal to the low-level voltage line VGL), This causes the shift register to output a low level at the output.
  • the second input module 12 also connects the first node PU with the input end of the receiving low level signal under the action of the first clock signal CLKB, so that the noise signal of the PU at the first node can be Discharge to the input of the low level signal so that the first node PU can be at a stable low level thereafter.
  • the method provided by the embodiment of the present disclosure can enable the output end of the shift register to output a high level and then output a low level, which is equivalent to extending the signal input by the input end. Time output, thus enabling the function of the shift register.
  • the second input module 12 can assist in pulling up the potential at the first node, and in the second stage, the second input module 12 can remove the noise signal at the first node PU, thereby removing the shift register.
  • the second input module 12 may include a first transistor M1.
  • the gate of the first transistor M1 is connected to the first clock signal CLKB, the drain is connected to the input terminal INPUT, and the source is connected to the first node PU.
  • the first transistor M1 can control the current through the input terminal INPUT and the first node PU under the action of the first clock signal CLKB, and thus the function of the second input module 12 can be realized.
  • transistors in FIG. 3 are exemplified by N-channel thin film transistors (TFTs) whose upper side is the drain and the lower side is the source, the transistors may be other types of transistors. Moreover, depending on the setting of the high and low levels in the specific circuit and the type and characteristics of the transistors, the source and the drain of each transistor may be all interchanged or partially interchanged, which is easily realized by a person skilled in the art according to practical applications. I will not repeat them here.
  • TFTs N-channel thin film transistors
  • the output module 13 may include a first capacitor C1 and a third transistor M3.
  • One end of the first capacitor C1 is connected to the first node PU, and the other end is connected to the output terminal OUTPUT.
  • the gate of the third transistor M3 is connected to the first node PU, the source is connected to the output terminal OUTPUT, and the drain is connected to the second clock signal CLK.
  • the third transistor M3 can make the second time of the high level A large current is passed between the clock signal CLK and the output terminal OUTPUT, and the first capacitor C1 can maintain the potential difference between the two ends, so that the potential at the first node PU is further pulled up, and the potential at the output terminal OUTPUT is made. It is pulled up to realize the function of pulling up the potential at the output terminal OUTPUT of the output module 13.
  • the output pull-down module 14 may include a second transistor M2.
  • the gate of the second transistor M2 is connected to the first clock signal CLKB, the drain is connected to the output terminal OUTPUT, and the source is connected to the low-level voltage line VGL. .
  • the second transistor M2 can control the current flowing from the output terminal OUTPUT to the low-level voltage line VGL under the action of the first clock signal CLKB, and thus the function of the output pull-down module 14 described above can be realized.
  • the first input module 11 may include a fifth transistor M5.
  • the gate of the fifth transistor M5 is connected to the input terminal INPUT, the drain is also connected to the input terminal INPUT, and the source is connected to the first node PU.
  • the fifth transistor M5 can pull up the potential at the first node PU through the current of the source and the drain, thereby realizing the function of the first input module 11 described above.
  • the reset module 15 may include a sixth transistor M6.
  • the gate of the sixth transistor M6 is connected to the reset terminal RESET, the drain is connected to the first node PU, and the source is connected to the low-level voltage line VGL.
  • the sixth transistor M6 can control the current flowing from the first node PU to the low-level voltage line VGL under the action of the signal connected to the reset terminal RESET, and thus the function of the reset module 15 can be realized.
  • the first clock signal CLKB is at a high level
  • the second clock signal CLK is at a low level
  • the input terminal INPUT is at a high level.
  • the first transistor M1 and the fifth transistor M5 jointly charge the first node PU such that the potential at the first node PU is gradually pulled up to a high level.
  • the first clock signal CLKB and the second clock signal CLK are both at a low level, and the input terminal INPUT is also turned to a low level, so that the first transistor M1 and the fifth transistor are M5 is turned off, and the second transistor M2 whose gate is connected to the first clock signal CLKB is also in an off state, and thus the potential at the first node PU remains at a high level.
  • the second clock signal CLK is at a high level
  • the first clock signal CLKB is at a low level
  • the output module 13 is in an active state
  • the gate is connected to a second of the first clock signal CLKB.
  • the transistor M2 is also in an off state, so that the potential at the first node PU is further pulled up by the synergistic action of the first capacitor C1 and the third transistor M3, so that the potential at the output terminal OUTPUT rises and the shift register is output.
  • the terminal outputs a high level.
  • the first clock signal CLKB and the second clock signal CLK are both low level, and at this time, the drain potential of the third transistor M3 is turned to a low level, which causes the first node.
  • the potential at the PU drops to a high level before it is further pulled up, and the output OUTPUT also returns to the previous low level. That is to say, at this time, the high potential at the output terminal OUTPUT is discharged to the low level through the third transistor M3.
  • the first clock signal CLKB is at a high level
  • the second clock signal CLK is at a low level
  • the reset terminal signal RESET is turned to a high level.
  • the high level at the first node PU is discharged to the low-level voltage line VGL through the sixth transistor M6, thereby dropping to a low level
  • the second transistor M2 is further subjected to the action of the first clock signal CLKB.
  • the noise voltage at the output terminal OUTPUT is discharged to a stable low level of the low-level voltage line VGL, so that the output of the shift register outputs a stable low level afterwards.
  • a fourth phase IV is added in the workflow of the shift register, so that the output terminal OUTPUT can be During this phase, the third transistor M3 is discharged to a low level, and the second transistor M2 only functions to remove the noise voltage at the output terminal OUTPUT, so that it does not need to have a large size, which is advantageous for forming a gate in the shift register.
  • the pole drive circuit is used, the width occupied by the gate drive circuit is reduced.
  • the duty ratios of the first clock signal CLKB and the second clock signal CLK may also be fifty percent, which is equivalent to removing the phase II and the phase IV, and the potential at the output terminal OUTPUT needs to pass the first
  • the second transistor M2 is pulled low, and in order to reduce the pull-down time, the second transistor M2 needs to have a larger size.
  • the larger size of the second transistor M2 increases the load of the second clock signal CLK, and the power consumption of the entire circuit is greatly increased.
  • the duty ratio of the second clock signal CLK is less than fifty percent, the size of the second transistor M2 can be reduced, thereby facilitating the formation of the gate driver in the shift register.
  • the width occupied by the gate driving circuit is reduced, and the power consumption of the entire circuit is reduced.
  • the duty ratio of the first clock signal CLKB in FIG. 4 is also less than fifty percent, the phase II thus increased does not greatly affect the original workflow, and thus it does not achieve the above effect. It is necessary that the duty ratio of the first clock signal CLKB is 50% or not. Moreover, since the duty ratio of the second clock signal CLK needs to make the output signal of the output terminal OUTPUT meet the requirements, different lower limit values may be used in different practical applications, and the specific duty ratio setting mode is Those skilled in the art are well known and will not be described herein.
  • FIG. 5 is a circuit configuration diagram of a shift register in another embodiment of the present disclosure.
  • the shift register has a fourth transistor M4 and a second capacitor C2 added to the circuit structure shown in FIG.
  • the gate of the fourth transistor M4 is connected to the reset terminal RESET, the drain is connected to the output terminal OUTPUT, and the source is connected to the low-level voltage line VGL.
  • One end of the second capacitor C2 is connected to the first node PU, and the other end is connected to the first clock signal CLKB.
  • Fig. 6 is a timing chart showing the operation of the circuit configuration of the shift register of Fig. 5.
  • the phase Ta in the workflow is the same as the first phase I described above
  • the phase Tb is the same as the third phase III described above
  • the phase Tc is the same as the fifth phase V described above.
  • the circuit structure shown in FIG. 3 and FIG. 5 differs in the working principle mainly in the phase Tc.
  • the first clock signal CLKB is switched from the low level to the high level
  • the second clock signal CLK is changed from the high level to the low level
  • the reset terminal is The signal RESRT is switched from low level to high level.
  • the sixth transistor M6 operates in the same manner as in the above-mentioned phase V, and the fourth transistor M4 and the second transistor M2 are both turned on at this time, and the potential at the output terminal OUTPUT can be pulled down by the two transistors together. .
  • the fourth transistor M4 can be designed as a transistor of a larger size, mainly for ensuring a normal discharge process of the potential at the output terminal OUTPUT.
  • the size of the second transistor M2 can be set small, the power consumption of the circuit can be reduced without increasing the load of the second clock signal CLK.
  • the setting of the second capacitor C2 can ensure that the timing at which the second clock signal CLK transitions from the low level to the high level coincides with the timing at which the first clock signal CLKB changes from the high level to the low level, thereby offsetting the The adverse effect caused by the parasitic capacitance generated when the second clock signal CLK is connected to the third transistor M3, and can effectively offset the second clock signal CLK from low level to high level for the first section
  • the coupling of the potential at the PU prevents the erroneous output of the shift register and improves the stability of the circuit.
  • the capacitance value of the second capacitor C2 may be equal to the capacitance value of the generated parasitic capacitance after the second clock signal CLK is connected to the third transistor M3 to achieve a better offset effect.
  • FIG. 7 is a structural block diagram of a gate driving circuit in an embodiment of the present disclosure.
  • the gate driving circuit includes a plurality of shift register units (U1, U2, U3, ..., Un-1, Un) having an input terminal INPUT, a reset terminal RESET, and an output terminal OUTPUT.
  • the input terminal INPUT of any one of the shift register units (U2, U3, ..., Un-1, Un) is the same as the previous one except that the input terminal INPUT of the first stage shift register unit U1 is connected to the initial scan signal STV.
  • the output terminal OUTPUT of the stage shift register unit is connected (for example, the input terminal INPUT of the shift register unit U3 is connected to the output terminal OUTPUT of the shift register unit U2), and the shift register unit of the gate drive circuit adopts any one of the above.
  • the circuit structure of the shift register is connected (for example, the input terminal INPUT of the shift register unit U3 is connected to the output terminal OUTPUT of the shift register unit U2), and the shift register unit of the gate drive circuit adopts any one of the above.
  • each stage shift register unit is connected to the output terminal of the shift register unit of the next stage.
  • the reset terminal RESET of the shift register unit U2 is connected to the output terminal OUTPUT of the shift register unit U3.
  • each stage shift register unit is connected to the first clock signal CLKB, the second clock signal CLK, and the low level voltage line VGL.
  • the initial scan signal can be transferred step by step by the multi-stage shift register unit and output as gate-level scan signals (G1, G2, G3, ..., Gn-1, Gn) of each row.
  • each stage shift register unit performs the function of the potential pull-down at the output terminal when its output pull-down module 14 performs the pull-down function at the output terminal
  • the second input module 12 can pass the output terminal OUTPUT of the first node PU and the shift register unit of the previous stage.
  • the input terminal INPUT of the shift register unit of the current stage is connected, so that the noise voltage on the first node PU at this time can be discharged and pulled down by the output pull-down module 14 in the shift register unit of the previous stage, thereby ensuring the shift of the stage.
  • the potentials at the first node PU and the output terminal OUTPUT of the register unit are effectively pulled down to a stable low level.
  • the above shift register circuit can be 5T1C (5 thin film transistors and 1 capacitor), or 6T2C (6 thin film transistors and 2 capacitors), which usually requires about ten compared to the prior art.
  • the shift register circuit of the transistor has fewer transistors, and also has some special designs in the size of each transistor, so that the gate drive circuit can reduce the width occupied by the gate drive circuit when it is composed of the gate drive circuit, which is advantageous for display.
  • the narrow bezel of the device is even a borderless design.
  • an embodiment of the present disclosure provides a display device including any one of the above-described gate driving circuits.
  • the display device can be any display product, component such as a display panel, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like. Further, the display device includes any of the above-described gate drive circuits, and thus the same technical problem can be solved, and the same technical effects can be obtained.
  • the orientation or positional relationship of the terms “upper”, “lower” and the like is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the embodiments and simplification of the present disclosure.
  • the terms “mounted,” “connected,” and “connected” are to be interpreted broadly. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal to both components. Connected.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。该移位寄存器包括：第一输入模块(11)，用于在输入端所接收信号作用下上拉第一节点的电位；输出模块(13)，用于在第一节点的电位作用下上拉输出端的电位；复位模块(15)，用于在复位端所接收信号作用下拉低第一节点的电位；输出下拉模块(14)，用于在第一时钟信号的作用下拉低输出端的电位；其中，第一输入模块（11）、输出模块(13)、输出下拉模块(14)和复位模块(15)均与第一节点相连，并且该移位寄存器还包括第二输入模块(12)，用于在第一时钟信号作用下在第一输入模块(11)和输出下拉模块(14)工作时间内将输入端与第一节点连接。该移位寄存器去除了下拉节点，可以减少晶体管数量，有利于减小栅极驱动电路所占边框宽度。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置 技术领域
本公开涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
目前，为了实现低成本和窄边框的目的，显示面板大部分都采用了GOA(Gate driver On Array，阵列基板行驱动)技术。而传统的GOA电路是设置在有效显示区域的两侧，需要一定宽度的黑矩阵区域遮挡，这样就导致显示面板本身会有一定宽度的边框。从用户的舒适性和操作性等方面考虑，超窄的边框或者无边框是目前的消费和技术潮流。然而，GOA电路主要实现的是移位寄存功能，在a-Si(非晶硅)或者氧化物工艺等不能实现CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)器件的GOA电路中，一般会采用具有上拉节点PU(Pulling up)和下拉节点PD(Pulling down)的电路结构。为了维持这种电路结构的正常工作，通常要为上拉节点和下拉节点分别设置多个用于调控其电位的晶体管，这会使得每个GOA单元中的晶体管数量都会在十个左右，不利于GOA电路所占边框宽度的减小。
发明内容
在本公开的若干实施例中提供一种移位寄存器及其驱动方法、栅极驱动电路、显示装置，用以解决具有上拉节点PU与下拉节点PD的电路结构制约GOA电路所占边框宽度的减小的问题。
第一方面，本公开提供了一种移位寄存器，包括输入端、复位端和输出端，其中，该移位寄存器还包括：
第一输入模块，与所述输入端相连，用于在输入端所接收信号的作用下上拉所述第一节点处的电位；
输出模块，与所述输出端相连，用于在所述第一节点处的电位的作用下上拉所述输出端处的电位；
复位模块，与所述复位端相连，用于在复位端所接信号的作用下拉低所述第一节点处的电位；以及
输出下拉模块，与所述输出端相连，用于在第一时钟信号的作用下拉低所述输出端的电位；
其中，所述第一输入模块、输出模块、复位模块和输出下拉模块均与第一节点相连；并且
该移位寄存器还包括与所述输入端以及所述第一节点相连的第二输入模块，所述第二输入模块用于在第一时钟信号的作用下在所述第一输入模块和所述输出下拉模块工作时间内将所述输入端与所述第一节点相连接。
可选地，所述第二输入模块包括第一晶体管，所述第一晶体管的栅极连接所述第一时钟信号，源极与漏极中的一个与所述输入端相连，另一个与所述第一节点相连。
可选地，所述输出模块包括第一电容与第三晶体管，其中：
所述第一电容的一端与所述第一节点相连，另一端与所述输出端相连；
所述第三晶体管的栅极与所述第一节点相连，源极与漏极中的一个与输出端相连，另一个连接第二时钟信号。
可选地，所述第二时钟信号的占空比小于百分之五十。
可选地，所述移位寄存器还包括第四晶体管，所述第四晶体管的栅极与所述复位端相连，源极与漏极中的一个与所述输出端相连，另一个与低电平电压线相连。
可选地，所述移位寄存器还包括第二电容，所述第二电容的一端与所述第一节点相连，另一端连接所述第一时钟信号。
可选地，所述第二电容的大小与第二时钟信号与所述第三晶体管之间的寄生电容的大小相等。
可选地，所述输出下拉模块包括第二晶体管，所述第二晶体管的栅极连接第一时钟信号，源极与漏极中的一个与所述输出端相连，另一个与低电平电压线相连。
可选地，所述输入模块包括第五晶体管，所述第五晶体管的栅极连接所述 输入端，源极与漏极中的一个连接所述输入端，另一个连接所述第一节点。
可选地，所述复位模块包括第六晶体管，所述第六晶体管的栅极连接所述复位端，源极与漏极中的一个连接所述第一节点，另一个连接低电平电压线。
第二方面，本公开还提供了一种栅极驱动电路，包括多级具有输入端、复位端和输出端的移位寄存单元，除第一级之外的任一级移位寄存单元的输入端均与上一级移位寄存单元的输出端相连，所述移位寄存单元采用上述任意一种的移位寄存器。
第三方面，本公开还提供了一种显示装置，包括上述任意一种栅极驱动电路。
第四方面，本公开还提供了一种驱动上述任意一种移位寄存器的方法，包括：
在第一阶段，向所述输入端输入第一电平，以使所述第一输入模块在第一电平的作用下上拉所述第一节点处的电位、所述第二输入模块在第一时钟信号的作用下导通所述输入端与所述第一节点，并使得所述输出模块在所述第一节点处的电位的作用下上拉所述输出端处的电位；
在第二阶段，向所述输入端输入第二电平，并向所述复位端处输入第二电平，以使所述复位模块拉低所述第一节点处的电位、所述输出下拉模块在在第一时钟信号的作用下拉低所述输出端的电位，并使得所述第二输入模块在第一时钟信号的作用下导通所述输入端与所述第一节点。
可选地，所述输出模块包括第三晶体管，所述第三晶体管的源极或漏极中的一个连接第二时钟信号另一个连接所述输出端，所述第二时钟信号的占空比小于百分之五十。
由上述技术方案可知，本公开的移位寄存器可以作为GOA单元的电路结构，此时第二输出模块可以在输出下拉模块将输出端处电位放电至低电平电压线的同时将第一节点(即上拉节点PU)处的噪声电压放电至输入端，从而在级联电路中可以经由上一级GOA单元的输出端和输出下拉模块放电至低电平电压线。所以，本公开同样可以实现现有技术中具有上拉节点PU与下拉节点PD的电路结构的功能。
进一步地，由于本公开仅去除了下拉节点PD，也就是说去除了移位寄存器和栅极驱动电路中用于调控下拉节点处电位的多个晶体管，因而可以减少其所用晶体管的数量，有利于减小栅极驱动电路所占的边框宽度。
附图说明
图1是本公开一个实施例中一种移位寄存器的电路结构框图；
图2是本公开一个实施例中一种移位寄存器的驱动方法的步骤流程图；
图3是本公开一个实施例中一种移位寄存器的电路结构示意图；
图4是图3中移位寄存器的电路结构的电路工作时序图；
图5是本公开另一实施例中一种移位寄存器的电路结构示意图；
图6是图5中移位寄存器的电路结构的电路时序图；
图7是本公开一个实施例中一种栅极驱动电路的结构示意图。
具体实施方式
为使本公开实施例的原理、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例进行清楚、完整地描述。显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开的范围。
图1是本公开一个实施例中一种移位寄存器的结构框图。参见图1，该移位寄存器包括输入端、复位端和输出端。而且，该移位寄存器包括均与第一节点PU相连的第一输入模块11、第二输入模块12、输出模块13、输出下拉模块14和复位模块15。
在图1中，第一输入模块11还与输入端相连，用于在输入端所接收信号的作用下上拉第一节点PU处的电位。
输出模块13还与输出端相连，用于在第一节点PU处的电位的作用下上拉输出端处的电位。
复位模块15还与复位端相连，用于在复位端所接收信号的作用下拉低第 一节点PU处的电位(图1中示例性地以连接低电平电压线VGL为例表示作用为下拉)。
输出下拉模块14还与输出端相连，用于在第一时钟信号CLKB的作用下拉低输出端的电位(图1中示例性地以连接低电平电压线VGL为例表示作用为下拉)。
第二输入模块12与输入端相连，用于在第一时钟信号CLKB的作用下在第一输入模块11和输出下拉模块14工作时间内将输入端与第一节点PU连接。
需要说明的是，本文所说的时钟信号可以分为频率相同而相位错开的两个或两个以上的时钟信号。
举例来说，第二输入模块12可以在第一输入模块11工作时间内将输入端与第一节点PU连接。若同一时间内输入端所接收的信号为高电平，则第二输入模块12可以起到辅助上拉第一节点PU处的电位的作用，使得第一节点处电位的上升时间更短。另一方面，第二输入模块12可以在输出下拉模块14工作时间内将输入端与第一节点PU连接，此时第二输入模块12可以在输出下拉模块14将输出端处电位放电至低电平电压线VGL的同时，将第一节点PU处的噪声电压放电至输入端，从而在级联电路中可以经由上一级GOA单元的输出端和输出下拉模块放电至低电平电压线VGL，从而第一节点PU可以被顺利地放电至稳定低电平。此外，在输入端和复位端所接收信号的控制下，该移位寄存器中的各个模块可以协同地完成信号的输出和复位(亦即输出端处电位的上拉与下拉)。所以，本公开的该实施例中同样可以实现具有上拉节点PU与下拉节点PD的电路结构的功能。
进一步地，由于在本公开的实施例中去除了下拉节点PD，也就是说，去除了移位寄存器和栅极驱动电路中用于调控下拉节点处电位的多个晶体管，因而可以减少其所用晶体管的数量，有利于减小栅极驱动电路所占的边框宽度。
需要说明的是，由于上述第一输入模块11、第二输入模块12、输出模块13、输出下拉模块14和复位模块15均具有明确的功能，并显然具有开关电路(在一端控制下导通或断开另外两端)的特性，因此本领域技术人员可以通过例如晶体管和继电器的开关元件或者开关元件的组合来实现。而且，在维持连 接关系和功能不变的情况下，本领域技术人员对于上述第一输入模块11、第二输入模块12、输出模块13、输出下拉模块14和复位模块15中的任意一个均可以得到多种不同实现方式，本公开对此不做限制。
图2是本公开一个实施例中一种移位寄存器的驱动方法的步骤流程示意图。参见图2，该方法包括下列工作过程：
在步骤201中：在第一阶段期间，向所述输入端输入第一电平，以使所述第一输入模块在第一电平的作用下上拉第一节点PU处的电位、所述第二输入模块在第一时钟信号的作用下将输入端与第一节点连接，并使得所述输出模块在第一节点PU处的电位的作用下上拉输出端处的电位；
在步骤202中：在第二阶段期间，向所述输入端输入第二电平，并向所述复位端处输入第二电平，以使复位模块拉低第一节点PU处的电位、输出下拉模块在第一时钟信号的作用下拉低输出端的电位，并使得所述第二输入模块在第一时钟信号的作用下将输入端与第一节点连接。
上述方法可以驱动上述任意一种移位寄存器从而实现其移位寄存的功能。举例来说，设第一电平为高电平、第二电平为低电平，参见图1，一种示例性的可选驱动方法的步骤流程可以如下所述：
在第一阶段中，由于向移位寄存器的输入端输入了高电平信号，因而在输入端所接收的高电平作用下，第一输入模块11执行上拉第一节点PU处电位的功能；同时，在第一时钟信号CLKB的作用下第二输入模块12将第一节点PU与输入端连接，使得输入端所接收的高电平可以通过第二输入模块12上拉第一节点PU处的电位，相当于第二输入模块12可以辅助执行第一节点PU处电位的上拉功能。在第一节点PU处电位被上拉后，输出模块13会在第一节点PU处电位的作用下上拉输出端的电位，使得移位寄存器于输出端输出高电平。
在第二阶段中，由于向输入端输入了低电平信号，因而第一输入模块11不再执行上拉第一节点PU处电位的功能。同时，由于向复位端输入了高电平信号，因而复位模块15执行拉低第一节点PU处的电位的功能(比如使第一节点PU与低电平电压线VGL连通)。并且，输出下拉模块14会在第一时钟信号CLKB的作用下拉低输出端的电位(比如使输出端与低电平电压线VGL连通)， 使得移位寄存器于输出端输出低电平。同时，第二输入模块12也在第一时钟信号CLKB的作用下将第一节点PU与接收低电平信号的输入端连接，因而第一节点处PU的噪声信号可以通过第二输入模块12被放电至接收低电平信号的输入端，使得第一节点PU可以在此后处于稳定的低电平。
可见，经过上述第一阶段和第二阶段，本公开实施例所提供的方法可以使移位寄存器的输出端先输出高电平再输出低电平，相当于将由输入端输入的信号进行了延时输出，因而可以实现移位寄存器的功能。进一步地，第一阶段中第二输入模块12可以辅助上拉第一节点处的电位，第二阶段中第二输入模块12可以去除第一节点PU处的噪声信号，因而可以去除移位寄存器中用于调控下拉节点PD处电位的多个晶体管，因而可以减少其所用晶体管的数量。
为了更清楚地说明本公开实施例中移位寄存器的可选电路结构以及可选驱动方法，下面以图3所示的一种移位寄存器的电路结构图进行举例说明。
参见图3，上述第二输入模块12可以包括第一晶体管M1，第一晶体管M1的栅极连接第一时钟信号CLKB，漏极与输入端INPUT相连，源极与第一节点PU相连。
第一晶体管M1可以在第一时钟信号CLKB的作用下控制通过输入端INPUT与第一节点PU的电流，因而可以实现上述第二输入模块12的功能。
需要说明的是，虽然图3中的晶体管均是以上方为漏极、下方为源极的N沟道薄膜晶体管(Thin Film Ttransistor，TFT)为例，但晶体管还可以是其他类型的晶体管。而且视具体电路中高低电平的设定以及晶体管的类型与特性的不同，各晶体管的源极与漏极可以全部互换或者部分互换，其是本领域技术人员根据实际应用容易实现的，在此不再赘述。
如图3所示，上述输出模块13可以包括第一电容C1与第三晶体管M3。第一电容C1的一端与第一节点PU相连，另一端与输出端OUTPUT相连。第三晶体管M3的栅极与第一节点PU相连，源极与输出端OUTPUT相连，漏极连接第二时钟信号CLK。
在第一节点PU处的电位被上拉后，第三晶体管M3可以使高电平的第二时 钟信号CLK与输出端OUTPUT之间通过较大的电流，而第一电容C1可以保持其两端的电位差，从而使得第一节点PU处的电位被进一步上拉，同时使输出端OUTPUT处的电位被上拉，实现上述输出模块13上拉输出端OUTPUT处的电位的功能。
如图3所示，上述输出下拉模块14可以包括第二晶体管M2，第二晶体管M2的栅极连接第一时钟信号CLKB，漏极与输出端OUTPUT相连，源极与低电平电压线VGL相连。
第二晶体管M2可以在第一时钟信号CLKB的作用下控制由输出端OUTPUT流向低电平电压线VGL的电流，因而可以实现上述输出下拉模块14的功能。
如图3所示，上述第一输入模块11可以包括第五晶体管M5，第五晶体管M5的栅极连接输入端INPUT，漏极也连接输入端INPUT，源极连接第一节点PU。由此，在输入端INPUT处为高电平时，第五晶体管M5可以通过源极和漏极的电流使第一节点PU处的电位上拉，从而实现上述第一输入模块11的功能。
如图3所示，上述复位模块15可以包括第六晶体管M6，第六晶体管M6的栅极连接复位端RESET，漏极连接第一节点PU，源极连接低电平电压线VGL。由此，第六晶体管M6可以在复位端RESET所接信号作用下控制由第一节点PU流向低电平电压线VGL的电流，因而可以实现上述复位模块15的功能。
图4是图3中所示移位寄存器的电路结构的工作流程的时序图。可以看出，其中第二时钟信号CLK的占空比小于百分之五十。基于这一设置及图3所示的电路结构，该移位寄存器的大致工作原理如下所述：
在图4所示的第一阶段I中：第一时钟信号CLKB为高电平、第二时钟信号CLK为低电平，同时输入端INPUT处为高电平。从而，第一晶体管M1与第五晶体管M5共同对第一节点PU进行充电，使得第一节点PU处电位逐步上拉至高电平。
在图4所示的第二阶段II中：第一时钟信号CLKB与第二时钟信号CLK均为低电平，同时输入端INPUT处也转为低电平，从而第一晶体管M1与第五晶体管M5关断，栅极连接第一时钟信号CLKB的第二晶体管M2也处于关断状态，因而第一节点PU处电位仍然保持为高电平。
在图4所示的第三阶段III中：第二时钟信号CLK为高电平、第一时钟信号CLKB为低电平，输出模块13处于工作状态，栅极连接第一时钟信号CLKB的第二晶体管M2也处于关断状态，从而在上述第一电容C1与第三晶体管M3的协同作用下第一节点PU处的电位被进一步上拉，使得输出端OUTPUT处的电位上升、移位寄存器于输出端输出高电平。
在图4所示的第四阶段IV中：第一时钟信号CLKB与第二时钟信号CLK均为低电平，此时第三晶体管M3的漏极电位转为低电平，会使得第一节点PU处电位降至没有被进一步上拉之前的高电平，同时输出端OUTPUT也回到之前的低电平。也就是说，此时输出端OUTPUT处的高电位通过第三晶体管M3放电至低电平。
在图4所示的第五阶段V中：第一时钟信号CLKB为高电平，第二时钟信号CLK为低电平，同时复位端信号RESET转变为高电平。此时，第一节点PU处的高电平通过第六晶体管M6向低电平电压线VGL进行放电，从而降至低电平，同时第二晶体管M2在第一时钟信号CLKB的作用下进一步将输出端OUTPUT的噪声电压放电至低电平电压线VGL的稳定低电平，从而使得移位寄存器的输出端在之后都输出稳定的低电平。
可见，由于将第二时钟信号CLK的占空比设定在小于百分之五十的范围内，因而移位寄存器的工作流程中多出了一个上述第四阶段IV，使得输出端OUTPUT可以在此阶段内通过第三晶体管M3放电至低电平，进而第二晶体管M2就只起到去除输出端OUTPUT处噪声电压的作用，因而不需要具有很大的尺寸，有利于在移位寄存器组成栅极驱动电路时减小栅极驱动电路所占的宽度。
当然，上述第一时钟信号CLKB与第二时钟信号CLK的占空比也可以均为百分之五十，此时相当于去除了上述阶段II与阶段IV，输出端OUTPUT处的电位需要通过第二晶体管M2来拉低，而为了减小拉低时间，第二晶体管M2需要具有较大的尺寸。同时，较大尺寸的第二晶体管M2会增加第二时钟信号CLK的负载，整个电路的功耗会大幅度增加。
所以，通过上述第二时钟信号CLK占空比小于百分之五十的设计，可以起到减小第二晶体管M2所需尺寸的作用，从而有利于在移位寄存器组成栅极驱 动电路时减小栅极驱动电路所占的宽度、并降低整个电路的功耗。
这里，第一时钟信号CLKB虽然在图4中的占空比也小于百分之五十，但是由此增加的阶段II并不会对原工作流程造成很大影响，因而其并不是达到上述效果所必要的，即第一时钟信号CLKB的占空比是否为50％可以不做限制。而且，上述第二时钟信号CLK的占空比由于需要使输出端OUTPUT的所输出的信号满足要求，因而在不同的实际应用中可以有不同的下限值，具体的占空比设置方式是本领域技术人员所熟知的，在此不再赘述。
图5是本公开另一实施例中一种移位寄存器的电路结构图。参见图5，该移位寄存器在上述图3所示的电路结构的基础上增设了第四晶体管M4和第二电容C2。图5中：第四晶体管M4的栅极与复位端RESET相连，漏极与输出端OUTPUT相连，源极与低电平电压线VGL相连。第二电容C2的一端与第一节点PU相连，另一端连接第一时钟信号CLKB。
图6是图5中移位寄存器的电路结构的工作流程的时序图。该工作流程中的阶段Ta与上述第一阶段I相同、阶段Tb与上述第三阶段III相同、阶段Tc与上述第五阶段V相同。具体来说，图3与图5所示的电路结构在工作原理上的区别主要在于阶段Tc中。
图5所示电路中，在图6所示的阶段Tc内第一时钟信号CLKB由低电平转为高电平，第二时钟信号CLK由高电平转为低电平，同时复位端所接信号RESRT由低电平转为高电平。此时，第六晶体管M6的工作方式与上述阶段V中的相同，而第四晶体管M4与第二晶体管M2在此时均处于开启状态，输出端OUTPUT处的电位可由这两个晶体管共同进行下拉。
由此，第四晶体管M4可以设计为较大尺寸的晶体管，主要用于保障输出端OUTPUT处电位的正常放电过程。同时由于第二晶体管M2的尺寸可以设置得较小，因而可以不增加第二时钟信号CLK的负载，降低电路的功耗。
此外，上述第二电容C2的设置可以保障第二时钟信号CLK由低电平转为高电平的时刻与第一时钟信号CLKB由高电位转为低电平的时刻一致，因此可以抵销第二时钟信号CLK与第三晶体管M3连接后产生的寄生电容所带来的不利影响，并且可以有效抵销第二时钟信号CLK由低电平转为高电平对于第一节 点PU处电位的耦合作用，防止移位寄存器的误输出、提高电路的稳定性。可替换地，可以使第二电容C2的电容值等于第二时钟信号CLK与第三晶体管M3连接后的产生的寄生电容的电容值，以达到更佳的抵销效果。
图7是本公开一个实施例中一种栅极驱动电路的结构框图。所述栅极驱动电路包括多级具有输入端INPUT、复位端RESET和输出端OUTPUT的移位寄存单元(U1、U2、U3……、Un-1、Un)。除第一级移位寄存单元U1的输入端INPUT与初始扫描信号STV相连之外，任一级移位寄存单元(U2、U3……、Un-1、Un)的输入端INPUT均与上一级移位寄存单元的输出端OUTPUT相连(如移位寄存单元U3的输入端INPUT与移位寄存单元U2的输出端OUTPUT相连)，而且，该栅极驱动电路的移位寄存单元采用上述任意一种移位寄存器的电路结构。
另外，除最后一级移位寄存单元的复位端连接其他信号(图7中未示出)之外，每一级移位寄存单元的复位端均与下一级移位寄存单元的输出端相连(例如移位寄存单元U2的复位端RESET与移位寄存单元U3的输出端OUTPUT相连)。而且，基于如图3或图5所示的电路结构，每一级移位寄存单元都要连接第一时钟信号CLKB、第二时钟信号CLK和低电平电压线VGL。
基于上述结构，初始扫描信号可以被多级移位寄存单元逐级地传递并输出为每一行的栅级扫描信号(G1、G2、G3、……Gn-1、Gn)。
进一步地，由于每一级移位寄存单元在其输出下拉模块14执行输出端处电位下拉的功能时第二输入模块12可以将第一节点PU与上一级移位寄存单元的输出端OUTPUT通过本级移位寄存单元的输入端INPUT相连，从而此时的第一节点PU上的噪声电压可以由上一级移位寄存单元中的输出下拉模块14进行放电下拉，从而可以保障本级移位寄存单元的第一节点PU与输出端OUTPUT处的电位均被有效地下拉至稳定的低电平。
同时可以看出，上述移位寄存器电路可以是5T1C(5个薄膜晶体管和1个电容)，也可以是6T2C(6个薄膜晶体管和2个电容)，相比于现有技术通常需要十个左右晶体管的移位寄存器电路具有更少的晶体管数量，同时也在各晶体管的尺寸上有一些特殊设计，使得其组成栅极驱动电路时可以减小栅极驱动电路所占的宽度，有利于实现显示装置的窄边框甚至是无边框的设计。
基于同样的发明构思，本公开实施例提供了一种显示装置，该显示装置包括上述任意一种栅极驱动电路。该显示装置可以为：显示面板、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。此外，该显示装置包括上述任意一种栅极驱动电路，因而可以解决相同的技术问题，取得同样的技术效果。
在本公开的描述中需要说明的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开的实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。
本申请要求于2015年3月9日递交的中国专利申请第201510102976.4号 的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (13)

  1. 一种移位寄存器，包括输入端、复位端和输出端，其中，该移位寄存器还包括：
    第一输入模块，与所述输入端相连，用于在所述输入端接收信号的作用下上拉第一节点处的电位；
    输出模块，与所述输出端相连，用于在所述第一节点处的电位的作用下上拉所述输出端处的电位；
    复位模块，与所述复位端相连，用于在复位端所接信号的作用下拉低所述第一节点处的电位；以及
    输出下拉模块，与所述输出端相连，用于在第一时钟信号的作用下拉低所述输出端的电位；
    其中，所述第一输入模块、输出模块、复位模块和输出下拉模块均与第一节点相连；并且
    该移位寄存器还包括与所述输入端以及所述第一节点相连的第二输入模块，所述第二输入模块用于在第一时钟信号的作用下在所述第一输入模块和所述输出下拉模块工作时间内将所述输入端与所述第一节点相连接。
  2. 根据权利要求1的移位寄存器，其中，所述第二输入模块包括第一晶体管，所述第一晶体管的栅极连接所述第一时钟信号，源极与漏极中的一个与所述输入端相连，另一个与所述第一节点相连。
  3. 根据权利要求1的移位寄存器，其中，所述输出模块包括第一电容与第三晶体管，其中：
    所述第一电容的一端与所述第一节点相连，另一端与所述输出端相连；
    所述第三晶体管的栅极与所述第一节点相连，源极与漏极中的一个与输出端相连，另一个连接第二时钟信号。
  4. 根据权利要求3的移位寄存器，其中，所述第二时钟信号的占空比小于百分之五十。
  5. 根据权利要求3的移位寄存器，其中，所述移位寄存器还包括第四晶体管，所述第四晶体管的栅极与所述复位端相连，源极与漏极中的一个与所述输出端相连，另一个与低电平电压线相连。
  6. 根据权利要求5的移位寄存器，其中，所述移位寄存器还包括第二电 容，所述第二电容的一端与所述第一节点相连，另一端连接所述第一时钟信号。
  7. 根据权利要求6的移位寄存器，其中，所述第二电容的大小与第二时钟信号与所述第三晶体管之间的寄生电容的大小相等。
  8. 根据权利要求1至7中任意一项所述的移位寄存器，其中，所述输出下拉模块包括第二晶体管，所述第二晶体管的栅极连接第一时钟信号，源极与漏极中的一个与所述输出端相连，另一个与低电平电压线相连。
  9. 根据权利要求1至7中任意一项所述的移位寄存器，其中，所述输入模块包括第五晶体管，所述第五晶体管的栅极连接所述输入端，源极与漏极中的一个连接所述输入端，另一个连接所述第一节点。
  10. 根据权利要求1至7中任意一项所述的移位寄存器，其中，所述复位模块包括第六晶体管，所述第六晶体管的栅极连接所述复位端，源极与漏极中的一个连接所述第一节点，另一个连接低电平电压线。
  11. 一种栅极驱动电路，包括多级具有输入端、复位端和输出端的移位寄存单元，除第一级之外的任一级移位寄存单元的输入端均与上一级移位寄存单元的输出端相连，其中，所述移位寄存单元采用如权利要求1至10中任意一项所述的移位寄存器。
  12. 一种显示装置，其中，包括权利要求11所述的栅极驱动电路。
  13. 一种驱动权利要求1至10中任意一项的移位寄存器的方法，其中，包括下列步骤：
    在第一阶段，向所述输入端输入第一电平，以使所述第一输入模块在第一电平的作用下上拉所述第一节点处的电位、所述第二输入模块在第一时钟信号的作用下导通所述输入端与所述第一节点，并使得所述输出模块在所述第一节点处的电位的作用下上拉所述输出端处的电位；
    在第二阶段，向所述输入端输入第二电平，并向所述复位端处输入第二电平，以使所述复位模块拉低所述第一节点处的电位、所述输出下拉模块在在第一时钟信号的作用下拉低所述输出端的电位，并使得所述第二输入模块在第一时钟信号的作用下导通所述输入端与所述第一节点。
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104616617B (zh) 2015-03-09 2017-03-22 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN106328042A (zh) * 2015-06-19 2017-01-11 上海和辉光电有限公司 移位寄存器及oled显示器驱动电路
CN104978922B (zh) * 2015-07-29 2017-07-18 京东方科技集团股份有限公司 移位寄存器、显示装置及移位寄存器驱动方法
CN105047127B (zh) * 2015-09-21 2017-12-22 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、行扫描驱动电路、显示装置
CN105161134B (zh) * 2015-10-09 2018-10-23 京东方科技集团股份有限公司 移位寄存器单元及其操作方法、移位寄存器
CN105185412A (zh) * 2015-10-19 2015-12-23 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN105427790B (zh) * 2016-01-05 2017-12-08 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN105741878B (zh) * 2016-01-28 2019-09-06 京东方科技集团股份有限公司 控制电路、移位寄存器单元、栅极驱动电路及显示装置
CN105590612B (zh) * 2016-03-22 2018-01-16 京东方科技集团股份有限公司 一种移位寄存器及驱动方法、栅极驱动电路和显示装置
CN105869563B (zh) 2016-05-30 2019-01-18 京东方科技集团股份有限公司 Goa单元电路及其驱动方法、goa电路
CN106057118A (zh) * 2016-06-30 2016-10-26 京东方科技集团股份有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置
CN106782663B (zh) * 2017-01-12 2019-12-17 上海天马有机发光显示技术有限公司 一种移位寄存器及栅极驱动电路
CN107424552B (zh) * 2017-06-13 2019-11-05 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
WO2019033294A1 (en) 2017-08-16 2019-02-21 Boe Technology Group Co., Ltd. NETWORK GRID DRIVER CIRCUIT, AMOLED DISPLAY PANEL PIXEL CIRCUIT, AMOLED DISPLAY PANEL, AND AMOLED DISPLAY PANEL PIXEL CIRCUIT DRIVING METHOD
CN107527599B (zh) * 2017-08-16 2020-06-05 深圳市华星光电半导体显示技术有限公司 扫描驱动电路、阵列基板与显示面板
CN109427277B (zh) * 2017-08-31 2020-11-03 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN108564910A (zh) * 2018-03-12 2018-09-21 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN109545152B (zh) * 2019-01-02 2020-09-01 合肥鑫晟光电科技有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN111445833B (zh) 2020-05-09 2022-09-13 合肥京东方卓印科技有限公司 移位寄存器单元及其控制方法、和栅极驱动电路
CN116666379B (zh) * 2023-05-11 2024-04-05 合芯科技有限公司 一种抗干扰的模块版图结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921016A (zh) * 2005-08-22 2007-02-28 三星Sdi株式会社 移位寄存器电路
CN103021358A (zh) * 2012-12-07 2013-04-03 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示器件
CN103226981A (zh) * 2013-04-10 2013-07-31 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路
CN103714792A (zh) * 2013-12-20 2014-04-09 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104616617A (zh) * 2015-03-09 2015-05-13 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI413050B (zh) * 2009-03-17 2013-10-21 Au Optronics Corp 高可靠度閘極驅動電路
CN102831861B (zh) * 2012-09-05 2015-01-21 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动器及显示装置
CN102831860B (zh) * 2012-09-05 2014-10-15 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动器及显示装置
US20150262703A1 (en) * 2012-10-05 2015-09-17 Sharp Kabushiki Kaisha Shift register, display device provided therewith, and shift-register driving method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921016A (zh) * 2005-08-22 2007-02-28 三星Sdi株式会社 移位寄存器电路
CN103021358A (zh) * 2012-12-07 2013-04-03 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示器件
CN103226981A (zh) * 2013-04-10 2013-07-31 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路
CN103714792A (zh) * 2013-12-20 2014-04-09 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104616617A (zh) * 2015-03-09 2015-05-13 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3270370A4 *

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