WO2016136604A1 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- WO2016136604A1 WO2016136604A1 PCT/JP2016/054809 JP2016054809W WO2016136604A1 WO 2016136604 A1 WO2016136604 A1 WO 2016136604A1 JP 2016054809 W JP2016054809 W JP 2016054809W WO 2016136604 A1 WO2016136604 A1 WO 2016136604A1
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- memory
- word line
- bit line
- antifuse
- gate electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 297
- 230000015654 memory Effects 0.000 claims abstract description 978
- 239000003990 capacitor Substances 0.000 claims abstract description 151
- 238000009792 diffusion process Methods 0.000 claims description 47
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- 101100301076 Canis lupus familiaris RBM47 gene Proteins 0.000 description 7
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- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
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- 238000005530 etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
- H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
Definitions
- the present invention relates to a semiconductor memory device, and is suitable for application to, for example, a semiconductor memory device in which antifuse memories are arranged in a matrix.
- Patent Document 1 As an antifuse memory capable of writing data only once by destroying an insulating film, an antifuse memory having a structure as shown in US Pat. No. 6,667,902 (Patent Document 1) is known. ing.
- the antifuse memory disclosed in Patent Document 1 has a two-transistor configuration in which a switch transistor and a memory capacitor are formed side by side on a well.
- a switch gate electrode is formed on a well via a switch gate insulating film, a word line is connected to the switch gate electrode, and a switch gate electrode is formed on the well surface.
- a bit line is connected to the diffusion region.
- the memory capacitor paired with the switch transistor has a memory gate electrode formed on the well via a memory gate insulating film, and a write word line different from the word line connected to the switch gate electrode Connected to the memory gate electrode.
- the memory capacitor has a dielectric breakdown caused by the voltage difference between the breakdown word voltage applied from the write word line to the memory gate electrode and the breakdown bit voltage applied to the bit line of the switch transistor.
- the memory gate electrode that is insulated from the well can be electrically connected to the surface of the well, that is, the region where the memory channel is formed, due to dielectric breakdown of the memory gate insulating film.
- the voltage applied to the write word line passes through the memory channel.
- the switch transistor is turned on by a voltage applied from the word line connected to the switch gate electrode and the bit line connected to the diffusion region, and the memory gate electrode in the paired memory capacitor, the memory channel, Can be determined based on the change in the voltage applied to the bit line to determine whether or not data is written.
- an object of the present invention is to propose a semiconductor memory device that can be made smaller than before.
- a semiconductor memory device of the present invention is a semiconductor memory device in which an antifuse memory is arranged at each intersection of a plurality of word lines and a plurality of bit lines, and each of the antifuse memories is a memory.
- a memory gate electrode is provided through a gate insulating film, and a memory capacitor in which the bit line is connected to one diffusion region formed in the well through a bit line contact; and the memory gate electrode and the word line.
- the voltage from the word line is applied to the memory gate electrode via a word line contact, and the voltage from the memory gate electrode is applied to the memory gate electrode and the word line.
- a rectifying element that blocks voltage application to the word line, and two or more antifuse memories One bit line contact is shared.
- the semiconductor memory device of the present invention is a semiconductor memory device in which an antifuse memory is arranged at each intersection of a plurality of word lines and a plurality of bit lines, and each antifuse memory includes a memory gate insulating film.
- a memory gate electrode provided between the memory gate electrode and the word line, and a memory capacitor in which the bit line is connected to one diffusion region formed in the well via a bit line contact.
- the voltage from the word line is applied to the memory gate electrode via a word line contact, while the voltage value applied to the memory gate electrode and the word line is changed from the memory gate electrode to the word line.
- a rectifying element that cuts off voltage application, and one word line in two or more antifuse memories. And wherein the sharing Ntakuto.
- voltage application from the memory gate electrode to the word line is cut off by the rectifying element according to the voltage value applied to the memory gate electrode and the word line of the memory capacitor without using a conventional control circuit.
- bit line contact and / or one word line contact is shared by at least two antifuse memories, a bit line contact and a word are provided for each antifuse memory.
- the size can be reduced as compared with the case where a line contact is provided.
- FIG. 1 is a circuit diagram showing a basic circuit configuration of a semiconductor memory device of the present invention.
- 2A is a schematic diagram illustrating a cross-sectional configuration at a location where two antifuse memories are arranged in parallel
- FIG. 2B is a schematic diagram illustrating a planar layout of the two antifuse memories illustrated in FIG. 2A.
- FIG. FIG. 5 is a schematic diagram showing a planar layout (1) when one word line contact and one bit line contact are shared by four antifuse memories. It is the schematic which shows the planar layout (1) of a word line and a bit line. It is the schematic which shows the planar layout (1) of the word line by another embodiment, and a bit line.
- FIG. 9A is a schematic diagram illustrating a cross-sectional configuration of the antifuse memory illustrated in FIG. 8, and FIG. 9B is a schematic diagram illustrating a planar layout of the antifuse memory illustrated in FIG. 9A.
- FIG. 9A is a schematic diagram illustrating a cross-sectional configuration of the antifuse memory illustrated in FIG. 8, and FIG. 9B is a schematic diagram illustrating a planar layout of the antifuse memory illustrated in FIG. 9A.
- FIG. 10 is a schematic diagram showing a planar layout (2) when one word line contact and one bit line contact are shared by four antifuse memories. It is the schematic which shows the planar layout (2) of a word line and a bit line. It is the schematic which shows the planar layout (2) of the word line by another embodiment, and a bit line. It is the schematic which shows the planar layout (1) of the contact by other embodiment. Schematic showing a planar layout (2) when two antifuse memories arranged in the row direction share one word line contact and a plurality of antifuse memories arranged in the column direction share one bit line contact FIG. It is the schematic which shows the planar layout (2) of the contact by other embodiment.
- FIG. 18A is a schematic diagram illustrating a cross-sectional configuration of an antifuse memory according to another embodiment
- FIG. 18B is a schematic diagram illustrating a planar layout of the antifuse memory illustrated in FIG. 18A.
- Configuration of planar layout 7-2 Configuration of planar layout of bit line and word line ⁇ 8. Configuration of planar layout of bit lines and word lines according to another embodiment> ⁇ In the case of sharing one word line contact with two antifuse memories and sharing one bit line contact with a plurality of antifuse memories arranged in the column direction> ⁇ 10. Multiple antifuse memories arranged in the row direction share one word line contact, and two antifuse memories share one bit line contact> ⁇ 11. Other embodiments> 11-1. Antifuse memory having a rectifying element made of a P-type MOS transistor 11-2. Configuration according to another embodiment of antifuse memory including a rectifying element having a transistor configuration 11-3. Other
- FIG. 1 denotes the semiconductor memory device of the present invention.
- the fuse memories 2a, 2b, 2c, and 2d are arranged in a matrix.
- the semiconductor memory device 1 shares the word lines WLa (WLb) with the antifuse memories 2a and 2b (2c and 2d) arranged in the row direction, and the antifuse memories 2a and 2c (columns arranged in the column direction).
- 2b, 2d) share the bit line BLa (BLb).
- the antifuse memory 2a includes a rectifying element 3 having a semiconductor junction structure of a PN junction diode, and a memory capacitor having a memory gate insulating film 6 that is dielectrically broken by a voltage difference between the memory gate electrode G and the bit line BLa. It consists of four.
- the rectifying element 3 has a configuration in which a P-type semiconductor region and an N-type semiconductor region are joined, and the P-type semiconductor region is connected to the word line WLa and the N-type semiconductor region.
- the semiconductor region is connected to the memory gate electrode G of the memory capacitor 4.
- the voltage applied to the word lines WLa, WLb is applied to the memory gate electrode G of the memory capacitor 4 via the rectifier element 3 during the data write operation,
- the memory gate insulating film 6 of the memory capacitor 4 breaks down and data can be written into the memory capacitor 4.
- the antifuse memories 2a, 2b, 2c and 2d of the present invention provided in the semiconductor memory device 1 will be described in detail.
- FIG. 1 for example, two antifuse memories 2a and 2b arranged in the first row will be described below.
- a P-type or N-type well S2 made of, for example, Si is formed on a semiconductor substrate S1
- a rectifying element made of an insulating member is formed on the surface of the well S2.
- Layer ILb is formed.
- element isolation layers ILa and ILc made of insulating members are formed on the surface of the well S2 with a predetermined distance from the rectifying element forming layer ILb so as to sandwich the rectifying element forming layer ILb.
- the memory capacitor 4 of one antifuse memory 2a is formed between the rectifying element forming layer ILb and one element isolating layer ILa, and between the rectifying element forming layer ILb and the other element isolating layer ILc.
- a memory capacitor 4 of another antifuse memory 2b can be formed.
- one diffusion region 5 is formed on the surface of the well S2 so as to be adjacent to the element isolation layer ILa.
- a memory capacitor 4 in which a memory gate electrode G is disposed via a memory gate insulating film 6 is formed on the well S2 between the rectifying element forming layer ILb.
- another diffusion region 5 is formed on the surface of the well S2 so as to be adjacent to the element isolation layer ILc between the rectifying element formation layer ILb and the other element isolation layer ILc.
- a memory capacitor 4 in which a memory gate electrode G is disposed via a memory gate insulating film 6 is formed on the well S2 between the rectifying element formation layers ILb.
- a bit line contact BC is erected on the silicide SC, and corresponding bit lines BLa and BLb are connected to the tip of the bit line contact BC, respectively.
- a predetermined voltage can be applied to the diffusion region 5 from the bit line BLa through the bit line contact BC to the memory capacitor 4 of the antifuse memory 2a.
- the rectifying element 3 is formed on the surface of the rectifying element forming layer ILb.
- a P-type semiconductor region 8 and N-type semiconductor regions 7 formed on both sides of the P-type semiconductor region 8 are provided on the surface of the rectifying element forming layer ILb.
- the rectifying element 3 of the PN junction diode is formed by the semiconductor junction structure including the N-type semiconductor region 7 and the P-type semiconductor region 8.
- the memory gate electrode G of the memory capacitor 4 is formed of an N-type semiconductor, and is formed on the end of the memory gate electrode G and the rectifying element formation layer ILb.
- the end of the N-type semiconductor region 7 of the rectifying element 3 is integrally formed.
- the N-type semiconductor region 7 and the P-type semiconductor region 8 of the rectifying element 3 and the memory gate electrodes G of the memory capacitor 4 are formed in the same wiring layer (same layer).
- the N-type semiconductor region 7 and the P-type semiconductor region 8 of the rectifying element 3 and the memory gate electrode G of the memory capacitor 4 are formed with the same film thickness.
- the junction surfaces of the N-type semiconductor region 7, the P-type semiconductor region 8 of the rectifying element 3 and the memory gate electrode G of the memory capacitor 4 have no step and can be thinned as a whole. It has been.
- the N-type semiconductor region 7 and the P-type semiconductor region 8 of the rectifying element 3 and the memory gate electrode G of the memory capacitor 4 can be formed in the same film formation process. As compared with the case where the P-type semiconductor region 8 and the memory gate electrode G of the memory capacitor 4 are separately formed, the manufacturing process can be simplified.
- the word line contact WC is erected on the silicide SC of the P-type semiconductor region 8, and the word line WLa disposed above the bit lines BLa and BLa is connected via the word line contact WC. It is connected to the P-type semiconductor region 8.
- the voltage from the word line WLa is changed to the word line contact WC and the P of the rectifying element 3.
- the voltage is applied to the memory gate electrode G of each memory capacitor 4 through the type semiconductor region 8 and the N type semiconductor region 7 sequentially.
- the antifuse memory 2a when a positive voltage relative to the word line WLa is applied to the memory gate electrode G of the memory capacitor 4, the voltage from the memory gate electrode G is reversed in the rectifying element 3. It becomes a bias voltage and can be cut off between the N-type semiconductor region 7 and the P-type semiconductor region 8.
- the bit line contact BC, the word line contact WC, the rectifying element 3, the memory gate electrode G, the bit lines BLa and BLb, and the word line WLa formed on the well S2 are covered with an interlayer insulating layer 9.
- FIG. 2B shows the configuration of the planar layout in the region where the antifuse memories 2a, 2b shown in FIG. 2A are provided.
- FIG. 2A is a side cross-sectional configuration taken along line AA ′ of FIG. 2B.
- each bit line contact BC is disposed in the corresponding active region 12 of the well S2.
- the rectangular N-type semiconductor regions 7 provided in the adjacent anti-fuse memories 2a and 2b are arranged symmetrically about the word line contact WC arranged at the center position of the rectangular P-type semiconductor region 8. Yes.
- Each N-type semiconductor region 7 has one end joined to the side of the P-type semiconductor region 8, has a longitudinal direction extending from the P-type semiconductor region 8 toward the active region 12, and is joined to the tip portion.
- the memory gate electrode G thus formed is disposed opposite to the corresponding active region 12. In the region where the memory gate electrode G and the active region 12 are opposed to each other, the memory gate insulating film 6 of the antifuse memories 2a and 2b is formed.
- the semiconductor memory device 1 having such a configuration can be formed by a general semiconductor manufacturing process using a photolithography technique, a film forming technique such as oxidation or CVD (Chemical Vapor Deposition), an etching technique, and an ion implantation method. Therefore, the description is omitted here.
- a non-destructive bit voltage of 3 [V] is applied to the bit line BLb (hereinafter also referred to as a write non-selected bit line) to which only the anti-fuse memories 2b and 2d as the write non-selected memory are connected. obtain.
- a breakdown word voltage of 5 [V] is applied to the semiconductor memory device 1 to a word line WLb (hereinafter also referred to as a write selection word line) to which an antifuse memory 2c serving as a write selection memory is connected.
- a non-destructive word voltage of 0 [V] can be applied to a word line WLa (hereinafter also referred to as a write non-selected word line) to which only the antifuse memories 2a and 2b serving as write non-selected memories are connected.
- a breakdown word voltage of 5 [V] is applied from the word line WLb serving as the write selection word line to the P-type semiconductor region 8 of the rectifier element 3, and the write selection bit line A breakdown bit voltage of 0 [V] can be applied from the bit line BLa to the diffusion region 5 at one end of the memory capacitor 4.
- a breakdown word voltage is applied from the rectifying element 3 to the memory gate electrode G of the memory capacitor 4, and 0 [V] is applied from the bit line BLa to the diffusion region 5.
- the channel (not shown) of memory capacitor 4 is turned on, and the channel potential is the same as the potential of bit line BLa.
- the potential difference between the channel and the memory gate electrode G is 4.3 [V].
- the lower memory gate insulating film 6 is broken down, so that the memory gate electrode G and the diffusion region 5 become conductive with low resistance through the channel, and data can be written.
- the anti-fuse memory 2d in the other column to which data is not written although it is connected to the word line (write selection word line) WLb to which a breakdown word voltage of 5 [V] is applied one end of the memory capacitor 4 Since a non-destructive bit voltage of 3 [V] is applied to the diffusion region 5 in the memory via the bit line (write non-selection bit line) BLb, the voltage between the memory gate electrode G and the diffusion region 5 in the memory capacitor 4 The difference is as small as 1.3 [V] (considering the built-in potential 0.7 [V]).
- the memory gate insulating film 6 below the memory gate electrode G is not broken down in the memory capacitor 4, the memory gate insulating film 6 is not broken down and is in an insulated state. The state in which no data is written can be maintained.
- the memory gate insulating film 6 is dielectrically broken down.
- a non-destructive word voltage of 0 [V] is applied from the word line (write unselected word line) WLa to the memory gate electrode G via the rectifying element 3, so that the memory gate in the memory capacitor 4
- the voltage difference between the electrode G and the diffusion region 5 connected to the bit line BLb is as small as 3 [V].
- the antifuse memory 2b even if the memory gate insulating film 6 below the memory gate electrode G in the memory capacitor 4 is not broken down, the memory gate insulating film 6 is not broken down. The state in which no data is written can be maintained.
- the location where the breakdown of the memory gate insulating film 6 is broken is, for example, a location very close to the diffusion region 5 to which the bit line (write unselected bit line) BLb is connected, the potential of the bit line BLb is There is a possibility that the non-destructive bit voltage of 3 [V] applied to the diffusion region 5 may be applied to the memory gate electrode G because it cannot be blocked by the channel of the capacitor 4.
- the rectifying element 3 formed of a PN junction diode by the semiconductor junction structure by the N-type semiconductor region 7 and the P-type semiconductor region 8 is used as the memory gate of the memory capacitor 4.
- the rectifying element 3 has an N-type.
- a reverse bias voltage is applied from the semiconductor region 7 to the P-type semiconductor region 8, and voltage application from the memory gate electrode G to the word line WLa can be reliably blocked by the rectifying element 3.
- the non-destructive bit voltage of 3 [V] of the bit line BLb is transmitted to the word line WLa via the antifuse memory 2b.
- the voltage of 3 [V] applied to the word line WLa via the antifuse memory 2b is connected to the memory gate electrode G of another antifuse memory 2a sharing the word line WLa via the word line WLa. It will be transmitted to.
- the voltage difference between the memory gate electrode G and the diffusion region 5 in the memory capacitor 4 becomes 0 [V], so that the memory gate insulating film 6 is temporarily insulated. Even when the memory gate insulating film 6 is not destroyed, the memory gate insulating film 6 remains in an insulated state without being broken down, and a state in which no data is written can be maintained.
- data can be written only to a desired antifuse memory 2c among the antifuse memories 2a, 2b, 2c, and 2d arranged in a matrix.
- bit line BLa (hereinafter also referred to as a read selection memory) and the anti-fuse memories 2b and 2d serving as read non-select memories that do not read data are connected.
- the bit line BLb (hereinafter also referred to as “read unselected bit line”) is initially charged to a voltage of 1.2 [V].
- a read selection word voltage of 1.2 [V] is applied to the word line WLb (hereinafter also referred to as a read selection word line) to which the antifuse memory 2c, which is a read selection memory, is connected.
- a read unselected word voltage of 0 [V] is applied to a word line WLa (hereinafter also referred to as a read unselected word line) to which only the antifuse memories 2a and 2b are connected.
- a read selection bit voltage of 0 [V] is applied to the read selection bit line BLb.
- a read selection word voltage of 1.2 [V] is applied from the word line WLb to the P-type semiconductor region 8 of the rectifying element 3 and the memory capacitor 4 from the bit line BLa to the antifuse memory 2c as the read selection memory.
- a read selection bit voltage of 0 [V] can be applied to the diffusion region 5 at one end of the electrode.
- the anti-fuse memory 2c serving as a read selection memory has a read selection voltage of 1.2 [V] on the word line WLb when the memory gate insulating film 6 of the memory capacitor 4 is in a dielectric breakdown state and data is written.
- a forward bias voltage is applied from the P-type semiconductor region 8 to the N-type semiconductor region 7 by the rectifying element 3.
- the read selection word voltage of the word line WLb can be applied from the rectifier 3 to the bit line BLa via the memory capacitor 4.
- a voltage obtained by reducing the read selection word voltage of 1.2 [V] by the built-in potential in the antifuse memory (read selection memory) 2c can be applied to the bit line BLa.
- the read selection bit voltage of 0 [V] becomes 0.5 [V] by being electrically connected to the word line WLb via the antifuse memory 2c, and the voltage value can change.
- the antifuse memory 2c serving as a read selection memory
- the memory capacitor 4 causes the word line WLb and the bit line BLa to be Will be cut off.
- the state of 0 [V] can be maintained as it is without changing the read selection bit voltage of 0 [V].
- the semiconductor memory device 1 detects whether or not the read selection bit voltage applied to the bit line (read selection bit line) BLa has changed, whereby data is stored in the antifuse memory 2c serving as the read selection memory. It can be determined whether or not is written.
- a read unselected word voltage of 0 [V] is applied to the word line (read unselected word line) WLa. Therefore, even if the memory gate insulating film 6 of the memory capacitor 4 is broken down, it does not contribute to the voltage change of the bit line (read selection bit line) BLa.
- the read selection bit line BLa is shared. Even if the memory gate insulating film 6 of the memory capacitor 4 is broken down in the antifuse memory 2a, a reverse bias voltage is applied to the rectifying element 3 in the antifuse memory 2a. It is possible to prevent the read selection bit voltage from being blocked by the rectifying element 3 and applied to the word line (read unselected word line) WLa.
- a reverse bias voltage is applied to the rectifier element 3, so the word line (read unselected word line) Voltage application from WLb to bit line (read unselected bit line) BLb can be blocked by rectifier element 3.
- the voltage values of the word line (read selected word line) WLb and the bit line (read unselected bit line) BLd are the same even if the memory gate insulating film 6 is broken down. Therefore, the read selection word voltage of 1.2 [V] does not fluctuate, and the read operation of the other antifuse memory 2c is not affected.
- the semiconductor memory device 1 only the desired data of the antifuse memory 2c can be read out of the antifuse memories 2a, 2b, 2c, and 2d arranged in a matrix.
- the memory gate electrode G is provided on the well S2 via the memory gate insulating film 6, and the surface of the well S2 Between the memory capacitor 4 in which the bit line BLa is connected to the one diffusion region 5 formed through the bit line contact BC and the memory gate electrode G and the word line WLb, and the voltage from the word line WLb. Is applied to the memory gate electrode G via the word line contact WC, while the voltage application from the memory gate electrode G to the word line contact WC becomes a reverse bias voltage, and the memory gate electrode G to the word line contact WC. And a rectifying element 3 for cutting off the voltage application.
- the write breakdown word voltage applied to the write selection word line WLa is applied to the memory gate electrode G of the memory capacitor 4 via the rectifier element 3,
- the memory gate insulating film 6 of the memory capacitor 4 is caused to break down due to the voltage difference between the memory gate electrode G and the write selection bit line BLa.
- the anti-fuse memory 2b of the data non-write operation in which no data is written when a high non-destructive bit voltage is applied to the bit line BLb connected to the memory capacitor 4, for example, the memory gate insulation of the memory capacitor 4 is insulated. Even if the film 6 is broken down, a non-destructive word voltage of 0 [V] is applied to the write non-selected word line WLb, so that no channel is formed in the memory capacitor 4, and the write non-selected bit line BLb
- the memory capacitor 4 can block voltage application to the word line WLa.
- the dielectric breakdown of the memory gate insulating film 6 occurs at a location very close to the diffusion region 5 to which the write unselected bit line BLb is connected, and the write unselected bit line BLb Even if the non-destructive bit voltage is applied to the memory gate electrode G of the memory capacitor 4 from the write non-selected bit line BLb and the non-destructive bit voltage is applied to the rectifying element 3 Therefore, the rectifying element 3 can reliably block voltage application from the memory gate electrode G to the word line WLa.
- the first by not forming a channel in the memory capacitor 4 by applying a non-destructive word voltage of 0 [V] to the write unselected word line WLb. It is possible to provide a double shutoff mechanism of a shutoff mechanism and (ii) a second shutoff mechanism that shuts off the non-destructive bit voltage by setting the rectifying element 3 in a reverse bias state, thereby enabling normal data writing operation Therefore, it is possible to reliably prevent malfunction during data reading.
- the voltage application from the memory gate electrode G to the word line WLa is reversed by the voltage value applied to the memory gate electrode G and the word line WLa without using a conventional control circuit. Since a rectifying element 3 having a semiconductor junction structure that provides a bias voltage is provided and the voltage application from the memory gate electrode G to the word line WLa is cut off by the rectifying element 3, the conventional memory capacitor can be obtained.
- the switch transistor that selectively applies the voltage and the switch control circuit for causing the switch transistor to perform the on / off operation become unnecessary, and the size can be reduced accordingly.
- the antifuse memories 2a, 2b, 2c, and 2d are configured so that the P-type semiconductor region 8 and the N-type semiconductor region 7 of the rectifying element 3 are in the same layer as the memory gate electrode G of the memory capacitor 4, as shown in FIG.
- the P of the rectifying element 3 is formed in the manufacturing process for forming the memory gate electrode G using a general semiconductor manufacturing process for forming the memory gate electrode G of the memory capacitor 4 having a single layer structure.
- the P of the rectifying element 3 is formed.
- a type semiconductor region 8 and an N type semiconductor region 7 can also be formed.
- 2B shows, for example, a total of 16 antifuse memories 2a 1 , 2a 2 , 2a 3 , 2a 4 , 2a 5 , 2a 6 , 2a 7 , 2a 8 ,
- the configuration of the planar layout when 2a 9 , 2a 10 , 2a 11 , 2a 12 , 2a 13 , 2a 14 , 2a 15 , 2a 16 are arranged in 4 rows and 4 columns is shown.
- the antifuse memories 2a 1 , 2a 2 , 2a 3 , 2a 4 , 2a 5 , 2a 6 , 2a 7 , 2a 8 , 2a 9 , 2a 10 , 2a 11 , 2a 12 , 2a 13 , 2a 14 , 2a 15 , 2a 16 all have the same configuration, and each have a rectifying element 3 and a memory capacitor 4 as in FIGS. 2A and 2B described above. Since the word line contacts WC11, WC12, WC13, and WC14 all have the same configuration, the following description will be given focusing on the word line contact WC12, for example.
- the P-type semiconductor region 8 in which the word line contact WC12 is erected is formed in a rectangular shape and is shared by the four antifuse memories 2a 3 , 2a 4 , 2a 7 , 2a 8 adjacent to each other. Yes.
- each N-type semiconductor region 7 of the two antifuse memories 2a 3 and 2a 4 adjacent in the column direction is joined to one side
- Each N-type semiconductor region 7 of the two antifuse memories 2a 7 and 2a 8 adjacent in the direction is joined to the other side facing the one side.
- the rectifying element 3 of the PN junction diode is formed by joining the P-type semiconductor region 8 and the N-type semiconductor region 7.
- the word line contact WC12 is connected to each rectifying element 3 of the four antifuse memories 2a 3 , 2a 4 , 2a 7 , 2a 8 sharing the P-type semiconductor region 8 with a word line (not shown).
- the predetermined word voltage from can be applied uniformly.
- Each of the N-type semiconductor regions 7 of these four antifuse memories 2a 3 , 2a 4 , 2a 7 , 2a 8 extends in the row direction away from the P-type semiconductor region 8,
- the memory gate electrodes G bonded to each other are arranged in different active regions 12.
- a memory gate insulating film 6 is formed.
- the semiconductor memory device 1 has a total of nine bit line contacts BC11, BC12, BC13, BC14, BC15, BC16, BC17, BC18, BC19 arranged in 3 rows and 3 columns.
- Each bit line contact BC11, BC12, BC13, BC14, BC15, BC16, BC17, BC18, BC19 is arranged in a different active region 12, and corresponds to a predetermined bit voltage from a bit line (not shown). Can be applied to each active region 12 to be applied.
- bit line contact BC11, BC12, BC13, BC14, BC15, BC16, BC17, BC18, BC19 the active region 12 in which the bit line contact BC15 arranged in the central region is arranged.
- bit line contact BC15 arranged in the central region is shared by the four antifuse memories 2a 6 , 2a 7 , 2a 10 , 2a 11 adjacent to each other, and a predetermined bit voltage from the bit line is
- These four antifuse memories 2a 6 , 2a 7 , 2a 10 and 2a 11 can be applied uniformly.
- the antifuse memories 2a 6 and 2a 7 and the antifuse memories 2a 10 and 2a 11 are symmetrical with respect to the bit line contact BC15.
- the memory gate electrodes G of the two antifuse memories 2a 6 and 2a 7 adjacent in the column direction are arranged to face each other.
- Each memory gate insulating film 6 of the fuse memories 2a 6 and 2a 7 is formed.
- memory gate electrodes G of other antifuse memories 2a 10 and 2a 11 that are also adjacent in the column direction are arranged to face each other, and each of the antifuse memories 2a 10 and 2a 11 A memory gate insulating film 6 is formed.
- the four bit line contacts BC11, BC13, BC17, BC19 arranged at the corners in the planar layout of the semiconductor memory device 1 have corresponding one antifuse memories 2a 1 , 2a 4 , 2a 13 , Only 2a 16 is connected.
- applying each bit line contacts arranged in these corners BC11, BC13, BC17, the BC19, only bit voltage to each corresponding one one antifuse memory 2a, 2a 4, 2a 13, 2a 16 Can do.
- the bit line contact BC12 is arranged other than the corners. Only two antifuse memories 2a 2 and 2a 3 are connected.
- the other bit line contacts arranged in addition to the corners BC14, BC16, BC18 also, only the corresponding two anti-fuse memory 2a 5, 2a 9, 2a 8 , 2a 12, 2a 14, 2a 15 It is connected.
- the other bit line contacts BC12, BC14, BC16, BC18 arranged at the corners have two anti-fuse memories and are arranged in the central region.
- the number of antifuse memories to be shared is four. Therefore, the bit line contact BC15 can be reduced in size as compared with the case where one antifuse memory is provided for each bit line contact.
- a word line write non-write
- the first blocking mechanism by not forming a channel in the memory capacitor 4 and (ii) making the rectifying element 3 in a reverse bias state
- a double shutoff mechanism with a second shutoff mechanism that shuts off the non-destructive bit voltage can be provided, so that a normal data write operation can be executed, thereby reliably preventing malfunction during data reading.
- the four antifuse memories 2a 6 , 2a 7 , 2a 10 , and 2a 11 adjacent to each other share one bit line contact BC15 and, for example, 4 adjacent to each other Since one word line contact WC12 is shared by each of the antifuse memories 2a 3 , 2a 4 , 2a 7 , 2a 8 , the bit line contact and the word line contact are individually provided for each antifuse memory. As a whole, the apparatus can be reduced in size as compared with the case where it is provided.
- the semiconductor memory device 1 has bit line contacts BC11 in the first row among the bit line contacts BC11, BC12, BC13 in the first column. And bit line contact BC13 in the third row are connected to bit line BL1a in the first column, and the other two columns are connected to bit line contact BC12 in the second row between bit line contacts BC11 and BC13.
- the bit line BL2a of the eye is connected.
- the semiconductor memory device 1 uniformly applies a predetermined bit voltage to the two antifuse memories 2a 1 and 2a 4 having different P-type semiconductor regions 8 by, for example, the bit line BL1a in the first column.
- a predetermined bit voltage different from that of the bit line BL1a in the first column is applied to the two antifuse memories 2a 2 and 2a 3 having different P-type semiconductor regions 8 by the bit line BL2a in the second column. Can be applied.
- the bit line BL3a in the third column is connected to the bit line contact BC14 in the first row and the bit line contact BC16 in the third row
- the bit line BL4a in the fourth column is connected to the bit line contact BC15 in the second row between the bit line contacts BC14 and BC16.
- the semiconductor memory device 1 uses a predetermined bit for the four antifuse memories 2a 5 , 2a 9 , 2a 8 , 2a 12 having different P-type semiconductor regions 8 by, for example, the bit line BL3a in the third column.
- the voltage can be applied uniformly, and further, the fourth column bit line BL4a allows the third column for four antifuse memories 2a 6 , 2a 7 , 2a 10 , 2a 11 having different P-type semiconductor regions 8 respectively.
- a predetermined bit voltage different from that of the bit line BL3a can be applied.
- the bit line BL5a in the fifth column is connected to the bit line contact BC17 in the first row and the bit line contact BC19 in the third row.
- the bit line BL6a in the sixth column is connected to the bit line contact BC18 in the second row between the line contacts BC17 and BC19.
- the semiconductor memory device 1 uniformly applies a predetermined bit voltage to the two antifuse memories 2a 13 and 2a 16 having different P-type semiconductor regions 8 by, for example, the bit line BL5a in the fifth column.
- a predetermined bit voltage different from that of the fifth column bit line BL5a is applied to the two antifuse memories 2a 14 and 2a 15 having different P-type semiconductor regions 8 by the sixth column bit line BL6a. Can be applied.
- different word lines WL1a, WL2a, WL3a, WL4a are connected to the word line contacts WC11, WC12, WC13, WC14, and each word line WL1a, WL2a, WL3a, WL4a
- Different word voltages can be applied to the contacts WC11, WC12, WC13, and WC14.
- the word line WL1a in the first row is connected to the word line contact WC11 in the first row and the first column, and the four antifuse memories 2a 1 , 2 sharing the word line contact WC11,
- a predetermined word voltage can be applied uniformly to 2a 2 , 2a 5 and 2a 6 .
- the other word lines WL2a, WL3a, WL4a have four antifuse memories 2a 9 , 2a 10 , 2a 13 , 2a 14, 2a 3 ,
- a predetermined word voltage can be uniformly applied to 2a 4 , 2a 7 , 2a 8, 2a 11 , 2a 12 , 2a 15 , 2a 16 .
- Word lines WL1a, WL2a, WL3a, WL4a that can be electrically controlled independently are connected to the memories 2a 6 , 2a 7 , 2a 10 , 2a 11, and are respectively connected to the word lines WL1a, WL2a, WL3a, WL4a. Different word voltages can be applied.
- bit lines BL1a, BL2a, BL3a, BL4a which can be electrically controlled independently, and differ depending on each bit line BL1a, BL2a, BL3a, BL4a A bit voltage can be applied.
- the voltage applied to the bit lines BL1a, BL2a, BL3a, BL4a, BL5a, BL6a and the word lines WL1a, WL2a, WL3a, WL4a is appropriately adjusted, so that “(1 -2) Data writing operation "allows data to be written only to the antifuse memory 2a 1 at a predetermined position, for example, and the above-mentioned" (1-3) Data read operation ", for example, an antifuse at a predetermined position. Data in the memory 2a 1 can be read.
- the word line WL1a is connected to only one word line contact WC11.
- the first word line WL1a and the second word line WL2a are alternately connected to a plurality of word line contacts arranged in the row direction one after another. It becomes the composition.
- one word line WL1a connected to the word line contact WC11 in the first row and first column is also connected to the word line contact in the first row and third column, the word line contact in the first row and fifth column, etc.
- the other word line WL2a connected to the word line contact WC13 in the first row and the second column is also connected to the word line contact in the first row and the fourth column, the word line contact in the first row and the sixth column, etc. It becomes.
- a total of 16 antifuse memories 2a 1 , 2a 2 , 2a 3 , 2a 4 , 2a 5 , 2a 6 , 2a 7 , 2a 8 , 2a 9 , 2a 10 , 2a 11 , 2a 12 , 2a 13 , 2a 14 , 2a 15 , 2a 16 are arranged in 4 rows and 4 columns, and these antifuse memories 2a 1 , 2a 2 , 2a 3 , 2a 4 , 2a 5 , 2a 6 , 2a 7 , 2a 8 , 2a 9 , 2a 10 , 2a 11 , 2a 12 , 2a 13 , 2a 14 , 2a 15 , 2a 16 according to the arrangement position of bit line BL1a , BL2a, BL3a, BL4a, BL5a, BL6a and the semiconductor memory device
- a column of bit line contacts BC11, BC12, BC13 is provided on one end side, and a column of bit line contacts BC17, BC18, BC19 is provided on the other end side.
- one anti-fuse memory 2a 1 (2a 4 ) is connected to the bit line contact BC11 in the first row and the first column on one end side and the bit line contact BC13 in the third row and the first column on the one end side.
- two antifuse memories 2a 2 and 2a 3 are connected to the bit line contact BC12 in the second row and the first column on the same end side.
- bit line BL1a in the first column connected to the bit line contacts BC11 and BC13 on one end side is connected only to a total of two antifuse memories 2a 1 and 2a 4 via the bit line contacts BC11 and BC13. Will be.
- only the two antifuse memories 2a 2 and 2a 3 are connected to the bit line BL2a in the second column connected to the bit line contact BC12 on one end side via the bit line contact BC12.
- bit line BL5a in the fifth column connected to the bit line contacts BC17 and BC19 on the other end side also has only two antifuse memories 2a 13 and 2a 16 in total via the bit line contacts BC17 and BC19.
- only two anti-fuse memories 2a 14 and 2a 15 are connected to the bit line BL6a in the sixth column connected to the bit line contact BC18 on the other end side via the bit line contact BC18. Will be connected.
- bit lines BL1a, BL2a (BL5a, BL6a) provided for the column of bit line contacts BC11, BC12, BC13 (BC17, BC18, BC19) arranged at the end, the number of antifuse memories connected is 2 It becomes a piece.
- a total of four antifuse memories 2a 5 , 2a 9 , 2a 8 , 2a 12 are connected to the bit line BL3a arranged in the central area via the bit line contacts BC14, BC16, and the central area
- the four antifuse memories 2a 6 , 2a 7 , 2a 10 , and 2a 11 are connected to the bit line BL4a arranged at 1 through the bit line contact BC15.
- the bit line BL1a in the first column and the bit line BL5a in the fifth column are short-circuited.
- the number of anti-fuse memories that operate at the same bit voltage is four, and the bit line BL2a in the second column and the bit line BL6a in the sixth column are also shorted, and the number of anti-fuse memories that operate at the same bit voltage is four, It is desirable to match the number of antifuse memories connected to the bit lines BL3a and BL4a in the central region (in this case, four).
- a total of two antifuse memories 2a 1 and 2a 4 respectively connected to the bit line BL1a in the first column via the bit line contacts BC11 and BC13, and the bit line in the fifth column A total of four anti-fuse memories 2a 1 , 2a 4 , 2a 13 , 2a 16 are combined with a total of two anti-fuse memories 2a 13 , 2a 16 connected to BL5a via bit line contacts BC17, BC19, respectively. It is desirable to operate with the two bit lines BL1a in the first column and the bit line BL5a in the fifth column.
- two antifuse memories 2a 2 and 2a 3 connected to the bit line BL2a in the second column via the bit line contact BC12 and the bit line BL6a in the sixth column are connected via the bit line contact BC18 two anti-fuse memory 2a 14, 2a 15 and a total of four anti-fuse memory 2a 2 of the combined, 2a 3, 2a 14, 2a 15 also, the second column of the bit line BL2a and sixth column of bits It is desirable to operate with two lines BL6a.
- the anti-fuse memories 2a 1 , 2a 4 , 2a 13 , and 2a 16 are uniformly specified by two lines, that is, the bit line BL1a in the first column and the bit line BL5a in the fifth column.
- the third column four antifuse memories 2a 5 , 2a 9 , 2a 8 , 2a 12 (2a 6 , 2a 7 , 2a 10 , 2a 11 ) are operated in one configuration
- the capacitance is different from that of the bit line BL3a and the bit line BL4a in the fourth column. Therefore, in the semiconductor memory device 1, there may be a problem such as a decrease in reading speed during the data reading operation.
- the word line contacts WC1a and WC2a are connected to one end side.
- a row of word line contacts WC5a and WC6a is arranged on the other end side, and further, between the row of word line contacts WC1a and WC2a on one end side and the row of central word line contacts WC3a and WC4a.
- One bit line contact BC1a, BC2a, BC3a is provided on the other end, and the other bit line contact BC4a is arranged between the column of the word line contacts WC5a, WC6a on the other end side and the column of the central word line contacts WC3a, WC4a. , BC5a and BC6a are arranged.
- the first row bit line contact BC1a and the third row bit line contact BC3a are connected to the first row bit line BL1b
- the second row bit line contact BC2a is connected to the second row bit line BL2b.
- the two antifuse memories 2b 1 and 2b 5 connected to the bit line contact BC1a in the first row and the two antifuse memories connected to the bit line contact BC3a in the third row are used.
- a fuse memory 2b 4, a total of four anti-fuse memory 2b and 2b 8 1, 2b 5, 2b 4, 2b 8, can be connected to one bit line BL1b at the first column, thus, 1
- the four antifuse memories 2b 1 , 2b 5 , 2b 4 , 2b 8 can be operated by the bit line BL1b configured as described above.
- each antifuse memories 2b 2 , 2b 3 , 2b 6 , 2b 7 connected to the bit line contact BC2a in the second row are connected to one bit line in the second column.
- the four antifuse memories 2b 2 , 2b 3 , 2b 6 , 2b 7 can be operated by the bit line BLb having a single configuration.
- the third row bit line BL3b is connected to the first row bit line contact BC4a and the third row bit line contact BC6a
- the fourth column bit line BL4b is connected to the second row bit line contact BC5a.
- the two antifuse memories 2b 9 and 2b 13 connected to the bit line contact BC4a in the first row and the two antifuse memories connected to the bit line contact BC6a in the third row are used.
- fuses total of four antifuse memory 2b 12, 2b 16 memory 2b 9, 2b 13, 2b 12 , 2b 16, can be connected to one bit line BL3b at the third column, thus, 1
- the four antifuse memories 2b 9 , 2b 13 , 2b 12 , 2b 16 can be operated by the bit line BLb having this configuration.
- four antifuse memories 2b 10 , 2b 11 , 2b 14 , 2b 15 connected to the bit line contact BC5a in the second row are connected to one bit line in the fourth column.
- the four antifuse memories 2b 10 , 2b 11 , 2b 14 , and 2b 15 can be operated by the bit line BL4b having a single configuration.
- the semiconductor memory device 1a does not require connection between bit lines, and the bit lines BL1b, BL2b, BL3b, and BL4b can be configured as one, and all are the same. Since the capacity can be set, problems such as a decrease in reading speed can be prevented during the data reading operation.
- the word line contacts WC1a, WC3a, WC5a in the first row have the same word line WL1b as the word line contact WC1a in the first column and the word line contact WC5a in the third column.
- Another word line WL2b different from the word line WL1b can be connected to the word line contact WC3a in the second column.
- the same word line WL3b is connected to the word line contact WC2a in the first column and the word line contact WC6a in the third column in the row of the word line contacts WC2a, WC4a, WC6a in the second row, so that two words Another word line WL4b different from the word line WL3b can be connected to the line contact WC4a.
- each antifuse memory 2b 2 , 2b 3 , 2b 6 are respectively connected to the bit line contact BC2a in the second row and the first column and the bit line contact BC5a in the second row and the second column.
- 2b 7 (2b 10 , 2b 11 , 2b 14 , 2b 15 ) can be realized, and downsizing can be achieved in the same manner as in the above-described embodiment.
- four antifuse memories 2b 5 , 2b 6 , 2b 9 , 2b are connected to the word line contact WC3a in the first row and second column and the word line contact WC4a in the second row and second column, respectively.
- 10 (2b 7 , 2b 8 , 2b 11 , 2b 12 ) can be realized, and downsizing can be achieved in the same manner as in the above-described embodiment.
- the bit line contact BC2a The four antifuse memories 2b 2 , 2b 3 , 2b 6 , 2b 7 are connected to word lines WL1b, WL2b, WL3b, WL4b that can be electrically controlled independently, and each word line WL1b , WL2b, WL3b, WL4b can apply different word voltages.
- Bit lines BL1b, BL2b, BL3b, BL4b which can be electrically controlled independently, are connected to the antifuse memories 2b 5 , 2b 6 , 2b 9 , 2b 10 , and each bit line BL1b, BL2b, BL3b, BL4b Therefore, different bit voltages can be applied.
- the voltage applied to the bit lines BL1b, BL2b, BL3b, BL4b and the word lines WL1b, WL2b, WL3b, WL4b is appropriately adjusted, so that “(1-2) Data writing described above” is performed.
- data can be written only to the antifuse memory 2b 1 at a predetermined position by the “operation”, and data can be read from the antifuse memory 2b 1 at the predetermined position by the “(1-3) data read operation” described above. You can also.
- two antifuse memories 2b are provided for each bit line contact BC1a, BC4a (BC3a, BC6a) arranged in one direction (in this case, the row direction) arranged at the end.
- each antifuse memories 2b 2 , 2b 3 , 2b 6 , 2b 7 (2b 10 , 2b 11 , 2b) are connected to the remaining bit line contacts BC2a (BC5a) arranged in the central region. 14 , 2b 15 ) and four antifuse memories 2b 5 , 2b 6 , 2b 9 , 2b 10 (2b 7 , 2b 8 , 2b) connected to the word line contact WC3a (WC4a) arranged in the central region 11 , 2b 12 ).
- the bit line contacts BC1a to BC6a and the word line contacts WC1a to WC6a can be shared by two or more antifuse memories, the overall size of the device can be reduced.
- the same number of antifuse memories connected to the bit line BL1d (4 in this case) can be set to the same capacity, thus causing problems such as a decrease in read speed during the data read operation. Can be prevented.
- the first word line WL1b and the second column The word lines WL2b are alternately connected to a plurality of word line contacts arranged in the row direction.
- the word line WL1b connected to the word line contact WC1a in the first row and first column is connected to the word line contact in the first row and the third column, the word line contact in the first row and the fifth column, etc.
- the word line WL2b connected to the word line contact WC3a in the first row and the second column is connected to the word line contact in the first row and the fourth column, the word line contact in the first row and the sixth column, and the like.
- the bit line contacts BC1a, BC4a,... (BC3a, BC6a when the number of antifuse memories is increased to 16 or more, the bit line contacts BC1a, BC4a,... (BC3a, BC6a,.
- the bit line contact rows and the word line contact rows are alternately arranged sequentially from one end toward the column direction, and when the number of bit line contacts arranged in one row is n, they are arranged in one row.
- the number of word line contacts is (n + 1).
- the number of bit line contacts arranged in one row is two and the number of word line contacts arranged in one row is three.
- the antifuse memories 2c 1 , 2c 2 , 2c 3 , 2c 4 , 2c 5 , 2c 6 , 2c 7 , 2c 8 , 2c 9 , 2c 10 , 2c 11 , 2c 12 , 2c 13 , 2c 14 , 2c 15 , 2c 16 all have the same configuration, and each have a rectifying element 3 and a memory capacitor 4 as in FIGS. 2A and 2B described above. Further, since the word line contacts WC21, WC22, WC23, WC24, WC25, WC26, WC27, WC28 all have the same configuration, the following description will focus on the word line contact WC22, for example.
- the P-type semiconductor region 8 in which the word line contact WC22 is erected is formed in a rectangular shape, and is shared by two antifuse memories 2c 2 and 2c 6 adjacent in the row direction.
- the P-type semiconductor region 8 in which the word line contact WC22 is erected is joined to the N-type semiconductor region 7 of the anti-fuse memory 2c 2 on one side, and the anti-fuse memory 2c 2 is adjacent to the other adjacent in the row direction.
- the N-type semiconductor region 7 of the antifuse memory 2c 6 is joined to the other side facing the one side.
- the P-type semiconductor region 8 and the N-type semiconductor region 7 are joined to form the rectifying element 3 of a PN junction diode.
- the word line contact WC22 uniformly applies a predetermined word voltage from the word line to the rectifying elements 3 of the two antifuse memories 2c 2 and 2c 6 sharing the P-type semiconductor region 8. obtain.
- Each of the N-type semiconductor regions 7 of the two antifuse memories 2c 2 and 2c 6 extends in the row direction so as to be away from the P-type semiconductor region 8, and each of the memories bonded to the tip portion.
- Gate electrodes G are arranged in different active regions 22. Further, each memory gate electrode G, which is integrally formed on the tip portion of the N-type semiconductor region 7, each region where the active region 22 opposed, memory gate insulation film 6 of each anti-fuse memory 2c 2, 2c 6 Is formed.
- bit line contacts BC21, BC22, BC23, BC24 will be described below.
- the semiconductor memory device 21 has a total of four bit line contacts BC21, BC22, BC23, BC24 arranged in the row direction.
- Each bit line contact BC21, BC22, BC23, BC24 is arranged in a different active region 22, so that a predetermined bit voltage from a bit line (not shown) can be applied to the corresponding active region 22, respectively. Has been made.
- the semiconductor memory device 21 is arranged in a matrix between the active region 22 in which the bit line contact BC21 in the first column is arranged and the active region 22 in which the bit line contact BC22 in the second column is arranged.
- the eight antifuse memories 2c 1 , 2c 2 , 2c 3 , 2c 4 , 2c 5 , 2c 6 , 2c 7 and 2c 8 are formed.
- the eight antifuse memories 2c 9 , 2c 10 , 2c 11 , 2c 12 , 2c 13 , 2c are also connected between the active regions 22 of the bit line contact BC23 in the third column and the bit line contact BC24 in the fourth column.
- 14 , 2c 15 , 2c 16 can be arranged in a matrix.
- bit line contact BC22 since these four bit line contacts BC21, BC22, BC23, BC24 all have the same configuration, the following description will focus on the bit line contact BC22.
- the active region 22 in which the bit line contact BC22 is arranged has a rectangular shape extending in the column direction along the four antifuse memories 2c 5 , 2c 6 , 2c 7 , 2c 8 arranged in the column direction.
- the memory gate electrodes G of the four antifuse memories 2c 5 , 2c 6 , 2c 7 , 2c 8 arranged in the column direction are provided.
- bit line contact BC22 is connected to the four antifuse memories 2c 5 , 2c 6 , 2c 7 , 2c 8 connected to the different word line contacts WC21, WC22, WC23, WC24 and arranged in the column direction.
- a predetermined bit voltage from the bit line can be applied uniformly through the active region 22.
- 2c 12 , 2c 13 , 2c 14 , 2c 15 , 2c 16 similarly to the above-mentioned “(1-4) Operation and effect of the semiconductor memory device having the above configuration”, a conventional control circuit is not used.
- the voltage applied from the memory gate electrode G to the word line can be cut off by the rectifying element 3 according to the voltage value applied to the memory gate electrode G and the word line of the memory capacitor 4, and thus voltage application to the memory capacitor as in the prior art can be prevented.
- a switch transistor to be selectively performed and a switch control circuit for causing the switch transistor to perform an on / off operation become unnecessary, and the size can be reduced accordingly.
- a word line write non-write
- the first blocking mechanism by not forming a channel in the memory capacitor 4 and (ii) making the rectifying element 3 in a reverse bias state
- a double shutoff mechanism with a second shutoff mechanism that shuts off the non-destructive bit voltage can be provided, so that a normal data write operation can be executed, thereby reliably preventing malfunction during data reading.
- the four antifuse memories 2c 5 , 2c 6 , 2c 7 , 2c 8 arranged in the column direction share one bit line contact BC22 and, for example, in the row direction Since two adjacent antifuse memories 2c 2 and 2c 6 share one word line contact WC22, a bit line contact and a word line contact are individually provided for each antifuse memory. Compared to the case, the entire apparatus can be reduced in size.
- Corresponding part to FIG. 7 with the same reference numerals attached thereto is, for example, a total of 16 antifuse memories 2d 1 , 2d 2 , 2d 3 , 2d 4 , 2d 5 , 2d 6 , 2d 7 , 2d 8 , 2d 9 , 2d 10 ,
- the configuration of the planar layout of the semiconductor memory device 31 in which 2d 11 , 2d 12 , 2d 13 , 2d 14 , 2d 15 , 2d 16 are arranged in 4 rows and 4 columns is shown.
- the antifuse memories 2d 1 , 2d 2 , 2d 3 , 2d 4 , 2d 5 , 2d 6 , 2d 7 , 2d 8 , 2d 9 , 2d 10 , 2d 11 , 2d 12 , 2d 13 , 2d 14 , 2d 15 , 2d 16 all have the same configuration, and have a rectifying element 3 and a memory capacitor 4, respectively, as in FIGS. 2A and 2B described above. Further, since the word line contacts WC31, WC32, WC33, WC34 all have the same configuration, the following description will focus on the word line contact WC32, for example.
- the word line contact WC32 is arranged in the P-type semiconductor region 8b having a longitudinal direction extending in the row direction, and four antifuse memories arranged in the row direction along the P-type semiconductor region 8b. 2d 2 , 2d 6 , 2d 10 , 2d 14 may be shared. Actually, each of the N-type semiconductor regions 7 of the four antifuse memories 2d 2 , 2d 6 , 2d 10 , 2d 14 arranged in the row direction is on one side in the P-type semiconductor region 8b where the word line contact WC32 is erected. It is joined to.
- the word line contact WC32 makes a predetermined word from the word line to each rectifying element 3 of the four antifuse memories 2d 2 , 2d 6 , 2d 10 , 2d 14 sharing the P-type semiconductor region 8b.
- a voltage can be applied uniformly.
- Each of the four antifuse memories 2d 2 , 2d 6 , 2d 10 , 2d 14 has an N-type semiconductor region 7 extending in the column direction away from the P-type semiconductor region 8b.
- the memory gate electrodes G bonded to each other are arranged in different active regions 12.
- each memory gate electrode G integrally formed at the tip of the N-type semiconductor region 7 and each region where the active region 12 is opposed to each other have anti-fuse memories 2d 2 , 2d 6 , 2d 10 , 2d 14
- a memory gate insulating film 6 is formed.
- the P-type semiconductor region 8b in which the word line contact WC32 in the second row is erected and the P-type semiconductor region 8b in which the word line contact WC33 in the third row is erected are paralleled. It is arranged such that they between two P-type semiconductor region 8b, eight anti-fuse memory 2d 2, 2d 3, 2d 6 , 2d 7, 2d 10, 2d 11, 2d 14, 2d 15 It can be arranged in a matrix.
- the word line contact WC31 in the first row is erected with respect to the other side of the P-type semiconductor region 8b in which the word line contact WC32 in the second row is erected. Adjacent one side of the P-type semiconductor region 8b is parallel. On the other side of the P-type semiconductor region 8b where the word line contact WC31 in the first row is erected, each of the N-types of the four antifuse memories 2d 1 , 2d 5 , 2d 9 , 2d 13 arranged in the row direction The semiconductor region 7 is joined.
- each N type of the four antifuse memories 2d 4 , 2d 8 , 2d 12 , 2d 16 arranged in the row direction is joined.
- bit line contacts BC31, BC32, BC33, BC34, BC35, BC36, BC37, BC38, BC39, BC40, BC41, BC42 will be described below.
- a total of 12 bit line contacts BC31, BC32, BC33, BC34, BC35, BC36, BC37, BC38, BC39, BC40, BC41, BC42 are arranged in 3 rows and 4 columns in the semiconductor memory device 31.
- These bit line contacts BC31, BC32, BC33, BC34, BC35, BC36, BC37, BC38, BC39, BC40, BC41, BC42 are arranged in different active regions 12, respectively, and are supplied from a bit line (not shown). Can be applied to the corresponding active regions 12 respectively.
- bit line contact BC35 since all the bit line contacts BC35, BC36, BC37, BC38 arranged in the row direction arranged in the central region have the same configuration, the following description will be focused on, for example, the bit line contact BC35.
- the bit line contact BC35 in the active region 12 where the bit line contact BC35 is disposed, two antifuse memories 2d 2 and 2d 3 connected to different P-type semiconductor regions 8b and arranged in the column direction are provided.
- the bit line contact BC35 is shared by the two antifuse memories 2d 2 and 2d 3 , and a predetermined bit voltage from the bit line is applied to the two antifuse memories 2d 2 and 2d 3. Can be applied uniformly.
- this bit line active region 12 contacts BC35 is erected, mainly the bit line contact BC35, and anti-fuse memory 2d 2 and antifuse memory 2d 3 are arranged vertically symmetrically. Specifically, on one side of the active region 12 in which the bit line contact BC35 is erected, one memory gate electrode G of the anti-fuse memory 2d 2 is opposed, of the anti-fuse memory 2d 2 memory gate insulating film 6 Is formed. Also, the other side of the active region 12, likewise the memory gate electrode G of the other anti-fuse memory 2d 3 are opposed, the memory gate insulating film 6 of the antifuse memory 2d 3 is formed.
- bit line contacts BC31, BC32, BC33, BC34 BC39, BC40, BC41, BC42 arranged in the row direction at the ends, one corresponding antifuse memory 2d 1 , 2d 5 , 2d
- a bit voltage can be applied only to 9 , 2d 13 (2d 4 , 2d 8 , 2d 12 , 2d 16 ).
- a predetermined bit voltage can be applied only to 8 , 2d 12 , and 2d 16
- each of the bit line contacts BC35, BC36, BC37, BC38 arranged in the central region has two corresponding anti Since a predetermined bit voltage can be uniformly applied to the fuse memories 2d 2 , 2d 3 , 2d 6 , 2d 7 , 2d 10 , 2d 11 , 2d 14 , 2d 15 , the four antifuse memories 2d 2 , 2d 3, 2d 6, 2d 7 , 2d 10, 2d 11, 2d 14, 2d 15 with one bit line contact BC35, BC36, BC37, BC38 as a whole only device correspondingly to share may downsized.
- the voltage applied from the memory gate electrode G to the word line can be cut off by the rectifying element 3 according to the voltage value applied to the memory gate electrode G and the word line of the memory capacitor 4, and thus voltage application to the memory capacitor as in the prior art can be prevented.
- a switch transistor to be selectively performed and a switch control circuit for causing the switch transistor to perform an on / off operation become unnecessary, and the size can be reduced accordingly.
- a word line write non-write
- the first blocking mechanism by not forming a channel in the memory capacitor 4 and (ii) making the rectifying element 3 in a reverse bias state
- a double shutoff mechanism with a second shutoff mechanism that shuts off the non-destructive bit voltage can be provided, so that a normal data write operation can be executed, thereby reliably preventing malfunction during data reading.
- one word line contact WC32 is formed by four antifuse memories 2d 2 , 2d 6 , 2d 10 , 2d 14 arranged in one direction (in this case, the row direction).
- one bit line contact BC35 between two antifuse memories 2d 2 and 2d 3 adjacent to each other, a bit line contact and a word line contact are provided for each antifuse memory.
- the entire apparatus can be reduced in size.
- Antifuse memory having a rectifying element composed of an N-type MOS (Metal-Oxide-Semiconductor) transistor (6-1) Basic configuration
- the rectifying element a P-type semiconductor region and an N-type
- the diode-type rectifying element 3 having a semiconductor junction structure with a semiconductor region and applying a reverse bias voltage to cut off the voltage from the memory gate electrode
- the present invention is not limited thereto, for example, A MOS transistor type rectifying element that includes a semiconductor junction structure including a rectifying element gate electrode, a drain region, and a source region, and cuts off the voltage from the memory gate electrode of the memory capacitor by a reverse bias voltage may be applied.
- FIG. 8 shows a rectifying element 43 having a semiconductor junction structure of an N-type MOS transistor, and a memory capacitor 44 including a memory gate insulating film 6 that is broken down by a voltage difference between the word line WL and the bit line BL.
- An antifuse memory 42 having In this case, the bit line BL is connected to the diffusion region at one end of the memory capacitor 44, and the rectifying element 43 is connected to the memory gate electrode G.
- the rectifying element 43 has a configuration in which the rectifying element gate electrode G1 and the drain region are connected to the word line WL, and the source region is connected to the memory gate electrode G of the memory capacitor 44.
- the antifuse memory 42 has a configuration in which an element isolation layer IL made of an insulating member is formed on the surface of a P-type or N-type well S2 made of, for example, Si.
- a rectifying element 43 is formed in one region of the element isolation layer IL
- a memory capacitor 44 is formed in the other region of the element isolation layer IL.
- one diffusion region 5b is formed on the surface of the well S2 on one side of the element isolation layer IL so as to be adjacent to the element isolation layer IL, and the other is separated from the diffusion region 5b by a predetermined distance.
- the diffusion region 5c is formed on the surface.
- a rectifying device gate electrode G1 is formed on the surface of the well S2 between these diffusion regions 5b and 5c via a gate insulating film 48, and the other diffusion region 5c serving as a drain region, and the rectifying device gate electrode G1
- a word line contact WC is erected over the area.
- the word line contact WC is connected to the surface of the rectifying device gate electrode G1 from the silicide SC on the surface of the other diffusion region 5c serving as the drain region via the sidewall of the rectifying device gate electrode G1. It is formed over the silicide SC, and further has a configuration in which the word line WL is connected to the tip.
- the word line contact WC can apply the word voltage applied from the word line WL to both the diffusion region 5c serving as the drain region of the rectifying element 43 and the rectifying element gate electrode G1.
- a diffusion region 5a is formed on the surface at a predetermined interval from the element isolation layer IL, and a bit line contact BC having a bit line BL connected to the tip thereof However, it is erected on the silicide SC on the surface of the diffusion region 5a.
- a memory gate electrode G is formed on the surface between the element isolation layer IL and the diffusion region 5a via the memory gate insulating film 6.
- the memory gate electrode G is formed from a partial region on the element isolation layer IL to the memory gate insulating film 6, and has sidewalls SW on both side walls.
- a contact C1 is formed from one diffusion region 5b serving as a source region of the rectifying element 43 to the memory gate electrode G on the element isolation layer IL. Diffusion region 5b and memory gate electrode G of memory capacitor 44 are electrically connected by contact C1.
- the rectifying element 43 is configured such that the channel of the rectifying element 43 is in a non-conductive state and can block the voltage application from the memory gate electrode G to the word line WL. ing.
- the rectifying element gate electrode G1 of the rectifying element 43 and the memory gate electrode G of the memory capacitor 44 are on the same wiring layer (same layer). Further, the film thickness of the rectifying element gate electrode G1 and the memory gate electrode G of the memory capacitor 44 are formed to the same film thickness. As a result, the antifuse memory 42 is also made thinner as a whole.
- the bit line contact BC, the word line contact WC, the contact C1, the rectifying element gate electrode G1, the memory gate electrode G, the bit line BL, and the word line WL formed on the well S2 are covered with the interlayer insulating layer 9. Yes.
- FIG. 9B shows the configuration of the planar layout in the region where the antifuse memory 42 shown in FIG. 9A is provided.
- FIG. 9A is a side cross-sectional configuration taken along line BB ′ of FIG. 9B.
- the bit line contact BC is arranged in one active region 46a corresponding to the well S2
- the word line contact WC is arranged in another active region 46b corresponding to the well. Has been.
- a part of the memory gate electrode G is disposed to face the one active region 46a, and the memory gate insulating film 6 can be formed in a region facing the memory gate electrode G and the active region 46a.
- the rectifying element gate electrode G1 of the rectifying element 43 is formed in the other active region 46a, and the rectification of the rectifying element 43 in another antifuse memory (not shown) adjacent to the antifuse memory 42 is further formed.
- An element gate electrode G1 is also formed.
- the antifuse memory 42 having such a configuration can be formed by a general semiconductor manufacturing process using a photolithography technique, a film forming technique such as oxidation or CVD (Chemical Vapor Deposition), an etching technique, and an ion implantation method. Therefore, the description is omitted here.
- the word line WL to which the antifuse memory 42 to which data is written is connected is applied with a destructive word voltage of 5 [V], and the word line to which only the antifuse memory 42 to which no data is written is connected.
- a non-destructive word voltage of 0 [V] can be applied to WL. Note that 0 [V], which is the same as the breakdown bit voltage, can be applied to the well in which the antifuse memory 42 is formed.
- a destructive bit voltage of 0 [V] can be applied to the bit line BL, and a destructive word voltage of 5 [V] can be applied to the word line WL.
- the rectifying element 43 is turned on by the voltage difference between the rectifying element gate electrode G1 and the source region because the breakdown word voltage of 5 [V] is applied from the word line WL to the rectifying element gate electrode G1.
- a forward bias voltage is applied from the drain region to the source region, and a breakdown word voltage lowered by a threshold voltage (Vth) can be applied to the memory gate electrode G of the memory capacitor 44 from the drain region through the source region.
- Vth threshold voltage
- the memory capacitor 44 is turned on by the relationship between the breakdown word voltage of the memory gate electrode G and the breakdown bit voltage of the bit line BL, and a channel is formed, and the potential of the bit line BL can be induced in the channel.
- the memory capacitor 44 a voltage difference due to the breakdown bit voltage and the breakdown word voltage may occur between the memory gate electrode G and the channel.
- the memory gate insulating film 6 below the memory gate electrode G is broken down in the memory capacitor 44, and the memory gate electrode G and the diffusion region become conductive with a low resistance. The data can be written in
- a non-destructive bit voltage of 3 [V] is applied to the bit line BL and a non-destructive word voltage of 0 [V] is applied to the word line WL.
- the non-destructive bit voltage of 3 [V] of the bit line BL is applied to the source region of the rectifying element 43 via the memory gate electrode G of the memory capacitor 44. Can be applied.
- the rectifying element gate electrode G1 and the drain region of the rectifying element 43 become 0 [V].
- the rectifying element 43 is turned off (non-conducting state) (second blocking mechanism).
- the potential of the wiring between the memory gate electrode G of the memory capacitor 44 and the source region of the rectifying element 43 is not supplied from the outside, it can be considered as 0 [V] in the steady state and the same potential as the well potential. . Therefore, when a high non-destructive bit voltage (in this case, 3 [V]) is applied to the bit line BL connected to the memory capacitor 44, for example, the memory gate insulating film 6 of the memory capacitor 44 is dielectrically broken down.
- a high non-destructive bit voltage in this case, 3 [V]
- the non-destructive word voltage of 0 [V] is applied to the word line (write unselected word line) WL, a channel is not formed in the memory capacitor 44, and the bit line (write unselected bit line) )
- the voltage application from BL to the word line WL can also be interrupted by the memory capacitor 44 (first interrupting mechanism).
- the memory gate is located at a position very close to the diffusion region 5a to which the bit line (write unselected bit line) BL to which the non-destructive bit voltage (3 [V]) is applied is connected.
- the dielectric breakdown of the insulating film 6 occurs, so that the potential of the write non-selected bit line BL cannot be cut off by the channel of the memory capacitor 44, and a non-destructive bit voltage is applied from the write non-selected bit line BL to the memory gate electrode G of the memory capacitor 44.
- the rectifying element 43 connected to the memory gate electrode G is in an off state (non-conducting state)
- the rectifying element 43 reliably applies a voltage from the memory gate electrode G to the word line WL. Can be blocked.
- the non-destructive bit voltage of 3 [V] applied from the bit line BL is also applied to the channel off operation (first cutoff mechanism) of the memory capacitor 44 and the rectifier element 43 is turned off. It can be interrupted by the operation (second interrupting mechanism), and the non-destructive bit voltage can be reliably prevented from being transmitted to the word line WL.
- a destructive word voltage of 5 [V] is applied from the word line WL and a non-destructive bit voltage of 3 [V] is applied from the bit line BL.
- the breakdown word voltage reduced by the threshold voltage is applied from 43 to the memory gate electrode G of the memory capacitor 44, the voltage difference between the memory gate electrode G and the channel and diffusion region becomes small. Even when the gate insulating film 6 is not broken down, the memory gate insulating film 6 remains in an insulated state without being broken down, and a state where data is not written can be maintained.
- the desired data of the antifuse memory 42 is read by the “(1-3) data read operation” described above. Therefore, the description thereof is omitted here.
- the memory gate electrode G and the word line WL can be set according to the voltage values of the memory gate electrode G without using a conventional control circuit. Since the rectifying element 43 with a transistor configuration that cuts off the voltage application from the G to the word line WL by an off operation is provided, the switch transistor that selectively applies each voltage to the memory capacitor 44 and the switch transistor on / off A switch control circuit for performing the operation is unnecessary, and the size can be reduced accordingly.
- 9B shows, for example, a total of 16 antifuse memories 2e 1 , 2e 2 , 2e 3 , 2e 4 , 2e 5 , 2e 6 , 2e 7 , 2e 8 , 2e 9 , 2e 10 , 2e 11 , 2e 12 , 2e 13 , 2e 14 , 2e 15 , 2e 16 is shown in a 4 ⁇ 4 layout.
- the antifuse memories 2e 1 , 2e 2 , 2e 3 , 2e 4 , 2e 5 , 2e 6 , 2e 7 , 2e 8 , 2e 9 , 2e 10 , 2e 11 , 2e 12 , 2e 13 , 2e 14 , 2e 15 , 2e 16 all have the same configuration, and have a rectifying element 43 and a memory capacitor 44, respectively, as in FIGS. 9A and 9B described above.
- the word line contacts WC51, WC52, WC53, and WC54 all have the same configuration, the following description will be given focusing on the word line contact WC52, for example.
- the active region 46b erected by the word line contact WC52 is shared by four adjacent antifuse memories 2e 3 , 2e 4 , 2e 7 and 2e 8 .
- the active region 46b in which the word line contact WC52 is erected has two rectifying element gate electrodes G1 shared by the two antifuse memories 2e 3 and 2e 4 adjacent in the column direction and two adjacent in the column direction.
- a rectifying element gate electrode G1 shared by the individual antifuse memories 2e 7 and 2e 8 is formed.
- the word line contact WC52 is formed across the two rectifying element gate electrodes G1 and the active region 46b.
- the word line contact WC52 is, 2e 3 of these anti-fuse memory, 2e 4, 2e 7, and the rectifying element gate electrode G1 of 2e 8, these anti-fuse memory 2e 3, 2e 4, 2e 7 , 2e 8
- the bit voltage from the bit line can be uniformly applied to each drain region in the rectifying element 43 of the first rectifying element 43.
- the memory gate electrodes G of the memories 2e 3 , 2e 4 , 2e 7 and 2e 8 are connected.
- the semiconductor memory device 41 has a total of nine bit line contacts BC51, BC52, BC53, BC54, BC55, BC56, BC57, BC58, BC59 arranged in three rows and three columns.
- Each bit line contact BC51, BC52, BC53, BC54, BC55, BC56, BC57, BC58, BC59 is arranged in a different active region 46a, and corresponds to a predetermined bit voltage from a bit line (not shown).
- Each of the active regions 46a to be applied can be applied.
- bit line contact BC51, BC52, BC53, BC54, BC55, BC56, BC57, BC58, BC59 the active region 46a in which the bit line contact BC55 arranged in the central region is arranged.
- bit line contact BC55 disposed in the central region is shared by the four antifuse memories 2e 6 , 2e 7 , 2e 10 , 2e 11 adjacent to each other, and a predetermined bit voltage from the bit line is
- These four antifuse memories 2e 6 , 2e 7 , 2e 10 , 2e 11 can be applied uniformly.
- the antifuse memories 2e 6 and 2e 7 and the antifuse memories 2e 10 and 2e 11 are symmetric with respect to the bit line contact BC55.
- the memory gate electrodes G of the two antifuse memories 2e 6 and 2e 7 adjacent in the column direction are arranged to face each other.
- Each memory gate insulating film 6 of the fuse memories 2e 6 and 2e 7 is formed.
- the Other side of the active region 46a is also the memory gate electrode G is opposed other anti-fuse memory 2e 10, 2e 11 adjacent in the column direction, each of these anti-fuse memory 2e 10, 2e 11 A memory gate insulating film 6 is formed.
- bit line contacts BC51, BC52, BC53, BC54, BC56, BC57, BC58, BC59 arranged along the end in the planar layout of the semiconductor memory device 41.
- the bit line contacts BC52 arranged other than the corners Only two antifuse memories 2e 2 and 2e 3 are connected.
- the other bit line contacts BC54, BC56, BC58 arranged other than the corners also have only two corresponding antifuse memories 2e 5 , 2e 9 , 2e 8 , 2e 12 , 2e 14 , 2e 15 respectively. It is connected.
- the other bit line contacts BC52, BC54, BC56, BC58 arranged at the corners have two antifuse memories to be shared and are arranged in the central region.
- the bit line contact BC55 since the number of antifuse memories shared is four, the size can be reduced as compared with the case where one antifuse memory is provided for each bit line contact.
- a word line write unselected word line
- a non-destructive word voltage of 0 [V] By applying a non-destructive word voltage of 0 [V] to the first blocking mechanism by not forming a channel in the memory capacitor 44, and (ii) setting the non-destructive bit voltage by turning off the rectifying element 43.
- a double shut-off mechanism with the second shut-off mechanism for shutting off can be provided, whereby a normal data write operation can be executed, so that a malfunction during data reading can be reliably prevented.
- the four antifuse memories 2e 6 , 2e 7 , 2e 10 , 2e 11 adjacent to each other share one bit line contact BC55 and, for example, 4 adjacent to each other
- the bit line contact and the word line contact are individually provided for each antifuse memory.
- the apparatus can be reduced in size as compared with the case where it is provided.
- the semiconductor memory device 41 has bit line contacts BC51 in the first row among the bit line contacts BC51, BC52, BC53 in the first column. Are connected to the bit line contact BC53 in the first row and the bit line contact BC53 in the third row. The other two columns are connected to the bit line contact BC52 in the second row between the bit line contacts BC51 and BC53.
- the bit line BL2c of the eye is connected.
- the semiconductor memory device 41 uniformly applies a predetermined bit voltage to the two antifuse memories 2e 1 and 2e 4 having different active regions 46b of the rectifying element 43, for example, by the bit line BL1c in the first column.
- the second column bit line BL2c can be applied to the two antifuse memories 2e 2 and 2e 3 having different active regions 46b of the rectifying element 43, and different from the first column bit line BL1c. Can be applied.
- bit line BL3c in the third column is connected to the bit line contact BC54 in the first row and the bit line contact BC56 in the third row
- the bit line BL4c in the fourth column is connected to the bit line contact BC55 in the second row between the bit line contacts BC54 and BC56.
- the semiconductor memory device 41 is predetermined for the four antifuse memories 2e 5 , 2e 9 , 2e 8 , 2e 12 having different active regions 46b of the rectifying element 43, for example, by the bit line BL3c in the third column.
- bit line BL5c in the fifth column is connected to the bit line contact BC57 in the first row and the bit line contact BC59 in the third row.
- the bit line BL6c in the sixth column is connected to the bit line contact BC58 in the second row between the line contacts BC57 and BC59.
- the semiconductor memory device 41 uniformly applies a predetermined bit voltage to the two antifuse memories 2e 13 and 2e 16 having different active regions 46b of the rectifying element 43, for example, by the bit line BL5c in the fifth column.
- the six columns of bit lines BL6c can be applied to two antifuse memories 2e 14 and 2e 15 having different active regions 46b of the rectifying element 43, and different from the fifth column of bit lines BL5c. Can be applied.
- different word lines WL1c, WL2c, WL3c, WL4c are connected to the word line contacts WC51, WC52, WC53, WC54, and each word line WL1c, WL2c, WL3c, WL4c is connected to each word line.
- Different word voltages can be applied to the contacts WC51, WC52, WC53, and WC54.
- the word line WL1c in the first row is connected to the word line contact WC51 in the first row and the first column, and the four antifuse memories 2e 1 , 2 sharing the word line contact WC51,
- a predetermined word voltage can be uniformly applied to 2e 2 , 2e 5 and 2e 6 .
- word lines WL2c, WL3c, WL4c are respectively provided with four antifuse memories 2e 9 , 2e 10 , 2e 13 , 2e 14, 2e 3 , via corresponding word line contacts WC53, WC52, WC54.
- a predetermined word voltage can be uniformly applied to 2e 4 , 2e 7 , 2e 8, 2e 11 , 2e 12 , 2e 15 , 2e 16 .
- the word lines WL1c, WL2c, WL3c, WL4c that can be electrically controlled independently are connected to the antifuse memories 2e 6 , 2e 7 , 2e 10 , 2e 11 , and the respective word lines WL1c, WL2c, WL3c Therefore, different word voltages can be applied by WL4c.
- four antifuse memories connected to the word line contact WC52 2e 3 , 2e 4 , 2e 7 , 2e 8 are connected to bit lines BL1c, BL2c, BL3c, BL4c that can be electrically controlled independently, and are different for each bit line BL1c, BL2c, BL3c, BL4c.
- a bit voltage can be applied.
- the voltage applied to the bit lines BL1c, BL2c, BL3c, BL4c, BL5c, BL6c and the word lines WL1c, WL2c, WL3c, WL4c is adjusted as appropriate, so that “(6 the -2) data write operation ", for example, it is possible to write data only to the anti-fuse memory 2e 1 at a predetermined position, the above-described" (1-3) data read operation ", for example, the anti-fuse at a predetermined position Data in the memory 2e 1 can be read out.
- the word line WL1c is connected to only one word line contact WC51.
- the word line WL1c in the first column and the word line WL2c in the second column are sequentially connected alternately to a plurality of word line contacts arranged in the row direction. It becomes the composition.
- the word line WL1c connected to the word line contact WC51 in the first row and the first column is also connected to the word line contact in the first row and the third column, the word line contact in the first row and the fifth column, etc.
- the word line WL2c connected to the word line contact WC53 in the second row and the second column is connected to the word line contact in the first row and the fourth column, the word line contact in the first row and the sixth column, and the like.
- a total of 16 antifuse memories 2e 1 , 2e 2 , 2e 3 , 2e 4 , 2e 5 , 2e 6 , 2e 7 , 2e 8 , 2e 9 , 2e 10 , 2e 11 , 2e 12 , 2e 13 , 2e 14 , 2e 15 , 2e 16 are arranged in 4 rows and 4 columns, and these antifuse memories 2e 1 , 2e 2 , 2e 3 , 2e 4 , 2e 5 , 2e 6 , 2e 7 , 2e 8 , 2e 9 , 2e 10 , 2e 11 , 2e 12 , 2e 13 , 2e 14 , 2e 15 , 2e 16 , BL2c, BL3c, BL4c, BL5c, BL6c and the semiconductor memory device 41 in which the word lines WL1c,
- the column of bit line contacts BC51, BC52, BC53 is provided on one end side, and the column of bit line contacts BC57, BC58, BC59 is provided on the other end side.
- one antifuse memory 2e 1 (2e 4 ) is connected to the bit line contact BC51 in the first row and the first column on one end side and the bit line contact BC53 in the third row and the first column on the other end side.
- two antifuse memories 2e 2 and 2e 3 are connected to the bit line contact BC52 in the second row and the first column on the same end side.
- bit line BL1c in the first column connected to the bit line contacts BC51 and BC53 on one end side is connected only to a total of two antifuse memories 2e 1 and 2e 4 via the bit line contacts BC51 and BC53. Will be.
- the two antifuse memories 2e 2 and 2e 3 are connected to the bit line BL2c in the second column connected to the bit line contact BC52 on one end side via the bit line contact BC52.
- bit lines BL1c, BL2c (BL5c, BL6c) provided for the column of bit line contacts BC51, BC52, BC53 (BC57, BC58, BC59) arranged at the end, the number of antifuse memories connected is 2 It becomes a piece.
- a total of four antifuse memories 2e 5 , 2e 9 , 2e 8 , 2e 12 are connected to the bit line BL3c arranged in the central region via the bit line contacts BC54, BC56, and the central region
- the four antifuse memories 2e 6 , 2e 7 , 2e 10 , and 2e 11 are connected to the bit line BL4c arranged at 1 through the bit line contact BC55. Therefore, in the semiconductor memory device 41 shown in FIG. 11, in order to efficiently perform the control by the row address and the column address, for example, the bit line BL1a in the first column and the bit line BL5a in the fifth column are short-circuited.
- the number of anti-fuse memories that operate at the same bit voltage is four, and the bit line BL2a in the second column and the bit line BL6a in the sixth column are also shorted, and the number of anti-fuse memories that operate at the same bit voltage is four, It is desirable to match the number of antifuse memories connected to the bit lines BL3c and BL4c in the central region (in this case, four).
- a total of two antifuse memories 2e 1 and 2e 4 respectively connected to the bit line BL1c in the first column via the bit line contacts BC51 and BC53, and the bit line in the fifth column A total of four anti-fuse memories 2e 1 , 2e 4 , 2e 13 , 2e 16 are combined with a total of two anti-fuse memories 2e 13 and 2e 16 connected to BL5c via bit line contacts BC57 and BC59, respectively. It is desirable to operate with the two bit lines BL1c in the first column and the bit line BL5c in the fifth column.
- two antifuse memories 2a 2 and 2a 3 connected to the bit line BL2a in the second column via the bit line contact BC12 and the bit line BL6a in the sixth column are connected via the bit line contact BC18 two anti-fuse memory 2a 14, 2a 15 and a total of four anti-fuse memory 2a 2 of the combined, 2a 3, 2a 14, 2a 15 also, the second column of the bit line BL2a and sixth column of bits It is desirable to operate with two lines BL6a.
- bit lines BL1c in the first column and bit lines BL5c in the fifth column are uniformly specified for the antifuse memories 2e 1 , 2e 4 , 2e 13 , 2e 16 .
- four antifuse memories 2e 5 , 2e 9 , 2e 8 , 2e 12 (2e 6 , 2e 7 , 2e 10 , 2e 11 ) are operated in one configuration
- the capacitance is different from that of the bit line BL3c and the bit line BL4c in the fourth column. Therefore, in the semiconductor memory device 41, there is a possibility that problems such as a decrease in reading speed may occur during the data reading operation.
- a row of word line contacts WC55a and WC56a is arranged on the other end side, and further, between the row of word line contacts WC51a and WC52a on one end side and the row of central word line contacts WC53a and WC54a.
- One bit line contact BC51a, BC52a, BC53a is provided on the other end, and the other bit line contact BC54a is arranged between the column of the word line contacts WC55a, WC56a on the other end side and the column of the central word line contacts WC53a, WC54a.
- BC55a and BC56a are arranged.
- one of the bit line contacts BC51a, BC52a, BC53a between the column of the word line contacts WC51a, WC52a on one end side and the column of the central word line contacts WC53a, WC54a The first row bit line contact BC51a and the third row bit line contact BC53a are connected to the first column bit line BL1d, and the second row bit line contact BC52a is connected to the second column bit line BL2d. obtain.
- a fuse memory 2f 4 a total of four anti-fuse memory 2f and 2f 8 1, 2f 5, 2f 4, 2f 8, can be connected to one bit line BL1d in the first column, thus, 1
- the four antifuse memories 2f 1 , 2f 5 , 2f 4 , 2f 8 can be operated by the bit line BL1d having this configuration.
- bit line BL3d in the third column is connected to the bit line contact BC54a in the first row and the bit line contact BC56a in the third row
- bit line BL4d in the fourth column is connected to the bit line contact BC55a in the second row.
- bit line contact BC56a two anti-connected to the third line the bit line contact BC56a fuses total of four antifuse memory 2f 12, 2f 16 memory 2f 9, 2f 13, 2f 12 , 2f 16, it can be connected to one bit line BL3d in the third column, thus, 1
- the four antifuse memories 2f 9 , 2f 13 , 2f 12 , 2f 16 can be operated by the bit line BL3d having this configuration.
- 1 bit line that was connected to the second line of the bit line contact BC55a 4 pieces of anti-fuse memory 2f 10, 2f 11, 2f 14 , 2f 15, in the fourth column
- the four antifuse memories 2f 10 , 2f 11 , 2f 14 , 2f 15 can be operated by the bit line BL4d having one configuration.
- the semiconductor memory device 41a does not require connection between the bit lines, and the bit lines BL1d, BL2d, BL3d, and BL4d can all have one configuration, and all are the same. Since the capacity can be set, problems such as a decrease in reading speed can be prevented during the data reading operation.
- the word line contacts WC51a, WC53a, WC55a in the first row have the same word line WL1d as the word line contact WC51a in the first column and the word line contact WC55a in the third column.
- Another word line WL2d different from the word line WL1d can be connected to the word line contact WC53a in the second column.
- the same word line WL3d is connected to the word line contact WC52a in the first column and the word line contact WC56a in the third column in the row of the word line contacts WC52a, WC54a, and WC56a in the second row, so that the words in the two columns
- Another word line WL4d different from the word line WL3d can be connected to the line contact WC54a.
- a semiconductor memory device 41a for example, four antifuse memories 2f 2 , 2f 3 , 2f 6 are connected to the bit line contact BC52a in the second row and the first column and the bit line contact BC55a in the second row and the second column, respectively.
- 2f 7 (2f 10 , 2f 11 , 2f 14 , 2f 15 ) can be realized, and downsizing can be achieved in the same manner as in the above-described embodiment.
- four antifuse memories 2f 5 , 2f 6 , 2f 9 , 2f are respectively connected to the word line contact WC53a in the first row and the second column and the word line contact WC54a in the second row and the second column, respectively.
- 10 (2f 7 , 2f 8 , 2f 11 , 2f 12 ) can be realized, and downsizing can be achieved in the same manner as in the above-described embodiment.
- the bit line contact BC52a the bit line contact BC52a
- the four antifuse memories 2f 2 , 2f 3 , 2f 6 , 2f 7 are connected to word lines WL1d, WL2d, WL3d, WL4d, which can be electrically controlled independently, and each word line WL1d , WL2d, WL3d, WL4d can apply different word voltages.
- the four antifuse memories connected to the word line contact WC53a each electrically controlled independently be the bit line BL1d, BL2d, BL3d, BL4d are connected, each bit line BL1d, BL2d, BL3d, BL4d Therefore, different bit voltages can be applied.
- the voltage applied to the bit lines BL1d, BL2d, BL3d, BL4d and the word lines WL1d, WL2d, WL3d, WL4d is appropriately adjusted, so that “(6-2) Data writing described above” is performed.
- data can be written only to the antifuse memory 2f 1 at a predetermined position by the “operation”, and data can be read from the antifuse memory 2f 1 at the predetermined position by the “(1-3) data read operation” described above. You can also.
- each of the bit line contacts BC51a, BC54a (BC53a, BC56a) arranged in one direction (in this case, the row direction) arranged at the end has two antifuse memories 2f. 1 , 2f 5 , 2f 9 , 2f 13 (2f 4 , 2f 8 , 2f 12 , 2f 16 ) are connected, and each word line contact WC51a arranged in the other direction (in this case, the column direction) arranged at the end , WC52a (WC55a, WC56a) also was to connect the two anti-fuse memory 2f respectively 1, 2f 2, 2f 3, 2f 4 (2f 13, 2f 14, 2f 15, 2f 16).
- each antifuse memories 2f 2 , 2f 3 , 2f 6 , 2f 7 (2f 10 , 2f 11 , 2f) are connected to the remaining bit line contacts BC52a (BC55a) arranged in the central region. 14 , 2 f 15 ) and four antifuse memories 2 f 5 , 2 f 6 , 2 f 9 , 2 f 10 (2 f 7 , 2 f 8 , 2 f) are connected to the word line contact WC53 a (WC54 a) arranged in the central region. 11 , 2f 12 ).
- the bit line contacts BC51a to BC56a and the word line contacts WC51a to WC56a can be shared by two or more antifuse memories, so that the size of the entire device can be reduced.
- the same number of antifuse memories connected to the bit line BL1d (4 in this case) can be set to the same capacity, thus causing problems such as a decrease in read speed during the data read operation. Can be prevented.
- the first word line WL1d and the second column The word lines WL2d are sequentially connected alternately to a plurality of word line contacts arranged in the row direction.
- the word line WL1d connected to the word line contact WC51a in the first row and the first column is connected to the word line contact in the first row and the third column, the word line contact in the first row and the fifth column, etc.
- the word line WL2d connected to the word line contact WC53a in the first row and the second column is connected to the word line contact in the first row and the fourth column, the word line contact in the first row and the sixth column, and the like.
- the bit line contact rows and the word line contact rows are alternately arranged sequentially from one end toward the column direction, and when the number of bit line contacts arranged in one row is n, they are arranged in one row.
- the number of word line contacts is (n + 1).
- the number of bit line contacts arranged in one row is two and the number of word line contacts arranged in one row is three.
- the active region 46b of the rectifying element 43 and the memory gate electrode G of the memory capacitor 44 are separated, the active region
- the contact C1 is formed from 46b to the memory gate electrode G and the active region 46b and the memory gate electrode G are electrically connected by the contact C1
- FIG. 13 the memory gate electrode Ga may be formed on the active region 46b of the rectifying element, and the contact C1 may be formed from the active region 46b to the memory gate electrode Ga.
- a contact C2 is provided in the source region of the rectifying element 43 in the active region 46b while separating the active region 46b of the rectifying element 43 from the memory gate electrode G of the memory capacitor 44, and the memory gate electrode
- Another contact C3 may be provided for G, and these contacts may be connected to C2 and C3 by wiring 54.
- the antifuse memory 2g 1, 2g 2, 2g 3 , 2g 4, 2g 5, 2g 6, 2g 7, 2g 8, 2g 9, 2g 10, 2g 11, 2g 12, 2g 13 , 2g 14 , 2g 15 , 2g 16 all have the same configuration, and have a rectifying element 43 and a memory capacitor 44, respectively, as in FIGS. 9A and 9B described above.
- the word line contacts WC61, WC62, WC63, WC64, WC65, WC66, WC67, and WC68 all have the same configuration. Therefore, the following description will be given focusing on the word line contact WC62, for example.
- the active region 55a of the rectifying element 43 erected by the word line contact WC62 is formed in a rectangular shape and is shared by two antifuse memories 2g 2 and 2g 6 adjacent in the row direction.
- the active region 55a of the rectifying element 43 that the word line contacts WC62 is erected, a rectifying element gate electrode G2 of the anti-fuse memory 2 g 2, other antifuse adjacent to the anti-fuse memory 2 g 2 in the row direction a rectifying element gate electrode G2 in the memory 2 g 6 are formed.
- the word line contact WC62 A predetermined word voltage can be uniformly applied to the drain region and the rectifying element gate electrode G2 through the first and second electrodes.
- a contact C1 is erected across the source region of the rectifying element 43 in the active region 55a and the memory gate electrode Ga of the memory capacitor 44, and the contact C1 causes the rectifying element 2
- the source region 43 and the memory gate electrode Ga of the memory capacitor 44 are electrically connected.
- the word line contact WC62 has a drain region of the rectifying device 43 of another anti-fuse memory 2 g 6 adjacent to the anti-fuse memory 2 g 2 in the row direction, it is erected even across the rectifying element gate electrode G2 Yes.
- the word line contact WC62 can uniformly apply a predetermined word voltage from the word line to the two antifuse memories 2g 2 and 2g 6 .
- the memory gate electrodes Ga of these two antifuse memories 2g 2 and 2g 6 respectively extend in the row direction away from the active region 55a, and the tip portions are arranged in different active regions 55b, respectively. ing. Further, each memory gate electrode Ga, and the active region 55b in the regions facing the memory gate insulating film 6 of each anti-fuse memory 2 g 2, 2 g 6 are formed.
- bit line contacts BC61, BC62, BC63, BC64 will be described below.
- a total of four bit line contacts BC61, BC62, BC63, BC64 are arranged in the row direction in the semiconductor memory device 51.
- Each bit line contact BC61, BC62, BC63, BC64 is arranged in a different active region 55b so that a predetermined bit voltage from a bit line (not shown) can be applied to the corresponding active region 55b. Has been made.
- the semiconductor memory device 51 is arranged in a matrix between the active region 55b where the bit line contact BC61 in the first column is arranged and the active region 55b where the bit line contact BC62 in the second column is arranged.
- the eight antifuse memories 2g 1 , 2g 2 , 2g 3 , 2g 4 , 2g 5 , 2g 6 , 2g 7 and 2g 8 are formed.
- bit line contact BC61 of the first column In the active region 55b where the bit line contact BC61 of the first column is arranged, four antifuse memories 2g 1 , 2g 2 , 2g 3 , 2g 4 arranged in the column direction are formed, while the second column Anti-fuse memories 2g 5 , 2g 6 , 2g 7 , 2g 8 arranged in the column direction are formed in the active region 55b where the bit line contacts BC62 are arranged.
- eight antifuse memories 2g 9 , 2g 10 , 2g 11 , 2g 12 , 2g 13 , 2g are also provided between the active regions 55b of the bit line contact BC63 in the third column and the bit line contact BC64 in the fourth column.
- 14 , 2g 15 , 2g 16 can be arranged in a matrix.
- bit line contact BC62 since these four bit line contacts BC61, BC62, BC63, BC64 all have the same configuration, the following description will focus on the bit line contact BC62.
- the active region 55b in which the bit line contact BC62 is arranged has a rectangular shape extending in the column direction along the four antifuse memories 2g 5 , 2g 6 , 2g 7 , 2g 8 arranged in the column direction.
- the memory gate electrodes Ga of the four antifuse memories 2g 5 , 2g 6 , 2g 7 , 2g 8 arranged in the column direction are provided.
- bit line contact BC62 is connected to the different word line contacts WC61, WC62, WC63, WC64 and connected to the four antifuse memories 2g 5 , 2g 6 , 2g 7 , 2g 8 arranged in the column direction.
- a predetermined bit voltage from the bit line can be applied uniformly through the active region 55b.
- the voltage applied from the memory gate electrode Ga to the word line can be cut off by the rectifying element 43 according to the voltage value applied to the memory gate electrode Ga and the word line of the memory capacitor 44.
- a switch transistor to be selectively performed and a switch control circuit for causing the switch transistor to perform an on / off operation become unnecessary, and the size can be reduced accordingly.
- a word line write unselected word line
- a word line write unselected word line
- a non-destructive word voltage of 0 [V] By applying a non-destructive word voltage of 0 [V] to the first blocking mechanism by not forming a channel in the memory capacitor 44, and (ii) setting the non-destructive bit voltage by turning off the rectifying element 43.
- a double shut-off mechanism with the second shut-off mechanism for shutting off can be provided, whereby a normal data write operation can be executed, so that a malfunction during data reading can be reliably prevented.
- the four antifuse memories 2g 5 , 2g 6 , 2g 7 , 2g 8 arranged in the column direction share one bit line contact BC62 and, for example, in the row direction Since two adjacent antifuse memories 2g 2 and 2g 6 share one word line contact WC62, a bit line contact and a word line contact are individually provided for each antifuse memory. Compared to the case, the entire apparatus can be reduced in size.
- the active region 55a of the rectifying element 43 and the memory gate electrode Ga of the memory capacitor 44 are overlapped, and the source of the rectifying element 43 in these active regions 55a.
- the contact C1 is formed over the region and the memory gate electrode Ga
- the present invention is not limited to this, and the active region 55a of the rectifier element 43 and the memory capacitor 44 are not limited to this as shown in FIG.
- a contact C2 is provided in the source region of the rectifying element 43 in the active region 55a
- another contact C3 is provided in the memory gate electrode G, and these contacts are connected to each other by wiring 54. You may make it do.
- the active region 46a and the memory gate electrode G of the memory capacitor 44 are arranged apart from each other, and the active region 46b and the memory gate electrode G are connected by one contact C1.
- a connection configuration can also be used in the semiconductor memory device 51 shown in FIG.
- an active region 55a in the anti-fuse memory 2 g 6, is disposed away and the memory gate electrode Ga, can become was connected up these active regions 55a and the memory gate electrode Ga in one contact C1 .
- FIG. 16 A case where a plurality of antifuse memories arranged in the row direction share one word line contact, and two antifuse memories share one bit line contact.
- FIG. FIG. 16 with the same reference numerals attached thereto is, for example, a total of 16 antifuse memories 2h 1 , 2h 2 , 2h 3 , 2h 4 , 2h 5 , 2h 6 , 2h 7 , 2h 8 , 2h 9 , 2h 10 ,
- the antifuse memory 2h 1, 2h 2, 2h 3 , 2h 4, 2h 5, 2h 6, 2h 7, 2h 8, 2h 9, 2h 10, 2h 11, 2h 12, 2h 13 , 2h 14 , 2h 15 , 2h 16 all have the same configuration, and have a rectifying element 43 and a memory capacitor 44, respectively, as in FIGS. 9A and 9B described above. Since the word line contacts WC71, WC72, WC73, and WC74 all have the same configuration, the following description will be given focusing on the word line contact WC72, for example.
- the word line contact WC72 is arranged in the active region 63 having a longitudinal direction extending in the row direction, and the four antifuse memories 2h 2 and 2h arranged in the row direction along the active region 63 are arranged. 6 , 2h 10 , 2h 14 .
- are further formed rectifying element gate electrode G3 is shared by these four anti-fuse memory 2h 2, 2h 6, 2h 10 , 2h 14.
- the rectifying element gate electrode G3 has a longitudinal direction extending in the row direction so as to be parallel to the longitudinal direction of the active region 63 extending in the row direction, so that the active region 63 can be divided vertically.
- a source region can be formed in one region close to the memory capacitor 44, and a drain region can be formed in the other region, with the rectifying element gate electrode G3 as a boundary.
- a word line contact WC72 is erected across the drain region of the rectifying element 43 and the rectifying element gate electrode G3, and the drain region and the rectifying element gate electrode G3 are interposed via the word line contact WC72.
- a predetermined word voltage can be applied.
- the rectifying element gate electrode G3 erected by the word line contact WC72 and the drain region of the active region 63 are four antifuse memories 2h 2 , 2h 6 , 2h 10 arranged along the active region 63. , because it is shared 2h 14, the word line contact WC72, for these four anti-fuse memory 2h 2, 2h 6, 2h 10 , 2h 14, uniformly a predetermined word voltage from the word line Can be applied.
- each memory gate electrode Ga of these anti-fuse memory 2h 2, 2h 3 are the same activity are arranged in the region 62, of the active region 62 and facing each anti-fuse memory 2h 2 in each area of, 2h 3 A memory gate insulating film 6 is formed.
- the active region 63 provided with the word line contact WC72 in the second row and the active region 63 provided with the word line contact WC73 in the third row are arranged in parallel.
- 8 antifuse memories 2h 2 , 2h 3 , 2h 6 , 2h 7 , 2h 10 , 2h 11 , 2h 14 , 2h 15 are arranged in a matrix between the two active regions 63 that run in parallel. Can be placed.
- the word line contact WC71 in the first row rises with respect to the drain region of the rectifying element 43 in the active region 63 in which the word line contact WC72 in the second row is erected.
- the drain regions of the rectifying element 43 in the provided active region 63 are adjacent to each other so as to run side by side.
- the source region of the rectifying element 43 in the active region 63 erected by the word line contact WC71 in the first row is a memory gate of four antifuse memories 2h 1 , 2h 5 , 2h 9 and 2h 13 arranged in the row direction. It is connected to the electrode Ga via a contact C1.
- drain region of the rectifier element in the active region 63 in which the word line contact WC74 in the fourth row is also applied to the drain region of the rectifier element 43 in the active region 63 in which the word line contact WC73 in the third row is erected. Adjacent to run side by side.
- the source region of the rectifying element 43 in the active region 63 erected by the word line contact WC74 in the fourth row is a memory gate of four antifuse memories 2h 4 , 2h 8 , 2h 12 , 2h 16 arranged in the row direction It is connected to the electrode Ga via a contact C1.
- the semiconductor memory device 61 has a total of 12 bit line contacts BC71, BC72, BC73, BC74, BC75, BC76, BC77, BC78, BC79, BC80, BC81, BC82 arranged in 3 rows and 4 columns. Has been. These bit line contacts BC71, BC72, BC73, BC74, BC75, BC76, BC77, BC78, BC79, BC80, BC81, BC82 are arranged in different active regions 62, respectively, and are supplied from a bit line (not shown). Can be applied to the corresponding active regions 62 respectively.
- bit line contacts BC75, BC76, BC77, and BC78 arranged in the row direction arranged in the central region all have the same configuration, the following description will be focused on, for example, the bit line contact BC75.
- the bit line contact BC75 in the active region 62 where the bit line contact BC75 is disposed, two antifuse memories 2h 2 and 2h 3 connected to different word line contacts WC72 and WC73 and arranged in the column direction are provided.
- the bit line contact BC75 is shared by the two antifuse memories 2h 2 and 2h 3 , and a predetermined bit voltage from the bit line is applied to the two antifuse memories 2h 2 and 2h 3. Can be applied uniformly.
- the antifuse memory 2h 2 and the antifuse memory 2h 3 are arranged vertically symmetrically around the bit line contact BC75. Specifically, on one side of the active region 62 where the bit line contact BC75 is erected, the memory gate electrode Ga of one antifuse memory 2h 2 is disposed opposite to the memory gate insulating film 6 of the antifuse memory 2h 2. Is formed. Also, the other side of the active region 62, likewise the memory gate electrode Ga of other antifuse memory 2h 3 are opposed, the memory gate insulating film 6 of the antifuse memory 2h 3 is formed.
- bit line contacts BC71, BC72, BC73, BC74 BC79, BC80, BC81, BC82 arranged in the row direction at the ends, one corresponding antifuse memory 2h 1 , 2h 5 , 2h
- a bit voltage can be applied only to 9 , 2h 13 (2h 4 , 2h 8 , 2h 12 , 2h 16 ).
- a predetermined bit voltage can be applied only to 8 , 2h 12 and 2h 16
- each of the bit line contacts BC75, BC76, BC77 and BC78 arranged in the central region has two corresponding anti Since the predetermined bit voltage can be uniformly applied to the fuse memories 2h 2 , 2h 3 , 2h 6 , 2h 7 , 2h 10 , 2h 11 , 2h 14 , 2h 15 , the four antifuse memories 2h 2 , 2h 3, 2h 6, 2h 7 , 2h 10, 2h 11, 2h 14, 2h 15 by one of the bit line contact BC75, BC76, BC77, BC78 as a whole only device correspondingly to share may downsized.
- the voltage applied from the memory gate electrode Ga to the word line can be cut off by the rectifying element 43 according to the voltage value applied to the memory gate electrode Ga and the word line of the memory capacitor 44.
- a switch transistor to be selectively performed and a switch control circuit for causing the switch transistor to perform an on / off operation become unnecessary, and the size can be reduced accordingly.
- a word line write unselected word line
- a word line write unselected word line
- a non-destructive word voltage of 0 [V] By applying a non-destructive word voltage of 0 [V] to the first blocking mechanism by not forming a channel in the memory capacitor 44, and (ii) setting the non-destructive bit voltage by turning off the rectifying element 43.
- a double shut-off mechanism with the second shut-off mechanism for shutting off can be provided, whereby a normal data write operation can be executed, so that a malfunction during data reading can be reliably prevented.
- one word line contact WC72 is formed by four antifuse memories 2h 2 , 2h 6 , 2h 10 , 2h 14 arranged in one direction (in this case, the row direction).
- one bit line contact BC75 with two antifuse memories 2h 2 and 2h 3 adjacent to each other, a bit line contact and a word line contact are provided for each antifuse memory.
- the entire apparatus can be reduced in size.
- the active region 63 of the rectifying element 43 and the memory gate electrode Ga of the memory capacitor 44 are separated, and one contact provided in the active region 63. And another contact provided in the memory gate electrode Ga may be connected by wiring.
- the active region 63 of the rectifying element 43 is separated from the memory gate electrode Ga of the memory capacitor 44, and the active region 63 and the memory gate electrode Ga are connected by a single contact C1. It is good also as the structure made to do.
- the antifuse memory 72 includes a rectifying element 73 having a semiconductor junction structure of a P-type MOS transistor, and a memory gate insulating film 6 that is dielectrically broken by a voltage difference between the bit line BL and the memory gate electrode G. And a memory capacitor 44.
- the bit line BL is connected to the diffusion region at one end of the memory capacitor 44, and the rectifying element 73 is connected to the memory gate electrode G.
- the rectifying element gate electrode G1 and the drain region are connected to the memory gate electrode G of the memory capacitor 44, the well is connected to the well control terminal, and the source region is connected to the word line WL.
- the rectifying element 73 is turned off unless an on-voltage is applied from the word line WL, so that voltage application from the memory gate electrode G to the word line WL can be cut off.
- the anti-fuse memory 72 including the rectifying element 73 having such a MOS transistor structure can be formed with the cross-sectional configuration as shown in FIG. 9A, so that the rectifying element gate electrode G1 of the rectifying element 73 and the memory capacitor 44
- the memory gate electrode G can be formed in the same wiring layer (same layer), and the film thickness of the rectifying element gate electrode G1 and the memory gate electrode G of the memory capacitor 44 can be formed in the same film thickness.
- the antifuse memory 72 is also made thinner as a whole.
- a destruction word voltage of 5 [V] can be applied to the word line WL and a destruction bit voltage of 0 [V] can be applied to the bit line BL during a data write operation.
- the same 5 [V] as the breakdown word voltage can be applied from the well control terminal to the well in which the rectifying element 73 is formed. Assuming that the potential of the source region of the rectifying element 73 is about 0 [V], the rectifying element 73 is turned on, and if the threshold voltage is ⁇ 0.7 [V], the source region is charged to 4.3 [V]. Will be.
- a breakdown word voltage of 5 [V] is applied from the rectifying element 73 to the memory gate electrode G.
- the bit line is turned on because of 0 [V], and the channel potential is also 0V. .
- a large voltage difference due to the breakdown bit voltage and the breakdown word voltage can occur between the memory gate electrode G and the channel and diffusion region.
- the memory gate insulating film 6 below the memory gate electrode G is broken down in the memory capacitor 44, and the memory gate electrode G and the diffusion region become conductive with a low resistance. The data can be written in
- a non-destructive bit voltage of 3 [V] is applied to the bit line BL and a non-destructive word of 0 [V] is applied to the word line WL.
- the non-destructive bit voltage of 3 [V] of the bit line BL is The voltage can be applied to the source region of the rectifying element 73 via the memory gate electrode G of the memory capacitor 44.
- the antifuse memory 72 can prevent the non-destructive bit voltage of 3 [V] of the bit line BL from being applied to the word line WL.
- the potential of the line WL does not change.
- the anti-fuse memory 72 in which data is not written when a destructive word voltage of 5 [V] is applied to the word line WL and a non-destructive bit voltage of 3 [V] is applied to the bit line BL is a memory capacitor.
- the voltage difference between the memory gate electrode G and the diffusion region becomes small. Therefore, even if the memory gate insulating film 6 does not break down in the memory capacitor 44, the memory gate insulating film 6 is insulated without being broken down. It can remain in a state and no data can be written.
- the desired data in the antifuse memory 72 is read out by the “(1-3) data read operation” described above. Therefore, the description thereof is omitted here.
- the voltage application from the memory gate electrode G to the word line WL is performed by the voltage values of the memory gate electrode G and the word line WL without using a conventional control circuit. Since the rectifying element 73 having a transistor configuration that is cut off by the off operation is provided, a switch transistor that selectively applies each voltage to the memory capacitor 44 and a switch control circuit that causes the switch transistor to perform an on / off operation are provided. It becomes unnecessary, and the size can be reduced accordingly.
- an antifuse memory 72 “(7) When four antifuse memories share one word line contact and one bit line contact” or “(8) Configuration of bit line and word line planar layout according to another embodiment ",” (9) Two antifuse memories share one word line contact and have a plurality of antifuses arranged in the column direction " When sharing one bit line contact in memory ”,“ (10) Multiple antifuse memories arranged in the row direction share one word line contact, and two antifuse memories Since the same configuration as in the case of sharing one bit line contact can be realized, a single anti-fuse memory 72 can Because you can share Tsu bets line contacts and one word line contact may miniaturized as a whole system as compared with a case where each anti-fuse memory bit line contact and word line contacts each provided separately.
- a word line contact WCa1 that connects the word line WL and the diffusion region 5c that becomes the drain region of the rectifying element 43 is provided, and the word line contact WCa1 and the rectifying element gate electrode G1 are connected to another word line contact.
- WCa2 and wiring 83 may be connected.
- one contact C1 extends from the diffusion region 5b serving as the source region of the rectifying element 43 to the memory gate electrode G of the memory capacitor 44.
- a columnar contact C1a is provided in the diffusion region 5b serving as the source region of the rectifying element 43.
- the memory gate electrode G of the memory capacitor 44 may also be provided with another contact C1b, and these two contacts C1a and C1b may be connected by the wiring 84. Further, even with the antifuse memory 82 having the configuration shown in FIGS. 18A and 18B, the same effect as that of the above-described embodiment can be obtained.
- the present invention is not limited to this embodiment, and various modifications can be made within the scope of the gist of the present invention.
- the fuse memories may be appropriately combined.
- the antifuse memory 42 having the N-type transistor rectifying element 43 shown in FIG. 9 or the P-type transistor rectifying element 73 shown in FIG.
- the anti-fuse memory 72 having the above, the side cross-sectional configurations of FIGS. 9A and 18A, and the like may be appropriately combined.
- a row direction or a column direction may be applied as one direction. At this time, the other direction is a column direction or a row direction orthogonal to the one direction.
- FIG. 9B and FIG. 9B The connection configuration between the active regions (source regions) 46b and 55a of the rectifying element 43 and the memory gate electrodes Ga and G as shown in FIG. 15 may be used in appropriate combination with the various embodiments described above. Good.
- the number of antifuse memories may be various.
- the number of bit line contacts and word line contacts, the number of bit lines and word lines, and the number of bit lines and word lines are determined according to the number of antifuse memories.
- the number will also increase or decrease. This also increases or decreases the number of bit line contacts and word line contacts arranged in the central region in the semiconductor memory device.
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Abstract
Description
以下、本発明を実施するための形態について説明する。なお、説明は以下に示す順序とする。
<1.行列状にアンチヒューズメモリが設けられた本発明の半導体記憶装置の基本的概念>
1-1.基本構成
1-2.データの書き込み動作
1-3.データの読み出し動作
1-4.上記構成による半導体記憶装置の作用および効果
<2.4個のアンチヒューズメモリで、1個のワード線コンタクトおよび1個のビット線コンタクトを共有する場合について>
2-1.平面レイアウトの構成について
2-2.ビット線およびワード線の平面レイアウトの構成について
<3.他の実施の形態によるビット線およびワード線の平面レイアウトの構成について>
<4.2個のアンチヒューズメモリで、1個のワード線コンタクトを共有し、列方向に並んだ複数のアンチヒューズメモリで、1個のビット線コンタクトを共有する場合について>
<5.行方向に並んだ複数のアンチヒューズメモリで、1個のワード線コンタクトを共有し、2個のアンチヒューズメモリで、1個のビット線コンタクトを共有する場合について>
<6.N型MOS(Metal-Oxide-Semiconductor)トランジスタからなる整流素子を有したアンチヒューズメモリ>
6-1.基本構成
6-2.データの書き込み動作
6-3.上記構成による半導体記憶装置の作用および効果
<7.4個のアンチヒューズメモリで、1個のワード線コンタクトおよび1個のビット線コンタクトを共有する場合について>
7-1.平面レイアウトの構成について
7-2.ビット線およびワード線の平面レイアウトの構成について
<8.他の実施の形態によるビット線およびワード線の平面レイアウトの構成について>
<9.2個のアンチヒューズメモリで、1個のワード線コンタクトを共有し、列方向に並んだ複数のアンチヒューズメモリで、1個のビット線コンタクトを共有する場合について>
<10.行方向に並んだ複数のアンチヒューズメモリで、1個のワード線コンタクトを共有し、2個のアンチヒューズメモリで、1個のビット線コンタクトを共有する場合について>
<11.他の実施の形態>
11-1.P型MOSトランジスタからなる整流素子を有したアンチヒューズメモリ
11-2.トランジスタ構成の整流素子を備えたアンチヒューズメモリにおける他の実施の形態による構成
11-3.その他
(1-1)基本構成
図1において、1は本発明の半導体記憶装置を示し、例えば4個のアンチヒューズメモリ2a,2b,2c,2dが行列状に配置された構成を有する。この場合、半導体記憶装置1は、行方向に並ぶアンチヒューズメモリ2a,2b(2c,2d)にてワード線WLa(WLb)を共有しているとともに、列方向に並ぶアンチヒューズメモリ2a,2c(2b,2d)にてビット線BLa(BLb)を共有している。各アンチヒューズメモリ2a,2b,2c,2dは、全て同一構成を有していることから、ここでは例えば1行1列目のアンチヒューズメモリ2aに着目して説明する。実際上、アンチヒューズメモリ2aは、PN接合ダイオードの半導体接合構造を有した整流素子3と、メモリゲート電極Gおよびビット線BLaの電圧差により絶縁破壊されるメモリゲート絶縁膜6を備えたメモリキャパシタ4とから構成されている。
次に、かかる構成を有した半導体記憶装置1において、例えば2行1列目のアンチヒューズメモリ2cにのみデータを書き込む際のデータ書き込み動作について説明する。なお、ここでは、データを書き込むアンチヒューズメモリ2cを書き込み選択メモリとも呼び、データを書き込まないアンチヒューズメモリ2a,2b,2dを書き込み非選択メモリとも呼ぶ。この場合、図1に示すように、半導体記憶装置1には、書き込み選択メモリとなるアンチヒューズメモリ2cが接続されたビット線BLa(以下、書き込み選択ビット線とも呼ぶ)に0[V]の破壊ビット電圧が印加され、書き込み非選択メモリとなるアンチヒューズメモリ2b,2dのみが接続されたビット線BLb(以下、書き込み非選択ビット線とも呼ぶ)に3[V]の非破壊ビット電圧が印加され得る。
次に、図1に示す半導体記憶装置1において、例えば2行1列目のアンチヒューズメモリ2cのデータを読み出す場合について説明する。この場合、読み出し選択メモリとなるアンチヒューズメモリ2cが接続されたビット線BLa(以下、読み出し選択ビット線とも呼ぶ)と、データを読み出さない読み出し非選択メモリとなるアンチヒューズメモリ2b,2dのみが接続されたビット線BLb(以下、読み出し非選択ビット線とも呼ぶ)は、初めに1.2[V]の電圧に充電される。この際、読み出し選択メモリたるアンチヒューズメモリ2cが接続されたワード線WLb(以下、読み出し選択ワード線とも呼ぶ)には、1.2[V]の読み出し選択ワード電圧が印加されるとともに、読み出し非選択メモリとなるアンチヒューズメモリ2a,2bのみが接続されたワード線WLa(以下、読み出し非選択ワード線とも呼ぶ)には、0[V]の読み出し非選択ワード電圧が印加される。
以上の構成において、例えばアンチヒューズメモリ2cでは、ウエルS2上にメモリゲート絶縁膜6を介してメモリゲート電極Gが設けられ、ウエルS2表面に形成された一方の拡散領域5にビット線コンタクトBCを介してビット線BLaが接続されたメモリキャパシタ4と、メモリゲート電極Gとワード線WLbとの間に設けられ、ワード線WLbからの電圧がワード線コンタクトWCを経由してメモリゲート電極Gへ印加される一方、メモリゲート電極Gからワード線コンタクトWCへの電圧印加が逆方向バイアスの電圧となり、メモリゲート電極Gからワード線コンタクトWCへの電圧印加を遮断する整流素子3とを設けるようにした。
(2-1)平面レイアウトの構成について
次に上述したアンチヒューズメモリが行列状に配置された半導体記憶装置1の平面レイアウトの構成について説明する。図2Bとの対応部分に同一符号を付して示す図3は、例えば合計16個のアンチヒューズメモリ2a1,2a2,2a3,2a4,2a5,2a6,2a7,2a8,2a9,2a10,2a11,2a12,2a13,2a14,2a15,2a16を4行4列に配置したときの平面レイアウトの構成を示している。この場合、半導体記憶装置1において、アンチヒューズメモリ2a1,2a2,2a3,2a4,2a5,2a6,2a7,2a8,2a9,2a10,2a11,2a12,2a13,2a14,2a15,2a16は全て同一構成を有しており、上述した図2Aおよび図2Bと同様に、それぞれ整流素子3とメモリキャパシタ4とを有している。また、ワード線コンタクトWC11,WC12,WC13,WC14についても全て同一構成でなることから、ここでは、例えばワード線コンタクトWC12に着目して以下説明する。
次に、図3に示した半導体記憶装置1におけるビット線およびワード線の平面レイアウトについて以下説明する。図3との対応部分に同一符号を付して示す図4のように、半導体記憶装置1には、1列目のビット線コンタクトBC11,BC12,BC13のうち、1行目のビット線コンタクトBC11と3行目のビット線コンタクトBC13とに対して1列目のビット線BL1aが接続されており、これらビット線コンタクトBC11,BC13間の2行目のビット線コンタクトBC12に対して他の2列目のビット線BL2aが接続されている。これにより、半導体記憶装置1は、例えば1列目のビット線BL1aによって、P型半導体領域8がそれぞれ異なる2個のアンチヒューズメモリ2a1,2a4に対して所定のビット電圧を一律に印加し得、さらに2列目のビット線BL2aによって、P型半導体領域8がそれぞれ異なる2個のアンチヒューズメモリ2a2,2a3に対して、1列目のビット線BL1aとは異なる所定のビット電圧を印加し得る。
図4では、一例として、合計16個のアンチヒューズメモリ2a1,2a2,2a3,2a4,2a5,2a6,2a7,2a8,2a9,2a10,2a11,2a12,2a13,2a14,2a15,2a16を4行4列に配置し、これらアンチヒューズメモリ2a1,2a2,2a3,2a4,2a5,2a6,2a7,2a8,2a9,2a10,2a11,2a12,2a13,2a14,2a15,2a16の配置位置に合わせてビット線BL1a,BL2a,BL3a,BL4a,BL5a,BL6aおよびワード線WL1a,WL2a,WL3a,WL4aを配置させた半導体記憶装置1について示した。
図3との対応部分に同一符号を付して示す図6は、例えば合計16個のアンチヒューズメモリ2c1,2c2,2c3,2c4,2c5,2c6,2c7,2c8,2c9,2c10,2c11,2c12,2c13,2c14,2c15,2c16を4行4列に配置した半導体記憶装置21の平面レイアウトの構成を示している。この場合、半導体記憶装置21において、アンチヒューズメモリ2c1,2c2,2c3,2c4,2c5,2c6,2c7,2c8,2c9,2c10,2c11,2c12,2c13,2c14,2c15,2c16は全て同一構成を有しており、上述した図2Aおよび図2Bと同様に、それぞれ整流素子3とメモリキャパシタ4とを有している。また、ワード線コンタクトWC21,WC22,WC23,WC24,WC25,WC26,WC27,WC28についても全て同一構成でなることから、ここでは、例えばワード線コンタクトWC22に着目して以下説明する。
図3との対応部分に同一符号を付して示す図7は、例えば合計16個のアンチヒューズメモリ2d1,2d2,2d3,2d4,2d5,2d6,2d7,2d8,2d9,2d10,2d11,2d12,2d13,2d14,2d15,2d16を4行4列に配置した半導体記憶装置31の平面レイアウトの構成を示している。この場合、半導体記憶装置31において、アンチヒューズメモリ2d1,2d2,2d3,2d4,2d5,2d6,2d7,2d8,2d9,2d10,2d11,2d12,2d13,2d14,2d15,2d16は全て同一構成を有しており、上述した図2Aおよび図2Bと同様に、それぞれ整流素子3とメモリキャパシタ4とを有している。また、ワード線コンタクトWC31,WC32,WC33,WC34についても全て同一構成でなることから、ここでは、例えばワード線コンタクトWC32に着目して以下説明する。
(6-1)基本構成
上述した実施の形態においては、整流素子として、P型半導体領域とN型半導体領域とによる半導体接合構造を備え、逆方向バイアスの電圧によりメモリゲート電極からの電圧を遮断するダイオード型の整流素子3を適用する場合について述べたが、本発明はこれに限らず、例えば、整流素子ゲート電極とドレイン領域とソース領域とによる半導体接合構造を備え、逆方向バイアスの電圧により、メモリキャパシタのメモリゲート電極からの電圧を遮断するMOSトランジスタ型の整流素子を適用してもよい。
ここで、行列状に並んだアンチヒューズメモリ42のうち、所定のアンチヒューズメモリ42にだけデータを書き込む場合には、図1に示した半導体記憶装置1と同様に、データを書き込むアンチヒューズメモリ42が接続されたビット線BLには0[V]の破壊ビット電圧が印加され、データを書き込まないアンチヒューズメモリ42のみが接続されたビット線BLには3[V]の非破壊ビット電圧が印加され得る。
以上の構成において、データを書き込まないアンチヒューズメモリ42でも、図2において上述したアンチヒューズメモリ2a,2bと同様に、メモリキャパシタ44に接続されたビット線BLに高電圧の非破壊ビット電圧が印加された際、例えばメモリキャパシタ44のメモリゲート絶縁膜6が絶縁破壊されていても、整流素子43のチャネルをオフ状態(非導通状態)とさせることで、メモリキャパシタ44のメモリゲート電極Gからワード線WLへの非破壊ビット電圧の印加を遮断するようにした。
(7-1)平面レイアウトの構成について
次に上述したアンチヒューズメモリ42が行列状に配置された半導体記憶装置の平面レイアウトの構成について説明する。図9Bとの対応部分に同一符号を付して示す図10は、例えば合計16個のアンチヒューズメモリ2e1,2e2,2e3,2e4,2e5,2e6,2e7,2e8,2e9,2e10,2e11,2e12,2e13,2e14,2e15,2e16を4行4列に配置したときの平面レイアウトの構成を示している。この場合、半導体記憶装置41において、アンチヒューズメモリ2e1,2e2,2e3,2e4,2e5,2e6,2e7,2e8,2e9,2e10,2e11,2e12,2e13,2e14,2e15,2e16は全て同一構成を有しており、上述した図9Aおよび図9Bと同様に、それぞれ整流素子43とメモリキャパシタ44とを有している。また、ワード線コンタクトWC51,WC52,WC53,WC54についても全て同一構成でなることから、ここでは、例えばワード線コンタクトWC52に着目して以下説明する。
次に、図10に示した半導体記憶装置41におけるビット線およびワード線の平面レイアウトについて以下説明する。図10との対応部分に同一符号を付して示す図11のように、半導体記憶装置41には、1列目のビット線コンタクトBC51,BC52,BC53のうち、1行目のビット線コンタクトBC51と3行目のビット線コンタクトBC53とに対して1列目のビット線BL1cが接続されており、これらビット線コンタクトBC51,BC53間の2行目のビット線コンタクトBC52に対して他の2列目のビット線BL2cが接続されている。これにより、半導体記憶装置41は、例えば1列目のビット線BL1cによって、整流素子43の活性領域46bがそれぞれ異なる2個のアンチヒューズメモリ2e1,2e4に対して所定のビット電圧を一律に印加し得、さらに2列目のビット線BL2cによって、整流素子43の活性領域46bがそれぞれ異なる2個のアンチヒューズメモリ2e2,2e3に対して、1列目のビット線BL1cとは異なる所定のビット電圧を印加し得る。
図11では、一例として、合計16個のアンチヒューズメモリ2e1,2e2,2e3,2e4,2e5,2e6,2e7,2e8,2e9,2e10,2e11,2e12,2e13,2e14,2e15,2e16を4行4列に配置し、これらアンチヒューズメモリ2e1,2e2,2e3,2e4,2e5,2e6,2e7,2e8,2e9,2e10,2e11,2e12,2e13,2e14,2e15,2e16の配置位置に合わせてビット線BL1c,BL2c,BL3c,BL4c,BL5c,BL6cおよびワード線WL1c,WL2c,WL3c,WL4cを配置させた半導体記憶装置41について示した。
図10との対応部分に同一符号を付して示す図14は、例えば合計16個のアンチヒューズメモリ2g1,2g2,2g3,2g4,2g5,2g6,2g7,2g8,2g9,2g10,2g11,2g12,2g13,2g14,2g15,2g16を4行4列に配置した半導体記憶装置51の平面レイアウトの構成を示している。この場合、半導体記憶装置51において、アンチヒューズメモリ2g1,2g2,2g3,2g4,2g5,2g6,2g7,2g8,2g9,2g10,2g11,2g12,2g13,2g14,2g15,2g16は全て同一構成を有しており、上述した図9Aおよび図9Bと同様に、それぞれ整流素子43とメモリキャパシタ44とを有している。また、ワード線コンタクトWC61,WC62,WC63,WC64,WC65,WC66,WC67,WC68についても全て同一構成でなることから、ここでは、例えばワード線コンタクトWC62に着目して以下説明する。
図10との対応部分に同一符号を付して示す図16は、例えば合計16個のアンチヒューズメモリ2h1,2h2,2h3,2h4,2h5,2h6,2h7,2h8,2h9,2h10,2h11,2h12,2h13,2h14,2h15,2h16を4行4列に配置した半導体記憶装置61の平面レイアウトの構成を示している。この場合、半導体記憶装置61において、アンチヒューズメモリ2h1,2h2,2h3,2h4,2h5,2h6,2h7,2h8,2h9,2h10,2h11,2h12,2h13,2h14,2h15,2h16は全て同一構成を有しており、上述した図9Aおよび図9Bと同様に、それぞれ整流素子43とメモリキャパシタ44とを有している。また、ワード線コンタクトWC71,WC72,WC73,WC74についても全て同一構成でなることから、ここでは、例えばワード線コンタクトWC72に着目して以下説明する。
(11-1)P型MOSトランジスタからなる整流素子を有したアンチヒューズメモリ
上述した「(6)N型MOS(Metal-Oxide-Semiconductor)トランジスタからなる整流素子を有したアンチヒューズメモリ」においては、N型MOSトランジスタでなる整流素子43を設けたアンチヒューズメモリ42について述べたが、本発明はこれに限らず、図8との対応部分に同一符号を付して示す図17のように、P型MOSトランジスタでなる整流素子73を設けたアンチヒューズメモリ72を適用してもよい。この場合、アンチヒューズメモリ72は、P型MOSトランジスタの半導体接合構造を有した整流素子73と、ビット線BLおよびメモリゲート電極G間の電圧差により絶縁破壊されるメモリゲート絶縁膜6を備えたメモリキャパシタ44とを備える。
なお、上述した実施の形態においては、図9Aおよび図9Bに示したように、整流素子43のドレイン領域となる拡散領域5cから、整流素子ゲート電極G1に亘って1個のワード線コンタクトWCが立設している場合について述べたが、本発明はこれに限らず、図9Aとの対応部分に同一符号を付して示す図18Aや、図9Bとの同一部分に同一符号を付して示す図18B(なお、図18Aは図18BのC-C´部分での側断面構成を示す)のように、ワード線WLと、整流素子43のドレイン領域となる拡散領域5cとを接続するワード線コンタクトWCa1を設け、さらに当該ワード線コンタクトWCa1および整流素子ゲート電極G1を別のワード線コンタクトWCa2と配線83とで接続させるようにしてもよい。
なお、本発明は、本実施形態に限定されるものではなく、本発明の要旨の範囲内で種々の変形実施が可能であり、例えば上述した各実施の形態に示すアンチヒューズメモリについては、適宜組み合わせるようにしてもよい。また、他の実施の形態として、上述した各実施の形態に、図9に示したN型トランジスタの整流素子43を有したアンチヒューズメモリ42や、図17に示したP型トランジスタの整流素子73を備えたアンチヒューズメモリ72、図9Aおよび図18Aの側断面構成等を適宜組み合わせるようにしてもよい。さらに、各実施の形態においては、一方向として、行方向または列方向を適用してもよく、このとき、他方向は、一方向と直交する列方向または行方向となる。
2a,2b,2c,2d,2a1…2a16,2b1…2b16,2c1…2c16,2d1…2d16,2e1…2e16,2f1…2f16,2g1…2g16,2h1…2h16,42,72,82 アンチヒューズメモリ
3,43 整流素子
4,44 メモリキャパシタ
G,Ga メモリゲート電極
6 メモリゲート絶縁膜
S2 ウエル
BC,BC11…BC19,BC1a…BC6a,BC21…BC24,BC31…BC42,BC51…BC59,BC51a…BC56a,BC61…BC64,BC71…BC82 ビット線コンタクト
WC,WC11…WC14,WC1a…WC6a,WC21…WC28,WC31…WC34,WC51…WC54,WC51a…WC56a,WC61…WC68,WC71…WC74 ワード線コンタクト
WLa,WLb,WL1a…WL4a,WL1b…WL4b,WL1c…WL4c,WL1d…WL4d ワード線
BLa,BLb,BL1a…BL6a,BL1b…BL4b,BL1c…BL6c,BL1d…BL4d ビット線
Claims (13)
- 複数のワード線および複数のビット線の各交差箇所にアンチヒューズメモリが配置された半導体記憶装置であって、
各前記アンチヒューズメモリは、
メモリゲート絶縁膜を介してメモリゲート電極が設けられ、ウエルに形成された一方の拡散領域にビット線コンタクトを介して前記ビット線が接続されたメモリキャパシタと、
前記メモリゲート電極と前記ワード線との間に設けられ、前記ワード線からの電圧がワード線コンタクトを経由して前記メモリゲート電極に印加される一方、前記メモリゲート電極および前記ワード線へ印加される電圧値により前記メモリゲート電極から前記ワード線への電圧印加が遮断される整流素子とを備えており、
2個以上の前記アンチヒューズメモリで1個の前記ビット線コンタクトを共有している
ことを特徴とする半導体記憶装置。 - 1個の前記ワード線コンタクトに対して、2個以上の前記アンチヒューズメモリが接続されている
ことを特徴とする請求項1に記載の半導体記憶装置。 - 複数のワード線および複数のビット線の各交差箇所にアンチヒューズメモリが配置された半導体記憶装置であって、
各前記アンチヒューズメモリは、
メモリゲート絶縁膜を介してメモリゲート電極が設けられ、ウエルに形成された一方の拡散領域にビット線コンタクトを介して前記ビット線が接続されたメモリキャパシタと、
前記メモリゲート電極と前記ワード線との間に設けられ、前記ワード線からの電圧がワード線コンタクトを経由して前記メモリゲート電極に印加される一方、前記メモリゲート電極および前記ワード線へ印加される電圧値により前記メモリゲート電極から前記ワード線への電圧印加が遮断される整流素子とを備えており、
2個以上の前記アンチヒューズメモリで1個の前記ワード線コンタクトを共有している
ことを特徴とする半導体記憶装置。 - 互いに隣接する4個の前記アンチヒューズメモリで1個の前記ビット線コンタクトを共有するとともに、互いに隣接する4個の前記アンチヒューズメモリで1個の前記ワード線コンタクトを共有する
ことを特徴とする請求項1~3のいずれか1項に記載の半導体記憶装置。 - 1個の前記ビット線コンタクトに接続される4個の前記アンチヒューズメモリは、各々電気的に独立に制御できる前記ワード線に接続され、
1個の前記ワード線コンタクトに接続される4個の前記アンチヒューズメモリは、各々電気的に独立に制御できる前記ビット線に接続されている
ことを特徴とする請求項4に記載の半導体記憶装置。 - 各前記ビット線は、前記ビット線コンタクトを介して2個以上の前記アンチヒューズメモリに電圧を印加し、各前記ワード線は、前記ワード線コンタクトを介して2個以上の前記アンチヒューズメモリに電圧を印加する
ことを特徴とする請求項1~5のいずれか1項に記載の半導体記憶装置。 - 末端に配置された所定の方向に並ぶ各前記ワード線コンタクトには、それぞれ2個の前記アンチヒューズメモリが接続されており、
中央領域に配置された残りの前記ワード線コンタクトには、それぞれ4個の前記アンチヒューズメモリが接続されている
ことを特徴とする請求項1~6のいずれか1項に記載の半導体記憶装置。 - 一方向に並ぶ複数の前記アンチヒューズメモリで、1個の前記ビット線コンタクトを共有するとともに、異なる前記ビット線コンタクトに接続された隣接する2個の前記アンチヒューズメモリで、1個の前記ワード線コンタクトを共有する
ことを特徴とする請求項1~3のいずれか1項に記載の半導体記憶装置。 - 一方向に並ぶ複数の前記アンチヒューズメモリで、1個の前記ワード線コンタクトを共有するとともに、異なる前記ワード線コンタクトに接続された隣接する2個の前記アンチヒューズメモリで、1個の前記ビット線コンタクトを共有する
ことを特徴とする請求項1~3のいずれか1項に記載の半導体記憶装置。 - 前記アンチヒューズメモリは、
前記メモリキャパシタにデータを書き込むときには、前記ワード線に印加された電圧が前記整流素子を介して前記メモリゲート電極に印加され、該メモリゲート電極と前記ビット線との電圧差により前記メモリゲート絶縁膜が絶縁破壊し、
前記メモリキャパシタにデータを書き込まないときには、前記メモリゲート電極が前記ワード線よりも電圧が高いと、前記メモリキャパシタの前記メモリゲート電極から前記ワード線への電圧印加を遮断する
ことを特徴とする請求項1~9のいずれか1項に記載の半導体記憶装置。 - 前記アンチヒューズメモリの前記整流素子は、P型半導体領域とN型半導体領域とが接合したPN接合ダイオードの半導体接合構造からなり、前記P型半導体領域が前記ワード線コンタクトを介して前記ワード線に接続され、前記N型半導体領域が前記メモリゲート電極に接続されている
ことを特徴とする請求項1~10のいずれか1項に記載の半導体記憶装置。 - 前記アンチヒューズメモリは、前記整流素子を構成する前記P型半導体領域と前記N型半導体領域とが、前記メモリゲート電極と一体形成されている
ことを特徴とする請求項11に記載の半導体記憶装置。 - 前記アンチヒューズメモリの前記整流素子は、N型MOS(Metal-Oxide-Semiconductor)トランジスタまたはP型MOSトランジスタからなり、一端のソース領域が前記メモリゲート電極に接続されているとともに、他端のドレイン領域が前記ワード線に接続され、整流素子ゲート電極が前記ワード線または前記メモリゲート電極のいずれか一方に接続されており、チャネルを非導通状態とすることで前記メモリゲート電極から前記ワード線への電圧印加を遮断する
ことを特徴とする請求項1~9のいずれか1項に記載の半導体記憶装置。
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