JP2010087494A - 半導体記憶装置、及び半導体装置 - Google Patents
半導体記憶装置、及び半導体装置 Download PDFInfo
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- JP2010087494A JP2010087494A JP2009202253A JP2009202253A JP2010087494A JP 2010087494 A JP2010087494 A JP 2010087494A JP 2009202253 A JP2009202253 A JP 2009202253A JP 2009202253 A JP2009202253 A JP 2009202253A JP 2010087494 A JP2010087494 A JP 2010087494A
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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- G—PHYSICS
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- G11C—STATIC STORES
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- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
【解決手段】複数のワード線と、複数のビット線と、複数のワード線のいずれか、及び複数のビット線のいずれか、の交差部に応じて設けられたメモリセルと、を有し、メモリセルは、pin型ダイオード及びアンチヒューズを有し、pin型ダイオードの陽極は、ビット線のいずれかに電気的に接続され、pin型ダイオードの陰極は、アンチヒューズの第1端子に電気的に接続され、アンチヒューズの第2端子は、ワード線のいずれかに電気的に接続され、アンチヒューズは、電極に挟持されたシリコン層及び絶縁層を有する。
【選択図】図1
Description
本実施の形態では、本発明の一態様の半導体記憶装置について説明する。
本実施形態では、上記実施の形態1で説明したアンチヒューズの素子構造の例について説明する。
本実施の形態では、半導体記憶装置の上面図及び当該上面図に対応する断面図について説明する。図8(A)は半導体記憶装置のメモリセルについての上面図であり、図8(B)は、図8(A)に示すA−Bの部分の断面図である。また図9(A)は半導体記憶装置のメモリセルについての上面図であり、図9(B)は、図9(A)に示すA−Bの部分の断面図である。なお本実施の形態における上面図、断面図に示す各素子は、構造を明確に記すために、誇張した縮尺により表記するものとする。
本実施の形態では、上記実施の形態3とは異なる上面図及び断面構造を有する半導体記憶装置について説明する。図10(A)は半導体記憶装置のメモリセルについての上面図であり、図10(B)、図11(A)、図11(B)は、図10(A)に示すA−Bの部分の断面図である。また図12(A)は半導体記憶装置のメモリセルについての上面図であり、図12(B)、図13(A)、図13(B)は、図12(A)に示すA−Bの部分の断面図である。なお本実施の形態における上面図、断面図に示す各素子は、構造を明確に記すために、誇張した縮尺により表記するものとする。
本実施の形態では、本発明の一態様の半導体記憶装置の適用例として、半導体記憶装置を備えた半導体装置について説明する。
本実施例では、アンチヒューズ型の半導体記憶装置を具備する半導体装置の製造方法について、図15(A)〜図15(D)及び図16(A)〜図16(C)を用いて以下に説明する。ここでは、同一基板上に論理回路部1550と、半導体記憶回路部1552と、アンテナ部1554と、を設けた半導体装置を製造する一例を示す。論理回路部1550は薄膜トランジスタを用いた回路が集積される。半導体記憶回路部1552は複数のpin型ダイオード及びアンチヒューズによりメモリセルが構成される。なお、便宜上、論理回路部1550を構成する2つの薄膜トランジスタ、半導体記憶回路部1552を構成する1つのpin型ダイオード及び1つのアンチヒューズ、並びにアンテナ部1554を構成する1つの容量及び1つの薄膜トランジスタの断面図を示している。なお本実施の形態における断面図に示す各素子は、構造を明確に記すために、誇張した縮尺により表記するものとする。
本実施の形態では、上記実施の形態5及び6で説明した本発明の一態様の半導体記憶装置を具備する半導体装置の使用形態の一例について説明する。
101 ビット線駆動回路
102 ワード線駆動回路
103 メモリセルアレイ
104 pin型ダイオード
105 アンチヒューズ
106 メモリセル
200 半導体記憶装置
201 インターフェース部
202 昇圧回路
301 矢印
302 矢印
303 矢印
351 スイッチ
401 矢印
501 期間
502 期間
503 期間
504 期間
600 半導体記憶装置
601 ビット線駆動回路
602 ワード線駆動回路
603 メモリセルアレイ
604 薄膜トランジスタ
605 アンチヒューズ
606 メモリセル
700 アンチヒューズ
702 電極
704 抵抗材料層
706 絶縁層
708 シリコン層
710 電極
800 支持基板
801 ブロッキング膜
802 半導体層
803 絶縁層
804 導電層
805 第1の層間膜
807 シリコン層
808 絶縁層
809 p型半導体領域
810 真性半導体領域
811 n型半導体領域
901 層間膜
1000 支持基板
1001 ブロッキング膜
1002 導電層
1003 p型半導体層
1004 真性半導体層
1005 n型半導体層
1006 導電層
1007 絶縁層
1008 シリコン層
1009 第1の層間膜
1010 導電層
1101 層間膜
1400 半導体装置
1401 リーダ/ライタ
1402 アンテナ
1403 無線信号
1404 アンテナ
1405 整流回路
1406 定電圧回路
1407 復調回路
1408 変調回路
1409 論理回路
1410 半導体記憶装置
1411 ROM
1501 支持基板
1502 金属層
1503 絶縁層
1504 ゲート電極
1505 ゲート電極
1506 ゲート電極
1507 ゲート電極
1509 電極
1510 サイドウォール絶縁層
1511 サイドウォール絶縁層
1512 ゲート絶縁層
1513 絶縁層
1520 開口
1522 絶縁層
1523 絶縁層
1525 導電層
1526 導電層
1527 導電層
1528 導電層
1529 配線
1530 配線
1531 導電層
1532 導電層
1533 導電層
1534 導電層
1535 配線
1536 配線
1537 配線
1538 配線
1539 配線
1540 電極
1541 電極
1542 電極
1543 絶縁層
1544 引出配線
1545 下地層
1546 アンテナ
1550 論理回路部
1552 半導体記憶回路部
1554 アンテナ部
1559 pin型ダイオード
1560 アンチヒューズ
1562 引出配線部
1700 半導体装置
806A 導電層
806B 導電層
1514a p型不純物領域
1514b p型半導体領域
1515a n型不純物領域
1516a チャネル形成領域
1516b 真性半導体領域
1517a 高濃度不純物領域
1517b 不純物領域
1517c 高濃度不純物領域
1519a 低濃度不純物領域
1519b 不純物領域
1519c 低濃度不純物領域
1521a チャネル形成領域
1521b 不純物領域
1521c チャネル形成領域
1524a アモルファスシリコン層
1524b 酸化窒化シリコン層
Claims (7)
- ワード線とビット線との交差部にマトリクス状に配置されたメモリセルを有し、
前記メモリセルは、pin型ダイオード及びアンチヒューズを有し、前記pin型ダイオードの陽極は、前記ビット線と電気的に接続され、前記pin型ダイオードの陰極は、前記アンチヒューズの第1端子に電気的に接続され、前記アンチヒューズの第2端子は、前記ワード線と電気的に接続され、
前記アンチヒューズは、電極に挟持されたシリコン層及び絶縁層を有することを特徴とする半導体記憶装置。 - ワード線とビット線との交差部にマトリクス状に配置されたメモリセルを有し、
前記メモリセルは、pin型ダイオード及びアンチヒューズを有し、前記アンチヒューズの第1端子は、前記ビット線と電気的に接続され、前記アンチヒューズの第2端子は、前記pin型ダイオードの陽極に電気的に接続され、前記pin型ダイオードの陰極は、前記ワード線と電気的に接続され、
前記アンチヒューズは、電極に挟持されたシリコン層及び絶縁層を有することを特徴とする半導体記憶装置。 - ワード線とビット線との交差部にマトリクス状に配置されたメモリセルを有し、
前記メモリセルは、pin型ダイオード及びアンチヒューズを有し、前記pin型ダイオードの陽極は、前記ビット線と電気的に接続され、前記pin型ダイオードの陰極は、前記アンチヒューズの第1端子に電気的に接続され、前記アンチヒューズの第2端子は、前記ワード線と電気的に接続され、
前記アンチヒューズは、電極に挟持されたシリコン層及び絶縁層を有し、
前記pin型ダイオードのp型半導体領域、真性半導体領域、及びn型半導体領域は、重畳して設けられていることを特徴とする半導体記憶装置。 - ワード線とビット線との交差部にマトリクス状に配置されたメモリセルを有し、
前記メモリセルは、pin型ダイオード及びアンチヒューズを有し、前記アンチヒューズの第1端子は、前記ビット線と電気的に接続され、前記アンチヒューズの第2端子は、前記pin型ダイオードの陽極に電気的に接続され、前記pin型ダイオードの陰極は、前記ワード線と電気的に接続され、
前記アンチヒューズは、電極に挟持されたシリコン層及び絶縁層を有し、
前記pin型ダイオードのp型半導体領域、真性半導体領域、及びn型半導体領域は、重畳して設けられていることを特徴とする半導体記憶装置。 - ワード線とビット線との交差部にマトリクス状に配置されたメモリセルを有し、
前記メモリセルは、pin型ダイオード及びアンチヒューズを有し、前記pin型ダイオードの陽極は、前記ビット線と電気的に接続され、前記pin型ダイオードの陰極は、前記アンチヒューズの第1端子に電気的に接続され、前記アンチヒューズの第2端子は、前記ワード線と電気的に接続され、
前記アンチヒューズは、電極に挟持されたシリコン層及び絶縁層を有し、
前記pin型ダイオードのp型半導体領域、真性半導体領域、及びn型半導体領域は、並んで設けられていることを特徴とする半導体記憶装置。 - ワード線とビット線との交差部にマトリクス状に配置されたメモリセルを有し、
前記メモリセルは、pin型ダイオード及びアンチヒューズを有し、前記アンチヒューズの第1端子は、前記ビット線と電気的に接続され、前記アンチヒューズの第2端子は、前記pin型ダイオードの陽極に電気的に接続され、前記pin型ダイオードの陰極は、前記ワード線と電気的に接続され、
前記アンチヒューズは、電極に挟持されたシリコン層及び絶縁層を有し、
前記pin型ダイオードのp型半導体領域、真性半導体領域、及びn型半導体領域は、並んで設けられていることを特徴とする半導体記憶装置。 - 請求項1乃至請求項6のいずれか一に記載の半導体記憶装置と、
アンテナと、整流回路と、定電圧回路と、復調回路と、変調回路と、論理回路と、を有することを特徴とする半導体装置。
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