WO2016124086A1 - 横向双扩散场效应管 - Google Patents

横向双扩散场效应管 Download PDF

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Publication number
WO2016124086A1
WO2016124086A1 PCT/CN2016/072281 CN2016072281W WO2016124086A1 WO 2016124086 A1 WO2016124086 A1 WO 2016124086A1 CN 2016072281 W CN2016072281 W CN 2016072281W WO 2016124086 A1 WO2016124086 A1 WO 2016124086A1
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Prior art keywords
well
source
region
conductivity type
effect transistor
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English (en)
French (fr)
Inventor
顾炎
苏巍
张森
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/658—Lateral DMOS [LDMOS] FETs having trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/657—Lateral DMOS [LDMOS] FETs having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to a lateral double-diffusion field effect transistor.
  • Power FET mainly includes vertical double diffusion field effect tube (Vertical Double-Diffused) MOSFET, VDMOS) and lateral double-diffused MOSFET (LDMOS) Two types.
  • VDMOS vertical double diffusion field effect tube
  • LDMOS lateral double-diffused MOSFET
  • the lateral double-diffused field effect transistor LDMOS has many advantages compared with the vertical double-diffused field effect transistor VDMOS. For example, the latter has better thermal stability and frequency stability, higher gain and durability, and lower Feedback capacitance and thermal resistance, as well as constant input impedance and simpler bias current circuits.
  • the conductive channel and drift region of the device are both lateral, so carriers move through the drift of the device surface when the device is conducting, and drift from the drain to the device surface during reverse withstand voltage. The area is exhausted. The current can only drift laterally to the other end, and the injection of carriers is concentrated on the surface, so the operating current of such a single device is small when it is turned on.
  • the drift region is designed to be long, and the size of the device is also elongated, which results in a large device area, and at the same time, the on-resistance of the device becomes large, and the switching characteristics of the device are also weakened. .
  • each gate trench structure including a trench and filling in the a conductive material in the trench, and a gate insulating layer is formed on an inner wall of the trench;
  • a second drain doping region having a second conductivity type formed on the epitaxial layer and located on a side of the field oxide layer away from the first well;
  • a drain terminal is electrically connected to the second drain doping region.
  • the lateral double-diffused field effect transistor has a plurality of gate trench structures added to the source structure portion in a single cell, and a gate terminal is taken as a gate electrode from the gate trench structure, and thus when added at the gate electrode
  • the gate insulating layer on both sides of the trench forms an inversion layer with the first well, that is, a conductive channel; when there is a voltage on the drain structure (second drain doping region), there is a conductive channel Current flows through. If the number of gate trench structures is N, there are 2N conductive channels flowing through the current, and the current density is significantly increased in the single cell structure of the conventional LDMOS, so that the overall cell structure can be Increases the current density of a single device.
  • the lateral double-diffused field effect transistor has a small device area and a small on-resistance due to a larger operating current of a single cell structure.
  • the above lateral double-diffused FET has a larger operating current.
  • FIG. 1 is a schematic structural view of a lateral double-diffusion field effect transistor of the first embodiment
  • FIG. 2 is an enlarged schematic view of the gate trench structure of FIG. 1;
  • FIG. 3 is a schematic structural view of a lateral double-diffusion field effect transistor of the second embodiment
  • FIG. 4 is a schematic structural view of a lateral double-diffusion field effect transistor of a third embodiment
  • Figure 5 is a schematic structural view of a lateral double-diffusion field effect transistor of the fourth embodiment
  • Fig. 6 is a schematic structural view of a lateral double-diffusion field effect transistor of the fifth embodiment.
  • the vocabulary of the semiconductor field cited herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • the first conductivity type is P type
  • the second conductivity type is N type
  • FIG. 1 is a schematic view showing the structure of a lateral double-diffusion field effect transistor of the first embodiment.
  • a lateral double-diffusion field effect transistor of the first embodiment includes: a substrate 100 having a first conductivity type, an insulating layer 200, an epitaxial layer 300 having a second conductivity type, a field oxide layer 400, and a first conductivity type a first well 500, a gate trench structure 600, a first source doped region 710 having a first conductivity type, a second source doped region 720 having a second conductivity type, and a second having a second conductivity type
  • the material of the substrate 100 is silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon, and the substrate is a P+ type substrate (P-sub).
  • the insulating layer 200 is formed on the substrate 100.
  • the material of the insulating layer is an oxide of silicon, which may be silicon dioxide.
  • the insulating layer 200 is functionally a buried oxide layer. Due to the barrier effect of the insulating layer 200, the substrate 100 has little effect on the device, and thus the substrate 100 may be heavily doped (P+).
  • the epitaxial layer 300 is formed on the insulating layer 200, and the epitaxial layer 300 is an N-type epitaxial layer.
  • Epitaxial layer 300 acts as a drift region and has a conductivity type opposite to substrate 100.
  • the material of the epitaxial layer 300 is silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon.
  • the field oxide layer 400 is formed on the epitaxial layer 300.
  • the material of the field oxide layer 400 is an oxide of silicon, which may be silicon dioxide.
  • the field oxide layer 400 is mainly used to separate the source structure and the drain structure.
  • the first well 500 is formed on the epitaxial layer 300 and is located on one side of the field oxide layer 400.
  • the first well is a P-type well, which serves as a source structure buffer region and plays a role in conducting hole injection and withstand voltage.
  • a plurality of trench gate structures 600 are interspersed in the first well 500, and a bottom of each gate trench structure 600 extends to the epitaxial layer 300.
  • Each gate trench structure 600 includes a trench 610 and a conductive material 620 filled in the trench, and a gate insulating layer 630 is further formed on the inner wall of the trench 610.
  • the conductive material 620 is polysilicon, and the material of the gate insulating layer 630 is an oxide of silicon, which may be silicon dioxide.
  • the gate terminal 10 is electrically connected to the conductive material 620 in the trench 610, and the gate terminal 10 is the gate contact electrode.
  • FIG. 2 is an enlarged schematic view of a gate trench structure.
  • the gate is buried in the first well 500 in the form of a trench, so that when a certain voltage is applied to the gate electrode (gate terminal 10), the gate insulating layer 630 and the first well 500 on both sides of the trench 610 Both form an inversion layer, that is, a conductive channel; when there is a voltage on the drain structure (second drain doping region 910), a current flows in the conductive channel.
  • the number of gate trench structures 600 is N, there are 2N conductive channels flowing through the current, and the current density is significantly increased in a single cell structure of a conventional single-channel SOI-LIGBT.
  • the current density of a single device is generally increased under a multi-cell structure.
  • a larger operating current of a single cell structure can result in a smaller device area and a small on-state voltage drop.
  • the above lateral double-diffused FET can have a larger operating current.
  • a second source doping region 720 is formed on a surface layer of the first well 500 on both sides of each gate trench structure 600.
  • the second source doping region 720 is an N+ source doped region and is surrounded by the first well 500.
  • the first source doping region 710 is formed on the surface layer of the first well 500 on the side of the second source doping region 720 away from the gate trench structure 600.
  • the first source doped region is a P+ source doped region and is also surrounded by the first well 500. That is, extending from both sides of the gate trench structure 600, respectively, is a second source doping region 720 and a first source doping region 710.
  • the source terminal 20 is electrically connected to the second source doping region 720 and the first source doping region 710, and the source terminal 20 is the source contact electrode.
  • the second drain doping region 910 is formed on the epitaxial layer 300 and is located on a side of the field oxide layer 400 away from the first well 500.
  • the second drain doping region 910 is an n+ type drain doping region.
  • One side of the field oxide layer 400 is the first well 500, and the other side is the second drain doping region 910.
  • the drain terminal 30 is electrically connected to the second drain doping region 910, and the drain terminal 30 is the drain contact electrode.
  • the gate terminal 10, the source terminal 20 and the drain terminal 30 are generally formed of a conductive material such as copper, aluminum, aluminum silicon alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, etc., which can pass physical / Chemical vapor deposition formation.
  • a conductive material such as copper, aluminum, aluminum silicon alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, etc., which can pass physical / Chemical vapor deposition formation.
  • the raw material used in the implementation uses a sandwich structure in which the buried oxide layer (insulating layer 200) is an intermediate layer, that is, an SOI structure, and may also be a double layer of an insulating substrate (substrate 100) plus a top layer single crystal silicon (epitaxial layer 300). material.
  • the buried oxide layer in the structure is electrically isolated from the substrate, and a dielectric isolation structure between the device and the device enables complete isolation of the entire device.
  • the top layer silicon (epitaxial layer 300) needs to have a certain thickness, which is thicker than the depth of the trench gate structure 600, so that there is sufficient between the trench gate structure 600 and the buried oxide layer (insulating layer 200).
  • the large distance makes the electron flow path wider, which makes the on-state resistance in the on state smaller, and also makes the electric field distribution more uniform in the reverse withstand voltage.
  • FIG. 3 is a schematic view showing the structure of a lateral double-diffusion field effect transistor of the second embodiment.
  • the lateral double-diffusion field effect transistor of the second embodiment is substantially the same as the first embodiment except that it further includes a second well 800 having a second conductivity type.
  • the second well 800 is formed on the epitaxial layer 300 and is located on a side of the field oxide layer 400 away from the first well 500.
  • the second well is an N-type well and belongs to a medium doping concentration.
  • One side of the field oxide layer 400 is the first well 500 and the other side is the second well 800.
  • the second drain doping region 910 is formed on the surface layer of the second well 800.
  • the second drain doping region 910 is an n+ type drain doping region and is surrounded by the second well 800.
  • the function of the second well 800 is to increase the concentration of the drift region around the drain structure.
  • the second drain doping region 910 of the protection drain structure is not depleted by adjusting the second well 800.
  • the implant dose ensures a lateral margin when fully depleted in the longitudinal direction, thus ensuring that the longitudinal breakdown of the device can be moved from the surface to the body while also reducing the on-resistance of the drain drift region.
  • FIG. 4 is a schematic structural view of a lateral double-diffusion field effect transistor of a third embodiment
  • the lateral double-diffusion field effect transistor of the third embodiment is substantially the same as the first embodiment except that the conductive member 40 is further included.
  • the conductive member 40 is formed on the field oxide layer 400 near one end of the second drain doping region 910.
  • the drain terminal 30 is also electrically connected to the conductive member 40.
  • the material of the conductive member may be polysilicon.
  • the conductive member 40 When the device is in reverse withstand voltage, the conductive member 40 has the same potential as the drain structure, so that the potential of the oxide layer structure 400 has an approximately linear change from the drain structure to the source structure, and the drift region (epitaxial layer) The electric field distribution in 300) also approximates a linear change, which can help the drift region to deplete, so that the rate of reverse depletion can be kept uniform.
  • the concentration of the drift region is slightly larger, local electric field lines will not be generated. A peak electric field appears when it gathers.
  • the concentration of the drift region can be appropriately increased to lower the conduction voltage drop without changing the breakdown voltage and the breakdown point.
  • Figure 5 is a schematic view showing the structure of a lateral double-diffusion field effect transistor of the fourth embodiment
  • the lateral double-diffusion field effect transistor of the fourth embodiment is substantially the same as the first embodiment except that it further includes a first embedded region 730 having a first conductivity type.
  • the first embedding region 730 is a P-type doping region and belongs to a medium doping concentration.
  • the first embedding region 730 is formed between the first source doping region 710 and the first well 500, that is, the first embedding region 730 encloses the first source doping region 710 such that the first source doping region The 710 is isolated from the first well 500.
  • the transistor When the device is turned on, there is a parasitic NPN transistor under the source structure. When the condition that the base of the transistor can be crossed, the transistor may be turned on, which may cause the device to fail during the turn-on phase. Adding a P-type doped region under the first source doping region 710 can increase the base region concentration of the NPN tube, and the minority carrier lifetime is reduced and cannot be passed to the emitter, thus effectively avoiding the source parasitic transistor opening. The phenomenon.
  • Figure 6 is a schematic view showing the structure of a lateral double-diffusion field effect transistor of the fifth embodiment
  • the lateral double-diffusion field effect transistor of the fifth embodiment is substantially the same as the first embodiment except that it further includes a second embedded region 740 having a second conductivity type.
  • the second embedding region 740 is an N-type embedding region and belongs to a medium doping concentration.
  • the second embedding region 740 is formed at the junction of the bottom of the gate trench structure 600 and the epitaxial layer (drift region) 300, that is, the second embedding region 740 encloses the bottom of the gate trench structure 600, so that the vertical conductive trench
  • the N-type carrier concentration below the track becomes large. When the device is conducting, the electrons pass through the conductive channel. Due to the large carrier concentration in this region, the on-resistance is significantly reduced and the current density is significantly enhanced.
  • the lateral breakdown voltage of the device and the on-resistance of the drift region can be made the most reasonable compromise.
  • the lateral breakdown voltage is greater than the longitudinal breakdown voltage, the breakdown point is still in the body.
  • the above lateral double-diffusion field effect transistor adds more than one gate trench structure to the source structure portion in a single cell, and extracts the gate terminal from the gate trench structure as a gate electrode, and thus When a certain voltage is applied to the electrodes, the gate insulating layer on both sides of the trench forms an inversion layer with the first well, that is, a conductive channel. When there is a voltage on the drain structure (second drain doping region), a current flows in the conductive channel. If the number of gate trench structures is N, there are 2N conductive channels flowing through the current, and the current density is significantly increased in the single cell structure of the conventional single-channel LDMOS, so that the multi-cell can be The overall density of the individual devices is increased overall under the structure.
  • the lateral double-diffused field effect transistor has a small device area and a small on-state voltage drop due to a larger operating current of a single cell structure.
  • the above lateral double-diffused FET has a larger operating current.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种横向双扩散场效应管包括：具有第一导电类型的衬底（100）；绝缘层（200），形成于所述衬底（100）上；具有第二导电类型的外延层（300），形成于所述绝缘层（200）上；场氧化层（400），形成于所述外延层（300）上；具有第一导电类型的第一阱（500），形成于所述外延层（300）上，且位于所述场氧化层（400）的一侧；多个栅极沟槽结构（600）；具有第二导电类型的第二源极掺杂区（720）；具有第一导电类型的第一源极掺杂区（710）；具有第二导电类型的第二漏极掺杂区（910），形成于所述外延层（300）上，且位于所述场氧化层（400）远离所述第一阱（500）的一侧；栅极引出端（10），与所述导电材料电连接；源极引出端（20），与所述第二源极掺杂区（720）及所述第一源极掺杂区（710）电连接；及漏极引出端（30），与所述第二漏极掺杂区（910）电连接。

Description

横向双扩散场效应管
【技术领域】
本发明涉及半导体器件技术领域，特别涉及一种横向双扩散场效应管。
【背景技术】
功率场效应管主要包括垂直双扩散场效应管（Vertical Double-Diffused MOSFET，VDMOS) 和横向双扩散场效应管（Lateral Double-Diffused MOSFET，LDMOS) 两种类型。其中，相较于垂直双扩散场效应管VDMOS，横向双扩散场效应管LDMOS具有诸多优点，例如，后者具有更好的热稳定性和频率稳定性、更高的增益和耐久性、更低的反馈电容和热阻，以及恒定的输入阻抗和更简单的偏流电路。
传统的LDMOS器件，器件的导电沟道和漂移区都为横向，所以在器件正向导通时，载流子通过器件表面的漂移而运动；反向耐压时，从漏端沿着器件表面漂移区耗尽。电流只能通过横向漂移到另一端，载流子的注入均集中在表面，因此这样的单个器件在导通时的工作电流就很小。为了达到更高的工作电流，将漂移区设计得很长，器件的尺寸也随之拉长，这样导致器件面积很大，同时导致器件的导通电阻变大，器件的开关特性也随之减弱。
【发明内容】
基于此，有必要提供一种横向双扩散场效应管，该横向双扩散场效应管具有工作电流大、器件面积小、导通电阻小的优点。
一种横向双扩散场效应管，包括：
具有第一导电类型的衬底；
绝缘层，形成于所述衬底上；
具有第二导电类型的外延层，形成于所述绝缘层上；
场氧化层，形成于所述外延层上；
具有第一导电类型的第一阱，形成于所述外延层上，且位于所述场氧化层的一侧；
多个栅极沟槽结构，间隔穿插设置在所述第一阱中，每一栅极沟槽结构的底部延伸至所述外延层；每一栅极沟槽结构包括沟槽和填充于所述沟槽内的导电材料，所述沟槽的内壁上还形成有栅绝缘层；
具有第二导电类型的第二源极掺杂区，形成于每一栅极沟槽结构两侧的所述第一阱的表层上；
具有第一导电类型的第一源极掺杂区，形成于所述第二源极掺杂区远离所述栅极沟槽结构一侧的所述第一阱的表层上；
具有第二导电类型的第二漏极掺杂区，形成于所述外延层上，且位于所述场氧化层远离所述第一阱的一侧；
栅极引出端，与所述导电材料电连接；
源极引出端，与所述第二源极掺杂区及所述第一源极掺杂区电连接；及
漏极引出端，与所述第二漏极掺杂区电连接。
上述横向双扩散场效应管，对单个元胞中的源极结构部分加入多个栅极沟槽结构，并从该栅极沟槽结构引出栅极引出端作为栅电极，因而当在栅电极加上一定电压时，沟槽两侧的栅绝缘层与第一阱都形成反型层，即导电沟道；当漏极结构（第二漏极掺杂区）上有电压时，导电沟道中有电流流过。如果栅极沟槽结构的个数为N个，则电流流过的导电沟道就有2N个，较之传统的LDMOS的单个元胞结构中电流密度显著增加，从而可以在多元胞结构下总体提高了单个器件的电流密度。因而，在同样的工作电流下，上述横向双扩散场效应管因为单个元胞结构更大的工作电流使得器件面积小、导通电阻小。而在同样的器件面积下，上述横向双扩散场效应管则拥有更大的工作电流。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是第一实施例的横向双扩散场效应管的结构示意图；
图2是图1中的栅极沟槽结构的放大示意图；
图3是第二实施例的横向双扩散场效应管的结构示意图；
图4是第三实施例的横向双扩散场效应管的结构示意图；
图5是第四实施例的横向双扩散场效应管的结构示意图；
图6是第五实施例的横向双扩散场效应管的结构示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本发明。本文所使用的术语“和／或”包括一个或多个相关的所列项目的任意的和所有的组合。
本文所引用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
下面结合附图，对本发明的具体实施方式进行详细描述。以下描述中，第一导电类型为P型，第二导电类型为N型。
第一实施例：
图1是第一实施例横向双扩散场效应管的结构示意图。
第一实施例的一种横向双扩散场效应管包括：具有第一导电类型的衬底100、绝缘层200、具有第二导电类型的外延层300、场氧化层400、具有第一导电类型的第一阱500、栅极沟槽结构600、具有第一导电类型的第一源极掺杂区710、具有第二导电类型的第二源极掺杂区720、具有第二导电类型的第二漏极掺杂区910、栅极引出端10、源极引出端20和漏极引出端30。
衬底100的材料为硅、碳化硅、砷化镓、磷化铟或锗硅，衬底为P+型衬底（P-sub）。
绝缘层200形成于衬底100上，绝缘层的材料为硅的氧化物，可以是二氧化硅。绝缘层200从功能上而言为埋氧层。由于绝缘层200的阻隔作用，衬底100对器件影响不大，因而衬底100可以是重掺杂的（P+）。
外延层300形成于绝缘层200上，外延层300为N-型外延层。外延层300作为漂移区，具有的导电类型与衬底100相反。外延层300的材料为硅、碳化硅、砷化镓、磷化铟或锗硅。
场氧化层400形成于外延层300上，场氧化层400的材料为硅的氧化物，可以是二氧化硅。场氧化层400主要用于分隔源极结构和漏极结构。
第一阱500形成于外延层300上，且位于场氧化层400的一侧。第一阱为P-型阱，作为源极结构缓冲区域，对器件导通空穴注入和耐压起一定作用。
多个沟槽栅结构600间隔穿插设置在第一阱500中，每一栅极沟槽结构600的底部延伸至外延层300。每一栅极沟槽结构600包括沟槽610和填充于沟槽内的导电材料620，沟槽610的内壁上还形成有栅绝缘层630。导电材料620为多晶硅，栅绝缘层630的材料为硅的氧化物，可以是二氧化硅。栅极引出端10与沟槽610内的导电材料620电连接，栅极引出端10就是栅极接触电极。
图2是栅极沟槽结构的放大示意图。
将栅极以沟槽的形式埋入第一阱500中，因而当在栅电极（栅极引出端10）加上一定电压时，沟槽610内两侧的栅绝缘层630与第一阱500都形成反型层，即导电沟道；当漏极结构（第二漏极掺杂区910）上有电压时，导电沟道中有电流流过。如果栅极沟槽结构600的个数为N个，则电流流过的导电沟道就有2N个，较之传统的单沟道SOI-LIGBT的单个元胞结构中电流密度显著增加，从而可以在多元胞结构下总体提高了单个器件的电流密度。因而，在同样的工作电流下，单个元胞结构更大的工作电流可以使得器件面积小、导通压降小。而在同样的器件面积下，可以使得上述横向双扩散场效应管则拥有更大的工作电流。
第二源极掺杂区720形成于每一栅极沟槽结构600两侧的第一阱500的表层上。第二源极掺杂区720为N+源极掺杂区，被第一阱500包住。
第一源极掺杂区710形成于第二源极掺杂区720远离栅极沟槽结构600一侧的第一阱500的表层上。第一源极掺杂区为P+源极掺杂区，同样被第一阱500包住。即从栅极沟槽结构600两边延伸，依次分别是第二源极掺杂区720、第一源极掺杂区710。
源极引出端20与第二源极掺杂区720、第一源极掺杂区710电连接，源极引出端20就是源极接触电极。
第二漏极掺杂区910形成于外延层300上，且位于场氧化层400远离第一阱500的一侧。第二漏极掺杂区910为n+型漏极掺杂区。即场氧化层400的一侧为第一阱500，另一侧为第二漏极掺杂区910。
漏极引出端30与第二漏极掺杂区910电连接，漏极引出端30就是漏极接触电极。
栅极引出端10、源极引出端20和漏极引出端30通常由导电材料形成，例如铜、铝、铝硅合金、钛、氮化钛、钨、多晶硅、金属硅化物等，可以通过物理/化学气相沉积形成。
在实现的原材料使用是以埋氧层（绝缘层200）为中间层的三明治结构，即SOI结构，也可以是绝缘衬底（衬底100）加顶层单晶硅（外延层300）的双层材料。在SOI结构制作器件时，仅使用顶层的硅层（外延层300）来作为器件制作层，即形成源、漏、沟道区等结构，衬底（衬底100）仅起支撑作用，这种结构中的埋氧层与衬底在电学上实现了隔离开，且在器件与器件之间再加以介质型隔离结构，就可以实现整个器件的完全隔离。
在原始材料中，顶层硅（外延层300）需要具有一定的厚度，要厚于沟槽栅结构600的深度，这样可以使沟槽栅结构600到埋氧层（绝缘层200）之间有足够大的距离，使得电子的流通路径更为宽阔，而使得在导通状态下的开态电阻更小，同时也使得在反向耐压时电场的分布更加均匀。
第二实施例：
图3是第二实施例横向双扩散场效应管的结构示意图。
第二实施例的横向双扩散场效应管与第一实施例大致相同，其不同之处在于，还包括具有第二导电类型的第二阱800。第二阱800形成于外延层300上，且位于场氧化层400远离第一阱500的一侧。第二阱为N型阱，属于中掺杂浓度。即场氧化层400的一侧为第一阱500，另一侧为第二阱800。
这种结构下，第二漏极掺杂区910形成于第二阱800的表层上。第二漏极掺杂区910为n+型漏极掺杂区，被第二阱800包住。
第二阱800的作用是将漏极结构周围的漂移区浓度提高，当器件反向耐压时，保护漏端结构的第二漏极掺杂区910不被耗尽，通过调整第二阱800的注入剂量可以保证在纵向完全耗尽时横向还有余量，这样就可以保证该器件纵向击穿可以从表面移至体内，同时也降低了漏端漂移区的导通电阻。
第三实施例：
图4是第三实施例横向双扩散场效应管的结构示意图
第三实施例的横向双扩散场效应管与第一实施例大致相同，其不同之处在于，还包括导电件40。导电件40形成于场氧化层400上靠近第二漏极掺杂区910的一端。漏极引出端30还与导电件40电连接。导电件的材料可以是多晶硅。
当器件在反向耐压时，导电件40与漏极结构上有相同的电位，使得氧化层结构400的电位从漏极结构至源极结构有一个近似于线性的变化，漂移区（外延层300）内的电场分布也随之近似一个线性的变化，这样可以辅助漂移区进行耗尽，让反向耗尽的速率能保持均匀，当漂移区的浓度略大时不会产生局部的电场线聚集而出现峰值电场。如此可以适当提高漂移区的浓度来降低导通压降而不改变击穿电压和击穿点。
第四实施例:
图5是第四实施例横向双扩散场效应管的结构示意图
第四实施例的横向双扩散场效应管与第一实施例大致相同，其不同之处在于，还包括具有第一导电类型的第一嵌入区730。第一嵌入区730为P型掺杂区，属于中掺杂浓度。第一嵌入区730形成于第一源极掺杂区710与第一阱500之间，也即第一嵌入区730将第一源极掺杂区710包住，使得第一源极掺杂区710与第一阱500之间隔绝。
当器件导通时，源端结构下方有一个寄生NPN三极管，当满足三极管的基极少子可以渡越的条件后，可能会使得此三极管开启，这样会使得器件在开启阶段发生失效。在第一源极掺杂区710下方加一个P型掺杂区，可以提高NPN管的基区浓度，少子寿命减小而无法渡越到发射极，这样就有效地避免了源端寄生三极管开启的现象。
第五实施例:
图6是第五实施例横向双扩散场效应管的结构示意图
第五实施例的横向双扩散场效应管与第一实施例大致相同，其不同之处在于，还包括具有第二导电类型的第二嵌入区740。第二嵌入区740为N型嵌入区，属于中掺杂浓度。第二嵌入区740形成于栅极沟槽结构600的底部和外延层（漂移区）300交接之处，也即第二嵌入区740将栅极沟槽结构600的底部包住，使得纵向导电沟道下方的N型载流子浓度变大。当器件正向导通时，电子通过导电沟道后，由于这片区域的载流子浓度较大，导通电阻明显减小，电流密度显著增强。调整好栅极沟槽结构600的深度和第二嵌入区740的杂质浓度之后，可以使器件横向击穿电压和漂移区导通电阻得到最合理的折中。当横向击穿电压大于纵向击穿电压时，击穿点仍在体内。
上述横向双扩散场效应管，对单个元胞中的源极结构部分加入多于一个的栅极沟槽结构，并从该栅极沟槽结构引出栅极引出端作为栅电极，因而当在栅电极加上一定电压时，沟槽两侧的栅绝缘层与第一阱都形成反型层，即导电沟道。当漏极结构（第二漏极掺杂区）上有电压时，导电沟道中有电流流过。如果栅极沟槽结构的个数为N个，则电流流过的导电沟道就有2N个，较之传统的单沟道LDMOS的单个元胞结构中电流密度显著增加，从而可以在多元胞结构下总体提高了单个器件的电流密度。因而，在同样的工作电流下，上述横向双扩散场效应管因为单个元胞结构更大的工作电流使得器件面积小、导通压降小。而在同样的器件面积下，上述横向双扩散场效应管则拥有更大的工作电流。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (13)

  1. 一种横向双扩散场效应管，包括：
    具有第一导电类型的衬底；
    绝缘层，形成于所述衬底上；
    具有第二导电类型的外延层，形成于所述绝缘层上；
    场氧化层，形成于所述外延层上；
    具有第一导电类型的第一阱，形成于所述外延层上，且位于所述场氧化层的一侧；
    多个栅极沟槽结构，间隔穿插设置在所述第一阱中，每一栅极沟槽结构的底部延伸至所述外延层；每一栅极沟槽结构包括沟槽和填充于所述沟槽内的导电材料，所述沟槽的内壁上还形成有栅绝缘层；
    具有第二导电类型的第二源极掺杂区，形成于每一栅极沟槽结构两侧的所述第一阱的表层上；
    具有第一导电类型的第一源极掺杂区，形成于所述第二源极掺杂区远离所述栅极沟槽结构一侧的所述第一阱的表层上；
    具有第二导电类型的第二漏极掺杂区，形成于所述外延层上，且位于所述场氧化层远离所述第一阱的一侧；
    栅极引出端，与所述导电材料电连接；
    源极引出端，与所述第二源极掺杂区及所述第一源极掺杂区电连接；及
    漏极引出端，与所述第二漏极掺杂区电连接。
  2. 根据权利要求1所述的横向双扩散场效应管，其中所述第一导电类型为P型，所述第二导电类型为N型。
  3. 根据权利要求1所述的横向双扩散场效应管，其中所述衬底为P+型衬底，所述外延层为N-型外延层；所述第一阱为P-型阱，所述第二源极掺杂区为N+源极掺杂区，所述第一源极掺杂区为P+源极掺杂区；所述第二漏极掺杂区为n+型漏极掺杂区。
  4. 根据权利要求1所述的横向双扩散场效应管，还包括具有第二导电类型的第二阱，形成于所述外延层上，且位于所述场氧化层远离所述第一阱的一侧；所述第二漏极掺杂区形成于所述第二阱的表层上。
  5. 根据权利要求1所述的横向双扩散场效应管，还包括导电件，所述导电件形成于所述场氧化层上靠近所述第二漏极掺杂区的一侧；所述漏极引出端还与所述导电件电连接。
  6. 根据权利要求1所述的横向双扩散场效应管，其中还包括具有第一导电类型的第一嵌入区，所述第一嵌入区形成于所述第一源极掺杂区与所述第一阱之间，使得所述第一源极掺杂区与所述第一阱之间隔离。
  7. 根据权利要求1所述的横向双扩散场效应管，还包括具有第二导电类型的第二嵌入区，所述第二嵌入区形成于所述栅极沟槽结构的底部和所述外延层交接之处；所述第二嵌入区为N型嵌入区。
  8. 根据权利要求1所述的横向双扩散场效应管，其中所述衬底的材料和所述外延层的材料为硅、碳化硅、砷化镓、磷化铟或锗硅。
  9. 根据权利要求1所述的横向双扩散场效应管，其中所述绝缘层、场氧化层和栅绝缘层的材料均为硅的氧化物。
  10. 根据权利要求1所述的横向双扩散场效应管，其中所述导电材料为多晶硅。
  11. 根据权利要求1所述的横向绝缘栅双极型晶体管，其中所述栅极引出端是栅极接触电极，源极引出端是源极接触电极。
  12. 根据权利要求1所述的横向绝缘栅双极型晶体管，其中所述栅绝缘层与第一阱均形成反型层。
  13. 根据权利要求1所述的横向绝缘栅双极型晶体管，其中所述栅极引出端、所述源极引出端和所述漏极引出端的材料为铜、铝、铝硅合金、钛、氮化钛、钨、多晶硅或金属硅化物。
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