WO2016124086A1 - Transistor à effet de champ à double diffusion latérale - Google Patents

Transistor à effet de champ à double diffusion latérale Download PDF

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Publication number
WO2016124086A1
WO2016124086A1 PCT/CN2016/072281 CN2016072281W WO2016124086A1 WO 2016124086 A1 WO2016124086 A1 WO 2016124086A1 CN 2016072281 W CN2016072281 W CN 2016072281W WO 2016124086 A1 WO2016124086 A1 WO 2016124086A1
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Prior art keywords
well
source
region
conductivity type
effect transistor
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PCT/CN2016/072281
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English (en)
Chinese (zh)
Inventor
顾炎
苏巍
张森
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无锡华润上华半导体有限公司
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Publication of WO2016124086A1 publication Critical patent/WO2016124086A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to a lateral double-diffusion field effect transistor.
  • Power FET mainly includes vertical double diffusion field effect tube (Vertical Double-Diffused) MOSFET, VDMOS) and lateral double-diffused MOSFET (LDMOS) Two types.
  • VDMOS vertical double diffusion field effect tube
  • LDMOS lateral double-diffused MOSFET
  • the lateral double-diffused field effect transistor LDMOS has many advantages compared with the vertical double-diffused field effect transistor VDMOS. For example, the latter has better thermal stability and frequency stability, higher gain and durability, and lower Feedback capacitance and thermal resistance, as well as constant input impedance and simpler bias current circuits.
  • the conductive channel and drift region of the device are both lateral, so carriers move through the drift of the device surface when the device is conducting, and drift from the drain to the device surface during reverse withstand voltage. The area is exhausted. The current can only drift laterally to the other end, and the injection of carriers is concentrated on the surface, so the operating current of such a single device is small when it is turned on.
  • the drift region is designed to be long, and the size of the device is also elongated, which results in a large device area, and at the same time, the on-resistance of the device becomes large, and the switching characteristics of the device are also weakened. .
  • each gate trench structure including a trench and filling in the a conductive material in the trench, and a gate insulating layer is formed on an inner wall of the trench;
  • a second drain doping region having a second conductivity type formed on the epitaxial layer and located on a side of the field oxide layer away from the first well;
  • a drain terminal is electrically connected to the second drain doping region.
  • the lateral double-diffused field effect transistor has a plurality of gate trench structures added to the source structure portion in a single cell, and a gate terminal is taken as a gate electrode from the gate trench structure, and thus when added at the gate electrode
  • the gate insulating layer on both sides of the trench forms an inversion layer with the first well, that is, a conductive channel; when there is a voltage on the drain structure (second drain doping region), there is a conductive channel Current flows through. If the number of gate trench structures is N, there are 2N conductive channels flowing through the current, and the current density is significantly increased in the single cell structure of the conventional LDMOS, so that the overall cell structure can be Increases the current density of a single device.
  • the lateral double-diffused field effect transistor has a small device area and a small on-resistance due to a larger operating current of a single cell structure.
  • the above lateral double-diffused FET has a larger operating current.
  • FIG. 1 is a schematic structural view of a lateral double-diffusion field effect transistor of the first embodiment
  • FIG. 2 is an enlarged schematic view of the gate trench structure of FIG. 1;
  • FIG. 3 is a schematic structural view of a lateral double-diffusion field effect transistor of the second embodiment
  • FIG. 4 is a schematic structural view of a lateral double-diffusion field effect transistor of a third embodiment
  • Figure 5 is a schematic structural view of a lateral double-diffusion field effect transistor of the fourth embodiment
  • Fig. 6 is a schematic structural view of a lateral double-diffusion field effect transistor of the fifth embodiment.
  • the vocabulary of the semiconductor field cited herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • the first conductivity type is P type
  • the second conductivity type is N type
  • FIG. 1 is a schematic view showing the structure of a lateral double-diffusion field effect transistor of the first embodiment.
  • a lateral double-diffusion field effect transistor of the first embodiment includes: a substrate 100 having a first conductivity type, an insulating layer 200, an epitaxial layer 300 having a second conductivity type, a field oxide layer 400, and a first conductivity type a first well 500, a gate trench structure 600, a first source doped region 710 having a first conductivity type, a second source doped region 720 having a second conductivity type, and a second having a second conductivity type
  • the material of the substrate 100 is silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon, and the substrate is a P+ type substrate (P-sub).
  • the insulating layer 200 is formed on the substrate 100.
  • the material of the insulating layer is an oxide of silicon, which may be silicon dioxide.
  • the insulating layer 200 is functionally a buried oxide layer. Due to the barrier effect of the insulating layer 200, the substrate 100 has little effect on the device, and thus the substrate 100 may be heavily doped (P+).
  • the epitaxial layer 300 is formed on the insulating layer 200, and the epitaxial layer 300 is an N-type epitaxial layer.
  • Epitaxial layer 300 acts as a drift region and has a conductivity type opposite to substrate 100.
  • the material of the epitaxial layer 300 is silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon.
  • the field oxide layer 400 is formed on the epitaxial layer 300.
  • the material of the field oxide layer 400 is an oxide of silicon, which may be silicon dioxide.
  • the field oxide layer 400 is mainly used to separate the source structure and the drain structure.
  • the first well 500 is formed on the epitaxial layer 300 and is located on one side of the field oxide layer 400.
  • the first well is a P-type well, which serves as a source structure buffer region and plays a role in conducting hole injection and withstand voltage.
  • a plurality of trench gate structures 600 are interspersed in the first well 500, and a bottom of each gate trench structure 600 extends to the epitaxial layer 300.
  • Each gate trench structure 600 includes a trench 610 and a conductive material 620 filled in the trench, and a gate insulating layer 630 is further formed on the inner wall of the trench 610.
  • the conductive material 620 is polysilicon, and the material of the gate insulating layer 630 is an oxide of silicon, which may be silicon dioxide.
  • the gate terminal 10 is electrically connected to the conductive material 620 in the trench 610, and the gate terminal 10 is the gate contact electrode.
  • FIG. 2 is an enlarged schematic view of a gate trench structure.
  • the gate is buried in the first well 500 in the form of a trench, so that when a certain voltage is applied to the gate electrode (gate terminal 10), the gate insulating layer 630 and the first well 500 on both sides of the trench 610 Both form an inversion layer, that is, a conductive channel; when there is a voltage on the drain structure (second drain doping region 910), a current flows in the conductive channel.
  • the number of gate trench structures 600 is N, there are 2N conductive channels flowing through the current, and the current density is significantly increased in a single cell structure of a conventional single-channel SOI-LIGBT.
  • the current density of a single device is generally increased under a multi-cell structure.
  • a larger operating current of a single cell structure can result in a smaller device area and a small on-state voltage drop.
  • the above lateral double-diffused FET can have a larger operating current.
  • a second source doping region 720 is formed on a surface layer of the first well 500 on both sides of each gate trench structure 600.
  • the second source doping region 720 is an N+ source doped region and is surrounded by the first well 500.
  • the first source doping region 710 is formed on the surface layer of the first well 500 on the side of the second source doping region 720 away from the gate trench structure 600.
  • the first source doped region is a P+ source doped region and is also surrounded by the first well 500. That is, extending from both sides of the gate trench structure 600, respectively, is a second source doping region 720 and a first source doping region 710.
  • the source terminal 20 is electrically connected to the second source doping region 720 and the first source doping region 710, and the source terminal 20 is the source contact electrode.
  • the second drain doping region 910 is formed on the epitaxial layer 300 and is located on a side of the field oxide layer 400 away from the first well 500.
  • the second drain doping region 910 is an n+ type drain doping region.
  • One side of the field oxide layer 400 is the first well 500, and the other side is the second drain doping region 910.
  • the drain terminal 30 is electrically connected to the second drain doping region 910, and the drain terminal 30 is the drain contact electrode.
  • the gate terminal 10, the source terminal 20 and the drain terminal 30 are generally formed of a conductive material such as copper, aluminum, aluminum silicon alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, etc., which can pass physical / Chemical vapor deposition formation.
  • a conductive material such as copper, aluminum, aluminum silicon alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, etc., which can pass physical / Chemical vapor deposition formation.
  • the raw material used in the implementation uses a sandwich structure in which the buried oxide layer (insulating layer 200) is an intermediate layer, that is, an SOI structure, and may also be a double layer of an insulating substrate (substrate 100) plus a top layer single crystal silicon (epitaxial layer 300). material.
  • the buried oxide layer in the structure is electrically isolated from the substrate, and a dielectric isolation structure between the device and the device enables complete isolation of the entire device.
  • the top layer silicon (epitaxial layer 300) needs to have a certain thickness, which is thicker than the depth of the trench gate structure 600, so that there is sufficient between the trench gate structure 600 and the buried oxide layer (insulating layer 200).
  • the large distance makes the electron flow path wider, which makes the on-state resistance in the on state smaller, and also makes the electric field distribution more uniform in the reverse withstand voltage.
  • FIG. 3 is a schematic view showing the structure of a lateral double-diffusion field effect transistor of the second embodiment.
  • the lateral double-diffusion field effect transistor of the second embodiment is substantially the same as the first embodiment except that it further includes a second well 800 having a second conductivity type.
  • the second well 800 is formed on the epitaxial layer 300 and is located on a side of the field oxide layer 400 away from the first well 500.
  • the second well is an N-type well and belongs to a medium doping concentration.
  • One side of the field oxide layer 400 is the first well 500 and the other side is the second well 800.
  • the second drain doping region 910 is formed on the surface layer of the second well 800.
  • the second drain doping region 910 is an n+ type drain doping region and is surrounded by the second well 800.
  • the function of the second well 800 is to increase the concentration of the drift region around the drain structure.
  • the second drain doping region 910 of the protection drain structure is not depleted by adjusting the second well 800.
  • the implant dose ensures a lateral margin when fully depleted in the longitudinal direction, thus ensuring that the longitudinal breakdown of the device can be moved from the surface to the body while also reducing the on-resistance of the drain drift region.
  • FIG. 4 is a schematic structural view of a lateral double-diffusion field effect transistor of a third embodiment
  • the lateral double-diffusion field effect transistor of the third embodiment is substantially the same as the first embodiment except that the conductive member 40 is further included.
  • the conductive member 40 is formed on the field oxide layer 400 near one end of the second drain doping region 910.
  • the drain terminal 30 is also electrically connected to the conductive member 40.
  • the material of the conductive member may be polysilicon.
  • the conductive member 40 When the device is in reverse withstand voltage, the conductive member 40 has the same potential as the drain structure, so that the potential of the oxide layer structure 400 has an approximately linear change from the drain structure to the source structure, and the drift region (epitaxial layer) The electric field distribution in 300) also approximates a linear change, which can help the drift region to deplete, so that the rate of reverse depletion can be kept uniform.
  • the concentration of the drift region is slightly larger, local electric field lines will not be generated. A peak electric field appears when it gathers.
  • the concentration of the drift region can be appropriately increased to lower the conduction voltage drop without changing the breakdown voltage and the breakdown point.
  • Figure 5 is a schematic view showing the structure of a lateral double-diffusion field effect transistor of the fourth embodiment
  • the lateral double-diffusion field effect transistor of the fourth embodiment is substantially the same as the first embodiment except that it further includes a first embedded region 730 having a first conductivity type.
  • the first embedding region 730 is a P-type doping region and belongs to a medium doping concentration.
  • the first embedding region 730 is formed between the first source doping region 710 and the first well 500, that is, the first embedding region 730 encloses the first source doping region 710 such that the first source doping region The 710 is isolated from the first well 500.
  • the transistor When the device is turned on, there is a parasitic NPN transistor under the source structure. When the condition that the base of the transistor can be crossed, the transistor may be turned on, which may cause the device to fail during the turn-on phase. Adding a P-type doped region under the first source doping region 710 can increase the base region concentration of the NPN tube, and the minority carrier lifetime is reduced and cannot be passed to the emitter, thus effectively avoiding the source parasitic transistor opening. The phenomenon.
  • Figure 6 is a schematic view showing the structure of a lateral double-diffusion field effect transistor of the fifth embodiment
  • the lateral double-diffusion field effect transistor of the fifth embodiment is substantially the same as the first embodiment except that it further includes a second embedded region 740 having a second conductivity type.
  • the second embedding region 740 is an N-type embedding region and belongs to a medium doping concentration.
  • the second embedding region 740 is formed at the junction of the bottom of the gate trench structure 600 and the epitaxial layer (drift region) 300, that is, the second embedding region 740 encloses the bottom of the gate trench structure 600, so that the vertical conductive trench
  • the N-type carrier concentration below the track becomes large. When the device is conducting, the electrons pass through the conductive channel. Due to the large carrier concentration in this region, the on-resistance is significantly reduced and the current density is significantly enhanced.
  • the lateral breakdown voltage of the device and the on-resistance of the drift region can be made the most reasonable compromise.
  • the lateral breakdown voltage is greater than the longitudinal breakdown voltage, the breakdown point is still in the body.
  • the above lateral double-diffusion field effect transistor adds more than one gate trench structure to the source structure portion in a single cell, and extracts the gate terminal from the gate trench structure as a gate electrode, and thus When a certain voltage is applied to the electrodes, the gate insulating layer on both sides of the trench forms an inversion layer with the first well, that is, a conductive channel. When there is a voltage on the drain structure (second drain doping region), a current flows in the conductive channel. If the number of gate trench structures is N, there are 2N conductive channels flowing through the current, and the current density is significantly increased in the single cell structure of the conventional single-channel LDMOS, so that the multi-cell can be The overall density of the individual devices is increased overall under the structure.
  • the lateral double-diffused field effect transistor has a small device area and a small on-state voltage drop due to a larger operating current of a single cell structure.
  • the above lateral double-diffused FET has a larger operating current.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention porte sur un transistor à effet de champ, à double diffusion latérale, qui comporte : un substrat (100) ayant un premier type de conductivité ; une couche isolante (200) formée sur le substrat (100) ; une couche épitaxiale (300) ayant un second type de conductivité et formée sur la couche isolante (200) ; une couche d'oxyde de champ (400) formée sur la couche épitaxiale (300) ; un premier puits (500) ayant le premier type de conductivité, formé sur la couche épitaxiale (300) et situé d'un côté de la couche d'oxyde de champ (400) ; une pluralité de structures de tranchée de grille (600) ; de secondes zones dopées de source (720) ayant le second type de conductivité ; de première zones dopées de source (710) ayant le premier type de conductivité ; une seconde zone dopée de drain (910) ayant le second type de conductivité, formée sur la couche épitaxiale (300) et située du côté de la couche d'oxyde de champ (400) à l'opposé du premier puits (500) ; des extrémités de sortie de grille (10) connectées électriquement à un matériau conducteur ; une extrémité de sortie de source (20) connectée électriquement aux secondes zones dopées de source (720) et aux premières zones dopées de source (710) ; une extrémité de sortie de drain (30) connectée électriquement à la seconde zone dopée de drain (910).
PCT/CN2016/072281 2015-02-02 2016-01-27 Transistor à effet de champ à double diffusion latérale WO2016124086A1 (fr)

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CN201510054806.3A CN105990423A (zh) 2015-02-02 2015-02-02 横向双扩散场效应管
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108899318A (zh) * 2018-08-30 2018-11-27 无锡摩斯法特电子有限公司 一种增加vdmos沟道密度的蛇形布图结构和布图方法
CN108987479A (zh) * 2017-06-05 2018-12-11 马克西姆综合产品公司 包括具有多个介电区段的垂直栅的ldmos晶体管及相关方法
CN112400236A (zh) * 2018-06-28 2021-02-23 华为技术有限公司 一种半导体器件及制造方法
CN113690303A (zh) * 2020-05-18 2021-11-23 华润微电子（重庆）有限公司 半导体器件及其制备方法
CN114420761A (zh) * 2022-03-30 2022-04-29 成都功成半导体有限公司 一种耐高压碳化硅器件及其制备方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108198853B (zh) * 2018-03-02 2020-02-07 成都信息工程大学 一种双通道变掺杂ldmos器件及其制造方法
CN112531026B (zh) * 2019-09-17 2022-06-21 无锡华润上华科技有限公司 横向扩散金属氧化物半导体器件及其制造方法
CN111933687B (zh) * 2020-07-07 2023-04-18 电子科技大学 具有高安全工作区的横向功率器件
CN115274862A (zh) * 2021-04-30 2022-11-01 无锡华润上华科技有限公司 二极管及其制造方法及半导体器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040065919A1 (en) * 2002-10-03 2004-04-08 Wilson Peter H. Trench gate laterally diffused MOSFET devices and methods for making such devices
CN1848455A (zh) * 2005-04-05 2006-10-18 精工电子有限公司 半导体器件及其制造方法
CN1929137A (zh) * 2005-09-11 2007-03-14 谢福渊 高密度混合金属氧化物半导体场效应晶体管(mosfet)器件
US20100127324A1 (en) * 2008-11-26 2010-05-27 Force Mos Technology Co., Ltd. Trench MOSFET with terrace gate and self-aligned source trench contact
CN102044563A (zh) * 2009-10-16 2011-05-04 上海华虹Nec电子有限公司 Ldmos器件及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69528944T2 (de) * 1994-09-16 2003-09-04 Toshiba Kawasaki Kk Halbleiteranordnung mit hoher Durchbruchspannung und mit einer vergrabenen MOS-Gatestruktur
JP2007200981A (ja) * 2006-01-24 2007-08-09 Fuji Electric Holdings Co Ltd 横型パワーｍｏｓｆｅｔおよびその製造方法
CN102683187B (zh) * 2012-05-09 2016-09-28 上海华虹宏力半导体制造有限公司 横向双扩散金属氧化物半导体器件及其制造方法
CN103811546B (zh) * 2012-11-13 2016-11-23 上海华虹宏力半导体制造有限公司 带面结型场效应管的ldmos复合管
CN104377245A (zh) * 2014-11-26 2015-02-25 张家港凯思半导体有限公司 一种沟槽型mos器件及其制造方法和终端保护结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040065919A1 (en) * 2002-10-03 2004-04-08 Wilson Peter H. Trench gate laterally diffused MOSFET devices and methods for making such devices
CN1848455A (zh) * 2005-04-05 2006-10-18 精工电子有限公司 半导体器件及其制造方法
CN1929137A (zh) * 2005-09-11 2007-03-14 谢福渊 高密度混合金属氧化物半导体场效应晶体管(mosfet)器件
US20100127324A1 (en) * 2008-11-26 2010-05-27 Force Mos Technology Co., Ltd. Trench MOSFET with terrace gate and self-aligned source trench contact
CN102044563A (zh) * 2009-10-16 2011-05-04 上海华虹Nec电子有限公司 Ldmos器件及其制造方法

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CN108987479A (zh) * 2017-06-05 2018-12-11 马克西姆综合产品公司 包括具有多个介电区段的垂直栅的ldmos晶体管及相关方法
CN108987479B (zh) * 2017-06-05 2023-12-05 马克西姆综合产品公司 包括含介电区段的垂直栅的ldmos晶体管及相关方法
CN112400236A (zh) * 2018-06-28 2021-02-23 华为技术有限公司 一种半导体器件及制造方法
CN112400236B (zh) * 2018-06-28 2022-12-06 华为技术有限公司 一种半导体器件及终端设备
CN108899318A (zh) * 2018-08-30 2018-11-27 无锡摩斯法特电子有限公司 一种增加vdmos沟道密度的蛇形布图结构和布图方法
CN108899318B (zh) * 2018-08-30 2024-01-26 无锡摩斯法特电子有限公司 一种增加vdmos沟道密度的蛇形布图结构和布图方法
CN113690303A (zh) * 2020-05-18 2021-11-23 华润微电子（重庆）有限公司 半导体器件及其制备方法
CN114420761A (zh) * 2022-03-30 2022-04-29 成都功成半导体有限公司 一种耐高压碳化硅器件及其制备方法
CN114420761B (zh) * 2022-03-30 2022-06-07 成都功成半导体有限公司 一种耐高压碳化硅器件及其制备方法

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