WO2016117410A1 - 信号伝達装置 - Google Patents
信号伝達装置 Download PDFInfo
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- WO2016117410A1 WO2016117410A1 PCT/JP2016/050677 JP2016050677W WO2016117410A1 WO 2016117410 A1 WO2016117410 A1 WO 2016117410A1 JP 2016050677 W JP2016050677 W JP 2016050677W WO 2016117410 A1 WO2016117410 A1 WO 2016117410A1
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- 230000008054 signal transmission Effects 0.000 title claims abstract description 92
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- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
- H03K17/691—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/493—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Definitions
- the present invention relates to a signal transmission device, and in particular, in a power conversion circuit (for example, an inverter), a low voltage region in which a control circuit (for example, a microcomputer) is disposed, and a semiconductor switch (for example, an IGBT (Insulated Gate Bipolar Transistor)) are disposed.
- the present invention relates to a signal transmission device for transmitting a gate drive signal for opening and closing a semiconductor switch from a control circuit to the semiconductor switch while electrically insulating the high voltage region.
- the signal transmission circuit device described in Patent Document 1 As an example of a device using a fine transformer formed on an integrated circuit.
- the receiving inductor is DC biased to the ground voltage or the power supply voltage. Further, only positive pulses among positive and negative pulse voltages induced in the receiving inductor are used for signal transmission.
- the present invention has been made to solve such a problem, and provides a signal transmission device that enables a stable signal transmission operation even when the delay time of the signal detection circuit varies while suppressing power consumption.
- the purpose is to obtain.
- the present invention operates with power from a first power supply, generates a transmission signal from an input signal, a transformer connected to the transmission circuit, operates with power from a second power supply, and transmits the transmission.
- a reception circuit that receives a transmission signal output from the circuit via the transformer, and the transformer includes a total of two transformers, a first transformer and a second transformer, and each transformer includes a transmission-side inductor and a reception-side.
- the transmission circuit is configured to input a transmission-side voltage signal composed of one or a plurality of pulses to the transmission terminal of the transmission-side inductor of the first transformer in synchronization with a rising edge of the input signal.
- the transmission side voltage signal composed of one or a plurality of pulses is applied to the transmission terminal of the transmission side inductor of the second transformer.
- Each of the two terminals of the receiving inductor of the first and second transformers is connected to the ground of the receiving circuit or the second power source, and the other terminals are
- the signal transmission device is connected to an input terminal of a signal detection circuit provided in the reception circuit via a capacitor, and the signal detection circuit includes a single-ended Schmitt trigger circuit.
- the ESD protection element connected to the transformer connecting terminal of the receiving circuit can be made unnecessary.
- the negative pulse generated in the side inductor can be used for signal transmission. As a result, signal transmission using both positive and negative pulses is possible, and stable signal transmission operation can be performed even when the delay time of the signal detection circuit varies. Further, by using a single-ended Schmitt trigger circuit for the signal detection circuit, a low power consumption receiver circuit can be configured.
- FIG. 5 is a diagram showing an equivalent circuit of the fine transformer shown in FIGS. 1 and 4.
- FIG. 7 is a diagram illustrating a transmission waveform and a reception waveform of the fine transformer illustrated in FIG. 6. It is a figure which shows the signal voltage which arises resulting from dV / dt noise. It is a figure which shows the simulation result of the signal voltage which originates in dV / dt noise when a receiving side inductor is biased to 2.5V. It is a figure which shows the simulation result of the signal voltage which originates in dV / dt noise when the receiving side inductor is DC biased to the ground level. It is a figure which shows the example of a signal detection circuit. It is a figure which shows the example of a signal detection circuit.
- FIG. 1 shows a configuration of a signal transmission device according to Embodiment 1 of the present invention.
- FIG. 2 shows signal waveforms at each terminal provided in the signal transmission device of FIG.
- the signal transmission device according to the first embodiment is roughly composed of a transformer 22, a transmission circuit 23, and a reception circuit 24.
- the signal transmission device includes a transmission pulse generation circuit 9, two transformers 22 (22a and 22b), two coupling capacitors 12, and two pairs as shown in FIG. Bias resistor 13, two single-ended Schmitt trigger circuits 14, and one RS flip-flop 15 are arranged.
- Each of the transformers 22a and 22b includes a pair of inductors, that is, a transmission-side inductor 10 and a reception-side inductor 11.
- the transformer 22a is a set signal transformer (first transformer)
- the transformer 22b is a reset signal transformer 22b (second transformer).
- the transmission pulse generation circuit 9 constitutes a transmission circuit 23, and the coupling capacitor 12, the bias resistor 13, the single-ended Schmitt trigger circuit 14, and the RS flip-flop 15 constitute a reception circuit 24. is doing.
- the single-ended Schmitt trigger circuit 14 constitutes a signal detection circuit.
- One of the two terminals of the transmission-side inductor 10 of the transformers 22a and 22b is connected to the ground GND1 of the transmission circuit 23, and the other terminal is connected to the output terminals S1 and R1 of the transmission pulse generation circuit 9. Yes.
- One of the two terminals of the receiving inductor 11 of the transformers 22a and 22b is connected to the ground level GND2 of the receiving circuit 24 and is DC biased to the ground level.
- the other terminal of the receiving inductor 11 is connected to the input terminals S4 and R4 of the single-ended Schmitt trigger circuit 14 via the coupling capacitor 12, respectively.
- a pair of bias resistors 13 is provided between each coupling capacitor 12 and the input terminals S4 and R4 of each single-ended Schmitt trigger circuit 14, respectively.
- the input terminals S4 and R4 of the single-ended Schmitt trigger circuit 14 are DC-biased by a bias resistor 13 to an intermediate voltage between the ground level GND2 and the power supply voltage VDD2.
- the power supply voltage VDD2 is 5V
- the resistance values of the bias resistors 13 are all 25 k ⁇ , so the DC bias voltage is set to 2.5V.
- the output terminals S 3 and R 3 of the single-ended Schmitt trigger circuit 14 are connected to the RS flip-flop 15.
- the transmission circuit 23 operates with power from the power supply VDD1 that is the first power supply.
- the transmission circuit 23 generates a transmission signal by the transmission pulse generation circuit 9 using an input signal IN input from the outside.
- the receiving circuit 24 operates with power from the power supply VDD2 that is the second power supply.
- the reception circuit 24 receives the transmission signal output from the transmission circuit 23 via the transformer 22.
- the transmission circuit 23 inputs a transmission-side voltage signal composed of a single pulse to the transmission terminal S1 of the transmission-side inductor 10 of the transformer 22a in synchronization with the rising edge of the input signal IN.
- the transmission circuit 23 inputs a transmission-side voltage signal composed of a single pulse to the transmission terminal R1 of the transmission-side inductor 10 of the transformer 22b in synchronization with the falling edge of the input signal IN.
- These single pulses are not necessarily a single pulse, and may be composed of a plurality of pulses.
- the transformer 22 and the receiving circuit 24 are formed on the same chip.
- the upper threshold voltage VSPH and the lower threshold voltage VSPL of the single-ended Schmitt trigger circuit 14 constituting the signal detection circuit are set so as to satisfy the following two conditions. (Condition 1): Voltages of the terminals S2 and R2 of the receiving inductor 11 of the transformers 22a and 22b when no input signal IN is input (or, if the bias resistor 13 is provided, the terminals S4 and S4). R4 voltage) is between the upper threshold voltage VSPH and the lower threshold voltage VSPL of the single-ended Schmitt trigger circuit 14.
- FIG. 5 shows signal waveforms at various parts on the signal transmission circuit shown in FIG.
- the signal transmission circuit in the comparative example shown in FIG. 4 includes a transmission pulse generation circuit 9, two transformers 22, a signal detection circuit 16, and an RS flip-flop 15. 1 is different from FIG. 1 in that the coupling capacitor 12, the bias resistor 13, and the single-ended Schmitt trigger circuit 14 shown in FIG. 1 are not provided, but a signal detection circuit 16 is provided instead. It has been.
- One end of the reception-side inductor 11 of the transformer 22 is connected to the reception-side ground GND2, and the other end (S2 and R2) is connected to the input terminal (+) of the signal detection circuit 16.
- the signal detection circuit 16 compares the voltages S2 and R2 input to the input terminal (+) with the reference voltage VREF and outputs a comparison result.
- a differential input comparator is used as the signal detection circuit 16.
- a configuration example of the differential input comparator is shown in FIGS. 11A and 11B.
- the output terminals S3 and R3 of the signal detection circuit 16 are connected to the set terminal (S) and the reset terminal (R) of the RS flip-flop 15.
- the RS flip-flop 15 outputs a signal voltage to the output terminal OUT according to the input of the set terminal (S) and the reset terminal (R).
- FIG. 5 shows signal waveforms at various parts on the circuit of FIG.
- the transmission pulse generation circuit 9 outputs a rectangular wave (voltage pulse) to the terminal S1 at the rising edge of the input signal IN. Further, the transmission pulse generation circuit 9 outputs a rectangular wave (voltage pulse) to the terminal R1 at the falling edge of the input signal IN.
- a voltage pulse is applied to the transmission-side inductor 10 of the transformer 22, a voltage is induced at the terminals S2 and R2 of the reception-side inductor 11.
- the signal detection circuit 16 compares the voltages S2 and R2 with the reference voltage VREF .
- the signal detection circuit 16 When the voltages of S2 and R2 are larger than V REF , the signal detection circuit 16 outputs a voltage equal to the power supply voltage VDD2 (hereinafter referred to as H). On the other hand, when the voltages of S2 and R2 are smaller than V REF , the signal detection circuit 16 outputs a voltage equal to the ground voltage GND2 (hereinafter referred to as L) to the terminals S3 and R3.
- the RS flip-flop 15 outputs a voltage corresponding to the input of the set terminal (S) and the reset terminal (R) to the output terminal OUT.
- the voltage according to the input of the set terminal (S) and the reset terminal (R) is a rising edge when the voltage from the terminal S3 input to the set terminal (S) becomes H, and the reset terminal ( This is a pulse signal having a falling edge when the voltage from the terminal R3 input to R) becomes H.
- the same voltage waveform as that of the input signal IN is reproduced at the output terminal OUT.
- only positive pulses are used for signal transmission, as can be seen by comparing S2 and S3 and comparing R2 and R3.
- FIG. 7 An equivalent circuit of the transformer 22 shown in FIG. 6 is a fine transformer formed on an integrated circuit.
- the inductance L of such a fine transformer is as small as about 100 nH, while the parasitic resistance R p is about 100 ⁇ .
- the response of such a transformer to a step voltage input is shown in FIG.
- the horizontal axis represents time. 7 represents the input voltage V IN and the output voltage V OUT shown in the circuit diagram of FIG.
- the signal detection circuit 16 is required to have high-speed response.
- FIG. 8 shows signal waveforms generated on the receiving side of the transformer when a rectangular wave is input to the transmitting side of the transformer.
- the horizontal axis represents time. 8 represents the input voltage V IN and the output voltage V OUT shown in the circuit diagram of FIG.
- a positive signal and a negative signal are generated on the reception side in response to the rising and falling edges of the transmission-side rectangular wave.
- signal transmission is performed using only positive pulses among them.
- the amplitude of the negative pulse is intentionally reduced by shortening the rise time of the transmission-side voltage waveform and lengthening the fall time. Thus, signal transmission is performed only with positive pulses.
- Patent Documents 2 and 3 Although the difference between Patent Documents 2 and 3 and the first embodiment will be described later, the configuration of the transmission / reception circuit described in Patent Documents 2 and 3 will be briefly described here.
- a set signal and a reset signal are transmitted by using a pair of transformers and changing the direction of current flowing through the transformer.
- one end of the receiving-side inductor is connected to a single-ended Schmitt trigger circuit via a capacitor.
- the receiving-side inductor 11 is DC biased to the ground voltage or the power supply voltage. This is due to the following reasons.
- FIG. 3 shows an example of a case where the signal transmission device 1 is used in a power conversion circuit.
- the power conversion circuit has a low voltage region 17 and a high voltage region 18.
- the control circuit 2 is arranged in the low voltage region 17.
- the control circuit 2 is composed of, for example, a microcomputer.
- the gate drive circuit 4 In the high voltage region 18, the gate drive circuit 4, the semiconductor switch 5, the high voltage power supply 6, the AC output terminal 7, and the free wheel diode 8 are arranged.
- the signal transmission device 1 It is electrically separated by.
- the gate drive signal 3 generated by the control circuit 2 is input to the gate drive circuit 4 through the signal transmission device 1.
- the gate drive circuit 4 opens and closes the semiconductor switch 5 according to the gate drive signal 3.
- a voltage severe to several thousand volts generated by the high-voltage power supply 6 from the ground level is applied to the AC output terminal 7 of the power conversion circuit according to the ON state time of the semiconductor switch 5.
- AC voltage in the range up to the level is generated.
- the horizontal axis represents time.
- 10A and 10B indicate the input voltage V IN and the output voltage V OUT .
- the transmission pulse generation circuit 9 generates a pulse at the terminal S1 at the rising edge of the input signal IN and simultaneously generates a pulse at the terminal R1 at the falling edge of the input signal IN.
- a voltage signal is generated at the receiving terminals S2 and R2 of the transformer 22 in accordance with the voltages of the transmitting terminals S1 and R1 of the transformer 22. As shown in FIG. 2, the voltage signals generated at the terminals S2 and R2 are a positive pulse and a negative pulse centered on the ground level.
- FIG. 12A A circuit configuration of the single-ended Schmitt trigger circuit 14 is shown in FIG. 12A.
- the single-ended Schmitt trigger circuit 14 includes three NMOSs (M1, M2, M3) and three PMOSs (M4, M5, M6).
- the circuit of FIG. 12A has only one input terminal.
- the single-ended type means a circuit that inputs a voltage signal based on the ground level, and is compared with a circuit that inputs a voltage difference between two input terminals as shown in FIGS. 11A and 11B. It is a designation.
- the operation of the single-ended Schmitt trigger circuit 14 is shown in FIG. 12B.
- FIG. 12B shows the relationship between the input voltage V IN and the output voltage V OUT .
- the horizontal axis represents the input voltage V IN and the vertical axis represents the output voltage V OUT .
- 12A is a CMOS (Complementary Metal-Oxide-Semiconductor) inverter 30 composed of M1 and M5.
- CMOS inverters 30 M1 and M5 when the input voltage V IN is lower than the preset threshold output voltage V OUT becomes H, when the input voltage V IN is higher than the threshold output voltage V OUT becomes L.
- the input voltage at which the output voltage V OUT changes from H to L is the switching point voltage V SP .
- M2 and M3 serve to shift the switching point voltage V SP to the switching point voltage V SPH on the high voltage side when the input V IN changes from L to H
- M4 and M6 are When the input voltage V IN changes from H to L, the switching point voltage V SP is shifted to the switching point voltage V SPL on the low voltage side.
- the coupling capacitor 12 and the bias resistor 13 do not exist and one end of the receiving inductor 11 is directly connected to the input terminal of the single-ended Schmitt trigger circuit 14, the following is performed. Problems arise.
- the current that can flow through the transmission-side inductor 10 has an upper limit because the current consumption cannot be increased very much. Further, the signal voltage generated in the receiving-side inductor 11 is often 1 ⁇ 2 or less of the power supply voltage. In this case, the switching point voltages V SPH and V SPL of the single-ended Schmitt trigger circuit 14 need to be smaller than 1 ⁇ 2 of the power supply voltage.
- V SPH is higher than the switching point voltage V SP of the CMOS inverter 30 composed of M1 and M5 and V SPL is lower than V SP
- the switching point voltage V SP of the CMOS inverter 30 is also the power supply voltage. It is necessary to set it smaller than 1/2. In this case, as shown in FIG. 13A and FIG. 13B, it is necessary to reduce the current driving force of M5 compared to M1, thereby increasing the time required to charge the output terminal, resulting in an output voltage of The delay time when changing from L to H becomes long, and it becomes impossible to follow a signal pulse having a pulse width of about 1 ns.
- 11A and 11B can be used for the signal detection circuit even if the signal voltage generated in the receiving-side inductor 11 is 1 ⁇ 2 or less of the power supply voltage.
- the signal voltage generated in the receiving-side inductor 11 is 1 ⁇ 2 or less of the power supply voltage.
- both the high voltage side switching point V SPH and the low voltage side switching point voltage V SPL are within the amplitude of the positive pulse.
- the positive pulse crosses the high voltage side switching point V SPH and the negative pulse is low.
- the voltage is set so as to cross the voltage side switching point voltage V SPL . In this way, by setting the switching point voltages V SPH and V SPL , the requirement for the delay time that the single-ended Schmitt trigger circuit 14 should satisfy is alleviated. This is illustrated in FIGS. 15A and 15B.
- FIGS. 24A and 24B the definition of the delay time of the Schmitt trigger circuit is shown in FIGS. 24A and 24B.
- the delay time from the time when the input signal S4 of the Schmitt trigger circuit exceeds V SPH to the time when the output signal S3 of the Schmitt trigger circuit falls below the threshold voltage of the logic circuit of the next stage is t pdLH.
- the delay time from the time when the input signal S4 of the Schmitt trigger circuit falls below V SPL to the time when the output signal S3 of the Schmitt trigger circuit exceeds the threshold voltage of the logic circuit of the next stage is represented by t pdHL.
- the delay time of the Schmitt trigger circuit varies depending on semiconductor manufacturing process variations, temperature, power supply voltage, and the value of parasitic capacitance caused by wiring delay.
- the delay time of the Schmitt trigger varies and becomes longer than the preset upper limit value, as shown in FIG. 23, the output S3 of the Schmitt trigger circuit does not reach the subsequent logic threshold voltage. It will malfunction.
- the switching point voltages V SPH and V SPL are set and signals using both positive and negative pulses as in the first embodiment shown in FIG. 14B. There is a need to communicate.
- FIG. 16B shows a chip configuration of the signal transmission circuit according to the first embodiment.
- the transformer 22 and the receiving circuit 24 are configured on the same chip. If the transformer 22 and the receiving circuit 24 are configured on separate chips as shown in FIG. 16A, the transformer 22 and the receiving circuit 24 are connected by a wire 25. At this time, in order to prevent the destruction of the chip due to electrostatic discharge (Electrostatic Discharge, ESD), it is necessary to add an ESD protection element 26 to the transformer connection portion of the receiving circuit 24 as shown in FIG.
- ESD Electrostatic Discharge
- the diode connected as the ESD protection element 26 is forward-biased. Therefore, a negative voltage exceeding the forward voltage of the diode is present at the terminal S2. Does not occur. Therefore, the negative pulse generated in the receiving inductor 11 cannot be used for signal transmission.
- the first embodiment as shown in FIG. 16B, since the transformer 22 and the receiving circuit 24 are configured on the same chip, it is necessary to add the ESD protection element 26 to the transformer connection terminal of the receiving circuit 24. Instead, the negative pulse generated at the terminal S2 of the receiving inductor 11 can be used for signal transmission.
- VDC is a DC bias voltage at the input of the single-ended Schmitt trigger circuit 14.
- the circuit of Patent Document 2 is compared with the circuit of the first embodiment.
- a single-end Schmitt trigger is used because a set signal and a reset signal are transmitted by changing the direction of current flowing through the transformer using a single transformer. Since the circuit cannot be used, it is necessary to use a differential input comparator for signal detection, which increases power consumption.
- the single-ended Schmitt trigger circuit 14 can be used, thereby reducing power consumption. There is a merit that you can.
- the circuit of Patent Document 3 is compared with the circuit of the first embodiment.
- one end of the receiving-side inductor is connected to a single-ended Schmitt trigger circuit via a capacitor.
- the set signal and the reset signal are distinguished by changing the direction of the current flowing through the transmission-side inductor.
- control for increasing the rising speed of the transmission voltage and reducing the falling speed is necessary, which complicates the transmission circuit.
- the voltage waveform applied to the transmission side does not need to control the rising speed and the falling speed, and can be realized with a simple circuit configuration.
- a circuit that changes a transmission voltage waveform by a combination of a PWM signal and a clock signal is necessary, and the transmission circuit becomes more complicated. That is, the circuit according to the first embodiment is superior in terms of circuit scale.
- FIG. 18 shows a simulation result when a gate drive signal is transmitted using the signal transmission circuit of the first embodiment.
- the horizontal axis indicates time.
- Each symbol on the vertical axis corresponds to each terminal in FIG. VIN represents an input voltage, and VOUT represents an output voltage.
- the output signal S3 of the single-ended Schmitt trigger circuit 14 is constant. It can be seen that it has a pulse width.
- FIG. 19 shows a simulation result when a 25 kV / ⁇ s dV / dt noise is applied to the signal transmission circuit of the first embodiment.
- the horizontal axis indicates time.
- Each symbol on the vertical axis corresponds to each terminal in FIG. VIN represents an input voltage, and VOUT represents an output voltage.
- dV / dt noise having an amplitude of 200 V and a rise and fall time of 8 ns is applied to VIN.
- the voltage signal generated in the receiving-side inductor 11 is very small, and the output signal S3 of the single-ended Schmitt trigger circuit 14 is inverted. It can be seen that the circuit is not malfunctioning.
- one or more transmission circuits 23 are connected to the transmission terminal S1 of the transmission-side inductor 10 of the transformer 22a in synchronization with the rising edge of the input signal IN.
- a transmission-side voltage signal consisting of one or more pulses is input to the transmission terminal R1 of the transmission-side inductor 10 of the transformer 22b in synchronization with the falling edge of the input signal IN.
- one of the two terminals of the receiving inductor 11 of the transformers 22a and 22b is connected to the ground of the receiving circuit 24 or the power supply VDD2, and the other terminal detects the signal of the receiving circuit 24 via the coupling capacitor 12. It is connected to the input terminal of the circuit.
- the signal detection circuit is composed of a single-ended Schmitt trigger circuit 14. Further, as shown in FIG. 2, the upper threshold voltage VSPH and the lower threshold voltage VSPL of the single-ended Schmitt trigger circuit 14 are compared with those of the transformers 22a and 22b when no input signal IN is input.
- the voltage at the terminals S2, R2 (or S4, R4) of the receiving inductor 11 is between the upper threshold voltage VSPH and the lower threshold voltage VSPL of the single-ended Schmitt trigger circuit 14, and At the rising edge of the transmission side voltage signal input to the transmission terminals S1 and R1 of the transmission side inductor 10 of the transformers 22a and 22b, the terminals S2 and R2 (or S4 and R4) of the reception side inductor 11 of the transformers 22a and 22b.
- the single-ended Schmitt trigger circuit 14 is set to be lower than the lower threshold voltage VSPL. Further, as shown in FIG. 16B, the transformer 22 and the receiving circuit 24 are formed on the same chip.
- the transformers 22a and 22b and the receiving circuit 24 are formed on the same chip as described above, the ESD protection element connected to the transformer connecting terminal of the receiving circuit 24 can be removed.
- the negative pulse generated in the receiving-side inductor 11 can be used for signal transmission.
- signal transmission using both positive and negative pulses is possible, and stable signal transmission operation can be performed even when the delay time of the signal detection circuit varies.
- a single-ended Schmitt trigger circuit for the signal detection circuit a low power consumption receiver circuit can be configured.
- the upper threshold voltage VSPH of the single-ended Schmitt trigger circuit 14 is the allowable change rate dV / of the transformer parasitic capacitance Cp of the transformers 22a and 22b and the input common mode voltage V.
- a current having a value obtained by multiplying dt is passed through the transformer parasitic capacitance 20 of the reception-side inductor 11 and the bias resistor 13 of the DC bias setting circuit provided in the reception-side inductor 11, and is higher than the voltage generated at that time.
- Embodiment 2 the output signal of the single-ended Schmitt trigger circuit 14 is directly input to the RS flip-flop 15 as shown in FIG.
- the single-ended Schmitt trigger circuit 14 may malfunction and the two circuits may output L simultaneously. Can happen.
- a malfunction prevention circuit 27 due to common-mode noise may be inserted between the single-ended Schmitt trigger circuit 14 and the RS flip-flop 15 as shown in FIG.
- the single-ended Schmitt trigger circuit 14 includes three NMOSs (M1, M2, M3) and three PMOSs (M4, M5, M6) as shown in FIGS. 12A and 12B.
- the present invention is not limited to this, and the single-ended Schmitt trigger circuit 14 uses three NMOSs (M1, M2, M3) and one PMOS (M5) as shown in FIG. 21A.
- one NMOS (M1) and three PMOSs (M4, M5, M6) as shown in FIG. 21B may be used.
- the transmission pulse generation circuit 9 generates a single pulse at the terminal S1 at the rising edge of the input signal IN, and a single pulse at the terminal R1 at the falling edge of the input signal IN.
- the present invention is not limited to this case, and in order to improve the accuracy of signal transmission, an arbitrary number of two or more pulses may be generated as shown in FIG. In this case, even if a malfunction occurs in the first pulse, the signal is corrected by any one of the subsequent pulses after the second pulse.
- Embodiment 5 FIG.
- the transformers 22a and 22b and the receiving circuit 24 are formed on the same chip, so that the ESD protection element connected to the transformer connecting terminal of the receiving circuit 24 can be removed. It has been described that the negative pulse generated in the inductor 11 can be used for signal transmission.
- the ESD protection element of the receiving circuit 24 is connected in multiple stages, thereby generating a negative current generated in the receiving inductor. This pulse can be used for signal transmission.
- FIG. 25 shows a signal transmission circuit according to the fifth embodiment.
- FIG. 25 shows a configuration in which the transformer 22 and the receiving circuit 24 are configured as separate chips as shown in FIG. 16A and the ESD protection elements 28 connected to the GND 2 included in the receiving circuit 24 are connected in multiple stages.
- the ESD protection element 28 is provided between the connection point between the terminal S2 of the reception-side inductor 11 and the coupling capacitor 12 and GND2 of the reception circuit 24. Is provided. Similarly, an ESD protection element 28 is provided between a connection point between the terminal R2 of the reception-side inductor 11 and the coupling capacitor 12 and GND2 of the reception circuit 24. In this way, each ESD protection element 28 is connected in series between the input terminals S2 and R2 of the receiving circuit 24 that receives the transmission signal from the transmitting circuit 23 and the GND2. Moreover, these ESD protection elements 28 are provided in parallel so as to constitute a multistage. In the example of FIG. 25, the ESD protection element 28 is provided in two stages. Note that the number of stages is not limited to two and may be an arbitrary number.
- the transformer 22 and the receiving circuit 24 are configured as separate chips, and the ESD protection elements 28 connected to the GND 2 provided in the receiving circuit 24 are connected in multiple stages, thereby suppressing chip destruction due to electrostatic discharge.
- negative pulses generated at the terminals S2 and R2 of the receiving inductor 11 can be used for signal transmission.
- the ESD protection elements 28 connected in multiple stages need to be set so as not to operate with a negative pulse voltage generated by signal transmission but to operate with electrostatic discharge. For example, when both positive and negative pulse voltages generated by signal transmission are ⁇ 1V with respect to GND2, and the forward voltage drop (VF) of the ESD protection element 28 is 0.6V, the ESD protection elements 28 connected to GND2 are connected in series.
- the ESD protection element 28 does not operate at a negative pulse voltage ⁇ 1V generated by signal transmission by being stacked in two stages, and the ESD protection element operates at a double forward voltage drop (VF) ⁇ 1.2V or less. .
- VF forward voltage drop
- the ESD protection elements 28 connected in multiple stages It does not operate with the received signal of the receiving circuit 24 generated by transmission, but operates with electrostatic discharge.
- the transformer 22 and the receiving circuit 24 are configured as separate chips, and the ESD protection elements connected to the GND 2 provided in the receiving circuit 24 are connected in multiple stages, thereby breaking the chip due to electrostatic discharge. , And negative pulses generated at the terminals S2 and R2 of the receiving inductor 11 can be used for signal transmission.
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Abstract
Description
図1に、本発明の実施の形態1に係る信号伝達装置の構成を示す。また、図2に、図1の信号伝達装置に設けられた各端子における信号波形を示す。図1の各端子の符号と図2の各端子の符号とは一致している。図1に示すように、本実施の形態1に係る信号伝達装置は、大きく分けて、トランス22と、送信回路23と、受信回路24とから構成されている。
また、受信回路24は、第2の電源である電源VDD2からの電力で動作する。受信回路24は、送信回路23が出力する送信信号をトランス22を介して受信する。
送信回路23は、図2に示すように、入力信号INの立ち上がりエッジに同期して、トランス22aの送信側インダクタ10の送信端子S1に、単一のパルスからなる送信側電圧信号を入力する。また、送信回路23は、入力信号INの立下りエッジに同期して、トランス22bの送信側インダクタ10の送信端子R1に、単一のパルスからなる送信側電圧信号を入力する。なお、これらの単一のパルスは、必ずしも単一である必要はなく、複数のパルスから構成されていてもよい。
また、後述する図16Bに示すように、トランス22と受信回路24とは、同一チップ上に形成されている。
(条件1):入力信号INが入力されていない無信号時のトランス22a,22bの受信側インダクタ11の端子S2,R2の電圧(あるいは、バイアス抵抗13が設けられている場合は、端子S4,R4の電圧)が、シングルエンド型シュミットトリガ回路14の上側しきい値電圧VSPHと下側しきい値電圧VSPLとの間にある。
(条件2):トランス22a,22bの送信側インダクタ10の送信端子S1,R1に入力される信号(送信側電圧信号)の立ち上がりエッジで、トランス22a,22bの受信側インダクタ11の端子S2,R2の電圧(または、端子S4,R4の電圧)が、シングルエンド型シュミットトリガ回路14の上側しきい値電圧VSPHよりも高くなり、当該信号(送信側電圧信号)の立ち下がりエッジで、端子S2,R2の電圧(または、端子S4,R4の電圧)が、シングルエンド型シュミットトリガ回路14の下側しきい値電圧VSPLよりも低くなる。
制御回路2が配置された低電圧領域17と、半導体スイッチ5が置かれた高電圧領域18との間は、制御回路2の誤動作を防ぐため、及び、感電防止のために、信号伝達装置1によって電気的に分離されている。
制御回路2が発生するゲート駆動信号3は、信号伝達装置1を通じて、ゲート駆動回路4に入力される。ゲート駆動回路4は、ゲート駆動信号3に従って、半導体スイッチ5の開閉を行う。半導体スイッチ5の開閉が行われると、半導体スイッチ5のON状態の時間に応じて、電力変換回路の交流出力端子7に、グラウンドレベルから高圧電源6で生成される電圧(数百から数千V)レベルまでの範囲の交流電圧が発生する。
本実施の形態では、このように、トランス22a,22bと受信回路24とを同一のチップ上に形成することにより、受信回路24のトランス接続端子に接続するESD保護素子を除くことができるため、受信側インダクタ11に発生する負のパルスを信号伝達に使用できるようになる。これによって、正パルスと負パルスの両方を用いた信号伝達が可能になり、信号検出回路の遅延時間がばらついた場合にも安定した信号伝達動作を行うことが可能になる。また、シングルエンド型シュミットトリガ回路を信号検出回路に用いることによって、低消費電力の受信回路を構成できる。
上述の実施の形態1では、図1に示すように、シングルエンド型シュミットトリガ回路14の出力信号が、直接、RSフリップフロップ15に入力されていた。しかしながら、許容限度として予め設定された値を超える大きさのdV/dtノイズが印加された場合には、シングルエンド型シュミットトリガ回路14が誤動作して、2つの回路が同時にLを出力する場合が起こり得る。このような誤動作を防ぐために、図20に示すように、同相ノイズによる誤動作防止回路27を、シングルエンド型シュミットトリガ回路14とRSフリップフロップ15との間に挿入しても良い。dV/dtノイズはセット信号用のトランス22とリセット信号用のトランス22の両方に印加されるため、同相ノイズによる誤動作防止回路27の入力端子IN1及びIN2(S3及びR3)の入力はどちらもLとなるが、その2つの出力はHに維持されるため、RSフリップフロップ15に設定された値が変化することはない。
上述の実施の形態1では、シングルエンド型シュミットトリガ回路14として、図12Aおよび図12Bに示すように、3つのNMOS(M1,M2,M3)と3つのPMOS(M4,M5,M6)から構成されるものを用いたが、その場合に限らず、シングルエンド型シュミットトリガ回路14として、図21Aに示すようなNMOSを3個(M1,M2,M3)およびPMOSを1個(M5)用いるものであっても、あるいは、図21Bに示すようなNMOSを1個(M1)およびPMOSを3個(M4,M5,M6)用いるものであってもよい。
上述の実施の形態1では、送信パルス生成回路9は、入力信号INの立ち上がりエッジにおいて、端子S1に単一のパルスを生成し、入力信号INの立ち下がりエッジにおいて、端子R1に単一のパルスを形成したが、その場合に限らず、信号伝達の精度を高めるために、図22に示すように、2発以上の任意の個数の複数のパルスを発生してもよい。この場合、1発目のパルスで誤動作が生じても、後続の2発目以降のいずれかのパルスによって信号の訂正が行われる。
上述の実施の形態1では、トランス22a,22bと受信回路24とを同一のチップ上に形成することにより、受信回路24のトランス接続端子に接続するESD保護素子を除くことができるため、受信側インダクタ11に発生する負のパルスを信号伝達に使用できるようになると説明した。実施の形態5では、図16Aに示すようにトランス22と受信回路24が別々のチップに構成されている場合に、受信回路24のESD保護素子を多段接続することで受信側インダクタに発生する負のパルスを信号伝達として使用可能とした。
Claims (6)
- 第1の電源からの電力で動作し、入力信号から送信信号を生成する送信回路と、
前記送信回路に接続されたトランスと、
第2の電源からの電力で動作し、前記送信回路が出力する送信信号を前記トランスを介して受信する受信回路と
を備え、
前記トランスは、第1のトランスと第2のトランスの合計2つのトランスを含み、各トランスは送信側インダクタと受信側インダクタとから構成され、
前記送信回路は、前記入力信号の立ち上がりエッジに同期して、前記第1のトランスの前記送信側インダクタの送信端子に、単数または複数のパルスからなる送信側電圧信号を入力し、前記入力信号の立下りエッジに同期して、前記第2のトランスの前記送信側インダクタの送信端子に、単数または複数のパルスからなる送信側電圧信号を入力し、
前記第1及び第2のトランスの前記受信側インダクタの2つの端子のうちの一方の各端子は、前記受信回路のグラウンドまたは前記第2の電源に接続され、他方の各端子は、容量を介して前記受信回路に設けられた信号検出回路の入力端子に接続され、
前記信号検出回路はシングルエンド型シュミットトリガ回路から構成される
信号伝達装置。 - 無信号時の前記第1及び第2のトランスの前記受信側インダクタの前記他方の各端子の電圧が、前記シングルエンド型シュミットトリガ回路の上側しきい値電圧と下側しきい値電圧の間にあり、且つ、前記第1及び前記第2のトランスの前記送信側インダクタの前記送信端子に入力される前記送信側電圧信号の立ち上がりエッジで、前記第1及び第2のトランスの前記受信側インダクタの前記他方の各端子の電圧が、前記シングルエンド型シュミットトリガ回路の前記上側しきい値電圧よりも高くなり、前記第1及び前記第2のトランスの前記送信側インダクタの前記送信端子に入力される前記送信側電圧信号の立ち下がりエッジで、前記第1及び第2のトランスの前記受信側インダクタの前記他方の各端子の電圧が、前記シングルエンド型シュミットトリガ回路の前記下側しきい値電圧よりも低くなるように、前記シングルエンド型シュミットトリガ回路の前記上側及び下側しきい値電圧が設定される
請求項1に記載の信号伝達装置。 - 前記シングルエンド型シュミットトリガ回路の前記上側しきい値電圧は、
前記第1及び第2のトランスのトランス寄生容量と入力コモンモード電圧の許容し得る変化速度とを乗算した値の電流を、前記受信側インダクタの寄生容量と前記受信側インダクタに設けられたDCバイアス設定回路のバイアス抵抗とに流した際に発生する電圧よりも高い値に設定される
請求項2に記載の信号伝達装置。 - 前記第1及び第2のトランスと前記受信回路とは、同一チップ上に形成されている
請求項1に記載の信号伝達装置。 - 前記第1及び第2のトランスと前記受信回路とは、別々のチップで形成され、
前記送信回路からの送信信号を受信する前記受信回路の入力端子とグラウンドとの間に直列で多段に接続されたESD保護素子を備える
請求項1に記載の信号伝達装置。 - 前記多段に接続されたESD保護素子の順方向降下電圧は、前記受信回路側のグラウンド電位以下の受信信号の振幅よりも大きく設定され、
前記多段接続されたESD保護素子は、信号伝達で生じる前記受信回路の受信信号では動作せずに、静電気放電で動作する
請求項5に記載の信号伝達装置。
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US20180013424A1 (en) | 2018-01-11 |
DE112016000392T5 (de) | 2017-10-05 |
DE112016000392B4 (de) | 2023-12-07 |
JP6272509B2 (ja) | 2018-01-31 |
US10014856B2 (en) | 2018-07-03 |
CN107210977A (zh) | 2017-09-26 |
CN107210977B (zh) | 2020-06-26 |
JPWO2016117410A1 (ja) | 2017-09-07 |
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