WO2016110970A1 - Procédé de fabrication de cellule solaire - Google Patents

Procédé de fabrication de cellule solaire Download PDF

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Publication number
WO2016110970A1
WO2016110970A1 PCT/JP2015/050285 JP2015050285W WO2016110970A1 WO 2016110970 A1 WO2016110970 A1 WO 2016110970A1 JP 2015050285 W JP2015050285 W JP 2015050285W WO 2016110970 A1 WO2016110970 A1 WO 2016110970A1
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Prior art keywords
wafer
defect
semiconductor wafer
normal
pair
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PCT/JP2015/050285
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English (en)
Japanese (ja)
Inventor
唐木田　昇市
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三菱電機株式会社
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Priority to PCT/JP2015/050285 priority Critical patent/WO2016110970A1/fr
Priority to JP2016568216A priority patent/JPWO2016110970A1/ja
Publication of WO2016110970A1 publication Critical patent/WO2016110970A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a solar cell using a semiconductor substrate.
  • the module filling rate in order to improve the substantial energy conversion efficiency based on the module area. Therefore, as a method for increasing the module filling rate, a method of processing and arranging solar cells into a square shape is generally performed. In this method, the disk-shaped semiconductor wafer is cut into a quadrangular shape, which causes a problem of loss of the semiconductor wafer.
  • Patent Document 1 in order to eliminate the loss of the semiconductor wafer and increase the module filling rate to improve the energy conversion efficiency, it was produced by connecting the solar cells divided by cutting one wafer. A solar cell module is disclosed.
  • Patent Document 1 it is assumed that a semiconductor wafer that satisfies the specifications is used, and the loss of the semiconductor wafer due to the generation of a semiconductor wafer that does not satisfy the specifications is not taken into consideration.
  • the semiconductor wafer is inspected for crystal defects and appearance before being put into the production line for solar cells. Semiconductor wafers that do not satisfy the specifications are excluded as defective products and are not put into the production line for solar cells.
  • Defective semiconductor wafers that do not satisfy the specifications can be recycled as scrap wafers.
  • all of the defective semiconductor wafers are scrap wafers, there is a problem that the loss of the semiconductor wafers increases and the production yield of the semiconductor wafers decreases. Therefore, in order to further reduce the loss of the semiconductor wafer in the manufacturing process of the solar battery cell, further effective use of the semiconductor wafer is necessary.
  • the present invention has been made in view of the above, and an object of the present invention is to obtain a solar cell manufacturing method capable of manufacturing solar cells by effectively using a semiconductor wafer that does not satisfy the specifications.
  • the present invention provides a first inspection of a crystal defect defect and an appearance defect on a first conductivity type semiconductor wafer having a square outer shape in a plane direction.
  • One step and the semiconductor wafer in which at least one of a crystal defect defect and an appearance defect is detected in the inspection, and is not less than half of the length of the pair of sides in the extending direction of the pair of sides in the square shape
  • a normal region having a normal region in the wafer in which the crystal defect defect or the appearance defect is not detected, the region extending over the entire length in the extending direction of the other pair of sides in the square shape.
  • a third step of forming a layer; a fourth step of forming a light-receiving surface side electrode in the normal region in the wafer on the impurity diffusion layer; and on the other surface facing the one surface in the selected partial normal semiconductor wafer In the fifth step of forming a back-side electrode in the normal region in the wafer and at any timing after the first step and after the end of the fifth step, the partial normal semiconductor wafer to the wafer And a sixth step of cutting out the inner normal region.
  • Sectional drawing which shows the principal part which shows the photovoltaic cell concerning Embodiment 1 of this invention. The flowchart explaining an example of the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention.
  • Sectional drawing explaining an example of the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention Sectional drawing explaining an example of the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention. Sectional drawing explaining an example of the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention. Sectional drawing explaining an example of the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention. Sectional drawing explaining an example of the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention.
  • Plan view of a wafer for explaining a half normal region according to the first embodiment of the present invention The top view which shows the state in which the silver paste was printed only with respect to the bisection area
  • the top view which shows the state which cut
  • Plane view of wafer for explaining half normal region according to second embodiment of the present invention Top view showing a half normal region in a wafer according to a second embodiment of the present invention.
  • FIG. 1 is a top view showing a solar battery cell 1 according to Embodiment 1 of the present invention.
  • FIG. 2 is a bottom view showing the solar battery cell 1 according to the first embodiment of the present invention.
  • FIG. 3 is a main part sectional view showing the solar battery cell 1 according to the first embodiment of the present invention, and is a main part sectional view of the solar battery cell 1 in the AA direction of FIG.
  • the n-type impurity diffusion layer 3 is formed by phosphorus diffusion on the light receiving surface side of the semiconductor substrate 2 made of p-type single crystal silicon, and the semiconductor substrate 11 has a pn junction. Is formed.
  • An antireflection film 4 made of a silicon nitride (SiN) film is formed on the n-type impurity diffusion layer 3.
  • the semiconductor substrate 2 is not limited to a p-type single crystal silicon substrate, and a p-type polycrystalline silicon substrate, an n-type polycrystalline silicon substrate, or an n-type single crystal silicon substrate may be used.
  • minute unevenness is formed as the texture structure 2 a on the light receiving surface side surface of the semiconductor substrate 11, that is, on the surface of the n-type impurity diffusion layer 3.
  • the micro unevenness increases the area for absorbing light from the outside on the light receiving surface, suppresses the reflectance on the light receiving surface, and has a structure for confining light.
  • the antireflection film 4 is made of a silicon nitride (SiN) film that is an insulating film.
  • the antireflection film 4 is not limited to a silicon nitride film, and may be formed of an insulating film such as a silicon oxide (SiO 2 ) film or a titanium oxide (TiO 2 ) film.
  • a plurality of long and narrow surface silver grid electrodes 5 are arranged side by side on the light receiving surface side of the semiconductor substrate 11, and a surface silver bus electrode 6 electrically connected to the surface silver grid electrode 5 is orthogonal to the surface silver grid electrode 5. Each of them is electrically connected to the n-type impurity diffusion layer 3 at the bottom portion.
  • the front silver grid electrode 5 and the front silver bus electrode 6 are made of a silver material.
  • the front silver grid electrode 5 has a width of about 100 ⁇ m to 200 ⁇ m and is arranged in parallel at intervals of about 2 mm, and collects electricity generated inside the semiconductor substrate 11. Further, the front silver bus electrodes 6 have a width of about 1 mm to 3 mm and are arranged for four solar cells, and take out the electricity collected by the front silver grid electrodes 5 to the outside.
  • the front silver grid electrode 5 and the front silver bus electrode 6 constitute a light receiving surface side electrode 12 which is a first electrode having a comb shape. Since the light receiving surface side electrode 12 blocks sunlight incident on the semiconductor substrate 11, it is preferable to reduce the area as much as possible from the viewpoint of improving the power generation efficiency. Therefore, the light receiving surface side electrode 12 is generally arranged as a comb-shaped surface silver grid electrode 5 and a bar-shaped surface silver bus electrode 6 as shown in FIG.
  • a silver paste is usually used, for example, lead boron glass is added.
  • This glass has a frit shape and is composed of, for example, lead (Pb) 5-30 wt%, boron (B) 5-10 wt%, silicon (Si) 5-15 wt%, and oxygen (O) 30-60 wt%.
  • lead (Pb) 5-30 wt%
  • boron (B) 5-10 wt%
  • silicon Si 5-15 wt%
  • oxygen (O) 30-60 wt% oxygen
  • zinc (Zn) or cadmium (Cd) may be mixed by several wt%.
  • Such lead boron glass has a property of melting by heating at several hundred degrees C. (for example, 800.degree. C.) and eroding silicon at that time.
  • a method of obtaining electrical contact between a silicon substrate and a silver paste by using the characteristics of the glass frit is used.
  • a back aluminum electrode 7 made of an aluminum material is provided over the entire surface except for a part of the outer edge region on the back surface, which is the surface facing the light receiving surface in the semiconductor substrate 11, and in the same direction as the front silver bus electrode 6
  • a back silver electrode 8 made of a silver material is provided.
  • the back aluminum electrode 7 and the back silver electrode 8 constitute a back electrode 13 as a second electrode.
  • the back aluminum electrode 7 is also expected to have a BSR (Back Surface Reflection) effect in which long wavelength light passing through the semiconductor substrate 11 is reflected and reused for power generation.
  • BSR Back Surface Reflection
  • a p + layer 9 which is a BSF (Back Surface Field) containing a high concentration impurity is formed on the surface layer portion on the back surface side of the semiconductor substrate 11.
  • the p + layer 9 is provided in order to obtain the BSF effect, and the electron concentration in the semiconductor substrate 2 is increased by an electric field having a band structure so that electrons in the semiconductor substrate 2 which is a p-type layer do not disappear.
  • the thus configured solar battery cell 1 has a pseudo-rectangular outer shape in the surface direction of the light-receiving surface, more specifically, a pseudo-rectangular shape.
  • the solar battery cell 1 is a half-cut cell having a size and a shape in which a solar battery cell having a pseudo-square shape is divided into two equal parts along a direction in which a pair of opposing sides extend in the outer shape. .
  • L the length of one side of the square shape in the solar cell having the pseudo-square shape
  • the length of the long side in the rectangular shape of the solar cell 1 is L
  • the length of the short side in the rectangular shape is L / 2. It is.
  • the pseudo-rectangular shape means a state in which the four corner portions are chamfered in the rectangular shape.
  • the pseudo-square shape means a state where the four corner portions are chamfered in the square shape.
  • the pseudo long shape of the outer shape of the solar battery cell 1 means a state in which a pair of corners located at both ends of one long side of the rectangular shape is chamfered among the four corners in the rectangular shape.
  • General solar cells are chamfered at the four corners of a square outer shape.
  • the chamfering is, for example, 45 ° chamfering or round chamfering.
  • Round chamfering is not a positively formed product, but a shape that occurs in order to use a silicon wafer having a circular outer shape as effectively as possible.
  • a pair of corners located at both ends of one long side in a rectangular shape are chamfered to form a chamfer 15a and a chamfer 15b.
  • the front silver grid electrode 5 is arranged along the direction in which the long side of the rectangular shape extends.
  • the front silver bus electrode 6 is arranged along the direction in which the short side of the rectangular shape extends.
  • the solar battery cell 1 is a solar battery cell manufactured using a semiconductor wafer that does not satisfy the specifications as a result of inspection of crystal defects and appearance. That is, the solar battery cell 1 is a solar battery cell manufactured using a scrap wafer that is not normally put into a solar cell manufacturing line.
  • FIG. 4 is a flowchart for explaining an example of the manufacturing process of the solar battery cell 1 according to the first embodiment of the present invention.
  • 5 to 11 are cross-sectional views for explaining an example of the manufacturing process of the solar battery cell 1 according to the first embodiment of the present invention.
  • a silicon wafer that is a semiconductor wafer is processed.
  • the silicon wafer is referred to as a wafer.
  • the outer periphery of a p-type single crystal ingot obtained by growing a molten silicon melt is ground so that the diameter is uniform.
  • a wafer having a thickness of about 0.2 mm is sliced from the single crystal ingot using a wire saw and cut into a desired outer shape.
  • the wafer is cut into a pseudo-square shape in which the outer shape in the surface direction has a square shape and the four corner portions of the outer shape are chamfered. That is, the wafer is cut into a polygonal shape.
  • the shape of the wafer may be a perfect square shape in which the four corners of the outer shape are not chamfered.
  • the surface of the wafer is cleaned to remove deposits on the wafer surface up to the previous step.
  • a p-type single crystal silicon wafer which is an as-sliced wafer having a thickness of about 170 ⁇ m to 230 ⁇ m is obtained.
  • the p-type single crystal silicon wafer has a pseudo-square shape in which the outer shape in the plane direction has a square shape and the four corners of the outer shape are chamfered.
  • step S20 the inspection of the crystal defects and the appearance of the wafer is performed using an inspection apparatus.
  • the inspection of crystal defects for example, crystal defects due to void defects in the wafer are detected by defect inspection using X-rays.
  • defect inspection for example, surface inspection using a laser detects appearance defects such as dirt, chipping, and scratches on the wafer.
  • step S30 it is determined whether or not the wafer satisfies a predetermined specification in the inspection of the inspection target wafer.
  • the inspection apparatus detects a crystal defect defect due to a void defect based on a predetermined determination criterion for a crystal defect defect in a wafer to be inspected, that is, if the wafer does not satisfy a predetermined specification ( In step S30, No), data on the detected crystal defect is input to the partial normal wafer determination apparatus.
  • Predetermined criteria for crystal defect defects are held in advance in the inspection apparatus.
  • the crystal defect defect data input from the inspection apparatus to the partial normal wafer determination apparatus includes crystal defect defect position data that is data of the position of the detected crystal defect defect in the plane of the wafer.
  • step S30 when the inspection apparatus detects an appearance defect such as dirt, chipping, or a scratch based on a predetermined criterion for appearance defect in the wafer to be inspected, that is, the wafer does not satisfy the predetermined specification. In that case (step S30, No), data on the detected appearance defect is input to the partial normal wafer determination apparatus. Predetermined criteria for appearance defects are stored in the inspection apparatus in advance.
  • the appearance defect data input from the inspection apparatus to the partially normal wafer determination apparatus includes appearance defect position data, which is data of the position of the detected appearance defect on the wafer.
  • step S120 the partial normal wafer determination device determines whether or not a half normal region exists in the surface of the wafer.
  • a partial normal wafer having a half normal region is selected.
  • the half normal region is defined by the in-plane of the wafer along a virtual line passing through the center of the wafer in the pseudo-square surface and along a direction in which a pair of opposing sides extend in the pseudo-square outer shape of the wafer.
  • One of the regions divided into two equal parts which is a continuous region in which no crystal defect defect and no appearance defect are detected.
  • the area that does not satisfy the specified specifications as a result of the inspection of crystal defects and appearance is less than half in the wafer plane, not the entire area in the wafer plane. This is a case where it is an area.
  • the partial normal wafer determination apparatus determines whether or not a half normal area exists in the wafer surface based on the crystal defect defect position data and the appearance defect position data input from the defect inspection apparatus and the surface inspection apparatus. Further, the partial normal wafer determination apparatus has a case where data relating to defects is input from only one of the defect inspection apparatus and the surface inspection apparatus, that is, only one of the crystal defect defect and the appearance defect is detected on the wafer. In this case, it is determined whether or not a half normal region exists in the wafer surface based on the inputted data on one defect.
  • step S120 if a half normal area exists in the wafer surface (step S120, Yes), a wafer having a half normal area is selected and the process proceeds to step S40 of the next process.
  • a semiconductor substrate 2 made of p-type single crystal silicon is obtained as shown in FIG.
  • the plane of the semiconductor substrate 2 made of p-type single crystal silicon there are continuous regions including a half normal region where no crystal defect defect and appearance defect are detected.
  • half normal area position information relating to the position of the half normal area in the surface of the wafer is held.
  • half normal area position information can be used in the process which processes to the position of a half normal area. That is, in the electrode forming process in step S180 and step S90 and the cutting process in step S110, the position of the half normal region can be specified and processed.
  • the wafer is recycled as a scrap wafer in step S130.
  • the in-plane of the wafer is equal to 2 etc. along a virtual line passing through the center of the wafer in the pseudo-square shape and along a direction in which a pair of opposite sides extend in the pseudo-square outline of the wafer.
  • crystal defect defect or an appearance defect in both of the divided areas There is a crystal defect defect or an appearance defect in both of the divided areas.
  • FIG. 12 is a plan view of the wafer 21 for explaining the half normal region according to the first embodiment of the present invention.
  • the wafer 21 is a wafer that does not satisfy the predetermined specifications in step S30.
  • the outer shape of the wafer 21 in the surface direction is a pseudo-square shape, and the corners of the four corners of the outer shape are chamfered to form a chamfered portion 15a, a chamfered portion 15b, a chamfered portion 15c, and a chamfered portion 15d.
  • the length of one side is L.
  • the wafer 21 has a crystal defect defect 31 and an appearance defect 32 that do not satisfy predetermined specifications in the plane.
  • the pair of sides 22 and 23 that extend through the center 21a of the wafer 21 in the pseudo-square shape and face each other in the pseudo-square shape of the wafer 21 extend in the X direction in FIG.
  • the regions where the in-plane surface of the wafer 21 is divided into two equal parts along the imaginary line BB one of the two equally divided regions Why on the side 22 side is a half normal region.
  • the distance between the side 22 and the virtual line BB is L / 2.
  • the other pair of sides 24 and 25 extending through the center 21a of the wafer 21 in the square surface and facing each other in the square shape of the wafer 21 extend, that is, Y in FIG.
  • one bisected region Whx on the side 25 side is a half normal region.
  • the region where the length in the Y direction between the side 22 and the crystal defect defect 31 in the Y direction in FIG. 12 is the normal length Ln includes the half normal region, and the crystal defect defect and the appearance defect.
  • the extension direction of the other pair of sides 22 and 23 in the pseudo-square shape is less than the length between the other pair of sides 22 and 23 in the pseudo-square shape. This is a region extending over the entire length of The normal area in the wafer is an area where no crystal defect defect or the appearance defect is detected.
  • step S30 the inspection apparatus does not detect a crystal defect due to a void defect based on a predetermined determination criterion and an appearance defect such as dirt, chipping, and scratches based on the predetermined determination criterion on the inspection target wafer. In this case, it is determined that the wafer satisfies the predetermined specification (step S30, Yes). In step S30, if the inspection apparatus determines that the wafer satisfies a predetermined specification, the process proceeds to step S40 of the next process.
  • step S40 a solar cell manufacturing method using the semiconductor substrate 2 made of p-type single crystal silicon, which is the wafer obtained in step S120, will be described, and the wafer obtained in step S30. Description of the case of using a p-type single crystal silicon substrate is omitted.
  • step S40 the texture structure 2a is formed on the semiconductor substrate 2 made of p-type single crystal silicon, which is the wafer determined to have a half normal region in the plane of the wafer in step S120.
  • the p-type single crystal silicon substrate is anisotropically etched with a solution obtained by adding IPA (isopropyl alcohol) to a low-concentration alkali solution so that the silicon (111) surface is exposed, and the light-receiving surface side of the p-type single crystal silicon substrate is exposed.
  • the texture structure 2a is formed by forming minute irregularities (texture) on the surface of the film.
  • a pn junction is formed in the semiconductor substrate 2 as shown in FIG. That is, a group V element such as phosphorus (P) is diffused into the semiconductor substrate 2 to form the n-type impurity diffusion layer 3 on the surface of the semiconductor substrate 2.
  • a pn junction is formed by diffusing phosphorus oxychloride (POCl 3 ) by thermal diffusion on a p-type single crystal silicon substrate having the texture structure 2a formed on both sides. Thereby, n-type impurity diffusion layer 3 is formed on the entire surface of the p-type single crystal silicon substrate.
  • the p-type single crystal silicon substrate is heated at a high temperature of about 800 ° C. to 900 ° C. by a vapor phase diffusion method in a mixed gas atmosphere of phosphorus oxychloride (POCl 3 ) gas, nitrogen gas, and oxygen gas.
  • POCl 3 phosphorus oxychloride
  • the n-type impurity diffusion layer 3 in which phosphorus (P) is diffused is uniformly formed on the surface layer of the p-type single crystal silicon substrate.
  • Good electrical characteristics of the solar cell can be obtained when the sheet resistance range of the n-type impurity diffusion layer 3 formed on the surface of the semiconductor substrate 2 is about 30 ⁇ / ⁇ to 80 ⁇ / ⁇ . It is possible to form n-type impurity diffusion layer 3 using ion implantation and heat treatment.
  • step S60 pn separation is performed to electrically insulate the back-side electrode 13 that is a p-type electrode and the light-receiving surface-side electrode 12 that is an n-type electrode. Since n-type impurity diffusion layer 3 is uniformly formed on the surface of the p-type single crystal silicon substrate, the front surface and the back surface are in an electrically connected state. For this reason, when the back surface side electrode 13 that is a p-type electrode and the light receiving surface side electrode 12 that is an n type electrode are formed, the back surface side electrode 13 that is a p type electrode and the light receiving surface side electrode that is an n type electrode. 12 are electrically connected.
  • the n-type impurity diffusion layer 3 formed in the end face region of the p-type single crystal silicon substrate is etched away by dry etching to perform pn separation.
  • a method for removing the influence of the n-type impurity diffusion layer 3 there is also a method of performing end face separation with a laser. Further, when the n-type impurity diffusion layer 3 is formed only on one surface on the light-receiving surface side in the p-type single crystal silicon substrate, this pn separation process is not necessary.
  • a phosphosilicate glass (PSG) layer which is a glassy material deposited on the surface during the diffusion treatment is formed. Therefore, the phosphosilicate glass layer is removed using a hydrofluoric acid solution or the like.
  • step S70 in order to improve the photoelectric conversion efficiency, the antireflection film 4 is uniformly formed on the surface of the semiconductor substrate 11 on the light receiving surface side, that is, the surface of the n-type impurity diffusion layer 3. Form with thickness.
  • the film thickness and refractive index of the antireflection film 4 are set to values that most suppress light reflection.
  • the antireflection film 4 is formed by using a plasma CVD method, using a mixed gas of silane (SiH 4 ) gas and ammonia (NH 3 ) gas as a raw material, at a temperature of 300 ° C. or higher and under reduced pressure. A silicon nitride film is formed.
  • the refractive index is, for example, about 2.0 to 2.2, and an appropriate antireflection film thickness is, for example, 70 nm to 90 nm.
  • an appropriate antireflection film thickness is, for example, 70 nm to 90 nm.
  • two or more films having different refractive indexes may be laminated as the antireflection film 4.
  • the antireflection film 4 may be formed by vapor deposition, thermal CVD, or the like. It should be noted that the antireflection film 4 formed in this manner is an insulator, and simply forming the light receiving surface side electrode 12 on the surface does not act as a solar battery cell.
  • step S80 on the antireflection film 4 that is the light receiving surface of the semiconductor substrate 11, the shapes of the surface silver grid electrode 5 that is the light receiving surface side electrode 12 and the surface silver bus electrode 6 are formed. Further, after applying silver paste 12a, which is an electrode material paste containing glass frit, by screen printing, the silver paste 12a is dried.
  • silver paste 12a which is an electrode material paste containing glass frit
  • the formation of the front silver grid electrode 5 and the front silver bus electrode 6 before firing that is, the printing of the silver paste 12a is performed in the above-described step S120 in the region on the antireflection film 4 which is the light receiving surface of the semiconductor substrate 11. It is performed only on the determined half normal area.
  • FIG. 13 is a top view showing a state in which the silver paste 12a is printed only on the half-divided region Why which is a half normal region on the antireflection film 4 which is the light receiving surface of the semiconductor substrate 11 in the first embodiment. It is.
  • the printed pattern of the silver paste 12a in the half normal region has the same shape as that of a normal wafer that is determined to satisfy a predetermined specification in the inspection of the crystal defect defect and the appearance defect. Accordingly, the silver paste 12a is printed on the antireflection film 4 in the same shape as that of a normal wafer only in a half region.
  • step S90 on the p-type single crystal silicon substrate which is the back surface of the semiconductor substrate 11, an aluminum paste 7a which is an electrode material paste is formed in the shape of the back aluminum electrode 7 by screen printing. Then, a silver paste as an electrode material paste is applied to the shape of the back silver electrode 8 and dried. In the figure, only the aluminum paste 7a is shown, and the description of the silver paste is omitted.
  • the formation of the back aluminum electrode 7 and the back silver electrode 8 before firing that is, the printing of the aluminum paste 7a and the silver paste is half of the back surface of the semiconductor substrate 11 corresponding to the half normal region, similarly to the light receiving surface side. Only done for regions.
  • the printing pattern of the aluminum paste 7a and the silver paste in the half region corresponding to the half normal region on the back surface of the semiconductor substrate 11 is determined to satisfy the predetermined specifications in the inspection of the crystal defect defect and the appearance defect. Is the same shape. Therefore, on the back surface of the semiconductor substrate 11, the aluminum paste 7a and the silver paste are printed in the same shape as that of a normal wafer only in a half region corresponding to the half normal region.
  • the order of arrangement of the paste, which is an electrode material, on the semiconductor substrate 11 may be switched between the light receiving surface side and the back surface side.
  • the electrode paste can be printed on the light receiving surface side and the back surface side of the semiconductor substrate 11 by specifying the position of the half normal region in the semiconductor substrate 11 by using the half normal region position information. Further, by using the half normal area position information, an alignment mark for alignment of the half normal area is provided in advance on the semiconductor substrate 11, and the position of the half normal area can be specified using the alignment mark. Good.
  • step S110 the electrode paste on the light-receiving surface side and the back surface side of the semiconductor substrate 11 is simultaneously fired at about 600 ° C. to 900 ° C., so that the glass contained in the silver paste 12a on the front side of the semiconductor substrate 11 is obtained. While the antireflective film 4 is melted by the material, the silver material comes into contact with the silicon and resolidifies. As a result, as shown in FIG. 11, the surface silver grid electrode 5 and the surface silver bus electrode 6 as the light receiving surface side electrode 12 are obtained, and conduction between the light receiving surface side electrode 12 and the silicon of the semiconductor substrate 11 is ensured. The Such a process is called a fire-through method.
  • the aluminum paste 7 a also reacts with the silicon of the semiconductor substrate 11 to obtain the back aluminum electrode 7, and the p + layer 9 is formed immediately below the back aluminum electrode 7. Further, the silver material of the silver paste comes into contact with silicon and re-solidifies to obtain the back silver electrode 8. Thereby, the back surface side electrode 13 is obtained.
  • the front silver grid electrode 5 and the back aluminum electrode 7 are shown, and the description of the front silver bus electrode 6 and the silver paste 8 is omitted.
  • step S110 the region corresponding to the half normal region where the light receiving surface side electrode 12 and the back surface side electrode 13 are formed in the semiconductor substrate 11 is cut out.
  • the cutting can be performed by specifying the position of the half normal region in the semiconductor substrate 11 by using the half normal region position information.
  • FIG. 14 is a top view showing a state in which the bisected region Why, which is a half normal region where the light receiving surface side electrode 12 and the back surface side electrode 13 are formed, is cut in the semiconductor substrate 11 of the first embodiment.
  • the region corresponding to the bisected region Whx is cut out.
  • a half region including a region where at least one of a crystal defect defect and an appearance defect is detected in the semiconductor substrate 11 is sent to recycling as a scrap wafer Ws.
  • the solar battery cell 1 according to the first embodiment shown in FIGS. 1 to 3 can be manufactured. That is, a half-cut cell can be manufactured while avoiding a region where at least one of a crystal defect defect and an appearance defect is detected in the wafer inspection. Therefore, in a wafer in which a crystal defect defect or an appearance defect is detected, the entire solar cell is not used as a scrap wafer for recycling, but an area in which no defect is detected in the wafer surface is effectively used. Can be made.
  • the inspection apparatus may be divided into a defect inspection apparatus and a surface inspection apparatus.
  • the partial normal wafer determination apparatus may be incorporated in the inspection apparatus.
  • the partial normal wafer determination device may be configured by a dedicated device, or may be configured by a computer device that realizes a function as the partial normal wafer determination device.
  • a computer device that realizes a function as a partial normal wafer determination device includes, for example, a display device such as an LCD (Liquid Crystal Display), an input device such as a keyboard, a central processing unit (CPU) that performs arithmetic operation, and a ROM (ROM). It is an interface with non-volatile memory such as Read Only Memory), volatile memory such as RAM (Random Access Memory), display memory that stores the display screen displayed on the display device, and removable external memory such as flash memory.
  • non-volatile memory such as Read Only Memory
  • volatile memory such as RAM (Random Access Memory)
  • display memory that stores the display screen displayed on the display device
  • removable external memory such as flash memory.
  • An external memory interface, a communication interface for communicating with an external device, and the like are connected via a bus. Then, a program describing a processing procedure as the partial normal wafer determination apparatus stored in the nonvolatile memory is loaded into the volatile memory and executed by the CPU.
  • the half normal area is used to perform half A cut cell can be produced. That is, in a wafer in which at least one of a crystal defect defect or an appearance defect is detected and does not satisfy a predetermined specification, an area that does not satisfy the predetermined specification is not an entire area in the wafer surface but an area less than half in the wafer surface. In this case, a half-cut cell can be produced while avoiding an area that does not satisfy the predetermined specification. Therefore, according to the first embodiment, a half-cut cell can be manufactured by effectively using a silicon wafer that does not satisfy a predetermined specification in the crystal defect defect inspection and the appearance defect inspection.
  • FIG. 15 is a plan view of the wafer 41 for explaining the half normal region according to the second embodiment of the present invention.
  • the wafer 41 is a wafer that does not satisfy the predetermined specifications in step S30 of the first embodiment.
  • the same members as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
  • the outer shape of the wafer 41 in the surface direction is a pseudo square shape, the four corners of the outer shape are chamfered, and the length of one side of the pseudo square shape is L.
  • the crystal defect defect 31 and the appearance defect 32 that do not satisfy the predetermined standard are close to one side in the plane of the wafer 41, that is, the side 22 side.
  • the normal length Ln in the Y direction between the side 23 and the crystal defect defect 31 in the Y direction in FIG. 15 has a length of about 3 / 4L, which is more than L / 2 required for the half normal region. Is also getting longer.
  • a region extending between the side 23 and the crystal defect defect 31 in the Y direction in FIG. 15 and extending over the entire length in the extending direction of the pair of sides 22 and 23 in the pseudo-square shape includes a crystal defect defect and an appearance defect. There is no normal area Wn in the wafer.
  • FIG. 16 is a top view showing the half normal region Wh in the wafer 41 according to the second embodiment.
  • FIG. 17 is a top view showing a state in which the solar battery cell 42 according to the second embodiment is cut out.
  • the central region in the Y direction of the normal region Wn in the wafer is set as a half normal region Wh as shown in FIG.
  • steps S80 and S90 of the first embodiment the light receiving surface side electrode 12 and the back surface side electrode 13 are formed in the half normal region Wh. Then, in step S110 of the first embodiment, as shown in FIG.
  • the half normal region Wh in which the light-receiving surface side electrode 12 and the back surface side electrode 13 are formed is cut and cut out, so that the second embodiment is applied.
  • the solar battery cell 42 can be produced.
  • the remaining portion of the wafer 41 from which the solar battery cells 42 are cut out is a scrap wafer Ws.
  • the solar battery cell 1 according to the first embodiment has a pseudo-rectangular shape in which a pair of corner portions located at both ends of one long side in a rectangular shape are chamfered to be chamfered portions 15a and chamfered portions 15b.
  • the solar battery cell 42 according to the second embodiment has a complete rectangular outer shape whose corners are not chamfered. And the light-receiving surface side electrode 12 and the back surface side electrode 13 are formed to the outer-periphery edge part of a corner
  • the photovoltaic cell 42 concerning this Embodiment 2 can ensure the length of the short side in the external shape longer than the photovoltaic cell 1 concerning Embodiment 1, it can ensure wide light-receiving area.
  • the amount of power generation can be increased as compared with the solar battery cell 1. That is, the solar cell 42 can increase the amount of power generation as compared with the solar cell 1 by setting the length of the short side of the outer shape to be larger than L / 2.
  • the second embodiment it is possible to increase the power generation amount of a cut cell produced by effectively using a silicon wafer that does not satisfy a predetermined specification in a crystal defect defect inspection and an appearance defect inspection.
  • the light-receiving surface side electrode 12 and the back surface side electrode 13 are formed in the half normal region of the in-wafer normal region Wn, and the half normal region is cut out to form a half cut. The case of manufacturing a cell is shown.
  • the light receiving surface side electrode 12 and the back surface side electrode 13 are formed in a region wider than the half normal region in the short side direction in the rectangular normal region Wn in the short side direction, and the solar cell is manufactured by cutting out the regions. You can also. That is, in the first embodiment and the second embodiment, the light receiving surface side electrode 12 and the back surface side in the region of the normal region Wn in the wafer having a region wider than the half normal region in the extending direction of the pair of opposing sides 24 and 25. The electrode 13 is formed, and the normal area Wn in the wafer is cut out to produce a solar battery cell.
  • a solar battery cell is manufactured using a rectangular region in which the short side is longer than half the long side and less than the long side in the normal region Wn in the wafer. To do. This makes it possible to effectively use a silicon wafer that does not satisfy the predetermined specifications in the crystal defect defect inspection and the appearance defect inspection, thereby realizing a solar battery cell having a larger power generation amount than the half-cut cell.
  • the configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.
  • 1,42 solar cells 2 semiconductor substrate, 2a texture structure, 3 n-type impurity diffusion layer, 4 antireflection film, 5 surface silver grid electrode, 6 surface silver bus electrode, 7 back aluminum electrode, 7a aluminum paste, 8 back Silver electrode, 9 p + layer, 11 semiconductor substrate, 12 light receiving surface side electrode, 12a silver paste, 13 back surface side electrode, 15a, 15b, 15c, 15d chamfer, 21,41 wafer, 21a wafer center, 22, 23, 24, 25 sides, 31 crystal defect defect, 32 appearance defect, B, C imaginary line, Wh, Whx, Why half normal area, Wn normal area in wafer, Ws scrap wafer.

Abstract

La présente invention porte sur un procédé qui comprend : une première étape consistant à inspecter une tranche de semi-conducteur pour détecter des défauts cristallins et un défaut d'aspect ; une deuxième étape consistant à sélectionner une tranche de semi-conducteur partiellement normale ayant un défaut détecté et comportant une zone normale intra-tranche, qui est une zone ayant une longueur supérieure ou égale à la moitié des longueurs d'une paire de côtés d'un carré, et s'étendant le long de ces derniers, et une longueur égale aux longueurs entières d'une autre paire de côtés du carré et s'étendant le long de ces derniers, et ne contenant aucun défaut cristallin ni défaut d'aspect détecté ; une troisième étape consistant à former une couche de diffusion d'impuretés sur une surface de la tranche de semi-conducteur partiellement normale, des éléments d'impureté d'un second type de conductivité étant diffusés dans la couche de diffusion d'impuretés ; une quatrième étape consistant à former une électrode côté surface de réception de lumière dans la zone normale intra-tranche sur la couche de diffusion d'impuretés ; une cinquième étape consistant à former une électrode côté surface arrière dans la zone normale intra-tranche sur une autre surface opposée à ladite surface de la tranche de semi-conducteur partiellement normale ; et une sixième étape consistant à découper en dés la zone normale intra-tranche à un moment arbitraire après la première étape et avant la fin de la cinquième étape.
PCT/JP2015/050285 2015-01-07 2015-01-07 Procédé de fabrication de cellule solaire WO2016110970A1 (fr)

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