WO2016109995A1 - 扫描驱动电路及其或非门逻辑运算电路 - Google Patents

扫描驱动电路及其或非门逻辑运算电路 Download PDF

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Publication number
WO2016109995A1
WO2016109995A1 PCT/CN2015/071714 CN2015071714W WO2016109995A1 WO 2016109995 A1 WO2016109995 A1 WO 2016109995A1 CN 2015071714 W CN2015071714 W CN 2015071714W WO 2016109995 A1 WO2016109995 A1 WO 2016109995A1
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Prior art keywords
electrically connected
inverter
transistor
gate
drain
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PCT/CN2015/071714
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English (en)
French (fr)
Inventor
戴超
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/438,606 priority Critical patent/US9805679B2/en
Publication of WO2016109995A1 publication Critical patent/WO2016109995A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a scan driving circuit for an oxide semiconductor thin film transistor and a NAND gate logic operation circuit thereof.
  • CMOS complementary metal-oxide-semiconductor
  • oxide semiconductor devices IGZO has become the focus of next-generation displays, and oxide semiconductors have better NTFT characteristics due to their special material structure.
  • oxide semiconductors have better NTFT characteristics due to their special material structure.
  • NTFT and PTFT devices in the TFT of the thin film transistor, but generally only the LTPS process can obtain a PTFT device with better performance. Therefore, how to make an Inverter, NAND or NOR using a single-type device (PTFT or NTFT) has also become A problem that needs to be solved urgently.
  • the main technical problem to be solved by the present invention is to provide a scan driving circuit for an oxide semiconductor thin film transistor and a NAND gate logic operation circuit capable of fabricating a NAND using a single type device (PTFT or NTFT).
  • a technical solution adopted by the present invention is to provide a NAND logic operation circuit, wherein the circuit includes a first inverter and a second inverter applied to a GOA circuit pull-down sustain circuit. And a thirteenth transistor, the gate is electrically connected to the output end of the first inverter, the drain is electrically connected to the constant voltage high potential; and the fourteenth transistor is electrically connected to the first An output of the two inverters, the drain is electrically connected to the source of the thirteenth transistor, the source is electrically connected to the output end of the logic operation circuit; and the fifteenth transistor is electrically connected to the gate a first input end of the logic operation circuit, a drain electrically connected to an output end of the logic operation circuit, a source electrically connected to a constant voltage low potential; a sixteenth transistor, a gate electrically connected to the a second input end of the logic operation circuit, the drain is electrically connected to the output end of the logic operation circuit, and the source is electrically connected to the constant voltage low
  • another technical solution adopted by the present invention is to provide a NAND logic operation circuit, wherein the circuit includes a first inverter and a second inverter applied to a GOA circuit pull-down sustain circuit. And a thirteenth transistor, the gate is electrically connected to the output end of the first inverter, the drain is electrically connected to the constant voltage high potential; and the fourteenth transistor is electrically connected to the gate An output end of the second inverter, the drain is electrically connected to the source of the thirteenth transistor, the source is electrically connected to the output end of the logic operation circuit; and the fifteenth transistor is electrically connected The first input end of the logic operation circuit is electrically connected to the output end of the logic operation circuit, the source is electrically connected to the constant voltage low potential; and the sixteenth transistor is electrically connected to the gate The second input end of the logic operation circuit is electrically connected to the output end of the logic operation circuit, and the source is electrically connected to the constant voltage low potential.
  • the first inverter is the same as the second inverter, and includes: a first transistor, the gate and the drain are electrically connected to a constant voltage high potential, and the source is electrically connected to the first node ;
  • the gate is electrically connected to the input end of the inverter, the drain is electrically connected to the first node, the source is electrically connected to the first negative potential; and the third transistor is electrically connected to the gate a first node, the drain is electrically connected to the constant voltage high potential, the source is electrically connected to the output end of the inverter; and the fourth transistor is electrically connected to the input end of the inverter, and is drained a source electrically connected to the output end of the inverter, the source is electrically connected to the second node; the fifth transistor, the gate and the drain are electrically connected to the constant voltage high potential, and the source is electrically connected to the third a sixth transistor, the gate is electrically connected to the input end of the inverter, the drain is electrically connected to the third node, the source is connected to the constant voltage low potential; and the seventh transistor is electrically connected to the gate a third node, the drain is electrically connected to the constant voltage high potential, the source is electrically connected to the second
  • first inverter and the second inverter pass the constant voltage low potential and the first negative potential receiving circuit control signal.
  • the first inverter is the same as the second inverter, and includes: a twenty-first transistor, wherein the gate and the drain are electrically connected to a constant voltage high potential, and the source is electrically connected to the first a node; a twenty-second transistor, the gate is electrically connected to the input end of the inverter, the drain is electrically connected to the first node, the source is electrically connected to the first negative potential; and the twenty-third transistor The gate is electrically connected to the first node, the drain is electrically connected to the constant voltage high potential, the source is electrically connected to the output end of the inverter; and the twenty-fourth transistor is electrically connected to the gate An input end of the inverter, the drain is electrically connected to the output end of the inverter, the source is electrically connected to the second node; and the twenty-fifth transistor is electrically connected to the third node and the drain Electrically connected to the constant voltage high potential, the source is electrically connected to the second node; the twenty-sixth transistor has
  • the first inverter includes: a first transistor, the gate and the drain are electrically connected to the constant voltage high potential, the source is electrically connected to the first node; and the second transistor is electrically connected to the gate
  • the input end of the inverter is electrically connected to the first node, the source is electrically connected to the first negative potential, and the third transistor is electrically connected to the first node, and the drain is electrically connected to the drain a constant voltage is high, the source is electrically connected to the output end of the inverter;
  • the fourth transistor is electrically connected to the input end of the inverter, and the drain is electrically connected to the inverter
  • the output terminal, the source is electrically connected to the second node;
  • the fifth transistor, the gate and the drain are electrically connected to the constant voltage high potential, the source is electrically connected to the third node;
  • the sixth transistor the gate electrical property Connected to the input end of the inverter, the drain is electrically connected to the third node, the source is connected to the constant
  • the first inverter receives the control signal through the constant voltage low potential and the first negative potential receiving circuit, and the second inverter receives the constant voltage high potential and the constant voltage low potential Circuit control signal.
  • the relationship between the first negative potential, the second negative potential and the constant voltage low potential is: a constant voltage low potential ⁇ a second negative potential ⁇ a first negative potential.
  • the NOR logic operation circuit controls the signal through the constant voltage high potential and the constant voltage low potential receiving circuit.
  • another technical solution adopted by the present invention is to provide a scan driving circuit for an oxide semiconductor thin film transistor, wherein the circuit includes a NAND logic operation circuit, wherein The circuit includes a first inverter and a second inverter applied to the GOA circuit pull-down sustain circuit, and a thirteenth transistor, the gate is electrically connected to the output end of the first inverter, and the drain is electrically Connected to the constant voltage high potential; the fourteenth transistor, the gate is electrically connected to the output end of the second inverter, the drain is electrically connected to the source of the thirteenth transistor, and the source is electrically connected The output terminal of the logic operation circuit; the fifteenth transistor, the gate is electrically connected to the first input end of the logic operation circuit, and the drain is electrically connected to the output end of the logic operation circuit, and the source is electrically Connected to the constant voltage low potential; the sixteenth transistor, the gate is electrically connected to the second input end of the logic operation circuit, the drain is electrically connected to the output
  • the first inverter is the same as the second inverter, and includes: a first transistor, the gate and the drain are electrically connected to a constant voltage high potential, and the source is electrically connected to the first node a second transistor, the gate is electrically connected to the input end of the inverter, the drain is electrically connected to the first node, the source is electrically connected to the first negative potential; and the third transistor is electrically connected In the first node, the drain is electrically connected to the constant voltage high potential, the source is electrically connected to the output end of the inverter, and the fourth transistor is electrically connected to the input end of the inverter.
  • the drain is electrically connected to the output end of the inverter, and the source is electrically connected to the second node;
  • the fifth transistor has a gate and a drain electrically connected to the constant voltage high potential, and the source is electrically connected to the first a third transistor, a gate electrically connected to the input end of the inverter, a drain electrically connected to the third node, a source connected to the constant voltage low potential, and a seventh transistor electrically connected to the gate
  • the drain is electrically connected to the constant voltage high potential
  • the source is electrically connected to the second node;
  • Transistor a gate is electrically connected to the inverter input terminal, the drain is electrically connected to the second node, a source connected to a constant potential down.
  • first inverter and the second inverter control signals by the constant voltage low potential and the first negative potential receiving circuit.
  • the first inverter is the same as the second inverter, and includes: a twenty-first transistor, wherein the gate and the drain are electrically connected to a constant voltage high potential, and the source is electrically connected to the first a node; a twenty-second transistor, the gate is electrically connected to the input end of the inverter, the drain is electrically connected to the first node, the source is electrically connected to the first negative potential; and the twenty-third transistor The gate is electrically connected to the first node, the drain is electrically connected to the constant voltage high potential, the source is electrically connected to the output end of the inverter; and the twenty-fourth transistor is electrically connected to the gate An input end of the inverter, the drain is electrically connected to the output end of the inverter, the source is electrically connected to the second node; and the twenty-fifth transistor is electrically connected to the third node and the drain Electrically connected to the constant voltage high potential, the source is electrically connected to the second node; the twenty-sixth transistor has
  • the first inverter includes: a first transistor, the gate and the drain are electrically connected to the constant voltage high potential, the source is electrically connected to the first node; and the second transistor is electrically connected to the gate
  • the input end of the inverter is electrically connected to the first node, the source is electrically connected to the first negative potential, and the third transistor is electrically connected to the first node, and the drain is electrically connected to the drain a constant voltage is high, the source is electrically connected to the output end of the inverter;
  • the fourth transistor is electrically connected to the input end of the inverter, and the drain is electrically connected to the inverter
  • the output terminal, the source is electrically connected to the second node;
  • the fifth transistor, the gate and the drain are electrically connected to the constant voltage high potential, the source is electrically connected to the third node;
  • the sixth transistor the gate electrical property Connected to the input end of the inverter, the drain is electrically connected to the third node, the source is connected to the constant
  • the first inverter receives the control signal through the constant voltage low potential and the first negative potential receiving circuit, and the second inverter receives the constant voltage high potential and the constant voltage low potential Circuit control signal.
  • the relationship between the first negative potential, the second negative potential and the constant voltage low potential is: a constant voltage low potential ⁇ a second negative potential ⁇ a first negative potential.
  • the NOR logic operation circuit controls the signal through the constant voltage high potential and the constant voltage low potential receiving circuit.
  • the invention has the beneficial effects that the present invention provides a scan driving circuit for an oxide semiconductor thin film transistor and a NAND gate logic operation circuit thereof, including a first inverter and a first applied to a GOA circuit pull-down sustain circuit.
  • the two inverters, as well as the multiple transistors, use the combination of NTFT and inverter to replace the functions of the original PMOS components, realizing similar to the original CMOS.
  • the characteristics of the NOR operation circuit solve the design problem of the logic operation circuit of the IGZO TFT single-type device, and are more suitable for the integration of large-scale digital integrated circuits in the liquid crystal display.
  • FIG. 1 is a circuit diagram of a NOR logic operation circuit in an embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a first inverter in a NOR logic operation circuit according to an embodiment of the present invention
  • FIG. 3 is a circuit diagram of a second inverter in a NOR logic operation circuit in an embodiment of the present invention.
  • FIG. 1 is a circuit diagram of a NOR logic operation circuit according to an embodiment of the present invention.
  • the NOR logic operation circuit 10 is a logic operation circuit applied to a scan driving circuit for an oxide semiconductor thin film transistor.
  • the circuit 10 includes a first inverter 100 and a second inverter 200, wherein the first inverter 100 and the second inverter 200 are both applied to an inverter in a GOA circuit pull-down sustain circuit.
  • first inverter 100 and the second inverter 200 are both main inverter sections applied to the GOA circuit pull-down sustain circuit.
  • the circuit 10 also includes:
  • the thirteenth transistor T13 has a gate electrically connected to the output end of the first inverter, and a drain electrically connected to the constant voltage high potential DCH.
  • the gate is electrically connected to the output end of the second inverter, the drain is electrically connected to the source of the thirteenth transistor T13, and the source is electrically connected to the output of the logic operation circuit End Vout.
  • the fifteenth transistor T15 has a gate electrically connected to the first input terminal A of the logic operation circuit, a drain electrically connected to the output terminal Vout of the logic operation circuit, and a source electrically connected to the constant voltage low potential DCL.
  • the sixteenth transistor T16 has a gate electrically connected to the second input terminal B of the logic operation circuit, a drain electrically connected to the output terminal Vout of the logic operation circuit, and a source electrically connected to the constant voltage low potential DCL.
  • the NAND logic operation circuit receives the circuit control signal through the constant voltage high potential DCH and the constant voltage low potential DCL.
  • FIG. 2 is a circuit diagram of an inverter in a NOR logic operation circuit according to an embodiment of the present invention.
  • the composition and connection relationship of the inverter are as follows:
  • the first transistor T1 has a gate and a drain electrically connected to the constant voltage high potential DCH, and the source is electrically connected to the first node S.
  • the second transistor T2 has a gate electrically connected to the input terminal Vin of the inverter, a drain electrically connected to the first node S, and a source electrically connected to the first negative potential VSS1.
  • the third transistor T3 has a gate electrically connected to the first node S, a drain electrically connected to the constant voltage high potential DCH, and a source electrically connected to the output terminal Vout of the inverter.
  • the fourth transistor T4 has a gate electrically connected to the input terminal Vin of the inverter, a drain electrically connected to the output terminal Vout of the inverter, and a source electrically connected to the second node K.
  • the fifth transistor T5 has a gate and a drain electrically connected to the constant voltage high potential DCH, and a source electrically connected to the third node M.
  • the sixth transistor T6 has a gate electrically connected to the input terminal Vin of the inverter, a drain electrically connected to the third node M, and a source connected to the constant voltage low potential DCL.
  • the seventh transistor T7 has a gate electrically connected to the third node M, a drain electrically connected to the constant voltage high potential DCH, and a source electrically connected to the second node K.
  • the eighth transistor T8 has a gate electrically connected to the input terminal Vin of the inverter, a drain electrically connected to the second node K, and a source connected to the constant voltage low potential DCL.
  • the inverter receives the circuit control signal through the constant voltage low potential DCL and the first negative potential VSS1.
  • the relationship between the first negative potential VSS1, the second negative potential VSS2, and the constant voltage low potential DCL is such that the constant voltage low potential DCL ⁇ the second negative potential VSS2 ⁇ the first negative potential VSS1.
  • FIG. 3 is a circuit diagram of an inverter in a NOR logic operation circuit according to another embodiment of the present invention.
  • the composition and connection relationship of the inverter are as follows:
  • the gate and the drain are electrically connected to the constant voltage high potential DCH, and the source is electrically connected to the first node S.
  • the second transistor T22 has a gate electrically connected to the input terminal Vin of the inverter, a drain electrically connected to the first node S, and a source electrically connected to the first negative potential VSS1.
  • the twenty-third transistor T23 has a gate electrically connected to the first node S, a drain electrically connected to the constant voltage high potential DCH, and a source electrically connected to the output terminal Vout of the inverter.
  • the twenty-fourth transistor T24 has a gate electrically connected to the input terminal Vin of the inverter, a drain electrically connected to the output terminal Vout of the inverter, and a source electrically connected to the second node K.
  • the twenty-fifth transistor T25 has a gate electrically connected to the third node M, a drain electrically connected to the constant voltage high potential DCH, and a source electrically connected to the second node K.
  • the twenty-sixth transistor T26 has a gate electrically connected to the input terminal Vin of the inverter, a drain electrically connected to the second node K, and a source connected to the constant voltage low potential DCL.
  • the inverter receives the circuit control signal through the constant voltage high potential DCH and the constant voltage low potential DCL.
  • the relationship between the first negative potential VSS1, the second negative potential VSS2, and the constant voltage low potential DCL is such that the constant voltage low potential DCL ⁇ the second negative potential VSS2 ⁇ the first negative potential VSS1.
  • the first inverter and the second inverter included in the circuit 10 are both inverters as shown in FIG. 2.
  • first inverter and the second inverter included in the circuit 10 are both inverters as shown in FIG.
  • the first inverter included in the circuit 10 is an inverter as shown in FIG. 2
  • the second inverter is an inverter as shown in FIG.
  • the present invention provides a scan driving circuit for an oxide semiconductor thin film transistor and a NAND gate logic operation circuit thereof, including a first inverter and a second inverter applied to a GOA circuit pull-down sustain circuit, and Transistors, using the combination of NTFT and inverter to replace the function of the original PMOS components, to achieve similar to the original CMOS
  • the characteristics of the NOR operation circuit solve the design problem of the logic operation circuit of the IGZO TFT single-type device, and are more suitable for the integration of large-scale digital integrated circuits in the liquid crystal display.

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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  • General Engineering & Computer Science (AREA)
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  • Theoretical Computer Science (AREA)
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Abstract

一种用于氧化物半导体薄膜晶体管的扫描驱动电路及其或非门逻辑运算电路，包括应用于GOA电路下拉维持电路中的第一反相器（100）和第二反相器（200），以及多个晶体管（T13，T14，T15，T16），利用NTFT与反相器的结合替代原有的PMOS元件的功能，实现类似原来的CMOS NOR运算电路的特性，从而解决了IGZO TFT单型器件逻辑运算电路的设计问题，更适合大型的数字集成电路集成在液晶显示器。

Description

扫描驱动电路及其或非门逻辑运算电路
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种用于氧化物半导体薄膜晶体管的扫描驱动电路及其或非门逻辑运算电路。
【背景技术】
对于大规模集成电路而言，逻辑运算电路最基本的三个器件就是反相器（Inverter）、与非门（NAND）、或非门（NOR），而通常这三种器件都是采用CMOS FET做成，也就是电路中有PMOS和NMOS两种器件。
在氧化物半导体器件中，IGZO已经成为了下一代显示器关注的焦点，而氧化半导体由于特殊的材料结构决定了其具备较好的NTFT特性。但是，在薄膜晶体管TFT中也有NTFT和PTFT两种器件，但是一般只有LTPS制程才能获得性能较好的PTFT器件，因此如何利用单型的器件（PTFT或NTFT）制作出Inverter、NAND或NOR也成为一个亟待解决的问题。
【发明内容】
本发明主要解决的技术问题是提供一种用于氧化物半导体薄膜晶体管的扫描驱动电路及其或非门逻辑运算电路，能够利用单型的器件（PTFT或NTFT）制作出NAND。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种或非门逻辑运算电路，其中，所述电路包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器，以及第十三晶体管，栅极电性连接于所述第一反相器的输出端，漏极电性连接于恒压高电位；第十四晶体管，栅极电性连接于所述第二反相器的输出端，漏极电性连接于所述第十三晶体管的源极，源极电性连接于所述逻辑运算电路的输出端；第十五晶体管，栅极电性连接于所述逻辑运算电路的第一输入端，漏极电性连接于所述逻辑运算电路的输出端，源极电性连接于恒压低电位；第十六晶体管，栅极电性连接于所述逻辑运算电路的第二输入端，漏极电性连接于所述逻辑运算电路的输出端，源极电性连接于恒压低电位；所述第一反相器和所述第二反相器通过所述恒压低电位以及所述第一负电位接收电路控制信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种或非门逻辑运算电路，其中，所述电路包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器，以及第十三晶体管，栅极电性连接于所述第一反相器的输出端，漏极电性连接于恒压高电位；第十四晶体管，栅极电性连接于所述第二反相器的输出端，漏极电性连接于所述第十三晶体管的源极，源极电性连接于所述逻辑运算电路的输出端；第十五晶体管，栅极电性连接于所述逻辑运算电路的第一输入端，漏极电性连接于所述逻辑运算电路的输出端，源极电性连接于恒压低电位；第十六晶体管，栅极电性连接于所述逻辑运算电路的第二输入端，漏极电性连接于所述逻辑运算电路的输出端，源极电性连接于恒压低电位。
其中，所述第一反相器与所述第二反相器相同，均包括：第一晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第一节点；
第二晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第一节点，源极电性连接于第一负电位；第三晶体管，栅极电性连接于第一节点，漏极电性连接于恒压高电位，源极电性连接于所述反相器的输出端；第四晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于所述反相器的输出端，源极电性连接第二节点；第五晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第三节点；第六晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第三节点，源极连接于恒压低电位；第七晶体管，栅极电性连接于第三节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第八晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第二节点，源极连接于恒压低电位。
其中，所述第一反相器和所述第二反相器通过所述恒压低电位\以及所述第一负电位接收电路控制信号。
其中，所述第一反相器与所述第二反相器相同，均包括：第二十一晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第一节点；第二十二晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第一节点，源极电性连接于第一负电位；第二十三晶体管，栅极电性连接于第一节点，漏极电性连接于恒压高电位，源极电性连接于所述反相器的输出端；第二十四晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于所述反相器的输出端，源极电性连接第二节点；第二十五晶体管，栅极电性连接于第三节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第二十六晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第二节点，源极连接于恒压低电位。
其中，所述第一反相器和所述第二反相器通过所述恒压高电位以及所述恒压低电位接收电路控制信号。
其中，所述第一反相器包括：第一晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第一节点；第二晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第一节点，源极电性连接于第一负电位；第三晶体管，栅极电性连接于第一节点，漏极电性连接于恒压高电位，源极电性连接于所述反相器的输出端；第四晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于所述反相器的输出端，源极电性连接第二节点；第五晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第三节点；第六晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第三节点，源极连接于恒压低电位；第七晶体管，栅极电性连接于第三节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第八晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第二节点，源极连接于恒压低电位；所述第二反相器包括：第二十一晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第一节点；第二十二晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第一节点，源极电性连接于第一负电位；第二十三晶体管，栅极电性连接于第一节点，漏极电性连接于恒压高电位，源极电性连接于所述反相器的输出端；第二十四晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于所述反相器的输出端，源极电性连接第二节点；第二十五晶体管，栅极电性连接于第三节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第二十六晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第二节点，源极连接于恒压低电位。
其中，所述第一反相器通过所述恒压低电位以及所述第一负电位接收电路控制信号，所述第二反相器通过所述恒压高电位以及所述恒压低电位接收电路控制信号。
其中，所述第一负电位、第二负电位与恒压低电位的关系为：恒压低电位<第二负电位<第一负电位。
其中，所述或非门逻辑运算电路通过所述恒压高电位以及所述恒压低电位接收电路控制信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述电路包括一种或非门逻辑运算电路，其中，所述电路包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器，以及第十三晶体管，栅极电性连接于所述第一反相器的输出端，漏极电性连接于恒压高电位；第十四晶体管，栅极电性连接于所述第二反相器的输出端，漏极电性连接于所述第十三晶体管的源极，源极电性连接于所述逻辑运算电路的输出端；第十五晶体管，栅极电性连接于所述逻辑运算电路的第一输入端，漏极电性连接于所述逻辑运算电路的输出端，源极电性连接于恒压低电位；第十六晶体管，栅极电性连接于所述逻辑运算电路的第二输入端，漏极电性连接于所述逻辑运算电路的输出端，源极电性连接于恒压低电位。
其中，所述第一反相器与所述第二反相器相同，均包括：第一晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第一节点；第二晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第一节点，源极电性连接于第一负电位；第三晶体管，栅极电性连接于第一节点，漏极电性连接于恒压高电位，源极电性连接于所述反相器的输出端；第四晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于所述反相器的输出端，源极电性连接第二节点；第五晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第三节点；第六晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第三节点，源极连接于恒压低电位；第七晶体管，栅极电性连接于第三节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第八晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第二节点，源极连接于恒压低电位。
其中，所述第一反相器和所述第二反相器通过所述恒压低电位以及所述第一负电位接收电路控制信号。
其中，所述第一反相器与所述第二反相器相同，均包括：第二十一晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第一节点；第二十二晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第一节点，源极电性连接于第一负电位；第二十三晶体管，栅极电性连接于第一节点，漏极电性连接于恒压高电位，源极电性连接于所述反相器的输出端；第二十四晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于所述反相器的输出端，源极电性连接第二节点；第二十五晶体管，栅极电性连接于第三节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第二十六晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第二节点，源极连接于恒压低电位D。
其中，所述第一反相器和所述第二反相器通过所述恒压高电位以及所述恒压低电位接收电路控制信号。
其中，所述第一反相器包括：第一晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第一节点；第二晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第一节点，源极电性连接于第一负电位；第三晶体管，栅极电性连接于第一节点，漏极电性连接于恒压高电位，源极电性连接于所述反相器的输出端；第四晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于所述反相器的输出端，源极电性连接第二节点；第五晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第三节点；第六晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第三节点，源极连接于恒压低电位；第七晶体管，栅极电性连接于第三节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第八晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第二节点，源极连接于恒压低电位；所述第二反相器包括：第二十一晶体管，栅极与漏极均电性连接于恒压高电位，源极电性连接于第一节点；第二十二晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第一节点，源极电性连接于第一负电位；第二十三晶体管，栅极电性连接于第一节点，漏极电性连接于恒压高电位，源极电性连接于所述反相器的输出端；第二十四晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于所述反相器的输出端，源极电性连接第二节点；第二十五晶体管，栅极电性连接于第三节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第二十六晶体管，栅极电性连接于所述反相器的输入端，漏极电性连接于第二节点，源极连接于恒压低电位。
其中，所述第一反相器通过所述恒压低电位以及所述第一负电位接收电路控制信号，所述第二反相器通过所述恒压高电位以及所述恒压低电位接收电路控制信号。
其中，所述第一负电位、第二负电位与恒压低电位的关系为：恒压低电位<第二负电位<第一负电位。
其中，所述或非门逻辑运算电路通过所述恒压高电位以及所述恒压低电位接收电路控制信号。
本发明的有益效果是：本发明提供了一种用于氧化物半导体薄膜晶体管的扫描驱动电路及其或非门逻辑运算电路，包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器，以及多个晶体管，利用NTFT与反相器的结合替代原有的PMOS元件的功能，实现类似原来的CMOS NOR运算电路的特性，从而解决了IGZO TFT单型器件逻辑运算电路的设计问题，更适合大型的数字集成电路集成在液晶显示器。
【附图说明】
图1为本发明实施方式中的或非门逻辑运算电路的电路图；
图2为本发明实施方式中的或非门逻辑运算电路中的第一反相器的电路图；
图3为本发明实施方式中的或非门逻辑运算电路中的第二反相器的电路图。
【具体实施方式】
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本发明一部分实施方式，而不是全部的实施方式。基于本发明中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，均属于本发明保护的范围。
请参阅图1，为本发明实施方式中的或非门逻辑运算电路的电路图。其中，该或非门逻辑运算电路10为应用于用于氧化物半导体薄膜晶体管的扫描驱动电路的逻辑运算电路。
该电路10包括第一反相器100、第二反相器200，其中，该第一反相器100和第二反相器200均为应用于GOA电路下拉维持电路中反相器。
进一步地，该第一反相器100和第二反相器200均为应用于GOA电路下拉维持电路中的主反相器部分。
该电路10还包括：
第十三晶体管T13，栅极电性连接于该第一反相器的输出端，漏极电性连接于恒压高电位DCH。
第十四晶体管T14，栅极电性连接于该第二反相器的输出端，漏极电性连接于该第十三晶体管T13的源极，源极电性连接于该逻辑运算电路的输出端Vout。
第十五晶体管T15，栅极电性连接于该逻辑运算电路的第一输入端A，漏极电性连接于该逻辑运算电路的输出端Vout，源极电性连接于恒压低电位DCL。
第十六晶体管T16，栅极电性连接于该逻辑运算电路的第二输入端B，漏极电性连接于该逻辑运算电路的输出端Vout，源极电性连接于恒压低电位DCL。
其中，该或非门逻辑运算电路通过该恒压高电位DCH以及该恒压低电位DCL接收电路控制信号。
请同时参阅图2，为本发明一实施方式中的或非门逻辑运算电路中的反相器的电路图。该反相器的组成及连接关系如下：
第一晶体管T1，栅极与漏极均电性连接于恒压高电位DCH，源极电性连接于第一节点S。
第二晶体管T2，栅极电性连接于该反相器的输入端Vin，漏极电性连接于第一节点S，源极电性连接于第一负电位VSS1。
第三晶体管T3，栅极电性连接于第一节点S，漏极电性连接于恒压高电位DCH，源极电性连接于该反相器的输出端Vout。
第四晶体管T4，栅极电性连接于该反相器的输入端Vin，漏极电性连接于该反相器的输出端Vout，源极电性连接第二节点K。
第五晶体管T5，栅极与漏极均电性连接于恒压高电位DCH，源极电性连接于第三节点M。
第六晶体管T6，栅极电性连接于该反相器的输入端Vin，漏极电性连接于第三节点M，源极连接于恒压低电位DCL。
第七晶体管T7，栅极电性连接于第三节点M，漏极电性连接于恒压高电位DCH，源极电性连接于第二节点K。
第八晶体管T8，栅极电性连接于该反相器的输入端Vin，漏极电性连接于第二节点K，源极连接于恒压低电位DCL。
其中，该反相器通过该恒压低电位DCL以及该第一负电位VSS1接收电路控制信号。
第一负电位VSS1、第二负电位VSS2与恒压低电位DCL的关系为：恒压低电位DCL<第二负电位VSS2<第一负电位VSS1。
请参阅图3，为本发明另一实施方式中的或非门逻辑运算电路中的反相器的电路图。该反相器的组成及连接关系如下：
第二十一晶体管T21，栅极与漏极均电性连接于恒压高电位DCH，源极电性连接于第一节点S。
第二十二晶体管T22，栅极电性连接于该反相器的输入端Vin，漏极电性连接于第一节点S，源极电性连接于第一负电位VSS1。
第二十三晶体管T23，栅极电性连接于第一节点S，漏极电性连接于恒压高电位DCH，源极电性连接于该反相器的输出端Vout。
第二十四晶体管T24，栅极电性连接于该反相器的输入端Vin，漏极电性连接于该反相器的输出端Vout，源极电性连接第二节点K。
第二十五晶体管T25，栅极电性连接于第三节点M，漏极电性连接于恒压高电位DCH，源极电性连接于第二节点K。
第二十六晶体管T26，栅极电性连接于该反相器的输入端Vin，漏极电性连接于第二节点K，源极连接于恒压低电位DCL。
其中，该反相器通过该恒压高电位DCH以及该恒压低电位DCL接收电路控制信号。
第一负电位VSS1、第二负电位VSS2与恒压低电位DCL的关系为：恒压低电位DCL<第二负电位VSS2<第一负电位VSS1。
在本实施方式中，该电路10包括的第一反相器和第二反相器均为如图2所示的反相器。
在另一实施方式中，该电路10包括的第一反相器和第二反相器均为如图3所示的反相器。
再一实施方式中，该电路10包括的第一反相器为如图2所示的反相器，第二反相器均为如图3所示的反相器。
本发明提供了一种用于氧化物半导体薄膜晶体管的扫描驱动电路及其或非门逻辑运算电路，包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器，以及多个晶体管，利用NTFT与反相器的结合替代原有的PMOS元件的功能，实现类似原来的CMOS NOR运算电路的特性，从而解决了IGZO TFT单型器件逻辑运算电路的设计问题，更适合大型的数字集成电路集成在液晶显示器。
在上述实施例中，仅对本发明进行了示范性描述，但是本领域技术人员在阅读本专利申请后可以在不脱离本发明的精神和范围的情况下对本发明进行各种修改。

Claims (19)

  1. 一种或非门逻辑运算电路，其中，所述电路包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器，以及
    第十三晶体管（T13），栅极电性连接于所述第一反相器的输出端，漏极电性连接于恒压高电位（DCH）；
    第十四晶体管（T14），栅极电性连接于所述第二反相器的输出端，漏极电性连接于所述第十三晶体管（T13）的源极，源极电性连接于所述逻辑运算电路的输出端（Vout）；
    第十五晶体管（T15），栅极电性连接于所述逻辑运算电路的第一输入端（A），漏极电性连接于所述逻辑运算电路的输出端（Vout），源极电性连接于恒压低电位（DCL）；
    第十六晶体管（T16），栅极电性连接于所述逻辑运算电路的第二输入端（B），漏极电性连接于所述逻辑运算电路的输出端（Vout），源极电性连接于恒压低电位（DCL）；
    所述第一反相器和所述第二反相器通过所述恒压低电位（DCL）以及第一负电位（VSS1）接收电路控制信号。
  2. 一种或非门逻辑运算电路，其中，所述电路包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器，以及
    第十三晶体管（T13），栅极电性连接于所述第一反相器的输出端，漏极电性连接于恒压高电位（DCH）；
    第十四晶体管（T14），栅极电性连接于所述第二反相器的输出端，漏极电性连接于所述第十三晶体管（T13）的源极，源极电性连接于所述逻辑运算电路的输出端（Vout）；
    第十五晶体管（T15），栅极电性连接于所述逻辑运算电路的第一输入端（A），漏极电性连接于所述逻辑运算电路的输出端（Vout），源极电性连接于恒压低电位（DCL）；
    第十六晶体管（T16），栅极电性连接于所述逻辑运算电路的第二输入端（B），漏极电性连接于所述逻辑运算电路的输出端（Vout），源极电性连接于恒压低电位（DCL）。
  3. 根据权利要求2所述的或非门逻辑运算电路，其中，所述第一反相器与所述第二反相器相同，均包括：
    第一晶体管（T1），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第一节点（S）；
    第二晶体管（T2），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第一节点（S），源极电性连接于第一负电位（VSS1）；
    第三晶体管（T3），栅极电性连接于第一节点（S），漏极电性连接于恒压高电位（DCH），源极电性连接于所述反相器的输出端（Vout）；
    第四晶体管（T4），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于所述反相器的输出端（Vout），源极电性连接第二节点（K）；
    第五晶体管（T5），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第三节点（M）；
    第六晶体管（T6），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第三节点（M），源极连接于恒压低电位（DCL）；
    第七晶体管（T7），栅极电性连接于第三节点（M），漏极电性连接于恒压高电位（DCH），源极电性连接于第二节点（K）；
    第八晶体管（T8），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第二节点（K），源极连接于恒压低电位（DCL）。
  4. 根据权利要求3所述的或非门逻辑运算电路，其中，所述第一反相器和所述第二反相器通过所述恒压低电位（DCL）以及所述第一负电位（VSS1）接收电路控制信号。
  5. 根据权利要求2所述的或非门逻辑运算电路，其中，所述第一反相器与所述第二反相器相同，均包括：
    第二十一晶体管（T21），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第一节点（S）；
    第二十二晶体管（T22），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第一节点（S），源极电性连接于第一负电位（VSS1）；
    第二十三晶体管（T23），栅极电性连接于第一节点（S），漏极电性连接于恒压高电位（DCH），源极电性连接于所述反相器的输出端（Vout）；
    第二十四晶体管（T24），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于所述反相器的输出端（Vout），源极电性连接第二节点（K）；
    第二十五晶体管（T25），栅极电性连接于第三节点（M），漏极电性连接于恒压高电位（DCH），源极电性连接于第二节点（K）；
    第二十六晶体管（T26），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第二节点（K），源极连接于恒压低电位（DCL）。
  6. 根据权利要求5所述的或非门逻辑运算电路，其中，所述第一反相器和所述第二反相器通过所述恒压高电位（DCH）以及所述恒压低电位（DCL）接收电路控制信号。
  7. 根据权利要求2所述的或非门逻辑运算电路，其中，所述第一反相器包括：
    第一晶体管（T1），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第一节点（S）；
    第二晶体管（T2），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第一节点（S），源极电性连接于第一负电位（VSS1）；
    第三晶体管（T3），栅极电性连接于第一节点（S），漏极电性连接于恒压高电位（DCH），源极电性连接于所述反相器的输出端（Vout）；
    第四晶体管（T4），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于所述反相器的输出端（Vout），源极电性连接第二节点（K）；
    第五晶体管（T5），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第三节点（M）；
    第六晶体管（T6），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第三节点（M），源极连接于恒压低电位（DCL）；
    第七晶体管（T7），栅极电性连接于第三节点（M），漏极电性连接于恒压高电位（DCH），源极电性连接于第二节点（K）；
    第八晶体管（T8），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第二节点（K），源极连接于恒压低电位（DCL）；
    所述第二反相器包括：
    第二十一晶体管（T21），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第一节点（S）；
    第二十二晶体管（T22），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第一节点（S），源极电性连接于第一负电位（VSS1）；
    第二十三晶体管（T23），栅极电性连接于第一节点（S），漏极电性连接于恒压高电位（DCH），源极电性连接于所述反相器的输出端（Vout）；
    第二十四晶体管（T24），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于所述反相器的输出端（Vout），源极电性连接第二节点（K）；
    第二十五晶体管（T25），栅极电性连接于第三节点（M），漏极电性连接于恒压高电位（DCH），源极电性连接于第二节点（K）；
    第二十六晶体管（T26），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第二节点（K），源极连接于恒压低电位（DCL）。
  8. 根据权利要求7所述的或非门逻辑运算电路，其中，所述第一反相器通过所述恒压低电位（DCL）以及所述第一负电位（VSS1）接收电路控制信号，所述第二反相器通过所述恒压高电位（DCH）以及所述恒压低电位（DCL）接收电路控制信号。
  9. 根据权利要求8所述的或非门逻辑运算电路，其中，所述第一负电位（VSS1）、第二负电位（VSS2）与恒压低电位（DCL）的关系为：恒压低电位（DCL）<第二负电位（VSS2）<第一负电位（VSS1）。
  10. 根据权利要求2所述的或非门逻辑运算电路，其中，所述或非门逻辑运算电路通过所述恒压高电位（DCH）以及所述恒压低电位（DCL）接收电路控制信号。
  11. 一种用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述电路包括一种或非门逻辑运算电路，其中，所述电路包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器，以及
    第十三晶体管（T13），栅极电性连接于所述第一反相器的输出端，漏极电性连接于恒压高电位（DCH）；
    第十四晶体管（T14），栅极电性连接于所述第二反相器的输出端，漏极电性连接于所述第十三晶体管（T13）的源极，源极电性连接于所述逻辑运算电路的输出端（Vout）；
    第十五晶体管（T15），栅极电性连接于所述逻辑运算电路的第一输入端（A），漏极电性连接于所述逻辑运算电路的输出端（Vout），源极电性连接于恒压低电位（DCL）；
    第十六晶体管（T16），栅极电性连接于所述逻辑运算电路的第二输入端（B），漏极电性连接于所述逻辑运算电路的输出端（Vout），源极电性连接于恒压低电位（DCL）。
  12. 如权利要求11所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述第一反相器与所述第二反相器相同，均包括：
    第一晶体管（T1），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第一节点（S）；
    第二晶体管（T2），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第一节点（S），源极电性连接于第一负电位（VSS1）；
    第三晶体管（T3），栅极电性连接于第一节点（S），漏极电性连接于恒压高电位（DCH），源极电性连接于所述反相器的输出端（Vout）；
    第四晶体管（T4），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于所述反相器的输出端（Vout），源极电性连接第二节点（K）；
    第五晶体管（T5），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第三节点（M）；
    第六晶体管（T6），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第三节点（M），源极连接于恒压低电位（DCL）；
    第七晶体管（T7），栅极电性连接于第三节点（M），漏极电性连接于恒压高电位（DCH），源极电性连接于第二节点（K）；
    第八晶体管（T8），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第二节点（K），源极连接于恒压低电位（DCL）。
  13. 如权利要求12所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述第一反相器和所述第二反相器通过所述恒压低电位（DCL）以及所述第一负电位（VSS1）接收电路控制信号。
  14. 如权利要求11所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述第一反相器与所述第二反相器相同，均包括：
    第二十一晶体管（T21），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第一节点（S）；
    第二十二晶体管（T22），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第一节点（S），源极电性连接于第一负电位（VSS1）；
    第二十三晶体管（T23），栅极电性连接于第一节点（S），漏极电性连接于恒压高电位（DCH），源极电性连接于所述反相器的输出端（Vout）；
    第二十四晶体管（T24），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于所述反相器的输出端（Vout），源极电性连接第二节点（K）；
    第二十五晶体管（T25），栅极电性连接于第三节点（M），漏极电性连接于恒压高电位（DCH），源极电性连接于第二节点（K）；
    第二十六晶体管（T26），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第二节点（K），源极连接于恒压低电位（DCL）。
  15. 如权利要求14所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述第一反相器和所述第二反相器通过所述恒压高电位（DCH）以及所述恒压低电位（DCL）接收电路控制信号。
  16. 如权利要求11所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述第一反相器包括：
    第一晶体管（T1），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第一节点（S）；
    第二晶体管（T2），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第一节点（S），源极电性连接于第一负电位（VSS1）；
    第三晶体管（T3），栅极电性连接于第一节点（S），漏极电性连接于恒压高电位（DCH），源极电性连接于所述反相器的输出端（Vout）；
    第四晶体管（T4），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于所述反相器的输出端（Vout），源极电性连接第二节点（K）；
    第五晶体管（T5），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第三节点（M）；
    第六晶体管（T6），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第三节点（M），源极连接于恒压低电位（DCL）；
    第七晶体管（T7），栅极电性连接于第三节点（M），漏极电性连接于恒压高电位（DCH），源极电性连接于第二节点（K）；
    第八晶体管（T8），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第二节点（K），源极连接于恒压低电位（DCL）；
    所述第二反相器包括：
    第二十一晶体管（T21），栅极与漏极均电性连接于恒压高电位（DCH），源极电性连接于第一节点（S）；
    第二十二晶体管（T22），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第一节点（S），源极电性连接于第一负电位（VSS1）；
    第二十三晶体管（T23），栅极电性连接于第一节点（S），漏极电性连接于恒压高电位（DCH），源极电性连接于所述反相器的输出端（Vout）；
    第二十四晶体管（T24），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于所述反相器的输出端（Vout），源极电性连接第二节点（K）；
    第二十五晶体管（T25），栅极电性连接于第三节点（M），漏极电性连接于恒压高电位（DCH），源极电性连接于第二节点（K）；
    第二十六晶体管（T26），栅极电性连接于所述反相器的输入端（Vin），漏极电性连接于第二节点（K），源极连接于恒压低电位（DCL）。
  17. 如权利要求16所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述第一反相器通过所述恒压低电位（DCL）以及所述第一负电位（VSS1）接收电路控制信号，所述第二反相器通过所述恒压高电位（DCH）以及所述恒压低电位（DCL）接收电路控制信号。
  18. 如权利要求17所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述第一负电位（VSS1）、第二负电位（VSS2）与恒压低电位（DCL）的关系为：恒压低电位（DCL）<第二负电位（VSS2）<第一负电位（VSS1）。
  19. 如权利要求11所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述或非门逻辑运算电路通过所述恒压高电位（DCH）以及所述恒压低电位（DCL）接收电路控制信号。
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