WO2016107200A1 - 像素电路及其驱动方法和显示装置 - Google Patents

像素电路及其驱动方法和显示装置 Download PDF

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Publication number
WO2016107200A1
WO2016107200A1 PCT/CN2015/088255 CN2015088255W WO2016107200A1 WO 2016107200 A1 WO2016107200 A1 WO 2016107200A1 CN 2015088255 W CN2015088255 W CN 2015088255W WO 2016107200 A1 WO2016107200 A1 WO 2016107200A1
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WIPO (PCT)
Prior art keywords
signal
transistor
pixel
circuit
line
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PCT/CN2015/088255
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English (en)
French (fr)
Inventor
王延峰
商广良
徐晓玲
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/917,335 priority Critical patent/US10424261B2/en
Priority to EP15874886.3A priority patent/EP3242290A4/en
Publication of WO2016107200A1 publication Critical patent/WO2016107200A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes

Definitions

  • the present disclosure relates to a pixel circuit, a driving method thereof, and a display device.
  • the liquid crystal display includes an integrated circuit (hereinafter referred to as a driver IC) and a pixel circuit.
  • the driver IC provides an analog signal to the pixel circuit through which the pixel capacitance in the pixel circuit is charged.
  • the driver IC includes a digital circuit portion, a digital-to-analog conversion circuit portion, and an analog circuit portion for charging the pixel capacitance in the pixel circuit after converting the digital signal into an analog signal.
  • the structures of the digital circuit portion, the digital-to-analog conversion circuit portion, and the analog circuit portion in the driver IC are often complicated and large in size, the overall structure of the driver IC is complicated and large in size, thereby increasing the manufacturing of the driver IC. cost.
  • a pixel circuit, a driving method thereof, and a display device are provided for reducing a manufacturing cost of a driving IC.
  • a pixel circuit includes:
  • a selection circuit wherein the input end is connected to the selection signal end, the high level signal end and the low level signal end, and is configured to control charging or discharging of the pixel capacitor according to the digital signal input by the selection signal end;
  • a charge and discharge circuit having an input end connected to an output end of the selection circuit and a same gate line signal end corresponding to the pixel capacitance, wherein an output end is connected to the pixel capacitor for controlling under the control circuit
  • the pixel capacitor is charged or discharged
  • the precharging circuit has an input end connected to the upper row of the gate line signal end corresponding to the pixel capacitance, and an output end connected to the pixel capacitor for providing a reference voltage for the pixel capacitor.
  • the selection circuit includes:
  • a first transistor T1 having a gate connected to the selection signal terminal, a source connected to the high-level signal terminal, and a drain connected to the charge and discharge circuit;
  • the second transistor T2 has a gate connected to the selection signal terminal, a drain connected to the low-level signal terminal, and a source connected to the charge and discharge circuit.
  • the selection signal end includes a first data line and a second data line, and the first data line and the digital signal on the second data line have opposite polarity levels, and the first transistor T1 A gate is connected to the first data line, and a gate of the second transistor T2 is connected to the second data line.
  • the charging and discharging circuit comprises:
  • a third transistor T3 having a gate connected to a same row of gate line signal terminals corresponding to the pixel capacitance, a source connected to a drain of the first transistor T1, and a source and a drain connected to the second transistor T2 The pixel capacitance.
  • the pre-charging circuit includes:
  • the fourth transistor T4 has a gate connected to the pixel line of the upper row corresponding to the pixel capacitance, and a source and a drain are connected to the pixel capacitor.
  • the digital signal on the first data line and the digital signal on the second data line are pulse digital signals with adjustable duty cycles.
  • the selection circuit includes:
  • a first transistor M1 having a gate connected to the selection signal terminal, a source connected to the pixel capacitor, and a drain connected to the charge and discharge circuit;
  • a second transistor M2 having a gate connected to the selection signal terminal, a drain connected to the low-level signal terminal, and a source connected to the pre-charge circuit;
  • the fifth transistor M5 has a gate connected to the selection signal terminal, a source connected to the high-level signal terminal, and a drain connected to the pre-charge circuit.
  • the selection signal terminal includes a data line connected to a gate of the first transistor M1, and a selection signal line connected to a gate of the second transistor M2 and the first The gate of the five transistor M5, one of the second transistor M2 and the fifth transistor M5 is a P-type transistor and the other is an N-type transistor.
  • the charging and discharging circuit comprises:
  • the third transistor M3 has a gate connected to the same row gate signal terminal corresponding to the pixel capacitance, and a source connected to the drain and the drain of the first transistor M1 to connect the pixel capacitor.
  • the pre-charging circuit includes:
  • a fourth transistor M4 having a gate connected to a previous row of gate line signal terminals corresponding to the pixel capacitance, a source connected to the pixel capacitor, a drain connected to a source of the second transistor M2, and a fifth crystal The drain of the tube M5.
  • the digital signal on the data line is a pulse digital signal with adjustable duty ratio.
  • a method of driving a pixel circuit including:
  • the pre-charging circuit receives an input signal on the signal line of the upper row of the gate line corresponding to the pixel capacitance, and provides a reference voltage for the pixel capacitor according to the input signal on the signal end of the previous row of gate lines;
  • the selection circuit receives the digital signal on the selection signal terminal, and determines whether the charge and discharge circuit is charged or discharged according to the digital signal on the selection signal terminal;
  • the charge and discharge circuit receives an input signal on the signal line of the same row of gate lines corresponding to the pixel capacitance, and charges or discharges the pixel capacitance according to an input signal on the signal line end of the same row of gate lines.
  • the pre-charging circuit receives an input signal on a signal line of a previous row of gate lines corresponding to a pixel capacitance, and provides a reference voltage for the pixel capacitor according to an input signal on a signal end of the previous row of gate lines.
  • a gate of the fourth transistor T4 receives an input signal on a signal line of a previous row of gate lines corresponding to the pixel capacitance
  • the fourth transistor T4 When the input signal on the signal line of the upper row of the gate line is a high level signal, the fourth transistor T4 is turned on to provide a reference voltage for the pixel capacitor.
  • the selection signal end includes a first data line and a second data line; the selection circuit receives the digital signal on the selection signal end, and determines the charging and discharging according to the digital signal on the selection signal end Charging or discharging the circuit, including:
  • the first transistor T1 When the digital signal on the first data line is a low level signal, and the digital signal on the second data line is a high level signal, the first transistor T1 is turned off, and the second transistor is turned on. It is determined that the charge and discharge circuit is discharged.
  • the charging and discharging circuit receives an input signal on a signal line end of the same row of gate lines corresponding to the pixel capacitance, and charges the pixel capacitor according to an input signal on a signal line end of the same row of gate lines.
  • discharge including:
  • a gate of the third transistor T3 receives an input signal on a signal line end of the same row corresponding to the pixel capacitance
  • the third transistor T3 When the input signal on the signal line of the same row gate line is a high level signal, the third transistor T3 is turned on to charge or discharge the pixel capacitor.
  • the digital signal on the first data line and the digital signal on the second data line are pulse digital signals with adjustable duty cycles.
  • the pre-charging circuit receives an input signal on a signal line of a previous row of gate lines corresponding to a pixel capacitance, and provides a reference voltage for the pixel capacitor according to an input signal on a signal end of the previous row of gate lines.
  • the fourth transistor M4 receives an input signal on a signal line of a previous row of gate lines corresponding to the pixel capacitance
  • the fourth transistor M4 When the input signal on the signal line of the upper row of the gate line is at a high level, the fourth transistor M4 is turned on.
  • the selection signal end includes a data line and a selection signal line;
  • the second transistor M2 is an N-type transistor, and the fifth transistor M5 is a P-type transistor;
  • the selection circuit receives the digital signal on the selection signal end, and according to Determining the charging or discharging of the charging and discharging circuit by the digital signal on the signal terminal, comprising:
  • the second transistor M2 When the input signal on the selection signal line is a high level signal, the second transistor M2 is turned off, and the fifth transistor M5 is turned on to determine that the charging and discharging circuit is charged;
  • the second transistor M2 When the input signal on the selection signal line is a low level signal, the second transistor M2 is turned on, the fifth transistor M5 is turned off, and the charging and discharging circuit is determined to be discharged;
  • the source and the drain of the first transistor M1 are turned on.
  • it also includes:
  • the second transistor M2 When the input signal on the selection signal line is a high level signal, the second transistor M2 is turned off, and the fifth transistor M5 is turned on to precharge the pixel capacitance;
  • the second transistor M2 When the input signal on the selection signal line is a low level signal, the second transistor M2 is turned on, and the fifth transistor M5 is turned off to pre-discharge the pixel capacitor.
  • the charging and discharging circuit receives an input signal on a signal line end of the same row of gate lines corresponding to the pixel capacitance, and charges the pixel capacitor according to an input signal on a signal line end of the same row of gate lines.
  • discharge including:
  • a gate of the third transistor M3 receives an input signal on a signal line end of the same row corresponding to the pixel capacitance
  • the pixel capacitor When the input signal on the signal line of the same row gate line is a high level signal, the pixel capacitor is charged or discharged.
  • the digital signal on the data line is a pulse digital signal with adjustable duty ratio.
  • a display device including any of the above pixel circuits.
  • the pixel circuit includes a selection circuit, a charge and discharge circuit, and a precharge circuit.
  • the selection circuit can control the charging and discharging circuit to charge or discharge the pixel capacitor according to the digital signal input from the connected selection signal terminal, so that the pixel circuit can be directly charged by the digital signal provided by the driving IC, and the digital mode in the driving IC is omitted.
  • the conversion circuit and the analog circuit portion simplify the structure of the driver IC and also reduce the size of the driver IC, thereby reducing the manufacturing cost of the driver IC.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided in a first embodiment of the present disclosure
  • FIG. 2 is a flowchart of a driving method of a pixel circuit provided in a first embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a pixel circuit provided in a second embodiment of the present disclosure.
  • FIG. 4 is a signal timing diagram of the pixel circuit provided in FIG. 3;
  • FIG. 5 is a flowchart of a driving method of a pixel circuit according to a second embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a pixel circuit according to a third embodiment of the present disclosure.
  • FIG. 7 is a signal timing diagram of the pixel circuit provided in FIG. 6;
  • FIG. 8 is a flowchart of a driving method of a pixel circuit provided in a third embodiment of the present disclosure.
  • FIG. 1 is a block diagram showing the structure of a pixel circuit provided in a first embodiment of the present disclosure.
  • the pixel circuit includes a selection circuit P1, a charge and discharge circuit P2, and a precharge circuit P3.
  • the input terminal of the selection circuit P1 is connected to the selection signal terminal S, the high-level signal terminal VH, and the low-level signal terminal VL, and the output terminal thereof is connected to the control terminal of the charge and discharge circuit P2.
  • the selection circuit P1 is for controlling the charge and discharge circuit P2 to charge or discharge the pixel capacitance C1 according to the digital signal input from the selection signal terminal S.
  • the charge and discharge circuit P2 is for charging or discharging the pixel capacitor C1 under the control of the selection circuit P1.
  • the input end of the precharge circuit P3 is connected to the upper row of the gate line signal terminal Gn -1 corresponding to the pixel capacitor C1, and the output end thereof is connected to the other end of the pixel capacitor C1.
  • the precharge circuit P3 is used to supply a reference voltage to the pixel capacitor C1.
  • the selection signal terminal S outputs a digital signal.
  • one or more resistors for voltage division may also be provided in the pixel circuit.
  • the precharge circuit in the pixel circuit of the current row is precharging the pixel capacitance of the current row
  • the charge and discharge circuit in the pixel circuit of the previous row is charging or discharging the pixel capacitance of the previous row.
  • FIG. 2 is a flow chart showing a driving method of a pixel circuit provided in the first embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a driving method of the pixel circuit shown in FIG. 1 above, which method includes the following processes:
  • the precharge circuit receives an input signal on the signal line of the upper row of the gate line corresponding to the pixel capacitance, and provides a reference voltage for the pixel capacitance according to the input signal on the signal terminal of the previous row of gate lines.
  • step 102 the selection circuit receives the digital signal on the selection signal terminal and determines whether the charge and discharge circuit is charged or discharged according to the digital signal on the selection signal terminal.
  • the charge and discharge circuit receives the input signal on the signal line of the same row of gate lines corresponding to the pixel capacitance, and charges or discharges the pixel capacitance according to the input signal on the signal line end of the same row of gate lines.
  • Embodiments of the present disclosure provide a pixel circuit including a selection circuit, a charge and discharge circuit, and a precharge circuit, and a method of driving the pixel circuit.
  • the selection circuit can control the charging and discharging circuit to charge or discharge the pixel capacitor according to the digital signal input from the connected selection signal terminal, so that the pixel circuit can be directly charged by the digital signal provided by the driving IC, and the digital mode in the driving IC is omitted.
  • the conversion circuit and the analog circuit portion simplify the structure of the driver IC and also reduce the size of the driver IC, thereby reducing the manufacturing cost of the driver IC.
  • FIG. 3 is a block diagram showing the structure of a pixel circuit provided in a second embodiment of the present disclosure.
  • the selection circuit P1 in the pixel circuit provided by the embodiment of the present disclosure includes a first transistor T1 and a second transistor T2.
  • the charge and discharge circuit P2 includes a third transistor T3, and the precharge circuit P3 includes a fourth transistor T4, which is an equivalent capacitance of the liquid crystal.
  • the gate of the first transistor T1 is connected to the first data line D1, the source is connected to the high-level signal terminal VH, and the drain is connected to the charge and discharge circuit P2.
  • the gate of the second transistor T2 is connected to the second data line D2, the drain is connected to the low-level signal terminal VL, and the source is connected to the charge and discharge circuit P2.
  • the gate of the third transistor connected to the pixel capacitor C1 corresponding to the same gate line G n T3 signal terminal, a source electrode connected to the drain of the first transistor T1 and the source of the second transistor T2, a drain connected to the pixel capacitor C1.
  • the gate of the fourth transistor T4 is connected to the upper row of gate signal terminals Gn -1 corresponding to the pixel capacitor C1, and the source and the drain are respectively connected to both ends of the pixel capacitor C1.
  • one or more resistors may be provided in the above pixel circuit.
  • the one or more resistors are equivalent to an equivalent resistor R, which is coupled to the pixel capacitor C1.
  • the selection signal terminal S may include a first data line D1 and a second data line D2.
  • the levels of the digital signals on the first data line D1 and the second data line D2 are opposite in polarity. For example, when the digital signal on the first data line D1 is a high level signal, the digital signal on the second data line D2 is a low level signal; when the digital signal on the first data line D1 is a low level signal The digital signal on the second data line D2 is a high level signal.
  • FIG. 4 shows a signal timing diagram of the pixel circuit provided in FIG. Referring to the signal timing chart shown in FIG. 4, the operation principle of the pixel circuit shown in FIG. 3 will be described below by taking the first transistor T1 to the fourth transistor T4 as N-type transistors as an example.
  • the signal timing diagram shown in FIG. 4 can be divided into four stages, namely, a pre-charging stage w1, a charging stage w2, a discharging stage w3, and a charging end stage w4.
  • the signal on the gate line signal terminal Gn -1 of the previous row is a high level signal
  • the fourth transistor T4 is turned on to pre-charge the pixel capacitor C1 until the voltage on the pixel capacitor C1 reaches the reference voltage.
  • the signal on the same row gate signal terminal G n corresponding to the pixel capacitor C1 is a low level signal
  • the third transistor T3 is turned off
  • the polarity of the digital signal on the first data line D1 is not limited, and may be a high level signal. It may also be a low level signal
  • the digital signal on the second data line D2 is opposite in polarity to the digital signal on the first data line D1.
  • the gate-line signal on the line end signal G n-1 is a low level signal
  • the fourth transistor T4 is turned off, the pre-charging has been completed, the capacitor C1 and the pixel corresponding to the same gate line G n signal terminal
  • the signal is a high level signal
  • the third transistor T3 is turned on, and the selection circuit P1 and the charge and discharge circuit P2 are connected.
  • the digital signal on the first data line D1 is a high level signal, and the first transistor T1 is turned on, and the second data is turned on.
  • the digital signal on line D2 is a low level signal, the second transistor T2 is turned off, and the high level signal terminal VH charges the pixel capacitor C1.
  • the capacitor C1 on the pixel signals corresponding to the same gate line G n is a signal terminal a high level signal
  • the third transistor T3 is turned on
  • the selection circuit P1 and P2 communication charge-discharge circuit the first data line D1
  • the upper digital signal is a low level signal
  • the first transistor T1 is turned off
  • the digital signal on the second data line D2 is a high level signal
  • the second transistor T2 is turned on
  • the low level signal terminal VL is discharged by the pixel capacitor C1.
  • the third transistor T3 is turned off, the selection circuit P1 and P2 charge-discharge circuit is turned off, stopping the pixel capacitance Charging or discharging.
  • the digital signal on the first data line D1 and the digital signal on the second data line D2 are pulse digital signals with adjustable duty ratio, that is, the digital signal on the first data line D1 is at a high level.
  • the duration and the duration of the digital signal on the first data line D1 being low level are adjustable, so that the time for charging or discharging the pixel capacitor C1 can be adjusted, thereby adjusting the voltage on the pixel capacitor C1.
  • FIG. 5 is a flow chart showing a driving method of a pixel circuit provided in a second embodiment of the present disclosure. Referring to FIG. 5, an embodiment of the present disclosure further provides a driving method of the pixel circuit as shown in FIG. 3. The method includes the following process:
  • step 201 the gate of the fourth transistor T4 receives the input signal on the signal line of the previous row of gate lines corresponding to the pixel capacitance C1.
  • step 202 when the input signal on the signal line of the previous row of gate lines is a high level signal, the fourth transistor T4 is turned on to provide a reference voltage for the pixel capacitor.
  • step 203 when the digital signal on the first data line is a high level signal and the digital signal on the second data line is a low level signal, the first transistor T1 is turned on, the second transistor is turned off, and the charging and discharging are determined. The circuit is charged.
  • step 204 when the digital signal on the first data line is a low level signal and the digital signal on the second data line is a high level signal, the first transistor T1 is turned off, and the second transistor is turned on to determine charging and discharging. The circuit is discharged.
  • step 205 the gate of the third transistor T3 receives an input signal on the signal line of the same row of gate lines corresponding to the pixel capacitance C1.
  • step 206 when the input signal on the signal line terminal of the same row line is a high level signal, the third transistor T3 is turned on to charge or discharge the pixel capacitance.
  • step 206 when it is determined in step 203 that the charging and discharging circuit charges the pixel capacitor C1, in step 206, the pixel capacitor C1 is charged; when in step 204, the charging and discharging circuit is determined to be a pixel. When the capacitor C1 is discharged, in step 206, the pixel capacitor C1 is discharged.
  • Embodiments of the present disclosure provide a pixel circuit including a selection power
  • the circuit, the charging and discharging circuit and the pre-charging circuit, the selection circuit can control the charging and discharging circuit to charge or discharge the pixel capacitor according to the digital signal input from the connected selection signal terminal, so that the pixel circuit can be directly charged by the digital signal provided by the driving IC.
  • the digital-to-analog conversion circuit and the analog circuit portion of the driver IC are omitted, the structure of the driver IC is simplified, and the size of the driver IC is also reduced, thereby reducing the manufacturing cost of the driver IC.
  • the time at which the pixel capacitance is charged or discharged can be adjusted by adjusting the duty ratio of the digital signal on the first data line and the second data line, thereby adjusting the voltage value on the pixel capacitance.
  • FIG. 6 is a block diagram showing the structure of a pixel circuit provided in a third embodiment of the present disclosure.
  • the selection circuit P1 in the pixel circuit includes a first transistor M1, a second transistor M2, and a fifth transistor M5.
  • the charge and discharge circuit P2 includes a third transistor M3.
  • the precharge circuit P3 includes a fourth transistor M4, C2. Is the equivalent capacitance of the liquid crystal.
  • the gate of the first transistor M1 is connected to the selection signal terminal S (not shown), the source is connected to the pixel capacitor C1, and the drain is connected to the charge and discharge circuit P2.
  • the gate of the second transistor M2 is connected to the selection signal terminal S (not shown), the drain is connected to the low-level signal terminal VL, and the source is connected to the pre-charge circuit P3.
  • the gate of the fifth transistor M5 is connected to the selection signal terminal S (not shown), the source is connected to the high level signal terminal VH, and the drain is connected to the precharge circuit P3.
  • the gate of the third transistor M3 is connected to the pixel capacitor C1 corresponding to the same gate line signal terminal G n, a source electrode connected to the drain of the first transistor M1, a drain connected to the pixel capacitor C1.
  • the gate of the fourth transistor M4 is connected to the upper row of gate signal terminals Gn -1 corresponding to the pixel capacitor C1, the source is connected to the pixel capacitor C1, and the drain is connected to the source of the second transistor M2 and the drain of the fifth transistor M5. .
  • one or more resistors can be placed in the pixel circuit.
  • the one or more resistors are equivalent to an equivalent resistor R, which is coupled to the pixel capacitor C1.
  • the selection signal terminal S includes a data line D and a selection signal line SL.
  • the data line D is connected to the gate of the first transistor M1
  • the selection signal line SL is connected to the gate of the second transistor M2 and the gate of the fifth transistor M5.
  • One of the second transistor M2 and the fifth transistor M5 is an N-type transistor and the other is a P-type transistor.
  • the fifth transistor M5 is a P-type transistor
  • the fifth transistor M5 is a P-type transistor.
  • FIG. 7 shows a signal timing diagram of the pixel circuit provided in FIG.
  • the operation principle of the pixel circuit shown in FIG. 6 will be described with reference to the signal timing chart shown in FIG. 7 in which the second transistor M2 is a P-type transistor and the fifth transistor M5 is an N-type transistor.
  • the signal timing diagram shown in FIG. 7 can be divided into four stages, namely, a pre-charging stage w5, a pre-discharging stage w6, a charging and discharging stage w7, and a charge and discharge junction.
  • Beam stage w8 Beam stage w8.
  • the signal on the signal line Gn-1 of the previous row is a high level signal
  • the fourth transistor M4 is turned on
  • the signal on the selection signal line SL is a high level signal
  • the second transistor M2 is turned off.
  • the fifth transistor M5 is turned on, pre-charging of pixel capacitance C1, the signal on the same gate line G n pixel signal terminal of the capacitor C1 corresponding to a low level signal
  • a digital M3 is turned off
  • the polarity of the signal is not limited, it can be a high level signal or a low level signal.
  • the signal on the gate line signal terminal Gn -1 of the previous row is a high level signal
  • the fourth transistor M4 is turned on
  • the signal on the selection signal line SL is a low level signal
  • the second transistor M2 leads
  • the fifth transistor M5 is turned off, and the pixel capacitor C1 is pre-discharged until the reference voltage is reached.
  • the signal corresponding to the pixel capacitance C1 of the same gate line G n signal terminal is low level signal
  • the third transistor M3 is turned off
  • the polarity of the digital signal data lines is not limited, and may be a high-level signal, may be Is a low level signal.
  • the signal on the signal line G n-1 of the previous row of gate lines is a low level signal
  • the fourth transistor T4 is turned off
  • the precharge including the precharge and/or pre-discharge process
  • the selection circuit communication charge-discharge circuit P1 and P2 the digital signal on the data line D is high level signal
  • the first transistor M1 is turned on, Charging or discharging the pixel capacitor C1.
  • the signal on the data line D is a low level signal
  • the first transistor M1 is turned off
  • the selection circuit P1 and the charge and discharge circuit P2 are turned off, and charging or discharging of the pixel capacitance is stopped.
  • the digital signal on the data line D is a pulse digital signal with adjustable duty ratio, that is, the duration of the digital signal on the data line D being high level and the digital signal on the data line D being low level.
  • the duration is adjustable so that the time during which the pixel capacitor C1 is charged or discharged can be adjusted to adjust the voltage across the pixel capacitor C1.
  • FIG. 8 is a flow chart showing a driving method of a pixel circuit provided in a third embodiment of the present disclosure. Referring to FIG. 8, the driving method of the pixel circuit shown in FIG. 6 includes the following processes:
  • step 301 the fourth transistor M4 receives an input signal on the signal line of the previous row of gate lines corresponding to the pixel capacitance C1.
  • step 302 when the input signal on the signal line of the previous row of gate lines is at a high level, the fourth transistor M4 is turned on.
  • step 303 when the input signal on the selection signal line is a high level signal, the second transistor M2 is turned off, and the fifth transistor M5 is turned on to precharge the pixel capacitance.
  • step 304 when the input signal on the selection signal line is a low level signal, the second transistor M2 is turned on, and the fifth transistor M5 is turned off to pre-discharge the pixel capacitor.
  • step 305 when the input signal on the selection signal line is a high level signal, the second transistor M2 is turned off, and the fifth transistor M5 is turned on to determine that the charge and discharge circuit is charged.
  • step 306 when the input signal on the selection signal line is a low level signal, the second transistor M2 is turned on, and the fifth transistor M5 is turned off to determine that the charge and discharge circuit is discharged.
  • step 307 when the digital signal on the data line is a high level signal, the first transistor M1 is turned on.
  • step 308 the gate of the third transistor M3 receives an input signal on the same row of gate line signal ends corresponding to the pixel capacitance.
  • step 309 when the input signal on the signal line terminal of the same row is a high level signal, the pixel capacitance is charged or discharged.
  • Embodiments of the present disclosure provide a pixel circuit including a selection circuit, a charge and discharge circuit, and a precharge circuit.
  • the selection circuit can control a charge and discharge circuit as a pixel capacitor according to a digital signal input from a connected selection signal terminal. Charging or discharging, the pixel circuit can be directly charged by the digital signal provided by the driver IC, eliminating the digital-to-analog conversion circuit and the analog circuit part in the driver IC, simplifying the structure of the driver IC and reducing the driving.
  • the size of the IC reduces the manufacturing cost of the driver IC.
  • the time of charging or discharging the pixel capacitance can be adjusted by adjusting the duty ratio of the digital signal on the data line, thereby adjusting the voltage value on the pixel capacitance.
  • Embodiments of the present disclosure also provide a display device including any of the above pixel circuits.
  • the display device can be any product or component having display function such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, and the like.

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Abstract

公开了一种像素电路及其驱动方法和显示装置。该像素电路包括：选择电路（P1），输入端连接选择信号端、高电平信号端和低电平信号端，用于根据选择信号端输入的数字信号控制像素电容的充电或放电；充放电电路（P2），输入端连接与像素电容对应的同一行栅线信号端，输出端连接像素电容，用于在选择电路的控制下为像素电容进行充电或放电；预充电电路（P3），输入端连接与像素电容对应的上一行栅线信号端，输出端连接像素电容，用于提供基准电压。还公开了该像素电路的驱动方法及包括该像素电路的显示装置。该像素电路省去了驱动IC中的数模转换电路和模拟电路部分，简化了驱动IC的结构，减小了驱动IC的尺寸，降低了驱动IC的制造成本。

Description

像素电路及其驱动方法和显示装置 技术领域
本公开涉及一种像素电路及其驱动方法和显示装置。
背景技术
随着液晶显示技术的发展，越来越多的电子设备采用液晶显示器作为显示屏幕。液晶显示器包括驱动集成电路(Integrated circuit，以下简称驱动IC)和像素电路。驱动IC为像素电路提供模拟信号，通过该模拟信号为像素电路中的像素电容充电。
驱动IC中包括数字电路部分、数模转换电路部分和模拟电路部分，用于在将数字信号转化为模拟信号后为像素电路中的像素电容进行充电。但是，由于驱动IC中的数字电路部分、数模转换电路部分、模拟电路部分的结构往往都较为复杂，且尺寸较大，使得驱动IC整体的结构复杂、尺寸大，进而增加了驱动IC的制造成本。
发明内容
在本公开的若干实施例中提供一种像素电路及其驱动方法和显示装置，用于降低驱动IC的制造成本。
按照本公开的一方面，提供一种像素电路。该像素电路包括：
选择电路，其输入端连接选择信号端、高电平信号端和低电平信号端，用于根据所述选择信号端输入的数字信号控制像素电容的充电或放电；
充放电电路，其输入端连接所述选择电路的输出端和与所述像素电容对应的同一行栅线信号端，其输出端连接所述像素电容，用于在所述选择电路的控制下为所述像素电容进行充电或放电；
预充电电路，其输入端连接与所述像素电容对应的上一行栅线信号端，其输出端连接所述像素电容，用于为所述像素电容提供基准电压。
可选地，所述选择电路包括：
第一晶体管T1，其栅极连接所述选择信号端、源极连接所述高电平信号端、漏极连接所述充放电电路；
第二晶体管T2，其栅极连接所述选择信号端、漏极连接所述低电平信号端、源极连接所述充放电电路。
进一步地，所述选择信号端包括第一数据线和第二数据线，所述第一数据线与所述第二数据线上的数字信号的电平极性相反，所述第一晶体管T1的栅极连接所述第一数据线，所述第二晶体管T2的栅极连接所述第二数据线。
可选地，所述充放电电路包括：
第三晶体管T3，其栅极连接与所述像素电容对应的同一行栅线信号端、源极连接所述第一晶体管T1的漏极和所述第二晶体管T2的源极、漏极连接所述像素电容。
可选地，所述预充电电路包括：
第四晶体管T4，其栅极连接与所述像素电容对应的上一行栅线信号端、源极和漏极均连接所述像素电容。
进一步地，所述第一数据线上的数字信号与所述第二数据线上的数字信号均为占空比可调的脉冲数字信号。
可选地，所述选择电路包括：
第一晶体管M1，其栅极连接所述选择信号端、源极连接所述像素电容、漏极连接所述充放电电路；
第二晶体管M2，其栅极连接所述选择信号端、漏极连接所述低电平信号端、源极与所述预充电电路相连；
第五晶体管M5，其栅极连接所述选择信号端、源极连接所述高电平信号端、漏极与所述预充电电路相连。
进一步地，所述选择信号端包括数据线和选择信号线，所述数据线连接所述第一晶体管M1的栅极，所述选择信号线连接所述第二晶体管M2的栅极和所述第五晶体管M5的栅极，所述第二晶体管M2和所述第五晶体管M5中的一个为P型晶体管、另一个为N型晶体管。
可选地，所述充放电电路包括：
第三晶体管M3，其栅极连接与所述像素电容对应的同一行栅线信号端、源极连接所述第一晶体管M1的漏极、漏极连接所述像素电容。
可选地，所述预充电电路包括：
第四晶体管M4，其栅极连接与所述像素电容对应的上一行栅线信号端、源极连接所述像素电容、漏极连接所述第二晶体管M2的源极和所述第五晶体 管M5的漏极。
进一步地，所述数据线上的数字信号为占空比可调的脉冲数字信号。
另一方面，提供一种像素电路的驱动方法，包括：
预充电电路接收与像素电容对应的上一行栅线信号端上的输入信号，并根据所述上一行栅线信号端上的输入信号，为所述像素电容提供基准电压；
选择电路接收选择信号端上的数字信号，并根据所述选择信号端上的数字信号，确定所述充放电电路充电或放电；
充放电电路接收与所述像素电容对应的同一行栅线信号端上的输入信号，并根据所述同一行栅线信号端上的输入信号，为所述像素电容进行充电或放电。
可选地，所述预充电电路接收与像素电容对应的上一行栅线信号端上的输入信号，并根据所述上一行栅线信号端上的输入信号，为所述像素电容提供基准电压，包括：
第四晶体管T4的栅极接收与所述像素电容对应的上一行栅线信号端上的输入信号；
当所述上一行栅线信号端上的输入信号为高电平信号时，所述第四晶体管T4导通，为所述像素电容提供基准电压。
可选地，所述选择信号端包括第一数据线和第二数据线；所述选择电路接收选择信号端上的数字信号，并根据所述选择信号端上的数字信号，确定所述充放电电路充电或放电，包括：
当所述第一数据线上的数字信号为高电平信号，所述第二数据线上的数字信号为低电平信号时，第一晶体管T1导通，第二晶体管截止，确定所述充放电电路充电；
当所述第一数据线上的数字信号为低电平信号，所述第二数据线上的数字信号为高电平信号时，所述第一晶体管T1截止，所述第二晶体管导通，确定所述充放电电路放电。
可选地，所述充放电电路接收与所述像素电容对应的同一行栅线信号端上的输入信号，并根据所述同一行栅线信号端上的输入信号，为所述像素电容进行充电或放电，包括：
第三晶体管T3的栅极接收与所述像素电容对应的同一行栅线信号端上的输入信号；
当所述同一行栅线信号端上的输入信号为高电平信号时，所述第三晶体管T3导通，为所述像素电容进行充电或放电。
进一步地，所述第一数据线上的数字信号与所述第二数据线上的数字信号均为占空比可调的脉冲数字信号。
可选地，所述预充电电路接收与像素电容对应的上一行栅线信号端上的输入信号，并根据所述上一行栅线信号端上的输入信号，为所述像素电容提供基准电压，包括：
第四晶体管M4接收与所述像素电容对应的上一行栅线信号端上的输入信号；
当所述上一行栅线信号端上的输入信号为高电平时，所述第四晶体管M4导通。
可选地，所述选择信号端包括数据线和选择信号线；第二晶体管M2为N型晶体管，第五晶体管M5为P型晶体管；所述选择电路接收选择信号端上的数字信号，并根据所述选择信号端上的数字信号，确定所述充放电电路充电或放电，包括：
当所述选择信号线上的输入信号为高电平信号时，所述第二晶体管M2截止，所述第五晶体管M5导通，确定所述充放电电路充电；
当所述选择信号线上的输入信号为低电平信号时，所述第二晶体管M2导通，所述第五晶体管M5截止，确定所述充放电电路放电；
当所述数据线上的数字信号为高电平信号时，第一晶体管M1的源极、漏极导通。
可选地，还包括：
当所述选择信号线上的输入信号为高电平信号时，所述第二晶体管M2截止，所述第五晶体管M5导通，为像素电容进行预充电；
当所述选择信号线上的输入信号为低电平信号时，所述第二晶体管M2导通，所述第五晶体管M5截止，为所述像素电容进行预放电。
可选地，所述充放电电路接收与所述像素电容对应的同一行栅线信号端上的输入信号，并根据所述同一行栅线信号端上的输入信号，为所述像素电容进行充电或放电，包括：
第三晶体管M3的栅极接收与所述像素电容对应的同一行栅线信号端上的输入信号；
当所述同一行栅线信号端上的输入信号为高电平信号时，为所述像素电容进行充电或放电。
进一步地，所述数据线上的数字信号为占空比可调的脉冲数字信号。
另一方面，提供一种显示装置，包括上述任一像素电路。
本公开实施例中提供的像素电路及其驱动方法和显示装置中，该像素电路包括选择电路、充放电电路和预充电电路。选择电路能够根据连接的选择信号端输入的数字信号控制充放电电路为像素电容进行充电或放电，从而可以直接利用驱动IC提供的数字信号对像素电路进行充电，省去了驱动IC中的数模转换电路和模拟电路部分，简化了驱动IC的结构，同时也减小了驱动IC的尺寸，从而降低了驱动IC的制造成本。
附图说明
图1为本公开的第一实施例中提供的一种像素电路的结构示意图；
图2为本公开的第一实施例中提供的一种像素电路的驱动方法的流程图；
图3为本公开的第二实施例中提供的一种像素电路的结构示意图；
图4为图3提供的像素电路的信号时序图；
图5为本公开的第二实施例中提供的一种像素电路的驱动方法的流程图；
图6为本公开的第三实施例中提供的一种像素电路的结构示意图；
图7为图6提供的像素电路的信号时序图；
图8为本公开的第三实施例中提供的一种像素电路的驱动方法的流程图。
具体实施方式
为了进一步说明本公开实施例提供的像素电路及其驱动方法和显示装置，下面结合说明书附图进行详细描述。
第一实施例
图1示出本公开的第一实施例中提供的一种像素电路的结构示意图。请参阅图1，该像素电路包括选择电路P1、充放电电路P2和预充电电路P3。图1中，选择电路P1的输入端连接选择信号端S、高电平信号端VH和低电平信号端VL，其输出端连接充放电电路P2的控制端。选择电路P1用于根据选择信号端S输入的数字信号控制充放电电路P2为像素电容C1进行充电或放电。充放电电路P2的输入端连接与像素电容C1对应的同一行栅线信号端Gn，其 输出端连接像素电容C1的一端。充放电电路P2用于在选择电路P1的控制下为像素电容C1进行充电或放电。预充电电路P3的输入端连接与像素电容C1对应的上一行栅线信号端Gn-1，其输出端连接像素电容C1的另一端。预充电电路P3用于为像素电容C1提供基准电压。这里，选择信号端S输出的是数字信号。示例性地，在像素电路中还可以设置一个或多个用于分压的电阻。
需要说明的是，当当前行的像素电路中的预充电电路正在对当前行的像素电容进行预充电时，上一行的像素电路中的充放电电路正在对上一行的像素电容进行充电或放电。
图2示出了本公开的第一实施例中提供的一种像素电路的驱动方法的流程图。请参阅图2，本公开实施例还提供了上述如图1所示的像素电路的驱动方法，该方法包括下列过程：
在步骤101中，预充电电路接收与像素电容对应的上一行栅线信号端上的输入信号，并根据上一行栅线信号端上的输入信号，为像素电容提供基准电压。
在步骤102中，选择电路接收选择信号端上的数字信号，并根据选择信号端上的数字信号，确定充放电电路充电或放电。
在步骤103中，充放电电路接收与像素电容对应的同一行栅线信号端上的输入信号，并根据同一行栅线信号端上的输入信号，为像素电容进行充电或放电。
本公开实施例提供了一种像素电路以及该像素电路的驱动方法，该像素电路包括选择电路、充放电电路和预充电电路。选择电路能够根据连接的选择信号端输入的数字信号控制充放电电路为像素电容进行充电或放电，从而可以直接利用驱动IC提供的数字信号对像素电路进行充电，省去了驱动IC中的数模转换电路和模拟电路部分，简化了驱动IC的结构，同时也减小了驱动IC的尺寸，从而降低了驱动IC的制造成本。
第二实施例
图3示出了本公开的第二实施例中提供的一种像素电路的结构示意图。进一步地，请参阅图3，本公开实施例提供的像素电路中的选择电路P1包括第一晶体管T1和第二晶体管T2。充放电电路P2包括第三晶体管T3，预充电电路P3包括第四晶体管T4，C2为液晶的等效电容。第一晶体管T1的栅极连接第一数据线D1，源极连接高电平信号端VH，漏极连接充放电电路P2。第二晶体管T2的栅极连接第二数据线D2，漏极连接低电平信号端VL，源极连接 充放电电路P2。第三晶体管T3的栅极连接与像素电容C1对应的同一行栅线信号端Gn，源极连接第一晶体管T1的漏极和第二晶体管T2的源极，漏极连接像素电容C1。第四晶体管T4的栅极连接与像素电容C1对应的上一行栅线信号端Gn-1，源极和漏极分别连接到像素电容C1的两端。
示例性地，可以在上述像素电路中设置一个或多个电阻。在图3中，将这一个或多个电阻等效为一个等效电阻R，该等效电阻R与像素电容C1连接。选择信号端S可以包括第一数据线D1和第二数据线D2。第一数据线D1和第二数据线D2上的数字信号的电平极性相反。比如，当第一数据线D1上的数字信号为高电平信号时，第二数据线D2上的数字信号为低电平信号；当第一数据线D1上的数字信号为低电平信号时，第二数据线D2上的数字信号为高电平信号。
图4示出图3提供的像素电路的信号时序图。结合图4所示的信号时序图，下面以第一晶体管T1至第四晶体管T4均为N型晶体管为例，对图3所示的像素电路的工作原理进行说明。图4所示的信号时序图可分为4个阶段，分别为预充电阶段w1、充电阶段w2、放电阶段w3和充电结束阶段w4。
在预充电阶段w1，上一行栅线信号端Gn-1上的信号为高电平信号，第四晶体管T4导通，为像素电容C1进行预充电，直至像素电容C1上的电压达到基准电压。与像素电容C1对应的同一行栅线信号端Gn上的信号为低电平信号，第三晶体管T3截止，第一数据线D1上的数字信号的极性不限，可以是高电平信号，也可以是低电平信号，第二数据线D2上的数字信号与第一数据线D1上的数字信号极性相反。
在充电阶段w2，上一行栅线信号端Gn-1上的信号为低电平信号，第四晶体管T4截止，预充电已完成，与像素电容C1对应的同一行栅线信号端Gn上的信号为高电平信号，第三晶体管T3导通，连通选择电路P1和充放电电路P2，第一数据线D1上的数字信号为高电平信号，第一晶体管T1导通，第二数据线D2上的数字信号为低电平信号，第二晶体管T2截止，高电平信号端VH为像素电容C1进行充电。
在放电阶段w3，与像素电容C1对应的同一行栅线信号端Gn上的信号为高电平信号，第三晶体管T3导通，选择电路P1和充放电电路P2连通，第一数据线D1上的数字信号为低电平信号，第一晶体管T1截止，第二数据线D2上的数字信号为高电平信号，第二晶体管T2导通，低电平信号端VL为像素 电容C1进行放电。
在充电结束阶段w4，与像素电容C1对应的同一行栅线信号端Gn上的信号为低电平信号，第三晶体管T3截止，选择电路P1和充放电电路P2断开，停止对像素电容的充电或放电。
上述实施例中，第一数据线D1上的数字信号与第二数据线D2上的数字信号均为占空比可调的脉冲数字信号，即第一数据线D1上的数字信号为高电平的持续时间和第一数据线D1上的数字信号为低电平的持续时间是可调的，从而可以调整对像素电容C1进行充电或放电的时间，进而调整像素电容C1上的电压。
图5示出本公开的第二实施例中提供的像素电路的驱动方法的流程图。请参阅图5，本公开实施例还提供了如图3所示的像素电路的驱动方法。该方法包括下列过程：
在步骤201中，第四晶体管T4的栅极接收与像素电容C1对应的上一行栅线信号端上的输入信号。
在步骤202中，当上一行栅线信号端上的输入信号为高电平信号时，第四晶体管T4导通，为所述像素电容提供基准电压。
在步骤203中，当第一数据线上的数字信号为高电平信号，第二数据线上的数字信号为低电平信号时，第一晶体管T1导通，第二晶体管截止，确定充放电电路充电。
在步骤204中，当第一数据线上的数字信号为低电平信号，第二数据线上的数字信号为高电平信号时，第一晶体管T1截止，第二晶体管导通，确定充放电电路放电。
在步骤205中，第三晶体管T3的栅极接收与像素电容C1对应的同一行栅线信号端上的输入信号。
在步骤206中，当同一行栅线信号端上的输入信号为高电平信号时，第三晶体管T3导通，为像素电容进行充电或放电。
图5所示实施例中，当在步骤203中，确定充放电电路为像素电容C1进行充电，则在步骤206中，为像素电容C1进行充电；当在步骤204中，确定充放电电路为像素电容C1进行放电，则在步骤206中，为像素电容C1进行放电。
本公开实施例提供了一种像素电路及其驱动方法，该像素电路包括选择电 路、充放电电路和预充电电路，选择电路能够根据连接的选择信号端输入的数字信号控制充放电电路为像素电容进行充电或放电，从而可以直接利用驱动IC提供的数字信号对像素电路进行充电，省去了驱动IC中的数模转换电路和模拟电路部分，简化了驱动IC的结构，同时也减小了驱动IC的尺寸，从而降低了驱动IC的制造成本。同时，还可以通过调整第一数据线和第二数据线上的数字信号的占空比来调节对像素电容进行充电或放电的时间，从而调整像素电容上的电压值。
第三实施例
图6示出本公开的第三实施例中提供的一种像素电路的结构示意图。请参阅图6，该像素电路中的选择电路P1包括第一晶体管M1、第二晶体管M2和第五晶体管M5，充放电电路P2包括第三晶体管M3，预充电电路P3包括第四晶体管M4，C2为液晶的等效电容。第一晶体管M1的栅极连接选择信号端S(未示出)，源极连接像素电容C1，漏极连接充放电电路P2。第二晶体管M2的栅极连接选择信号端S(未示出)，漏极连接低电平信号端VL，源极与预充电电路P3相连。第五晶体管M5的栅极连接选择信号端S(未示出)，源极连接高电平信号端VH，漏极与预充电电路P3相连。第三晶体管M3的栅极连接与像素电容C1对应的同一行栅线信号端Gn，源极连接第一晶体管M1的漏极，漏极连接像素电容C1。第四晶体管M4的栅极连接与像素电容C1对应的上一行栅线信号端Gn-1，源极连接像素电容C1，漏极连接第二晶体管M2的源极和第五晶体管M5的漏极。
示例性地，可以在像素电路中设置一个或多个电阻。在图6中，将这一个或多个电阻等效为一个等效电阻R，该等效电阻R与像素电容C1连接。选择信号端S包括数据线D和选择信号线SL。数据线D连接第一晶体管M1的栅极，选择信号线SL连接第二晶体管M2的栅极和第五晶体管M5的栅极。第二晶体管M2和第五晶体管M5中的一个为N型晶体管、另一个为P型晶体管，比如：第二晶体管M2为N型晶体管时，第五晶体管M5为P型晶体管；第二晶体管M2为P型晶体管时，第五晶体管M5为N型晶体管。
图7示出图6提供的像素电路的信号时序图。结合图7所示的信号时序图，以第二晶体管M2为P型晶体管，第五晶体管M5为N型晶体管为例，对图6所示的像素电路的工作原理进行说明。这里，图7所示的信号时序图可分为4个阶段，分别为预充电阶段w5、预放电阶段w6、充放电阶段w7和充放电结 束阶段w8。
在预充电阶段w5，上一行栅线信号端Gn-1上的信号为高电平信号，第四晶体管M4导通，选择信号线SL上的信号为高电平信号，第二晶体管M2截止，第五晶体管M5导通，为像素电容C1进行预充电，与像素电容C1对应的同一行栅线信号端Gn上的信号为低电平信号，第三晶体管M3截止，数据线上的数字信号的极性不限，可以是高电平信号，也可以是低电平信号。
在预放电阶段w6，上一行栅线信号端Gn-1上的信号为高电平信号，第四晶体管M4导通，选择信号线SL上的信号为低电平信号，第二晶体管M2导通，第五晶体管M5截止，为像素电容C1进行预放电，直至达到基准电压。与像素电容C1对应的同一行栅线信号端Gn上的信号为低电平信号，第三晶体管M3截止，数据线上的数字信号的极性不限，可以是高电平信号，也可以是低电平信号。
在充放电阶段w7，上一行栅线信号端Gn-1上的信号为低电平信号，第四晶体管T4截止，预充电(包含预充电和/或预放电过程)已完成，与像素电容C1对应的同一行栅线信号端Gn上的信号为高电平信号，连通选择电路P1和充放电电路P2，数据线D上的数字信号为高电平信号，第一晶体管M1导通，为像素电容C1进行充电或放电。
在充放电结束阶段w8，数据线D上的信号为低电平信号，第一晶体管M1截止，选择电路P1和充放电电路P2断开，停止对像素电容的充电或放电。
可替换地，数据线D上的数字信号为占空比可调的脉冲数字信号，即数据线D上的数字信号为高电平的持续时间和数据线D上的数字信号为低电平的持续时间是可调的，从而可以调整对像素电容C1进行充电或放电的时间，进而调整像素电容C1上的电压。图8示出本公开的第三实施例中提供的一种像素电路的驱动方法的流程图。请参阅图8，该如图6所示的像素电路的驱动方法，包括下列过程：
在步骤301中、第四晶体管M4接收与像素电容C1对应的上一行栅线信号端上的输入信号。
在步骤302中，当上一行栅线信号端上的输入信号为高电平时，第四晶体管M4导通。
在步骤303中，当选择信号线上的输入信号为高电平信号时，第二晶体管M2截止，第五晶体管M5导通，为像素电容进行预充电。
在步骤304中，当选择信号线上的输入信号为低电平信号时，第二晶体管M2导通，第五晶体管M5截止，为所述像素电容进行预放电。
在步骤305中，当选择信号线上的输入信号为高电平信号时，第二晶体管M2截止，第五晶体管M5导通，确定充放电电路充电。
在步骤306中，当选择信号线上的输入信号为低电平信号时，第二晶体管M2导通，第五晶体管M5截止，确定充放电电路放电。
在步骤307中，当数据线上的数字信号为高电平信号时，第一晶体管M1导通。
在步骤308中，第三晶体管M3的栅极接收与像素电容对应的同一行栅线信号端上的输入信号。
在步骤309中，当同一行栅线信号端上的输入信号为高电平信号时，为像素电容进行充电或放电。
本公开实施例提供了一种像素电路及其驱动方法，该像素电路包括选择电路、充放电电路和预充电电路，选择电路能够根据连接的选择信号端输入的数字信号控制充放电电路为像素电容进行充电或放电，从而可以直接利用驱动IC提供的数字信号对像素电路进行充电，省去了驱动IC中的数模转换电路和模拟电路部分，简化了驱动IC的结构，同时也减小了驱动IC的尺寸，从而降低了驱动IC的制造成本。同时，还可以通过调整数据线上的数字信号的占空比来调节对像素电容进行充电或放电的时间，从而调整像素电容上的电压值。
本公开的实施例还提供一种显示装置，包括上述任一种像素电路。显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年1月4日递交的中国专利申请第201510004106.3号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (20)

  1. 一种像素电路，包括：
    选择电路，其输入端连接选择信号端、高电平信号端和低电平信号端，用于根据所述选择信号端输入的数字信号控制像素电容的充电或放电；
    充放电电路，其输入端连接所述选择电路的输出端和与所述像素电容对应的同一行栅线信号端，其输出端连接所述像素电容，用于在所述选择电路的控制下为所述像素电容进行充电或放电；
    预充电电路，其输入端连接与所述像素电容对应的上一行栅线信号端，其输出端连接所述像素电容，用于为所述像素电容提供基准电压。
  2. 根据权利要求1所述的像素电路，其中，所述选择电路包括：
    第一晶体管T1，其栅极连接所述选择信号端、源极连接所述高电平信号端、漏极连接所述充放电电路；
    第二晶体管T2，其栅极连接所述选择信号端、漏极连接所述低电平信号端、源极连接所述充放电电路。
  3. 根据权利要求2所述的像素电路，其中，所述选择信号端包括第一数据线和第二数据线，所述第一数据线与所述第二数据线上的数字信号的电平极性相反，所述第一晶体管T1的栅极连接所述第一数据线，所述第二晶体管T2的栅极连接所述第二数据线。
  4. 根据权利要求2所述的像素电路，其中，所述充放电电路包括：
    第三晶体管T3，其栅极连接与所述像素电容对应的同一行栅线信号端、源极连接所述第一晶体管T1的漏极和所述第二晶体管T2的源极、漏极连接所述像素电容。
  5. 根据权利要求3或4所述的像素电路，其中，所述预充电电路包括：
    第四晶体管T4，其栅极连接与所述像素电容对应的上一行栅线信号端、源极和漏极均连接所述像素电容。
  6. 根据权利要求3或4所述的像素电路，其中，所述第一数据线上的数字信号与所述第二数据线上的数字信号均为占空比可调的脉冲数字信号。
  7. 根据权利要求1所述的像素电路，其中，所述选择电路包括：
    第一晶体管M1，其栅极连接所述选择信号端、源极连接所述像素电容、漏极连接所述充放电电路；
    第二晶体管M2，其栅极连接所述选择信号端、漏极连接所述低电平信号端、源极与所述预充电电路相连；
    第五晶体管M5，其栅极连接所述选择信号端、源极连接所述高电平信号端、漏极与所述预充电电路相连。
  8. 根据权利要求7所述的像素电路，其中，所述选择信号端包括数据线和选择信号线，所述数据线连接所述第一晶体管M1的栅极，所述选择信号线连接所述第二晶体管M2的栅极和所述第五晶体管M5的栅极，所述第二晶体管M2和所述第五晶体管M5中的一个为P型晶体管、另一个为N型晶体管。
  9. 根据权利要求8所述的像素电路，其中，所述充放电电路包括：
    第三晶体管M3，其栅极连接与所述像素电容对应的同一行栅线信号端、源极连接所述第一晶体管M1的漏极、漏极连接所述像素电容。
  10. 根据权利要求7或8所述的像素电路，其中，所述预充电电路包括：
    第四晶体管M4，其栅极连接与所述像素电容对应的上一行栅线信号端、源极连接所述像素电容、漏极连接所述第二晶体管M2的源极和所述第五晶体管M5的漏极。
  11. 一种像素电路的驱动方法，包括下列步骤：
    预充电电路接收与像素电容对应的上一行栅线信号端上的输入信号，并根据所述上一行栅线信号端上的输入信号，为所述像素电容提供基准电压；
    选择电路接收选择信号端上的数字信号，并根据所述选择信号端上的数字信号，控制所述像素电容的充电或放电；
    充放电电路接收与所述像素电容对应的同一行栅线信号端上的输入信号，并根据所述同一行栅线信号端上的输入信号，为所述像素电容进行充电或放电。
  12. 根据权利要求11所述的像素电路的驱动方法，其中，所述预充电电路接收与像素电容对应的上一行栅线信号端上的输入信号，并根据所述上一行栅线信号端上的输入信号，为所述像素电容提供基准电压，包括：
    第四晶体管T4的栅极接收与所述像素电容对应的上一行栅线信号端上的输入信号；
    当所述上一行栅线信号端上的输入信号为高电平信号时，所述第四晶体管T4导通，为所述像素电容提供基准电压。
  13. 根据权利要求11所述的像素电路的驱动方法，其中，所述选择信号 端包括第一数据线和第二数据线；所述选择电路接收选择信号端上的数字信号，并根据所述选择信号端上的数字信号，控制所述像素电容的充电或放电，包括：
    当所述第一数据线上的数字信号为高电平信号，所述第二数据线上的数字信号为低电平信号时，第一晶体管T1导通，第二晶体管截止，所述充放电电路对所述像素电容进行充电；
    当所述第一数据线上的数字信号为低电平信号，所述第二数据线上的数字信号为高电平信号时，所述第一晶体管T1截止，所述第二晶体管导通，所述充放电电路对所述像素电容进行放电。
  14. 根据权利要求11所述的像素电路的驱动方法，其中，所述充放电电路接收与所述像素电容对应的同一行栅线信号端上的输入信号，并根据所述同一行栅线信号端上的输入信号，为所述像素电容进行充电或放电，包括：
    第三晶体管T3的栅极接收与所述像素电容对应的同一行栅线信号端上的输入信号；
    当所述同一行栅线信号端上的输入信号为高电平信号时，所述第三晶体管T3导通，为所述像素电容进行充电或放电。
  15. 根据权利要求13所述的像素电路的驱动方法，其中，所述第一数据线上的数字信号与所述第二数据线上的数字信号均为占空比可调的脉冲数字信号。
  16. 根据权利要求11所述的像素电路的驱动方法，其中，所述预充电电路接收与像素电容对应的上一行栅线信号端上的输入信号，并根据所述上一行栅线信号端上的输入信号，为所述像素电容提供基准电压，包括：
    第四晶体管M4接收与所述像素电容对应的上一行栅线信号端上的输入信号；
    当所述上一行栅线信号端上的输入信号为高电平时，所述第四晶体管M4导通。
  17. 根据权利要求11所述的像素电路的驱动方法，其中，所述选择信号端包括数据线和选择信号线；第二晶体管M2为P型晶体管，第五晶体管M5为N型晶体管；所述选择电路接收选择信号端上的数字信号，并根据所述选择信号端上的数字信号，控制所述像素电容的充电或放电，包括：
    当所述选择信号线上的输入信号为高电平信号时，所述第二晶体管M2截 止，所述第五晶体管M5导通，所述充放电电路对所述像素电容进行充电；
    当所述选择信号线上的输入信号为低电平信号时，所述第二晶体管M2导通，所述第五晶体管M5截止，所述充放电电路对所述像素电容进行放电；
    当所述数据线上的数字信号为高电平信号时，第一晶体管M1导通。
  18. 根据权利要求17所述的像素电路的驱动方法，其中，还包括：
    当所述选择信号线上的输入信号为高电平信号时，所述第二晶体管M2截止，所述第五晶体管M5导通，为像素电容进行预充电；
    当所述选择信号线上的输入信号为低电平信号时，所述第二晶体管M2导通，所述第五晶体管M5截止，为所述像素电容进行预放电。
  19. 根据权利要求11所述的像素电路的驱动方法，其中，所述充放电电路接收与所述像素电容对应的同一行栅线信号端上的输入信号，并根据所述同一行栅线信号端上的输入信号，为所述像素电容进行充电或放电，包括：
    第三晶体管M3的栅极接收与所述像素电容对应的同一行栅线信号端上的输入信号；
    当所述同一行栅线信号端上的输入信号为高电平信号时，为所述像素电容进行充电或放电。
  20. 一种显示装置，包括权利要求1-10中任意一项所述的像素电路。
PCT/CN2015/088255 2015-01-04 2015-08-27 像素电路及其驱动方法和显示装置 WO2016107200A1 (zh)

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