WO2016106861A1 - 触控面板 - Google Patents

触控面板 Download PDF

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Publication number
WO2016106861A1
WO2016106861A1 PCT/CN2015/070831 CN2015070831W WO2016106861A1 WO 2016106861 A1 WO2016106861 A1 WO 2016106861A1 CN 2015070831 W CN2015070831 W CN 2015070831W WO 2016106861 A1 WO2016106861 A1 WO 2016106861A1
Authority
WO
WIPO (PCT)
Prior art keywords
disposed
layer
hole
touch panel
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/070831
Other languages
English (en)
French (fr)
Inventor
薛景峰
张鑫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/440,659 priority Critical patent/US9552114B2/en
Publication of WO2016106861A1 publication Critical patent/WO2016106861A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the present invention relates to the field of touch, and in particular, to a touch panel.
  • the touch device is a common device, and because of its low power consumption, small size, and light weight, it is favored by users.
  • the touch device usually includes a touch panel, and a low temperature polysilicon (LTPS) thin film transistor (TFT) can make the touch panel have higher resolution, lower power consumption, and higher.
  • LTPS low temperature polysilicon
  • TFT thin film transistor
  • the mobility and low preparation temperature have been widely studied and applied.
  • the pixel electrode and the drain are separated from each other, and the pixel electrode is connected to the drain of the thin film transistor through the through hole.
  • a spacer between the pixel electrode and the drain (such as an insulating layer or a flat surface)
  • the layer or the like is thicker such that the depth of the through hole connecting the pixel electrode and the drain is deep. Therefore, when the pixel electrode is connected to the drain through the through hole, the pixel electrode is easily broken and dropped, so that the yield of the touch panel is lowered.
  • the invention provides a touch panel, the touch panel comprising:
  • a source and a drain the source and the drain are disposed on the second insulating layer, and the source and the drain are spaced apart, and the source and the drain respectively pass through a hole is connected to the low temperature polysilicon layer;
  • the layer is provided with a first through hole, and the first through hole is disposed corresponding to the drain;
  • a third insulating layer is disposed on the flat layer, the third insulating layer is provided with a second through hole, and the second through hole is disposed corresponding to the filling portion;
  • a pixel electrode disposed on the third insulating layer and electrically connected to the filling portion through the second through hole.
  • the filling portion includes a first portion and a second portion connected to the first portion, the first portion is electrically connected to the drain through the first through hole, and the second portion is disposed in the On the flat layer and covering the first through hole.
  • the touch panel further includes a light shielding layer disposed on a surface of the substrate, the low temperature polysilicon layer being disposed on a surface of the substrate through the light shielding layer, and the low temperature polysilicon layer It is disposed in the middle of the light shielding layer.
  • the touch panel further includes a touch receiving line and a touch emitting line, wherein the touch receiving line is configured to receive a detection signal to detect a touch action on the touch panel and a position of the touch action.
  • the touch emitting line is configured to transmit a signal representing the touch action and the touch position to a chip, and at least one of the touch receiving line and the touch emitting line includes a first transparent wire and a metal wire The metal wire is disposed on the flat layer, and the metal wire is electrically connected to the first transparent wire.
  • the material of the filling portion is metal, and the filling portion is formed simultaneously with the metal wire.
  • the touch panel of the present invention is provided with a first through hole on the flat layer, and fills the filling portion in the first through hole, and the filling portion is electrically connected to the drain,
  • a second through hole is disposed on the third insulating layer, and the second through hole is disposed corresponding to the filling portion.
  • the pixel electrodes are not easily broken and dropped, thereby improving the yield of the touch panel.
  • the material of the filling portion is a metal or an alloy, and the resistance value thereof is smaller than that of the pixel electrode which is a transparent metal oxide, the pixel electrode of the prior art is directly connected to the drain electrode, and the present invention is When the pixel electrode is connected to the drain through the filling portion, the resistance value between the pixel electrode and the drain can be reduced.
  • the invention provides a touch panel, the touch panel comprising:
  • Two first type heavily doped regions disposed on the first insulating layer are stacked, and two of the first type heavily doped regions are spaced apart;
  • a second insulating layer disposed on the first type of heavily doped region
  • the source and the drain are disposed on the third insulating layer, and the source and the drain are spaced apart, and the source and the drain respectively pass through a hole is connected to the first type of heavily doped region;
  • a flat layer is disposed on the source, the drain, and the third insulating layer, the flat layer is provided with a first through hole, and the first through hole is disposed corresponding to the drain;
  • a fourth insulating layer is disposed on the flat layer, the fourth insulating layer is provided with a second through hole, and the second through hole is disposed corresponding to the filling portion;
  • a pixel electrode disposed on the fourth insulating layer and electrically connected to the filling portion through the second through hole.
  • the filling portion includes a first portion and a second portion connected to the first portion, the first portion is electrically connected to the drain through the first through hole, and the second portion is disposed in the On the flat layer and covering the first through hole.
  • the touch panel further includes a light shielding layer disposed on a surface of the substrate, the low temperature polysilicon layer being disposed on a surface of the substrate through the light shielding layer, and the low temperature polysilicon layer It is disposed in the middle of the light shielding layer.
  • the touch panel further includes a touch signal line, wherein the touch signal line is used to detect a touch action on the touch panel and a position of the touch action, and the touch action and the touch action are characterized.
  • the signal of the position is transmitted to a chip, the touch signal line includes a first transparent wire and a metal wire, the metal wire is disposed on the flat layer, and the metal wire is electrically connected to the first transparent wire .
  • the material of the filling portion is metal, and the filling portion is formed simultaneously with the metal wire.
  • the touch panel further includes a first type of lightly doped region, and the first type of lightly doped region A domain is disposed on the first insulating layer and disposed between two of the first type of heavily doped regions.
  • the touch panel of the present invention is provided with a first through hole on the flat layer, and fills the filling portion in the first through hole, and the filling portion is electrically connected to the drain.
  • a second through hole is disposed on the fourth insulating layer, and the second through hole is disposed corresponding to the filling portion.
  • the material of the filling portion is a metal or an alloy, and the resistance value thereof is smaller than that of the pixel electrode which is a transparent metal oxide, the pixel electrode of the prior art is directly connected to the drain electrode, and the present invention is When the pixel electrode is connected to the drain through the filling portion, the resistance value between the pixel electrode and the drain can be reduced.
  • FIG. 1 is a cross-sectional structural view of a touch panel according to a preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional structural view of a touch panel according to another preferred embodiment of the present invention.
  • FIG. 1 is a cross-sectional structural diagram of a touch panel according to a preferred embodiment of the present invention.
  • the touch panel 100 includes a substrate 110 , and a low temperature polysilicon layer 112 , a first insulating layer 113 , a gate electrode 114 , and a second insulating layer 115 disposed on a surface of the substrate 110 are sequentially stacked.
  • the touch panel 100 further includes a source 116 and a drain 117, the source 116 and the drain 117 are disposed on the second insulating layer 115, and the source 116 and the drain 117 are spaced apart, The source 116 and the drain 117 are respectively connected to the low temperature polysilicon layer 112 through via holes.
  • the touch panel 100 further includes a flat layer 118.
  • the flat layer 118 is stacked on the source 116, the drain 117, and the second insulating layer 115.
  • the flat layer 118 is provided with a first layer.
  • the through hole 1181, the first through hole 1181 is disposed corresponding to the drain 117.
  • the touch panel 100 further includes a filling portion 119 filling the first through hole 1181 , and the filling portion 119 is electrically connected to the drain 117 .
  • the touch panel 100 further includes a third insulating layer 121 and a pixel electrode 122.
  • the third insulating layer 121 is stacked on the flat layer 118.
  • the third insulating layer 121 is provided with a second through hole 1211.
  • the second through hole 1211 is disposed corresponding to the filling portion 119.
  • the pixel electrode 122 is disposed on the third insulating layer 121 and electrically connected to the filling portion 119 through the second through hole 1211.
  • the material of the pixel electrode 122 is different from the material of the filling portion 119.
  • the filling portion 119 includes a first portion 1191 and a second portion 1192 connected to the first portion 119.
  • the first portion 1191 is electrically connected to the drain 117 through the first through hole 1181
  • the second portion A portion 1192 is disposed on the flat layer 118 and covers the first through hole 1181.
  • the shape of the filling portion 119 is "T" shape.
  • the material of the filling portion 119 is a metal or an alloy.
  • the material of the filling portion 119 is selected from one of copper, tungsten, chromium, aluminum, and a combination thereof.
  • the touch panel 100 further includes a light shielding layer 111 disposed on a surface of the substrate 110, and the low temperature polysilicon layer 112 is disposed on a surface of the substrate 110 through the light shielding layer 111, and The low temperature polysilicon layer 112 is disposed in the middle of the light shielding layer 111.
  • the low temperature polysilicon layer 112, the first insulating layer 113, the gate electrode 114, the second insulating layer 115, the source electrode 116, and the drain electrode 117 constitute the low temperature polysilicon thin film transistor, and the light shielding layer 111 is used to prevent The low temperature polysilicon thin film transistor on the touch panel 100 leaks light.
  • the touch panel 100 is a mutual capacitive touch panel.
  • the touch panel 100 further includes a touch receiving line 123 and a touch emitting line (not shown).
  • the touch receiving line 123 is configured to receive a detection signal for detecting a position of a touch action and a touch action on the touch panel 100, where the touch emission line is used to represent the touch action and the touch position.
  • the signal is transmitted to a chip for the chip to perform the operations corresponding to the touch action and the position of the touch action.
  • the touch receiving line 123 and at least one of the touch emission lines include a first transparent wire 1231 and a metal wire 1232, the metal wire 1232 is disposed on the flat layer 118, and the metal wire 1232 and the first transparent
  • the wire 1231 is electrically connected.
  • the material of the first transparent conductive line 1231 may be a transparent metal oxide and has conductivity.
  • the first transparent conductive line 1231 may include one of indium tin oxide, indium zinc oxide, indium oxide or zinc oxide or In any combination, the conductive property of the first transparent wire 1231 made of a metal oxide is inferior to that of the metal, and the conductive property of the first transparent wire 1231 is poor, and therefore, the wire is passed through the first wire and the first transparent
  • the signal lines formed by the electrical connection of the wires 1231 increase the conductivity of the signal lines while ensuring transparency.
  • the filling portion 119 is made of metal, and the filling portion 119 is formed simultaneously with the metal wire 1232.
  • the filling portion 119 is formed in the same process as the metal wire 1232 to save the manufacturing process of the touch panel 100.
  • the filling portion 119 and the metal wire 1232 may be formed in the following manner. First, a metal layer is disposed on the flat layer 118, and then the metal layer is patterned to form the filling portion 119 and the metal wire 1232.
  • the substrate 110 may be a glass substrate. In other embodiments, the substrate 110 may be a plastic substrate or an insulating substrate.
  • the material of the first insulating layer 113, the second insulating layer 115, and the third insulating layer 121 may be one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the surface of the substrate 110 is further provided with a buffer layer for buffering stress received during the process of fabricating other structures of the touch panel 100 on the substrate 110 to avoid the substrate 110. Damaged or broken.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the light shielding layer 111, the low temperature polysilicon layer 112, the first insulating layer 113, and other layers are disposed on the surface of the substrate 110 through the buffer layer.
  • the touch panel 100 of the present invention is provided with a first through hole 1181 on the flat layer 118, and fills the filling portion 119 in the first through hole 1181, and the filling portion 119 and the drain portion
  • the pole 117 is electrically connected, and the third through hole 1211 is disposed on the third insulating layer 121, and the second through hole 1211 is disposed corresponding to the filling portion 119.
  • the pixel electrode 122 is connected to the drain electrode 117, the pixel electrode 122 only needs to be electrically connected to the filling portion 119 through the second through hole 1211.
  • the filling portion 119 is configured to reduce the depth between the pixel electrode 122 and the drain electrode 117 such that when the pixel electrode 122 is connected to the drain electrode 117, the pixel electrode 122 is not easily broken and dropped. Thereby, the yield of the touch panel 100 is improved. Further, since the material of the filling portion 119 is a metal or an alloy, and the resistance thereof is smaller than that of the pixel electrode 122 which is a transparent metal oxide, the present invention is directly connected to the drain electrode in comparison with the prior art. When the pixel electrode 122 is connected to the drain electrode 117 through the filling portion 119, the resistance value between the pixel electrode 122 and the drain electrode 117 can be reduced.
  • FIG. 2 is a cross-sectional structural diagram of a touch panel according to another preferred embodiment of the present invention.
  • the touch panel 200 includes a substrate 210, and a low temperature polysilicon layer 212 and a first insulating layer 213 disposed on the surface of the substrate 210 are sequentially stacked.
  • the touch panel 200 further includes two first type heavily doped regions 214 stacked on the first insulating layer 213, and two of the first type heavily doped regions 214 are spaced apart.
  • the touch panel 200 further includes a second insulating layer 216 that sequentially stacks the gate electrode 217 and the third insulating layer 218 disposed on the second insulating layer 216.
  • the second insulating layer 216 is disposed on the first type heavily doped region 214.
  • the touch panel 200 further includes a source 219 and a drain 221, the source 219 and the drain 221 are disposed on the third insulating layer 218, and the source 219 and the drain 221 The source 219 and the drain 221 are respectively connected to the first type heavily doped region 214 through via holes.
  • the touch panel 200 further includes a flat layer 222.
  • the flat layer 222 is stacked on the source 219, the drain 221, and the third insulating layer 218.
  • the flat layer 222 is provided with a first layer.
  • the through hole 2221, the first through hole 2221 is disposed corresponding to the drain 221 .
  • the touch panel 200 further includes a filling portion 223 filling the first through hole 2221 , and the filling portion 223 is electrically connected to the drain 221 .
  • the touch panel 200 further includes a fourth insulating layer 224 and a pixel electrode 225.
  • the fourth insulating layer 224 is stacked on the flat layer 222, and the fourth insulating layer 224 is provided with a second through hole 2241.
  • the second through hole 2241 is disposed corresponding to the filling portion 223.
  • the pixel electrode 225 is disposed on the fourth insulating layer 224 and electrically connected to the filling portion 223 through the second through hole 2241.
  • the material of the pixel electrode 225 is different from the material of the filling portion 223.
  • the filling portion 223 includes a first portion 2231 and a second portion 2232 connected to the first portion 2231.
  • the first portion 2231 is electrically connected to the drain 221 through the first through hole 2241
  • the second portion A portion 2232 is disposed on the flat layer 222 and covers the first through hole 2241.
  • the shape of the filling portion 223 is a "T" shape.
  • the material of the filling portion 223 is a metal or an alloy.
  • the material of the filling portion 223 is selected from one of copper, tungsten, chromium, aluminum, and a combination thereof.
  • the touch panel 200 further includes a light shielding layer 211 disposed on a surface of the substrate 210, and the low temperature polysilicon layer 212 is disposed on the substrate through the light shielding layer 211. On the surface of 210, and the low temperature polysilicon layer 212 is disposed in the middle of the light shielding layer 211.
  • the low temperature multi-pass layer 212, the first insulating layer 213, the first type heavily doped region 214, the second insulating layer 216, the gate 217, the first The third insulating layer 218, the source 219 and the drain 221 form a low temperature polysilicon thin film transistor, and the light shielding layer 211 is configured to prevent light leakage of the low temperature polysilicon thin film transistor on the touch panel 200.
  • the touch panel 200 is a self-capacitive touch panel, and the touch panel 200 further includes a touch signal line 226 for detecting the touch panel 200. a touch action and a position of the touch action, and transmitting a signal representing the touch action and the text of the touch action to a chip, wherein the chip performs the touch action and the position of the touch action Corresponding operation.
  • the touch signal line 226 includes a first transparent wire 2261 and a metal wire 2262.
  • the metal wire 2262 is disposed on the flat layer 222, and the metal wire is electrically connected to the first transparent wire 2261.
  • the first transparent conductive wire 2261 is made of a transparent metal oxide and has electrical conductivity, and the first transparent conductive wire 2261 includes one or any combination of indium tin oxide, indium zinc oxide, indium oxide or zinc oxide.
  • the conductive property of the first transparent wire 12261 made of a metal oxide is inferior to that of the metal.
  • the conductive property of the first transparent wire 2261 is poor. Therefore, the wire 2262 and the first transparent wire 2261 are electrically connected.
  • the signal lines formed by the connections increase their conductivity by ensuring transparency.
  • the material of the filling portion 223 is metal, and the filling portion 223 is formed simultaneously with the metal wire 2262.
  • the filling portion 223 is formed in the same process as the metal wire 2262 to save the manufacturing process of the touch panel 200.
  • the filling portion 223 and the wire 2262 may be formed in the following manner. First, a metal layer is disposed on the flat layer 222, and then the metal layer is patterned to form the filling portion 223 and the metal wire 1232.
  • the touch panel 200 further includes a first type of lightly doped region 215 disposed on the first insulating layer 213 and disposed in two of the first types of heavily doped Miscellaneous area Between domains 214.
  • the first type of lightly doped region 215 is disposed between the two first type heavily doped regions 214 to reduce leakage current of the low temperature polysilicon thin film transistor and improve performance of the low temperature polysilicon thin film transistor.
  • the first type is a P-type.
  • the first type of heavily doped regions are P-type heavily doped, and the first type of lightly doped is P-type lightly doped.
  • the first type is N-type.
  • the first type of heavily doped region is N-type heavily doped, and the first type is lightly doped to N-type lightly doped. .
  • the substrate 210 may be a glass substrate. It is to be understood that in other embodiments, the substrate 110 may be a plastic substrate or an insulating substrate.
  • the material of the first insulating layer 213, the second insulating layer 216, the third insulating layer 218, and the fourth insulating layer 224 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and One of the combinations.
  • the surface of the substrate 210 is further provided with a buffer layer for buffering stress received during the process of fabricating other structures of the touch panel 200 on the substrate 210 to avoid the substrate 210. Damaged or broken.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the light shielding layer 211, the low temperature polysilicon layer 212, the first insulating layer 213, and other layers are disposed on the surface of the substrate 210 through the buffer layer.
  • the touch panel 200 of the present invention is provided with a first through hole 2221 on the flat layer 222, and fills the filling portion 223 in the first through hole 2221, and the filling portion 223 is
  • the drain 219 is electrically connected to the fourth insulating layer 224, and the second through hole 2241 is disposed corresponding to the filling portion 223.
  • the pixel electrode 225 is connected to the drain 221, the pixel electrode 225 only needs to be electrically connected to the filling portion 223 through the second through hole 2241.
  • the present invention is directly connected to the drain electrode in comparison with the prior art.
  • the resistance value between the pixel electrode 225 and the drain electrode 221 can be reduced.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Position Input By Displaying (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种触控面板(100)，包括：基板(110)；依次层叠设置在基板(110)的表面上的低温多晶硅层(112)、第一绝缘层(113)、栅极(114)及第二绝缘层(115)；源极(116)和漏极(117)，源极(116)和漏极(117)设置在第二绝缘层(115)上，且源极(116)和漏极(117)间隔设置，源极(116)及漏极(117)分别通过通孔与低温多晶硅层(112)相连；平坦层(118)，层叠设置在源极(116)、漏极(117)及第二绝缘层(115)上，平坦层(118)设置有第一贯孔(1181)，第一贯孔(1181)对应漏极(117)设置；填充部(119)，填充第一贯孔(1181)，且填充部(119)与漏极(117)电连接；第三绝缘层(121)，层叠设置在平坦层(118)上，第三绝缘层(121)设置有第二贯孔(1211)，第二贯孔(1211)对应填充部(119)设置；像素电极(122)，设置在第三绝缘层(121)上且通过第二贯孔(1211)与填充部(119)电连接。所述触控面板(100)的像素电极(122)不容易断线和脱落。

Description

触控面板
本发明要求2014年12月30日递交的发明名称为“触控面板”的申请号201410842861.4的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及触控领域，尤其涉及一种触控面板。
背景技术
触控装置是一种常见的设备，由于其具有功耗低、体积小、质量轻等特点，因此备受用户的青睐。触控装置通常包括触控面板，低温多晶硅(Low Temperature Ploy-silicon，LTPS)薄膜晶体管(Thin Film Transistor,TFT)由于能够使得触控面板具有更高的分辨率、更低的能耗、更高的迁移率以及较低的制备温度而得到了广泛的研究及应用。在触控面板中，像素电极与漏极之间相隔隔离，并且像素电极通过贯孔与薄膜晶体管的漏极相连，通常情况下，像素电极与漏极之间的间隔物(比如绝缘层或者平坦层等)较厚从而使得连接像素电极与漏极之间的贯孔的深度较深。因此，当像素电极通过贯孔与漏极相连时，容易造成像素电极的断线，脱落，从而使得触控面板的良率下降。
发明内容
本发明提供了一种触控面板，所述触控面板包括：
基板；
依次层叠设置在所述基板的表面上的低温多晶硅层、第一绝缘层、栅极及第二绝缘层；
源极和漏极，所述源极和所述漏极设置在所述第二绝缘层上，且所述源极和所述漏极间隔设置，所述源极及所述漏极分别通过通孔与所述低温多晶硅层相连；
平坦层，层叠设置在所述源极、所述漏极及所述第二绝缘层上，所述平坦 层设置有第一贯孔，所述第一贯孔对应所述漏极设置；
填充部，填充所述第一贯孔，且所述填充部与所述漏极电连接；
第三绝缘层，层叠设置在所述平坦层上，所述第三绝缘设置有第二贯孔，所述第二贯孔对应所述填充部设置；
像素电极，设置在所述第三绝缘层上且通过所述第二贯孔与所述填充部电连接。
其中，所述填充部包括第一部分及与所述第一部分相连的第二部分，所述第一部分穿过所述第一贯孔与所述漏极电连接，所述第二部分设置在所述平坦层上且覆盖所述第一贯孔。
其中，所述触控面板还包括遮光层，所述遮光层设置在所述基板的表面上，所述低温多晶硅层通过所述遮光层设置在所述基板的表面上，且所述低温多晶硅层设置在所述遮光层的中部。
其中，所述触控面板还包括触控接收线及触控发射线，所述触控接收线用于接收检测信号，以检测所述触控面板上的触控动作以及触控动作的位置，所述触控发射线用于将表征触控动作及触控位置的信号传输至一芯片，所述触控接收线及所述触控发射线中的至少一条线包括第一透明导线及金属丝线，所述金属丝线设置在所述平坦层上，且所述金属丝线与所述第一透明导线电连接。
其中，所述填充部的材料为金属，所述填充部与所述金属丝线同时形成。
相较于现有技术，本发明触控面板通过在平坦层上设置第一贯孔，并在第一贯孔内填充所述填充部，所述填充部与所述漏极电连接，所述第三绝缘层上设置第二贯孔，所述第二贯孔对应所述填充部设置。当所述像素电极与所述漏极相连时，所述像素电极仅需通过第二贯孔与所述填充部电连接即可。换句话说，通过在平坦层上设置第一贯孔以及在第一贯孔内填充所述填充部以减小所述像素电极与所述漏极之间的深度，从而使得所述像素电极与所述漏极相连时，所述像素电极不容易断线和脱落，从而提高了所述触控面板的良率。进一步地，由于所述填充部的材质为金属或者合金，其阻值小于为透明金属氧化物的像素电极，因此，相较于现有技术中的像素电极直接与漏极相连，本发明的所述像素电极通过所述填充部与所述漏极相连时，能够减小像素电极与所述漏极之间的电阻值。
本发明提供了一种触控面板，所述触控面板包括：
基板；
依次层叠设置在所述基板的表面上的低温多晶硅层及第一绝缘层；
层叠设置在所述第一绝缘层上的两个第一类型重掺杂区域，且两个所述第一类型重掺杂区域间隔设置；
第二绝缘层，设置在所述第一类型重掺杂区域上；
依次层叠设置在所述第二绝缘层上的栅极及第三绝缘层；
源极和漏极，所述源极和所述漏极设置在所述第三绝缘层上，且所述源极和所述漏极间隔设置，所述源极及所述漏极分别通过通孔与所述第一类型重掺杂区域相连；
平坦层，层叠设置在所述源极、所述漏极及所述第三绝缘层上，所述平坦层设置有第一贯孔，所述第一贯孔对应所述漏极设置；
填充部，填充所述第一贯孔，且所述填充部与所述漏极电连接；
第四绝缘层，层叠设置在所述平坦层上，所述第四绝缘层设置有第二贯孔，所述第二贯孔对应所述填充部设置；
像素电极，设置在所述第四绝缘层上且通过所述第二贯孔与所述填充部电连接。
其中，所述填充部包括第一部分及与所述第一部分相连的第二部分，所述第一部分穿过所述第一贯孔与所述漏极电连接，所述第二部分设置在所述平坦层上且覆盖所述第一贯孔。
其中，所述触控面板还包括遮光层，所述遮光层设置在所述基板的表面上，所述低温多晶硅层通过所述遮光层设置在所述基板的表面上，且所述低温多晶硅层设置在所述遮光层的中部。
其中，所述触控面板还包括触控信号线，所述触控信号线用于检测所述触控面板上的触控动作以及触控动作的位置，且将表征触控动作及触控动作的位置的信号传输至一芯片，所述触控信号线包括第一透明导线及金属丝线，所述金属丝线设置在所述平坦层上，且所述金属丝线与所述第一透明导线电连接。
其中，所述填充部的材料为金属，所述填充部与所述金属丝线同时形成。
其中，所述触控面板还包括第一类型轻掺杂区域，所述第一类型轻掺杂区 域设置在所述第一绝缘层上，且设置在两个所述第一类型重掺杂区域之间。
相较于现有技术，本发明触控面板通过在所述平坦层上设置第一贯孔，并在第一贯孔内填充所述填充部，所述填充部与所述漏极电连接，所述第四绝缘层上设置第二贯孔，所述第二贯孔对应所述填充部设置。当所述像素电极与所述漏极相连时，所述像素电极仅需通过第二贯孔与所述填充部电连接即可。换句话说，通过在所述平坦层上设置第一贯孔以及在所述第一贯孔内填充所述填充部以减小所述像素电极与所述漏极之间的深度，从而使得所述像素电极与所述漏极相连时，所述像素电极不容易断线和脱落，从而提高了所述触控面板的良率。进一步地，由于所述填充部的材质为金属或者合金，其阻值小于为透明金属氧化物的像素电极，因此，相较于现有技术中的像素电极直接与漏极相连，本发明的所述像素电极通过所述填充部与所述漏极相连时，能够减小像素电极与所述漏极之间的电阻值。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的触控面板的剖面结构示意图。
图2为本发明另一较佳实施方式的触控面板的剖面结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的触控面板的剖面结构示意图。所述触控面板100包括基板110，依次层叠设置在所述基板110的表面上的低温多晶硅层112、第一绝缘层113、栅极114及第二绝缘层115。所述触控面板 100还包括源极116和漏极117，所述源极116和所述漏极117设置在所述第二绝缘层115上，且所述源极116和所述漏极117间隔设置，所述源极116及所述漏极117分别通过通孔与所述低温多晶硅层112相连。所述触控面板100还包括平坦层118，所述平坦层118层叠设置在所述源极116、所述漏极117及所述第二绝缘层115上，所述平坦层118设置有第一贯孔1181，所述第一贯孔1181对应所述漏极117设置。所述触控面板100还包括填充部119，所述填充部119填充所述第一贯孔1181，且所述填充部119与所述漏极117电连接。所述触控面板100还包括第三绝缘层121和像素电极122，所述第三绝缘层121层叠设置在所述平坦层118上，所述第三绝缘层121设置有第二贯孔1211，所述第二贯孔1211对应所述填充部119设置。所述像素电极122设置在所述第三绝缘层121上且通过所述第二贯孔1211与所述填充部119电连接。优选地，所述像素电极122的材料与所述填充部119的材料不同。
所述填充部119包括第一部分1191和与所述第一部分119相连的第二部分1192，所述第一部分1191穿过所述第一贯孔1181与所述漏极117电连接，所述第二部分1192设置在所述平坦层118上且覆盖所述第一贯孔1181。在本实施方式中，所述填充部119的形状为“T”形。所述填充部119的材质为金属或者合金，举例而言，所述填充部119的材质选自铜、钨、铬、铝及其组合的其中之一。
所述触控面板100还包括遮光层111，所述遮光层111设置在所述基板110的表面上，所述低温多晶硅层112通过所述遮光层111设置在所述基板110的表面上，且所述低温多晶硅层112设置在所述遮光层111的中部。在本实施方式中，低温多晶硅层112、第一绝缘层113、栅极114、第二绝缘层115、源极116和漏极117组成所述低温多晶硅薄膜晶体管，所述遮光层111用于防止所述触控面板100上的低温多晶硅薄膜晶体管漏光。
在本实施方式中，所述触控面板100为互电容式触控面板，所述触控面板100还包括触控接收线123和触控发射线(图未示)。所述触控接收线123用于接收检测信号，以检测所述触控面板100上的触控动作及触控动作的位置，所述触控发射线用于将表征触控动作及触控位置的信号传输至一芯片，以供所述芯片执行所述触控动作及所述触控动作的位置对应的操作。所述触控接收线 123及所述触控发射线中的至少一条线包括第一透明导线1231及金属丝线1232，所述金属丝线1232设置在所述平坦层118上，且所述金属丝线1232与所述第一透明导线1231电连接。所述第一透明导线1231的材质可以为透明的金属氧化物且具有导电性，所述第一透明导电线1231可以包含铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合，材质为金属氧化物的第一透明导线1231的导电性能与金属的导电性能相较，第一透明导线1231的导电性能较差，因此，通过所述金属丝线1232与所述第一透明导线1231电连接形成的信号线在保证透明度的基础上增加了其导电性能。
优选地，所述填充部119的材质为金属，所述填充部119与所述金属丝线1232同时形成。换句话说，所述填充部119与所述金属丝线1232在同一制程中形成，以节约所述触控面板100的制备工序。所述填充部119和所述金属丝线1232可以通过以下方式形成。首先，在所述平坦层118上设置一层金属层，接着，图案化所述金属层，以形成所述填充部119及所述金属丝线1232。
在本实施方式中，所述基板110可以为玻璃基板，可以理解地，在其他实施方式中，所述基板110也可以为塑料基板或者是绝缘基板。所述第一绝缘层113、所述第二绝缘层115及所述第三绝缘层121的材质可以为氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
优选地，所述基板110的表面还设置缓冲层，所述缓冲层用于缓冲在所述基板110上制作所述触控面板100的其他结构的过程中受到的应力，以避免所述基板110的损坏或者破裂。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。此时，所述遮光层111、所述低温多晶硅层112、所述第一绝缘层113以及其他各层通过所述缓冲层设置在所述基板110的表面上。
相较于现有技术，本发明触控面板100通过在平坦层118上设置第一贯孔1181，并在第一贯孔1181内填充所述填充部119，所述填充部119与所述漏极117电连接，所述第三绝缘层121上设置第二贯孔1211，所述第二贯孔1211对应所述填充部119设置。当所述像素电极122与所述漏极117相连时，所述像素电极122仅需通过第二贯孔1211与所述填充部119电连接即可。换句话说，通过在平坦层118上设置第一贯孔1181以及在第一贯孔1181内填充所述 填充部119以减小所述像素电极122与所述漏极117之间的深度，从而使得所述像素电极122与所述漏极117相连时，所述像素电极122不容易断线和脱落，从而提高了所述触控面板100的良率。进一步地，由于所述填充部119的材质为金属或者合金，其阻值小于为透明金属氧化物的像素电极122，因此，相较于现有技术中的像素电极直接与漏极相连，本发明的所述像素电极122通过所述填充部119与所述漏极117相连时，能够减小像素电极122与所述漏极117之间的电阻值。
请参阅图2，图2为本发明另一较佳实施方式的触控面板的剖面结构示意图。所述触控面板200包括基板210，依次层叠设置在所述基板210的表面上的低温多晶硅层212及第一绝缘层213。所述触控面板200还包括层叠设置在所述第一绝缘层213上的两个第一类型重掺杂区域214，且两个所述第一类型重掺杂区域214间隔设置。所述触控面板200还包括第二绝缘层216，依次层叠设置在所述第二绝缘层216上的栅极217及第三绝缘层218。所述第二绝缘层216设置在所述第一类型重掺杂区域214上。所述触控面板200还包括源极219和漏极221，所述源极219和所述漏极221设置在所述第三绝缘层218上，且所述源极219和所述漏极221间隔设置，所述源极219及所述漏极221分别通过通孔与所述第一类型重掺杂区域214相连。所述触控面板200还包括平坦层222，所述平坦层222层叠设置在所述源极219、所述漏极221及所述第三绝缘层218上，所述平坦层222设置有第一贯孔2221，所述第一贯孔2221对应所述漏极221设置。所述触控面板200还包括填充部223，所述填充部223填充所述第一贯孔2221，且所述填充部223与所述漏极221电连接。所述触控面板200还包括第四绝缘层224及像素电极225，所述第四绝缘层224层叠设置在所述平坦层222上，所述第四绝缘层224设置有第二贯孔2241，所述第二贯孔2241对应所述填充部223设置。所述像素电极225设置在所述第四绝缘层224上且通过所述第二贯孔2241与所述填充部223电连接。优选地，所述像素电极225的材料与所述填充部223的材料不同。
所述填充部223包括第一部分2231及与所述第一部分2231连接的第二部分2232，所述第一部分2231穿过所述第一贯孔2241与所述漏极221电连接，所述第二部分2232设置在所述平坦层222上且覆盖所述第一贯孔2241。在本 实施方式中，所述填充部223的形状为“T”形。所述填充部223的材质为金属或者合金，举例而言，所述填充部223的材质选自铜、钨、铬、铝及其组合的其中之一。
在本实施方式中，所述触控面板200还包括遮光层211，所述遮光层211设置在所述基板210的表面上，所述低温多晶硅层212通过所述遮光层211设置在所述基板210的表面上，且所述低温多晶硅层212设置在所述遮光层211的中部。在本实施方式中，所述低温多经过层212、所述第一绝缘层213、所述第一类型重掺杂区域214、所述第二绝缘层216、所述栅极217、所述第三绝缘层218、所述源极219及所述漏极221形成低温多晶硅薄膜晶体管，所述遮光层211用于防止所述触控面板200上的低温多晶硅薄膜晶体管漏光。
在本实施方式中，所述触控面板200为自电容式触控面板，所述触控面板200还包括触控信号线226，所述触控信号线226用于检测所述触控面板200上的触控动作以及触控动作的位置，且将表征触控动作及触控动作的文字的信号传输至一芯片，以供所述芯片执行所述触控动作及所述触控动作的位置对应的操作。所述触控信号线226包括第一透明导线2261和金属丝线2262，所述金属丝线2262设置在所述平坦层222上，且所述金属丝线与所述第一透明导线2261电连接。所述第一透明导线2261的材质为透明的金属氧化物且具有导电性，所述第一透明导线2261包含铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合，材质为金属氧化物的第一透明导线12261的导电性能与金属的导电性能相较，第一透明导线2261的导电性能较差，因此，通过所述金属丝线2262与所述第一透明导线2261电连接形成的信号线在保证透明度的基础上增加了其导电性能。
优选地，所述填充部223的材料为金属，所述填充部223与所述金属丝线2262同时形成。换句话说，所述填充部223与所述金属丝线2262在同一制程中形成，以节约所述触控面板200的制备工序。所述填充部223和所述金属丝线2262可以通过以下方式形成。首先，在所述平坦层222上设置一层金属层，接着，图案化所述金属层，以形成所述填充部223及所述金属丝线1232。
所处触控面板200还包括第一类型轻掺杂区域215，所述第一类型轻掺杂区域215设置在所述第一绝缘层213上，且设置在两个所述第一类型重掺杂区 域214之间。所述第一类型轻掺杂区域215设置在两个所述第一类型重掺杂区域214之间，以减小所述低温多晶硅薄膜晶体管的泄露电流，提高所述低温多晶硅薄膜晶体管的性能。在本实施方式中，所述第一类型为P型，此时，所述第一类型重掺杂区域为P型重掺杂，第一类型轻掺杂为P型轻掺杂。可以理解地，在其他实施方式中，所述第一类型为N型，此时，所述第一类型重掺杂区域为N型重掺杂，第一类型轻掺杂为N型轻掺杂。
在本实施方式中，所述基板210可以为玻璃基板，可以理解地，在其他实施方式中，所述基板110也可以为塑料基板或者是绝缘基板。所述第一绝缘层213、所述第二绝缘层216、所述第三绝缘层218及所述第四绝缘层224的材质可以为氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
优选地，所述基板210的表面还设置缓冲层，所述缓冲层用于缓冲在所述基板210上制作所述触控面板200的其他结构的过程中受到的应力，以避免所述基板210的损坏或者破裂。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。此时，所述遮光层211、所述低温多晶硅层212、所述第一绝缘层213以及其他各层通过所述缓冲层设置在所述基板210的表面上。
相较于现有技术，本发明触控面板200通过在所述平坦层222上设置第一贯孔2221，并在第一贯孔2221内填充所述填充部223，所述填充部223与所述漏极219电连接，所述第四绝缘层224上设置第二贯孔2241，所述第二贯孔2241对应所述填充部223设置。当所述像素电极225与所述漏极221相连时，所述像素电极225仅需通过第二贯孔2241与所述填充部223电连接即可。换句话说，通过在所述平坦层222上设置第一贯孔2221以及在所述第一贯孔2221内填充所述填充部223以减小所述像素电极225与所述漏极221之间的深度，从而使得所述像素电极225与所述漏极221相连时，所述像素电极225不容易断线和脱落，从而提高了所述触控面板200的良率。进一步地，由于所述填充部223的材质为金属或者合金，其阻值小于为透明金属氧化物的像素电极225，因此，相较于现有技术中的像素电极直接与漏极相连，本发明的所述像素电极225通过所述填充部223与所述漏极221相连时，能够减小像素电极225与所述漏极221之间的电阻值。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (11)

  1. 一种触控面板，其中，所述触控面板包括：
    基板；
    依次层叠设置在所述基板的表面上的低温多晶硅层、第一绝缘层、栅极及第二绝缘层；
    源极和漏极，所述源极和所述漏极设置在所述第二绝缘层上，且所述源极和所述漏极间隔设置，所述源极及所述漏极分别通过通孔与所述低温多晶硅层相连；
    平坦层，层叠设置在所述源极、所述漏极及所述第二绝缘层上，所述平坦层设置有第一贯孔，所述第一贯孔对应所述漏极设置；
    填充部，填充所述第一贯孔，且所述填充部与所述漏极电连接；
    第三绝缘层，层叠设置在所述平坦层上，所述第三绝缘设置有第二贯孔，所述第二贯孔对应所述填充部设置；
    像素电极，设置在所述第三绝缘层上且通过所述第二贯孔与所述填充部电连接。
  2. 如权利要求1所述的触控面板，其中，所述填充部包括第一部分及与所述第一部分相连的第二部分，所述第一部分穿过所述第一贯孔与所述漏极电连接，所述第二部分设置在所述平坦层上且覆盖所述第一贯孔。
  3. 如权利要求1所述的触控面板，其中，所述触控面板还包括遮光层，所述遮光层设置在所述基板的表面上，所述低温多晶硅层通过所述遮光层设置在所述基板的表面上，且所述低温多晶硅层设置在所述遮光层的中部。
  4. 如权利要求1所述的触控面板，其中，所述触控面板还包括触控接收线及触控发射线，所述触控接收线用于接收检测信号，以检测所述触控面板上的触控动作以及触控动作的位置，所述触控发射线用于将表征触控动作及触控位置的信号传输至一芯片，所述触控接收线及所述触控发射线中的至少一条线包 括第一透明导线及金属丝线，所述金属丝线设置在所述平坦层上，且所述金属丝线与所述第一透明导线电连接。
  5. 如权利要求4所述的触控面板，其中，所述填充部的材料为金属，所述填充部与所述金属丝线同时形成。
  6. 一种触控面板，其中，所述触控面板包括：
    基板；
    依次层叠设置在所述基板的表面上的低温多晶硅层及第一绝缘层；
    层叠设置在所述第一绝缘层上的两个第一类型重掺杂区域，且两个所述第一类型重掺杂区域间隔设置；
    第二绝缘层，设置在所述第一类型重掺杂区域上；
    依次层叠设置在所述第二绝缘层上的栅极及第三绝缘层；
    源极和漏极，所述源极和所述漏极设置在所述第三绝缘层上，且所述源极和所述漏极间隔设置，所述源极及所述漏极分别通过通孔与所述第一类型重掺杂区域相连；
    平坦层，层叠设置在所述源极、所述漏极及所述第三绝缘层上，所述平坦层设置有第一贯孔，所述第一贯孔对应所述漏极设置；
    填充部，填充所述第一贯孔，且所述填充部与所述漏极电连接；
    第四绝缘层，层叠设置在所述平坦层上，所述第四绝缘层设置有第二贯孔，所述第二贯孔对应所述填充部设置；
    像素电极，设置在所述第四绝缘层上且通过所述第二贯孔与所述填充部电连接。
  7. 如权利要求6所述的触控面板，其中，所述填充部包括第一部分及与所述第一部分相连的第二部分，所述第一部分穿过所述第一贯孔与所述漏极电连接，所述第二部分设置在所述平坦层上且覆盖所述第一贯孔。
  8. 如权利要求6所述的触控面板，其中，所述触控面板还包括遮光层，所 述遮光层设置在所述基板的表面上，所述低温多晶硅层通过所述遮光层设置在所述基板的表面上，且所述低温多晶硅层设置在所述遮光层的中部。
  9. 如权利要求6所述的触控面板，其中，所述触控面板还包括触控信号线，所述触控信号线用于检测所述触控面板上的触控动作以及触控动作的位置，且将表征触控动作及触控动作的位置的信号传输至一芯片，所述触控信号线包括第一透明导线及金属丝线，所述金属丝线设置在所述平坦层上，且所述金属丝线与所述第一透明导线电连接。
  10. 如权利要求9所述的触控面板，其中，所述填充部的材料为金属，所述填充部与所述金属丝线同时形成。
  11. 如权利要求6所述的触控面板，其中，所述触控面板还包括第一类型轻掺杂区域，所述第一类型轻掺杂区域设置在所述第一绝缘层上，且设置在两个所述第一类型重掺杂区域之间。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104952792B (zh) * 2015-07-13 2017-12-29 深圳市华星光电技术有限公司 Tft基板结构的制作方法
TW201704958A (zh) * 2015-07-17 2017-02-01 群創光電股份有限公司 觸控顯示面板及觸控模式的驅動方法
CN105572993A (zh) * 2016-01-25 2016-05-11 武汉华星光电技术有限公司 阵列基板及液晶显示装置
CN107024813B (zh) 2017-06-06 2020-10-02 厦门天马微电子有限公司 阵列基板、液晶显示面板及显示装置
CN108550612B (zh) * 2018-05-29 2020-11-13 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法
CN109375405B (zh) * 2018-11-30 2021-06-18 厦门天马微电子有限公司 显示面板及其制作方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241284A (zh) * 2007-02-08 2008-08-13 精工爱普生株式会社 电光装置用基板、电光装置以及电子设备
JP2009048063A (ja) * 2007-08-22 2009-03-05 Seiko Epson Corp 電気光学装置及びその製造方法、並びに電子機器
US20130082269A1 (en) * 2011-10-03 2013-04-04 Seiko Epson Corporation Electro-optical apparatus and electronic apparatus
KR20140004887A (ko) * 2012-07-03 2014-01-14 엘지디스플레이 주식회사 액정 디스플레이 장치의 제조방법
CN103713792A (zh) * 2013-12-23 2014-04-09 京东方科技集团股份有限公司 阵列基板及其制造方法和触摸显示装置
CN104199586A (zh) * 2014-09-16 2014-12-10 重庆京东方光电科技有限公司 一种阵列基板、内嵌式触摸屏和触控显示装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW367564B (en) * 1995-09-25 1999-08-21 Toshiba Corp Forming method for polycrystalline silicon, thin film transistor containing the polycrystalline silicon and manufacturing method thereof, and the liquid crystal display containing the thin film transistor
JP3399432B2 (ja) * 1999-02-26 2003-04-21 セイコーエプソン株式会社 電気光学装置の製造方法及び電気光学装置
JP3826618B2 (ja) * 1999-05-18 2006-09-27 ソニー株式会社 液晶表示装置
JP3520417B2 (ja) * 2000-12-14 2004-04-19 セイコーエプソン株式会社 電気光学パネルおよび電子機器
TW471181B (en) * 2000-12-27 2002-01-01 Ind Tech Res Inst Manufacturing method of wide view angle flat panel display cell
KR20030016051A (ko) * 2001-08-20 2003-02-26 삼성전자주식회사 액정 표시 장치용 박막 트랜지스터 기판 및 그 제조 방법
WO2004063805A1 (fr) * 2002-12-03 2004-07-29 Quanta Display Inc. Structure de pixels et groupement de transistors en couches minces
KR101043991B1 (ko) * 2004-07-28 2011-06-24 엘지디스플레이 주식회사 액정표시소자 및 그 제조방법
TWI374544B (en) * 2006-11-13 2012-10-11 Au Optronics Corp Thin film transistor array substrates and fbricating method thereof
US8497494B2 (en) * 2006-11-24 2013-07-30 Lg Display Co., Ltd. Thin film transistor and array substrate for liquid crystal display device comprising organic insulating material
CN202057936U (zh) * 2011-05-20 2011-11-30 北京京东方光电科技有限公司 阵列基板及液晶面板
CN202057935U (zh) * 2011-05-20 2011-11-30 北京京东方光电科技有限公司 阵列基板及液晶显示装置
TWI479663B (zh) * 2011-12-22 2015-04-01 友達光電股份有限公司 陣列基板及其製作方法
US8518729B1 (en) * 2012-09-07 2013-08-27 Shenzhen China Star Optoelectronics Technology Co., Ltd. Method for manufacturing liquid crystal display panel
CN102955615B (zh) * 2012-11-09 2016-04-06 北京京东方光电科技有限公司 一种触摸屏、触控显示装置及一种触摸屏的制造方法
CN103681693B (zh) * 2013-12-05 2017-05-24 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN104157608B (zh) * 2014-08-20 2017-02-15 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241284A (zh) * 2007-02-08 2008-08-13 精工爱普生株式会社 电光装置用基板、电光装置以及电子设备
JP2009048063A (ja) * 2007-08-22 2009-03-05 Seiko Epson Corp 電気光学装置及びその製造方法、並びに電子機器
US20130082269A1 (en) * 2011-10-03 2013-04-04 Seiko Epson Corporation Electro-optical apparatus and electronic apparatus
KR20140004887A (ko) * 2012-07-03 2014-01-14 엘지디스플레이 주식회사 액정 디스플레이 장치의 제조방법
CN103713792A (zh) * 2013-12-23 2014-04-09 京东方科技集团股份有限公司 阵列基板及其制造方法和触摸显示装置
CN104199586A (zh) * 2014-09-16 2014-12-10 重庆京东方光电科技有限公司 一种阵列基板、内嵌式触摸屏和触控显示装置

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