WO2016106791A1 - 液晶显示面板及其阵列基板 - Google Patents

液晶显示面板及其阵列基板 Download PDF

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Publication number
WO2016106791A1
WO2016106791A1 PCT/CN2015/070189 CN2015070189W WO2016106791A1 WO 2016106791 A1 WO2016106791 A1 WO 2016106791A1 CN 2015070189 W CN2015070189 W CN 2015070189W WO 2016106791 A1 WO2016106791 A1 WO 2016106791A1
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Prior art keywords
layer
electrode
capacitor
array substrate
metal layer
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PCT/CN2015/070189
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English (en)
French (fr)
Inventor
郝思坤
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/433,655 priority Critical patent/US10168593B2/en
Publication of WO2016106791A1 publication Critical patent/WO2016106791A1/zh
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a liquid crystal display panel and an array substrate thereof.
  • more and more liquid crystal display devices use a Gate Driver On Array (GOA) technology on an array substrate to reduce the width of the frame of the array substrate to meet the narrow frame design trend of the liquid crystal display device.
  • GOA Gate Driver On Array
  • the prior art GOA circuit is generally composed of a plurality of shift register units, each shift register unit is connected to one gate line, and the capacitor in the shift register unit is charged by the high level signal outputted by the previous row of gate lines.
  • each shift register unit is connected to one gate line, and the capacitor in the shift register unit is charged by the high level signal outputted by the previous row of gate lines.
  • the gate line of the line output a high level signal
  • a large area of the capacitor is disadvantageous for the narrow bezel design of the liquid crystal display panel.
  • the technical problem to be solved by the embodiments of the present invention is to provide a liquid crystal display panel and an array substrate thereof, which can reduce the area occupied by the GOA circuit on the array substrate, and is advantageous for the narrow bezel design of the liquid crystal display panel.
  • a technical solution adopted by the present invention is to provide an array substrate including a substrate and a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, and an electrode layer formed on the substrate.
  • the first metal layer, the first dielectric layer and the second metal layer constitute a first capacitor
  • the second metal layer, the insulating layer and the electrode layer form a second capacitor
  • the electrode layer passes through the channel penetrating the first dielectric layer and the insulating layer
  • the hole is connected to the first metal layer to connect the first capacitor and the second capacitor in parallel
  • the array substrate further comprises a thin film transistor disposed on the substrate and a shift register unit located in the non-display area, wherein the first capacitor and the second capacitor are connected in parallel
  • the thin film transistor includes a gate electrode, a source electrode and a drain electrode, the gate electrode is formed in synchronization with the first metal layer, and the source/drain electrode layer composed of the source electrode and the drain electrode is formed in synchronization
  • the area of the projection area of the first metal layer on the substrate is larger than the area of the projection area of the second metal layer on the substrate in a direction perpendicular to the substrate, and the channel hole is disposed outside the corresponding projection area of the second metal layer.
  • the area of the projection area of the first metal layer on the substrate is larger than the area of the projection area of the second metal layer on the substrate in a direction perpendicular to the substrate, and the channel hole is disposed outside the corresponding projection area of the second metal layer.
  • the array substrate includes a first region and a second region, the thin film transistor is located in the first region, and the electrode layer is disposed on the insulating layer of the second region.
  • the thin film transistor further includes a semiconductor layer formed on the substrate, and a second dielectric layer is interposed between the semiconductor layer and the gate electrode, the first metal layer is disposed on the second dielectric layer, and the source electrode and the drain electrode are both penetrated The first dielectric layer and the second dielectric layer are connected to the semiconductor layer.
  • the thin film transistor further includes a semiconductor layer formed between the gate electrode and the source/drain electrode layer, and a second dielectric layer interposed between the semiconductor layer and the gate electrode, the first dielectric layer being sandwiched between the semiconductor layer and the source leakage Between the pole layers, the source electrode and the drain electrode both penetrate the first dielectric layer and are connected to the semiconductor layer.
  • an array substrate including a substrate and a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, and an electrode formed on the substrate.
  • a layer, the first metal layer, the first dielectric layer and the second metal layer constitute a first capacitor
  • the second metal layer, the insulating layer and the electrode layer constitute a second capacitor
  • the electrode layer passes through the first dielectric layer and the insulating layer
  • the via hole is connected to the first metal layer to connect the first capacitor and the second capacitor in parallel.
  • the array substrate further includes a shift register unit located in the non-display area, and the first capacitor and the second capacitor are connected in parallel to the shift register unit.
  • the area of the projection area of the first metal layer on the substrate is larger than the area of the projection area of the second metal layer on the substrate in a direction perpendicular to the substrate, and the channel hole is disposed outside the corresponding projection area of the second metal layer.
  • the array substrate further includes a thin film transistor disposed on the substrate, the thin film transistor includes a gate electrode, a source electrode and a drain electrode, the gate electrode is formed in synchronization with the first metal layer, and the source and drain electrode layers are composed of the source electrode and the drain electrode.
  • the two metal layers are formed synchronously, and the first dielectric layer interposed between the source and drain electrode layers and the gate electrode is formed in synchronization with the first dielectric layer of the first capacitor.
  • the array substrate includes a first region and a second region, the thin film transistor is located in the first region, and the electrode layer is disposed on the insulating layer of the second region.
  • the thin film transistor further includes a semiconductor layer formed on the substrate, and a second dielectric layer is interposed between the semiconductor layer and the gate electrode, the first metal layer is disposed on the second dielectric layer, and the source electrode and the drain electrode are both penetrated The first dielectric layer and the second dielectric layer are connected to the semiconductor layer.
  • the thin film transistor further includes a semiconductor layer formed between the gate electrode and the source/drain electrode layer, and a second dielectric layer interposed between the semiconductor layer and the gate electrode, the first dielectric layer being sandwiched between the semiconductor layer and the source leakage Between the pole layers, the source electrode and the drain electrode both penetrate the first dielectric layer and are connected to the semiconductor layer.
  • the distance between the second metal layer and the source/drain electrode layer and the substrate is equal.
  • the thickness of the gate electrode and the first metal layer are equal, and the thickness of the source/drain electrode layer and the second metal layer are equal.
  • a liquid crystal display panel comprising a color film substrate and an array substrate disposed at a relatively spaced interval, and a liquid crystal layer interposed therebetween, the array substrate including the substrate And a first metal layer, a first dielectric layer, a second metal layer, an insulating layer and an electrode layer formed on the substrate, the first metal layer, the first dielectric layer and the second metal layer forming a first capacitor, and second
  • the metal layer, the insulating layer and the electrode layer constitute a second capacitor, and the electrode layer is connected to the first metal layer through a via hole penetrating the first dielectric layer and the insulating layer to connect the first capacitor and the second capacitor in parallel.
  • the array substrate further includes a shift register unit located in the non-display area, and the first capacitor and the second capacitor are connected in parallel to the shift register unit.
  • the array substrate further includes a thin film transistor disposed on the substrate, the thin film transistor includes a gate electrode, a source electrode and a drain electrode, the gate electrode is formed in synchronization with the first metal layer, and the source and drain electrode layers are composed of the source electrode and the drain electrode.
  • the two metal layers are formed synchronously, and the first dielectric layer interposed between the source and drain electrode layers and the gate electrode is formed in synchronization with the first dielectric layer of the first capacitor.
  • the array substrate includes a first region and a second region, the thin film transistor is located in the first region, and the electrode layer is disposed on the insulating layer of the second region.
  • the thin film transistor further includes a semiconductor layer formed on the substrate, and a second dielectric layer is interposed between the semiconductor layer and the gate electrode, the first metal layer is disposed on the second dielectric layer, and the source electrode and the drain electrode are both penetrated The first dielectric layer and the second dielectric layer are connected to the semiconductor layer.
  • the thin film transistor further includes a semiconductor layer formed between the gate electrode and the source/drain electrode layer, A second dielectric layer is interposed between the semiconductor layer and the gate electrode, the first dielectric layer is interposed between the semiconductor layer and the source/drain electrode layer, and the source electrode and the drain electrode are both penetrated through the first dielectric layer and the semiconductor layer connection.
  • the beneficial effects of the embodiments of the present invention are: the first metal layer, the first dielectric layer and the second metal layer are configured to form a first capacitor, a second metal layer, an insulating layer and an electrode.
  • the layer constitutes a second capacitor, and is connected to the first metal layer through the via hole of the first dielectric layer and the insulating layer through the electrode layer, thereby connecting the first capacitor and the second capacitor in parallel, thereby reducing GOA when ensuring a sufficiently large capacitance
  • the area occupied by the circuit on the array substrate is favorable for the narrow bezel design of the liquid crystal display panel.
  • FIG. 1 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • Figure 2 is a cross-sectional view showing the structure of an embodiment of the array substrate shown in Figure 1;
  • FIG. 3 is a schematic view showing the structure of a pixel of an embodiment of the liquid crystal display panel of FIG. 1.
  • the liquid crystal display panel 10 includes a first substrate 11 , a second substrate 12 , and a liquid crystal layer 13 .
  • the first substrate 11 and the second substrate 12 are relatively spaced apart, and the second substrate 12 may be a CF (Color Filter,
  • the color filter substrate may be a TFT (Thin Film Transistor) array substrate.
  • Figure 2 is a cross-sectional view showing the structure of an embodiment of the array substrate shown in Figure 1.
  • the array substrate (first substrate) 11 includes a substrate 111 and a thin film transistor T, a first metal layer 112, a first dielectric layer 113, a second metal layer 114, and an insulating layer laminated on the substrate 111.
  • Electrode layer 116 among them:
  • the array substrate 11 includes a first area A and a second area B, and the thin film transistor T is located in the first area The domain A, the electrode layer 116 is disposed on the insulating layer 115 of the second region B.
  • the thin film transistor T includes a gate electrode g, a source electrode s, a drain electrode d, and a semiconductor layer 117 formed on the substrate 111, wherein a second dielectric layer 118 is interposed between the semiconductor layer 117 and the gate electrode g, and the substrate 111 A second dielectric layer 118 is disposed on the second semiconductor layer 118, and the source electrode s and the drain electrode d of the thin film transistor T are disposed on the second dielectric layer 118 of the second region.
  • Each of the first dielectric layer 113 and the second dielectric layer 118 is electrically connected to the semiconductor layer 117.
  • the embodiment of the present invention may provide the thin film transistor T having other structures, for example, forming the semiconductor layer 117 between the source/drain electrode layer composed of the source electrode s and the drain electrode d and the gate electrode g, correspondingly located
  • the second dielectric layer 118 of the first region A is interposed between the semiconductor layer 117 and the gate electrode g
  • the first dielectric layer 113 is interposed between the semiconductor layer 117 and the source/drain electrode layer
  • Both the s and the drain electrode d penetrate through the first dielectric layer 113 and are electrically connected to the semiconductor layer 117.
  • the area of the projection area of the first metal layer 112 on the substrate 111 is larger than the area of the projection area of the second metal layer 114 on the substrate in a direction perpendicular to the substrate 111.
  • the via hole V 0 is disposed on the second metal layer 114. Outside the corresponding projection area.
  • the first metal layer 112 is formed in synchronization with the gate electrode g of the thin film transistor T
  • the second metal layer 114 is formed in synchronization with the source/drain electrode layer of the thin film transistor T
  • the source/drain electrode layer of the thin film transistor T is interposed between the gate electrode and the gate electrode g.
  • the first dielectric layer 113 is formed in synchronization with the first dielectric layer 113 of the first capacitor C 1 (between the first metal layer 112 and the second metal layer 114), and is located in the second region B and the first region A.
  • the second dielectric layer 118 is formed simultaneously.
  • the distance between the second metal layer 114 and the substrate 111 is equal to the distance between the source/drain electrode layer of the thin film transistor T and the substrate 111.
  • the gate electrode g of the thin film transistor T is equal in thickness to the first metal layer 112, for example, (Amy), the source-drain electrode layer of the thin film transistor T (ie, the portion on the first dielectric layer 113) is equal in thickness to the second metal layer 114, and may be, for example, Further, the embodiment of the present invention can set the thickness of other layers, for example, the maximum thickness of the first dielectric layer 113 is The maximum thickness of the semiconductor layer 117 is The maximum thickness of the second dielectric layer 118 is
  • the array substrate 11 further includes a gate driver 31, data driver 32, a plurality of gate lines disposed in parallel G 1, G 2, ..., G n and a plurality of gate lines disposed in parallel and 3 G 1 , G 2 , . . . , G n insulation intersecting data lines D 1 , D 2 , . . . , D n , wherein a plurality of gate lines G 1 , G 2 , . . . , G n and The strip data lines D 1 , D 2 , . . . , D n define a plurality of pixel regions 33 arranged in an array manner.
  • Each of the pixel regions 33 includes a pixel electrode P and a thin film transistor T shown in FIG. 2, and the pixel electrode P is disposed opposite to the common electrode of the liquid crystal display panel 10.
  • the pixel electrode P corresponds to the drain electrode d of the thin film transistor T
  • the gate line corresponds to Connecting the gate electrode g of the thin film transistor T, the data line corresponding to the source electrode s of the connection thin film transistor T, and transmitting the data driving signal to the pixel electrode P via the source electrode s when the thin film transistor T is turned on, so that the gate driver 31 passes through the gate of the corresponding connection
  • the polar line supplies a scan signal to the pixel unit of the pixel area 33, and the data driver 32 supplies the gray scale signal to the pixel unit of the pixel area 33 through the corresponding connected data line.
  • the array substrate 11 further includes a plurality of shift register units of the non-display area, each shift register unit controls a potential of the gate line, for example, connected to the shift n-th gate line G n of the register unit control gate
  • the potential of the line G n , the plurality of shift register units are connected to the gate driver 31 to obtain a driving signal, and the adjacent two shift register units are also connected by a signal line, thereby ensuring that each shift register unit can be controlled column by column. Charging and discharging of the gate lines.
  • the first capacitor C 1 and the second capacitor C 2 are connected in parallel to the shift register unit, and the high level signal outputted by the upper row of gate lines is opposite to the first capacitor C 1 and the first in the shift register unit.
  • the second capacitor C 2 is charged, and the gate line of the current line is powered by the first capacitor C 1 and the second capacitor C 2 to output a high level signal, and then the high level signal outputted by the next line of the gate line is used. Reset.
  • the embodiment of the present invention charges and discharges through the two capacitors of the first capacitor C 1 and the second capacitor C 2 , so that the first capacitor C can be reduced when a sufficiently large capacitor is ensured.
  • a second capacitor C 2 and the direction perpendicular to the direction occupied by the array substrate 11 in the area of the array substrate 11, i.e., reducing the area of the GOA circuit on the array substrate 11 occupied by the narrow frame design is conducive to the liquid crystal display panel 10.

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Abstract

一种液晶显示面板及其阵列基板。该阵列基板（11）包括基体（111）以及形成于基体（111）上的第一金属层（112）、第一介电层（113）、第二金属层（114）、绝缘层（115）、电极层（116），第一金属层（112）、第一介电层（113）和第二金属层（114）构成第一电容，第二金属层（114）、绝缘层（115）和电极层（116）构成第二电容，电极层（116）通过贯穿第一介电层（113）和绝缘层（115）的通道孔与第一金属层（112）连接，以将第一电容和第二电容并联。通过上述方式，能够减少GOA电路在阵列基板上所占的面积，有利于液晶显示面板的窄边框设计。

Description

液晶显示面板及其阵列基板 【技术领域】
本发明涉及液晶显示技术领域，具体而言涉及一种液晶显示面板及其阵列基板。
【背景技术】
当前，越来越多的液晶显示装置采用在阵列基板上制作栅极驱动电路(Gate driver On Array，简称GOA)技术，减少阵列基板的边框宽度，以迎合液晶显示装置的窄边框设计趋势。
现有技术的GOA电路通常由多个移位寄存单元组成，每一移位寄存单元连接一条栅极线，利用上一行栅极线输出的高电平信号对移位寄存单元中的电容充电，以使本行的栅极线输出高电平信号，再利用下一行栅极线输出的高电平信号实现复位。其中，为使本行的栅极线输出高电平信号，必须确保足够大的电容，即电容在阵列基板上所占的面积，然而面积较大的电容不利于液晶显示面板的窄边框设计。
【发明内容】
有鉴于此，本发明实施例所要解决的技术问题是提供一种液晶显示面板及其阵列基板，能够减少GOA电路在阵列基板上所占的面积，有利于液晶显示面板的窄边框设计。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括基体以及形成于基体上的第一金属层、第一介电层、第二金属层、绝缘层、电极层，第一金属层、第一介电层和第二金属层构成第一电容，第二金属层、绝缘层和电极层构成第二电容，电极层通过贯穿第一介电层和绝缘层的通道孔与第一金属层连接，以将第一电容和第二电容并联；阵列基板进一步包括设置于基体上的薄膜晶体管以及位于非显示区的移位寄存单元，第一电容和第二电容并联连接于移位寄存单元，薄膜晶体管包括栅电极、源电极和漏电极，栅电极与第一金属层同步形成，由源电极和漏电极组成的源漏电极层与第二金属层同步形成，源漏电极层与栅电极之 间夹设的第一介电层，与第一电容的第一介电层同步形成。
其中，沿垂直于基体的方向，第一金属层在基体上的投影区域的面积大于第二金属层在基体上的投影区域的面积，通道孔设置于第二金属层对应的投影区域之外。
其中，沿垂直于基体的方向，第一金属层在基体上的投影区域的面积大于第二金属层在基体上的投影区域的面积，通道孔设置于第二金属层对应的投影区域之外。
其中，阵列基板包括第一区域和第二区域，薄膜晶体管位于第一区域，电极层设置于第二区域的绝缘层上。
其中，薄膜晶体管还包括形成于基体上的半导体层，半导体层和栅电极之间夹设有第二介电层，第一金属层设置于第二介电层上，源电极和漏电极均贯穿第一介电层和第二介电层并与半导体层连接。
其中，薄膜晶体管还包括形成于栅电极和源漏电极层之间的半导体层，半导体层和栅电极之间夹设有第二介电层，第一介电层夹设于半导体层和源漏电极层之间，源电极和漏电极均贯穿第一介电层并与半导体层连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括基体以及形成于基体上的第一金属层、第一介电层、第二金属层、绝缘层、电极层，第一金属层、第一介电层和第二金属层构成第一电容，第二金属层、绝缘层和电极层构成第二电容，电极层通过贯穿第一介电层和绝缘层的通道孔与第一金属层连接，以将第一电容和第二电容并联。
其中，阵列基板进一步包括位于非显示区的移位寄存单元，第一电容和第二电容并联连接于移位寄存单元。
其中，沿垂直于基体的方向，第一金属层在基体上的投影区域的面积大于第二金属层在基体上的投影区域的面积，通道孔设置于第二金属层对应的投影区域之外。
其中，阵列基板还包括设置于基体上的薄膜晶体管，薄膜晶体管包括栅电极、源电极和漏电极，栅电极与第一金属层同步形成，由源电极和漏电极组成的源漏电极层与第二金属层同步形成，源漏电极层与栅电极之间夹设的第一介电层，与第一电容的第一介电层同步形成。
其中，阵列基板包括第一区域和第二区域，薄膜晶体管位于第一区域，电极层设置于第二区域的绝缘层上。
其中，薄膜晶体管还包括形成于基体上的半导体层，半导体层和栅电极之间夹设有第二介电层，第一金属层设置于第二介电层上，源电极和漏电极均贯穿第一介电层和第二介电层并与半导体层连接。
其中，薄膜晶体管还包括形成于栅电极和源漏电极层之间的半导体层，半导体层和栅电极之间夹设有第二介电层，第一介电层夹设于半导体层和源漏电极层之间，源电极和漏电极均贯穿第一介电层并与半导体层连接。
其中，第二金属层和源漏电极层与基体之间的距离相等。
其中，栅电极与第一金属层的厚度相等，源漏电极层与第二金属层的厚度相等。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，包括相对间隔设置的彩膜基板和阵列基板以及夹设于两者之间的液晶层，阵列基板包括基体以及形成于基体上的第一金属层、第一介电层、第二金属层、绝缘层、电极层，第一金属层、第一介电层和第二金属层构成第一电容，第二金属层、绝缘层和电极层构成第二电容，电极层通过贯穿第一介电层和绝缘层的通道孔与第一金属层连接，以将第一电容和第二电容并联。
其中，阵列基板进一步包括位于非显示区的移位寄存单元，第一电容和第二电容并联连接于移位寄存单元。
其中，阵列基板还包括设置于基体上的薄膜晶体管，薄膜晶体管包括栅电极、源电极和漏电极，栅电极与第一金属层同步形成，由源电极和漏电极组成的源漏电极层与第二金属层同步形成，源漏电极层与栅电极之间夹设的第一介电层，与第一电容的第一介电层同步形成。
其中，阵列基板包括第一区域和第二区域，薄膜晶体管位于第一区域，电极层设置于第二区域的绝缘层上。
其中，薄膜晶体管还包括形成于基体上的半导体层，半导体层和栅电极之间夹设有第二介电层，第一金属层设置于第二介电层上，源电极和漏电极均贯穿第一介电层和第二介电层并与半导体层连接。
其中，薄膜晶体管还包括形成于栅电极和源漏电极层之间的半导体层， 半导体层和栅电极之间夹设有第二介电层，第一介电层夹设于半导体层和源漏电极层之间，源电极和漏电极均贯穿第一介电层并与半导体层连接。
通过上述技术方案，本发明实施例所产生的有益效果是：本发明实施例设计第一金属层、第一介电层和第二金属层构成第一电容，第二金属层、绝缘层和电极层构成第二电容，通过电极层贯穿第一介电层和绝缘层的通道孔与第一金属层连接，从而将第一电容和第二电容并联，在确保足够大的电容时，能够减少GOA电路在阵列基板上所占的面积，有利于液晶显示面板的窄边框设计。
【附图说明】
图1是本发明液晶显示面板一实施例的结构示意图；
图2是图1所示阵列基板一实施例的结构剖视图；
图3是图1所示液晶显示面板一实施例的像素结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，本发明以下所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
图1是本发明液晶显示面板一实施例的结构示意图。如图1所示，液晶显示面板10包括第一基板11、第二基板12以及液晶层13，第一基板11和第二基板12相对间隔设置，其中第二基板12可以为CF(Color Filter，彩色滤光片)彩膜基板，对应地，第一基板11可以为TFT(Thin Film Transistor，薄膜晶体管)阵列基板。
图2是图1所示阵列基板一实施例的结构剖视图。如图2所示，阵列基板(第一基板)11包括基体111以及层叠形成于基体111上的薄膜晶体管T、第一金属层112、第一介电层113、第二金属层114、绝缘层115、电极层116。其中：
阵列基板11包括第一区域A和第二区域B，薄膜晶体管T位于第一区 域A，电极层116设置于第二区域B的绝缘层115上。
在第一区域A，
薄膜晶体管T包括栅电极g、源电极s、漏电极d以及形成于基体111上的半导体层117，其中，半导体层117和栅电极g之间夹设有第二介电层118，并且基体111上除半导体层117覆盖区域之外还设置有第二介电层118，第一金属层112设置于位于第二区域的第二介电层118上，薄膜晶体管T的源电极s和漏电极d均贯穿第一介电层113和第二介电层118并与半导体层117电连接。
应该理解到，本发明实施例可设置薄膜晶体管T具有其他结构，例如，将半导体层117形成于由源电极s和漏电极d组成的源漏电极层和栅电极g之间，对应地，位于第一区域A的第二介电层118夹设于半导体层117和栅电极g之间，第一介电层113夹设于半导体层117和源漏电极层之间，薄膜晶体管T的源电极s和漏电极d均贯穿第一介电层113并与半导体层117电连接。
在第二区域B，
第一金属层112、第一介电层113和第二金属层114构成第一电容C1，第二金属层114、绝缘层115和电极层116构成第二电容C2，电极层116通过贯穿第一介电层113和绝缘层115的通道孔Vo与第一金属层112连接，以将第一电容C1和第二电容C2并联。
其中，沿垂直于基体111的方向，第一金属层112在基体111上的投影区域的面积大于第二金属层114在基体上的投影区域的面积，通道孔V0设置于第二金属层114对应的投影区域之外。
第一金属层112与薄膜晶体管T的栅电极g同步形成，第二金属层114与薄膜晶体管T的源漏电极层同步形成，并且薄膜晶体管T的源漏电极层与栅电极g之间夹设的第一介电层113，与第一电容C1(位于第一金属层112和第二金属层114之间)的第一介电层113同步形成，位于第二区域B和第一区域A的第二介电层118同步形成。
在本实施例中，第二金属层114与基体111之间的距离等于薄膜晶体管T的源漏电极层与基体111之间的距离。
另外，薄膜晶体管T的栅电极g与第一金属层112的厚度相等，例如 可以为
Figure PCTCN2015070189-appb-000001
(埃米)，薄膜晶体管T的源漏电极层(即位于第一介电层113上的部分)与第二金属层114的厚度相等，例如可以为
Figure PCTCN2015070189-appb-000002
进一步地，本发明实施例可对其他各层的厚度进行设置，例如第一介电层113的最大厚度为
Figure PCTCN2015070189-appb-000003
半导体层117的最大厚度为
Figure PCTCN2015070189-appb-000004
第二介电层118的最大厚度为
Figure PCTCN2015070189-appb-000005
图3是图1所示液晶显示面板一实施例的像素结构示意图。如图3所示，阵列基板11还包括栅极驱动器31、数据驱动器32、多条平行设置的栅极线G1，G2，...，Gn以及多条平行设置且与栅极线G1，G2，...，Gn绝缘交叉的数据线D1，D2，...，Dn，其中多条栅极线G1，G2，...，Gn和多条数据线D1，D2，...，Dn定义多个阵列方式排布的像素区域33。
每一像素区域33包括像素电极P和图2所示的薄膜晶体管T，像素电极P与液晶显示面板10的公共电极相对设置，像素电极P对应连接薄膜晶体管T的漏电极d，栅极线对应连接薄膜晶体管T的栅电极g，数据线对应连接薄膜晶体管T的源电极s，薄膜晶体管T导通时经源电极s传输数据驱动信号至像素电极P，使得栅极驱动器31通过对应连接的栅极线为像素区域33的像素单元提供扫描信号，数据驱动器32通过对应连接的数据线为像素区域33的像素单元提供灰阶信号。
阵列基板11还包括位于非显示区的多个移位寄存单元，每一移位寄存单元控制一条栅极线的电位，例如与第n条栅极线Gn连接的移位寄存单元控制栅极线Gn的电位，多个移位寄存单元与栅极驱动器31连接以获得驱动讯号，相邻两个移位寄存单元之间也通过讯号线连接，从而保证各个移位寄存单元能逐列控制栅极线的充电和放电。
在本实施例中，第一电容C1和第二电容C2并联连接于移位寄存单元，上一行栅极线输出的高电平信号对移位寄存单元中的第一电容C1和第二电容C2充电，并通过第一电容C1和第二电容C2为本行的栅极线供电以使其输出高电平信号，再利用下一行栅极线输出的高电平信号实现复位。相比较于现有技术的一个电容，本发明实施例通过第一电容C1和第二电容C2这两个电容进行充电和放电，因此在确保足够大的电容时，能够减少第一电容C1和第二电容C2沿垂直于阵列基板11方向在阵列基板11上所占的面积，即减少GOA电路在阵列基板11上所占的面积，有利于液晶显示面板 10的窄边框设计。
再次说明，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括基体以及形成于所述基体上的第一金属层、第一介电层、第二金属层、绝缘层、电极层，其中，所述第一金属层、所述第一介电层和所述第二金属层构成第一电容，所述第二金属层、所述绝缘层和所述电极层构成第二电容，所述电极层通过贯穿所述第一介电层和所述绝缘层的通道孔与所述第一金属层连接，以将所述第一电容和所述第二电容并联；
    所述阵列基板进一步包括设置于所述基体上的薄膜晶体管以及位于非显示区的移位寄存单元，所述第一电容和所述第二电容并联连接于所述移位寄存单元，所述薄膜晶体管包括栅电极、源电极和漏电极，所述栅电极与所述第一金属层同步形成，由所述源电极和所述漏电极组成的源漏电极层与所述第二金属层同步形成，所述源漏电极层与所述栅电极之间夹设的第一介电层，与所述第一电容的第一介电层同步形成。
  2. 根据权利要求1所述的阵列基板，其中，沿垂直于所述基体的方向，所述第一金属层在所述基体上的投影区域的面积大于所述第二金属层在所述基体上的投影区域的面积，所述通道孔设置于所述第二金属层对应的投影区域之外。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括第一区域和第二区域，所述薄膜晶体管位于所述第一区域，所述电极层设置于所述第二区域的所述绝缘层上。
  4. 根据权利要求3所述的阵列基板，其中，所述薄膜晶体管还包括形成于所述基体上的半导体层，所述半导体层和所述栅电极之间夹设有第二介电层，所述第一金属层设置于所述第二介电层上，所述源电极和所述漏电极均贯穿所述第一介电层和所述第二介电层并与所述半导体层连接。
  5. 根据权利要求3所述的阵列基板，其中，所述薄膜晶体管还包括形成于所述栅电极和所述源漏电极层之间的半导体层，所述半导体层和所述栅电极之间夹设有第二介电层，所述第一介电层夹设于所述半导体层和所述源漏电极层之间，所述源电极和所述漏电极均贯穿所述第一介电层并与所述半导体层连接。
  6. 一种阵列基板，其中，所述阵列基板包括基体以及形成于所述基体上的第一金属层、第一介电层、第二金属层、绝缘层、电极层，其中，所述第一金属层、所述第一介电层和所述第二金属层构成第一电容，所述第二金属层、所述绝缘层和所述电极层构成第二电容，所述电极层通过贯穿所述第一介电层和所述绝缘层的通道孔与所述第一金属层连接，以将所述第一电容和所述第二电容并联。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板进一步包括位于非显示区的移位寄存单元，所述第一电容和所述第二电容并联连接于所述移位寄存单元。
  8. 根据权利要求6所述的阵列基板，其中，沿垂直于所述基体的方向，所述第一金属层在所述基体上的投影区域的面积大于所述第二金属层在所述基体上的投影区域的面积，所述通道孔设置于所述第二金属层对应的投影区域之外。
  9. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括设置于所述基体上的薄膜晶体管，所述薄膜晶体管包括栅电极、源电极和漏电极，所述栅电极与所述第一金属层同步形成，由所述源电极和所述漏电极组成的源漏电极层与所述第二金属层同步形成，所述源漏电极层与所述栅电极之间夹设的第一介电层，与所述第一电容的第一介电层同步形成。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板包括第一区域和第二区域，所述薄膜晶体管位于所述第一区域，所述电极层设置于所述第二区域的所述绝缘层上。
  11. 根据权利要求10所述的阵列基板，其中，所述薄膜晶体管还包括形成于所述基体上的半导体层，所述半导体层和所述栅电极之间夹设有第二介电层，所述第一金属层设置于所述第二介电层上，所述源电极和所述漏电极均贯穿所述第一介电层和所述第二介电层并与所述半导体层连接。
  12. 根据权利要求10所述的阵列基板，其中，所述薄膜晶体管还包括形成于所述栅电极和所述源漏电极层之间的半导体层，所述半导体层和所述栅电极之间夹设有第二介电层，所述第一介电层夹设于所述半导体层和所述源漏电极层之间，所述源电极和所述漏电极均贯穿所述第一介电层并与所述半导体层连接。
  13. 根据权利要求9所述的阵列基板，其中，所述第二金属层和所述源漏电极层与所述基体之间的距离相等。
  14. 根据权利要求9所述的阵列基板，其中，所述栅电极与所述第一金属层的厚度相等，所述源漏电极层与所述第二金属层的厚度相等。
  15. 一种液晶显示面板，其中，所述液晶显示面板包括相对间隔设置的彩膜基板和阵列基板以及夹设于两者之间的液晶层，所述阵列基板包括基体以及形成于所述基体上的第一金属层、第一介电层、第二金属层、绝缘层、电极层，其中，所述第一金属层、所述第一介电层和所述第二金属层构成第一电容，所述第二金属层、所述绝缘层和所述电极层构成第二电容，所述电极层通过贯穿所述第一介电层和所述绝缘层的通道孔与所述第一金属层连接，以将所述第一电容和所述第二电容并联。
  16. 根据权利要求15所述的液晶显示面板，其中，所述阵列基板进一步包括位于非显示区的移位寄存单元，所述第一电容和所述第二电容并联连接于所述移位寄存单元。
  17. 根据权利要求15所述的液晶显示面板，其中，所述阵列基板还包括设置于所述基体上的薄膜晶体管，所述薄膜晶体管包括栅电极、源电极和漏电极，所述栅电极与所述第一金属层同步形成，由所述源电极和所述漏电极组成的源漏电极层与所述第二金属层同步形成，所述源漏电极层与所述栅电极之间夹设的第一介电层，与所述第一电容的第一介电层同步形成。
  18. 根据权利要求18所述的液晶显示面板，其中，所述阵列基板包括第一区域和第二区域，所述薄膜晶体管位于所述第一区域，所述电极层设置于所述第二区域的所述绝缘层上。
  19. 根据权利要求19所述的液晶显示面板，其中，所述薄膜晶体管还包括形成于所述基体上的半导体层，所述半导体层和所述栅电极之间夹设有第二介电层，所述第一金属层设置于所述第二介电层上，所述源电极和所述漏电极均贯穿所述第一介电层和所述第二介电层并与所述半导体层连接。
  20. 根据权利要求18所述的液晶显示面板，其中，所述薄膜晶体管还包括形成于所述栅电极和所述源漏电极层之间的半导体层，所述半导体层 和所述栅电极之间夹设有第二介电层，所述第一介电层夹设于所述半导体层和所述源漏电极层之间，所述源电极和所述漏电极均贯穿所述第一介电层并与所述半导体层连接。
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