WO2016104370A1 - 電力変換装置 - Google Patents
電力変換装置 Download PDFInfo
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- WO2016104370A1 WO2016104370A1 PCT/JP2015/085516 JP2015085516W WO2016104370A1 WO 2016104370 A1 WO2016104370 A1 WO 2016104370A1 JP 2015085516 W JP2015085516 W JP 2015085516W WO 2016104370 A1 WO2016104370 A1 WO 2016104370A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/12—Arrangements for reducing harmonics from ac input or output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
- H02M1/0022—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters the disturbance parameters being input voltage fluctuations
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
Definitions
- the present invention relates to a power converter that converts a DC voltage into an AC voltage having a variable voltage and a variable frequency by PWM (pulse width modulation) control, and outputs a high-order harmonic component in a wide range of output voltage.
- PWM pulse width modulation
- Japanese Patent Application Laid-Open No. H10-228707 describes a switching method of low-order harmonic elimination PWM in a so-called multilevel inverter.
- Patent Document 2 describes a five-level inverter with a two-stage (two-leg) series configuration in which three-level switching is one stage, preventing generation of a switching voltage twice as much as a line voltage and reducing harmonics.
- a design method of a low-order harmonic elimination PWM that performs switching at a timing to perform is disclosed.
- the modulation factor corresponding to the ratio of the output voltage to the input voltage is determined, and at the same time, the harmonic component included in the output voltage is also determined.
- a switching pattern that can reduce a harmonic component of a desired order can be selected from the plurality of switching patterns.
- This switching pattern is a function having n switching phases determined according to the number of switching pulses in PWM control as variables. Specifically, for example, as shown in Expression (4) of Patent Document 2 , A total of n simultaneous equations consisting of an equation necessary for obtaining a desired modulation factor m and an equation necessary for individually reducing harmonic components of desired orders (5, 7, 11, 13th order) An equation can be established, and n switching phases can be obtained from the solution to specify a desired switching pattern.
- the present invention has been made to solve the conventional problems as described above, and the number of types of harmonics to be reduced is not directly limited by the number of pulses. Therefore, even if the number of pulses is relatively small.
- An object of the present invention is to obtain a power conversion device that can reduce harmonic components of a wide range of orders in the output voltage.
- the power conversion device includes an inverter that includes a switching element, inputs a DC voltage of a DC voltage source, converts the DC voltage to an AC voltage having a variable voltage and a variable frequency, and outputs the AC voltage to a load.
- An output voltage command value and an output frequency command value And a control unit that performs PWM control of on / off driving of the switching element.
- the control unit includes a modulation factor calculator that calculates a modulation factor of the inverter based on the DC voltage of the DC voltage source and the output voltage command value, and a fundamental half cycle in the PWM control based on the output frequency command value.
- a pulse number determination unit that determines the number of pulses per hit, and a modulation pattern that specifies a switching phase that is a timing for turning on and off the switching element according to the modulation factor and the number of pulses is calculated in advance to calculate the modulation factor and the A switching pattern determining unit for storing each pulse number; and reading out the switching pattern corresponding to the modulation rate from the modulation factor calculator and the pulse number from the pulse number determining unit from the switching pattern determining unit, On-off drive of the switching element based on the switching pattern And a gate signal generator for generating a that gate signal.
- the switching pattern determination unit generates a first function that is a function for securing the modulation rate and relates the fundamental wave component of the output waveform of the inverter and the modulation rate, with the switching phase as a variable.
- a harmonic reduction unit that generates a second function having the switching phase as a variable, a first function, the second function, and one or more additional variables, wherein the switching phase and the additional variable are variables.
- the switching pattern determination unit in the power conversion device is a function for ensuring the modulation rate, and relates the fundamental wave component of the output waveform of the inverter and the modulation rate.
- a modulation factor securing unit that generates a first function with the switching phase as a variable, and a function for reducing harmonic components of the output waveform of the inverter, each harmonic component of the output waveform of the inverter
- a harmonic reduction unit that generates a second function having the switching phase as a variable, which is an added value of each determined harmonic element, the first function, the second function, and one or more additional variables;
- a function synthesis unit for setting a third function having the switching phase and the additional variable as variables; and minimizing the third function with respect to the switching phase and the additional variable.
- Rate and the switching pattern storage unit for storing each number of pulses, the number of harmonic order types to be reduced is not directly limited by the number of pulses, and therefore even if the number of pulses is relatively small, A wide range of harmonic components in the output voltage can be reduced.
- FIG. It is a figure which shows the internal structure of the switching pattern determination part in Embodiment 2 of this invention. It is a figure which shows the internal structure of the gate signal generation part in Embodiment 4 of this invention. It is a figure which shows the replacement frequency determination procedure of the switching pattern used by two switching legs of the inverter in Embodiment 4 of this invention. It is explanatory drawing of the switching frequency determination by load current in Embodiment 4 of this invention.
- FIG. 1 is a circuit diagram showing an overall configuration of a power conversion device 2 according to Embodiment 1 of the present invention.
- the power conversion device 2 includes an inverter 4 and a control unit 10 that controls the inverter 4, and the DC voltages of the U, V, and W phase DC voltage sources 1 a, 1 b, and 1 c are converted to variable voltage variable frequency AC The voltage is converted and output to the motor 3 as a load.
- FIG. 2 is a circuit diagram showing the configuration of the inverter 4.
- the inverter 4 includes two series of positive side capacitors 5a and negative side capacitors 5b that divide the DC voltage of the DC voltage source 1a, a plurality of switching elements 6 each of which has an anti-parallel connected diode, and a clamp diode 7.
- the inverter 4 includes two series of positive side capacitors 5a and negative side capacitors 5b that divide the DC voltage of the DC voltage source 1a, a plurality of switching elements 6 each of which has an anti-parallel connected diode, and a clamp diode 7.
- FIG. 3 shows an example of the two-level inverter 40, and each phase is composed of one switching leg 80. Two two-level switching legs 80 shown in FIG. 3 may be connected in series for each phase and used in an inverter.
- the inverter 4 converts the DC voltage of the DC voltage sources 1a to 1c into an AC voltage having an arbitrary magnitude and frequency and outputs it by driving the switching element 6 on and off by PWM (pulse width modulation) control. Further, the inverter 4 includes a current sensor 19 as a load current detection unit that detects a current of the motor 3 that is a load current iL at a connection portion with the motor 3. The inverter 4 includes an element current detection unit that detects a current flowing through the switching element 6 and an element current / temperature sensor 18 as an element temperature detection unit that detects the temperature of the switching element 6.
- the control unit 10 includes a modulation factor calculator 11, a pulse number determination unit 13, a switching pattern determination unit 12, a pulse number switching unit 14, and a gate signal generation unit 16. These components will be described below.
- the modulation factor calculator 11 calculates the modulation factor m according to the equation (1) based on the DC voltage Vdc of the DC voltage sources 1a to 1c and the output voltage command value (phase voltage amplitude) Vp of the inverter 4.
- the pulse number determination unit 13 determines the pulse number Pnum per fundamental wave half cycle in PWM control.
- the inverter 4 having an element with a slow switching speed such as a large capacity inverter, when the output frequency command value Fc becomes high, it is necessary to reduce the number of pulses Pnum per half cycle step by step to reduce the number of times of switching.
- the number of pulses Pnum is set to 1 (one pulse in a half cycle) during high-speed operation.
- the pulse number switching unit 14 When the pulse number Pnum determined by the pulse number determination unit 13 changes, the pulse number switching unit 14 provides a switching transition period, and when the output voltage phase (th) of the inverter 4 reaches a predetermined phase, the switching pattern determination unit The switching command 15 for switching the switching pattern read out from the terminal 12 is output to the switching pattern determination unit 12.
- the switching pattern determination unit 12 obtains in advance a switching pattern for specifying a switching phase, which is a timing for driving the switching element 6 on and off, for each magnitude of the modulation factor m by calculating the modulation factor m and the pulse number Pnum.
- a switching phase which is a timing for driving the switching element 6 on and off
- the modulation factor m is a timing for driving the switching element 6 on and off
- This calculation is to obtain a switching pattern that realizes the required modulation factor m and reduces the harmonic component, and forms the main part of the present invention.
- the switching pattern and the calculation procedure are described in detail later. Explained.
- the gate signal generator 16 reads the switching pattern corresponding to the modulation factor m from the modulation factor calculator 11 and the pulse number Pnum from the pulse number determiner 13 from the switching pattern determiner 12 and the switching pattern and the output voltage phase ( th) and a gate signal 17 for driving the switching element 6 on and off is generated.
- FIG. 4 is a diagram illustrating a hardware configuration of the power conversion device 2.
- the control unit 10 includes a processor 301, a storage device 302, and a switching pattern storage device 303.
- the program of the control unit 10 is stored in advance.
- the processor 301 executes a function program stored in the storage device 302.
- the processor 301 implements the modulation factor calculator 11, the switching pattern determination unit 12, the pulse number determination unit 13, the pulse number switching unit 14, and the gate signal generation unit 16 in the control unit 10.
- the switching pattern storage device 303 stores the switching pattern determined by the switching pattern determination unit 12 according to the program executed by the processor 301, and may be stored during the execution of the function program or stored at the time of activation. Also good.
- the calculation processing of the processor 301 A gate signal 17 for driving the switching element 6 of the inverter 4 on and off is generated.
- the figure shows a pulse voltage waveform over one period (2 ⁇ ), and shows a single-phase output voltage Vs of the five-level inverter 4, an output voltage VLa of the switching leg 8a, and an output voltage VLb of the switching leg 8b.
- the switching leg is abbreviated as a leg.
- the switching phase that is the timing for turning on or off the switching element 6, th1a, th2a and th3a in the switching leg 8a, and th1b in the switching leg 8b, Th2b and th3b are determined.
- the output waveforms of the respective switching legs 8a and 8b and the output voltage waveform of the 5-level inverter 4 are determined. That is, the switching pattern specifies these six switching phases th1a, th2a, th3a, th1b, th2b, th3b, and the output voltage waveform of the inverter 4 is specified by this switching pattern.
- FIG. 2 a comparative example showing determination of a switching pattern using the technique described in Patent Document 2 is shown in FIG. This will be described below with reference to FIGS.
- the description based on the drawing showing the control configuration is not particularly given, but here, in order to clarify the comparison with the present invention, the switching pattern determination in the first embodiment is intentionally made. It is assumed that the control configuration corresponding to the unit 12 is a comparative example.
- the configuration of the inverter is the same as that of the 5-level inverter 4 used in the first embodiment.
- the switching pattern determining means 100 frequency-converts a time-series switching pattern determined by the number of pulses, the modulation rate, and the output frequency, and the amplitude of the output voltage fundamental wave and the integer frequency component of the amplitude are multiplied by the Fourier series.
- the switching pattern determining means 100 determines the degree of freedom of simultaneous equations, which will be described later, determined from the number of switching phases based on the modulation factor securing means 101 that secures the modulation factor amplitude and the number of pulses and the determined number of series stages of the switching legs.
- the harmonic order type number determining means 102 for determining the number of types of harmonic orders that can be deleted from this and the number of degrees of freedom used by the modulation factor securing means 101, and the harmonic order type number determining means 102
- Switching for calculating the switching phase of the switching pattern by solving the equations set by the harmonic canceling means 103 for performing harmonic canceling, the modulation factor securing means 101 and the harmonic canceling means 103 for the harmonic order that can be canceled
- the phase calculation means 104 and the switching phase calculated by the switching phase calculation means 104 Composed of the switching pattern storage section 105 for storing each modulation rate and the respective number of pulses of the switching pattern determined.
- the output voltage waveform output by each switching leg is symmetrical with each phase of 120 ° and symmetric with 1/4 cycle and 1/2 cycle, regardless of the number of pulses.
- the even order and triple order do not occur theoretically. Therefore, when the order of the fundamental wave is 1, the generated harmonic order is represented by 6n ⁇ 1. That is, the harmonic order based on the fundamental frequency is 6n ⁇ 1st when the natural number n is used, and is 5, 7, 11, 13, 17, 19, 23, 25, 29, 31, 35, 37,. ⁇ Take numerical values like
- the first stage is an expression that defines the relationship between the switching phases th1a, th2a, and th3a of the switching leg 8a and the modulation factor m
- the second stage is the switching phases th1b and th2b of the switching leg 8b.
- Th3b and a modulation rate m which are set by the modulation rate securing means 101 in FIG.
- the harmonic order type number determining means 102 calculates the number of switching phases of the harmonic output voltage fundamental half-cycle from the number of pulses and the number of stages of the switching leg per phase of the inverter 4, and can be eliminated. Determine the number of types.
- the harmonic canceling means 103 sequentially sets the fourth, fifth, eleventh, and thirteenth harmonic components from zero to zero, and the third to sixth formulas of the formula (2). Will be set.
- the switching phase calculation means 104 is the first to second expression of the expression (2) set by the modulation factor securing means 101, and the third to second expressions of the expression (2) set by the harmonic elimination means 103.
- Six variables that specify the switching pattern, that is, the switching phases (th1a to th3b) are calculated by solving a six-element simultaneous equation consisting of the sixth-stage equation.
- FIG. 7 is a diagram showing the characteristics of each switching phase obtained over the range of a predetermined modulation factor m by this equation (2).
- FIG. 7A shows the switching phases th1a, th2a, th3a
- FIG. 7B shows the characteristics of the switching phases th1b, th2b, and th3b of the switching leg 8b.
- phase difference between some of the switching phases th1a and th2a adjacent to each other in the same switching element in the area “maria” centering on the modulation factor m1 is mainly the viewpoint of the switching speed performance. From the lower limit phase difference thlim allowed by the switching element.
- the content of the harmonic order type number determining means 102 is changed while the modulation factor securing means 101 is left as it is, and in Equation (2), the number of harmonic orders to be reduced is reduced by one, and instead the lower limit.
- a method for obtaining a solution by employing an equation for securing the phase difference thlim may be employed.
- the number of harmonic order types to be reduced is not directly limited by the number of pulses. Therefore, even if the number of pulses Pnum is relatively small, the number of order types in the output voltage is higher than the total number of pulses.
- the wave component can also be reduced, and the specific contents thereof will be described in detail below.
- FIG. 8 is a diagram showing an internal configuration of the switching pattern determination unit 12 employed in the power conversion device 2 according to Embodiment 1 of the present invention.
- the switching pattern determination unit 12 includes a modulation factor securing unit 121, a harmonic reduction unit 122, a function synthesis unit 123, a switching phase calculation unit 124, and a switching pattern storage unit 125.
- the switching pattern determination unit 12 is realized by the processor 301, but the switching pattern storage unit 125 in the switching pattern determination unit 12 is realized by the switching pattern storage device 303.
- the modulation rate securing unit 121 is a function for securing the modulation rate, and is a first function that relates the fundamental wave component of the output waveform of the inverter 4 and the modulation rate based on the modulation rate, the number of pulses, and the number of switching leg stages. f is generated.
- the harmonic reduction unit 122 is a function for reducing the harmonic component of the output waveform of the inverter 4 and is determined by each harmonic component based on the number of pulses and the number of switching leg stages.
- a second function Y that is an added value of is set.
- the function synthesis unit 123 sets an evaluation function X that is a third function including the first function f, the second function Y, and one or more additional variables described later.
- the switching phase calculation unit 124 calculates a switching phase that secures the modulation rate by minimizing the evaluation function X with respect to the switching phase and the additional variable and reduces the added value of each harmonic component.
- the switching pattern storage unit 125 stores a switching pattern determined by the switching phase calculated by the switching phase calculation unit 124 for each modulation factor and each number of pulses.
- the modulation factor securing unit 121 secures the modulation factor m obtained by connecting both switching legs 8a and 8b in series, so that each switching phase (here, th1a, th2a, th3a) is obtained.
- Th1b, th2b, and th3b which are also hereinafter referred to as thi
- a first function f (thi) that defines each switching phase thi as a variable is defined.
- the harmonic reduction unit 122 reduces each harmonic of the output waveform of the inverter 4 as an addition value of each switching phase thi and each harmonic element in order to reduce harmonics.
- k represents the harmonic order to be reduced, and here, the order of the total of 8 types of 5th order,..., 25th order is targeted, but it is not limited to these. Absent.
- the weighting coefficient w (k) will be further described later.
- the function synthesis unit 123 secures the modulation rate and reduces the above-described square sum related to each harmonic voltage component, so that the first function f and the second function Y are free.
- An evaluation function X is defined in which the degree of freedom is increased by adding additional variables to degrees (corresponding to the number of switching phases thi as variables, here six variables). Specifically, each switching phase, which is the sum of the function Y (thi) shown in Expression (6) and the value obtained by multiplying the function f (thi) shown in Expression (5) by the weighting variable ⁇ as an additional variable.
- An evaluation function X (thi, ⁇ ) is defined with thi and weighting variable ⁇ as variables. The evaluation function X may be formed by multiplying the second function Y by an additional variable.
- the switching phase calculation unit 124 takes the partial differentiation of the seven variables ⁇ and th1a to th3b of the evaluation function X (thi, ⁇ ) and sets them all to 0. Create an equation. Then, by solving the seven simultaneous equations using, for example, a Newton method, the required modulation factor m is ensured, and the switching pattern that minimizes the total value of the harmonic voltage components of many orders is minimized. Can be obtained.
- FIG. 9A shows the characteristics of the switching phases th1a, th2a and th3a of the switching leg 8a
- FIG. 9B shows the characteristics of the switching phases th1b, th2b and th3b of the switching leg 8b.
- the harmonic component reduction degree of the order can be made larger than that of other orders.
- harmonic components of a specific order may be high, which may cause harmful torque ripple due to the harmonics. is there.
- the weighting coefficient w (k) of the specific order is set to a larger value than the others, it is possible to prevent harmful torque ripples from occurring and to reduce the overall harmonics. Can be obtained.
- the figure shows a pulse voltage waveform over one period (2 ⁇ ), and shows a single-phase output voltage Vs of the five-level inverter 4, an output voltage VLa of the switching leg 8a, and an output voltage VLb of the switching leg 8b.
- the switching leg 8a has th1a as the switching phase that is the timing for turning on or off the switching element 6.
- th1b is determined in the leg 8b.
- the output waveform of each switching leg 8a, 8b and the output voltage waveform of the 5-level inverter are determined. That is, the switching pattern specifies these two switching phases th1a and th1b, and the output voltage waveform of the inverter 4 is specified by this switching pattern.
- the modulation factor securing unit 121 defines the relationship between each switching phase (th1a, th1b, hereinafter also referred to as thi) and the modulation factor m by the equation (9), and uses the first function with each switching phase thi as a variable.
- f (thi) The harmonic reduction unit 122 obtains the relationship between each switching phase thi and the sum of squares of values obtained by multiplying each order harmonic voltage component of the output waveform of the inverter 4 by each order weighting coefficient w (k) by Expression (10).
- a defined second function Y (thi) with each switching phase thi as a variable is defined.
- the function synthesis unit 123 multiplies the second function Y (thi) shown in the formula (10) by the formula (11) and the first function f (thi) shown in the formula (9) by the weighting variable ⁇ as an additional variable.
- An evaluation function X (thi, ⁇ ) is defined that uses each switching phase thi and the weighting variable ⁇ as variables.
- the switching phases th1a and th1b change smoothly according to the modulation factor m.
- both the 7th-order and 11th-order harmonic components other than the 5th-order elimination target are high.
- Expression (12) according to this embodiment shown without hatching the harmonic components of the respective orders are low as a whole. Then, it can be confirmed that the total value of the harmonic amplitudes is reduced, and the harmonic components can be suppressed in a range where the number of types of orders is (Pnum ⁇ number of leg series stages) or more.
- the total voltage distortion which is a value obtained by dividing the square root of the sum of squares of each harmonic voltage component by the reference wave voltage component, is a measure of the harmonic content.
- This distortion factor is obtained, it is 17% in this embodiment compared with 25% in the comparative example, and it can be confirmed that the distortion factor can be reduced at a rate of about 1/3.
- the switching pattern determination unit 12 of the power conversion device 2 according to Embodiment 1 of the present invention includes the modulation factor securing unit 121, the harmonic reduction unit 122, and the function synthesis unit 123 described in detail above. Further, a switching phase calculation unit 124 and a switching pattern storage unit 125 are provided.
- the modulation factor securing unit 121 is a function for securing the modulation factor, and relates a first function f (thi) with the switching phase thi as a variable, which relates the fundamental wave component of the output waveform of the inverter 4 and the modulation factor.
- the harmonic reduction unit 122 is a function for reducing the harmonic component of the output waveform of the inverter 4 and is an added value of each harmonic element determined by each harmonic component of the output waveform of the inverter 4.
- a second function Y (thi) having a certain switching phase thi as a variable is set.
- the function synthesis unit 123 includes a first function f (thi), a second function Y (thi), and an additional variable ⁇ , and an evaluation function X as a third function having the switching phase thi and the additional variable ⁇ as variables.
- (Thi, ⁇ ) Y (thi) + ⁇ ⁇ f (thi) is set.
- the evaluation function X (thi, ⁇ ) is subjected to partial differentiation with respect to the switching phase thi and the additional variable ⁇ , and a simultaneous equation that sets them all to 0 is solved to minimize the evaluation function X (thi, ⁇ ).
- the switching phase thi that secures the modulation rate and reduces the added value of each harmonic component can be calculated by the switching phase calculation unit 124, and the switching pattern specified by the calculated switching phase thi is calculated for each modulation rate. And it memorize
- FIG. 13 is a diagram showing an internal configuration of the switching pattern determination unit 12A according to the second embodiment.
- the countermeasure in the comparative example adopts the solution based on the simultaneous equations shown in the equation (3) instead of the equation (2) for the area area including the modulation factor m1.
- the phase difference between the adjacent switching phases is equal to or greater than the lower limit phase difference thlim. Absent. However, it is considered that this problem may also occur in the first embodiment depending on the calculation conditions. Therefore, in the second embodiment, a countermeasure for that case is realized.
- the phase difference between the adjacent switching phases th1a and th2a is less than the lower limit phase difference thlim. It is assumed that it has become.
- the switching pattern determination unit 12A shown in FIG. 13 is different from the switching pattern determination unit 12 shown in FIG. 6 of the first embodiment in that a switching phase difference limiting unit 126 is newly provided.
- the explanation will be focused on. Other configurations are the same as those in the first embodiment.
- the switching phase difference limiting unit 126 newly sets a function P that defines the phase difference between the adjacent switching phases th1a and th2a in order to set the lower limit (thlim) of the switching phase difference.
- this function P (th1a, th2a) is defined by equation (13).
- This function P is reflected in the equations (14) and (15) described later, which are defined by the function synthesis unit 123 and the switching phase calculation unit 124, respectively, so that the phase difference between the switching phases th1a and th2a ⁇ Lower limit phase difference thlim is ensured. Furthermore, the evaluation function X (thi, ⁇ ) shown in the previous equation (7) is replaced with the evaluation function X (thi, ⁇ , ⁇ ) shown in the following equation (14). The function f (thi) and the function Y (thi) are the same as those in the first embodiment.
- the switching pattern determining unit 12A stores the switching pattern obtained by the above equation (8) and stores the switching rate obtained in the above formula (8) in the same manner as in the first embodiment when the modulation rate is other than the area area. Stores the switching pattern obtained by equation (15) in place of the switching pattern obtained by equation (8).
- the number of harmonic order types to be reduced is not directly limited by the number of pulses. Therefore, even if the number of pulses is relatively small, the output voltage level Further, it is possible to reduce harmonic voltage components or harmonic current components in which the number of types of orders is greater than the total number of pulses.
- the switching pattern determining unit 12A includes the switching phase difference limiting unit 126, the phase difference between the switching phases adjacent to each other in a part of the obtained switching pattern becomes less than the lower limit phase difference, and the switching element 6 When there is a problem in the switching operation, the following can be dealt with.
- the switching phase calculation unit 124 obtains this evaluation function X (thi, ⁇ , ⁇ ) by solving partial equations for the switching phase thi and the additional variables ⁇ , ⁇ and setting them to 0 or 0 or more.
- the above switching pattern is replaced with the partial switching pattern. As a result, the necessary phase difference thlim between adjacent switching phases can be ensured, and troubles in the switching operation can be eliminated.
- Embodiment 3 a power conversion device according to Embodiment 3 of the present invention will be described.
- the overall configuration of power conversion device 2 is the same as that shown in FIGS. 1 and 2 of the first embodiment.
- the first function set by the modulation factor securing unit 121 in the switching pattern determination unit 12 is different from that in the first embodiment.
- Other configurations are the same as those of the first embodiment.
- the function f for securing the modulation rate obtained by connecting both the switching legs 8a and 8b in series as the first function that defines the relationship between each switching phase and the modulation rate is expressed by the equation (5).
- the switching pattern is obtained under the condition that the modulation rate to be output is the same in both switching legs 8a and 8b. An outline of the procedure is described below.
- a function fa (th1a, th2a, th3a as a first function that defines the relationship between the switching phase and the modulation factor is provided.
- a function fb (th1b, th2b, th3b).
- the function fa and the function fb are set so that the modulation rate m to be output is equally divided between both the switching legs 8a and 8b.
- the evaluation function X (thi, ⁇ 1, ⁇ 2) shown in the equation (18) is defined as the third function instead of the evaluation function X shown in the equation (7) in the first embodiment.
- the function Y (thi) is the same as that in the first embodiment, and the function Y (thi) defined by the above formulas (6) and (10) is used.
- the number of harmonic order types to be reduced is not directly limited by the number of pulses. Therefore, even in a relatively small number of pulses, the output voltage level Further, it is possible to reduce harmonic voltage components or harmonic current components in which the number of types of orders is greater than the total number of pulses. Furthermore, the switching pattern can be determined so that the modulation rates output from both of the switching legs 8a and 8b are equal to each other, and the burden on both the switching legs 8a and 8b can be made uniform.
- the functions Y (thi) defined by the above formulas (6) and (10) are intended to reduce the sum of squares of the harmonic voltage components.
- the load is the motor 3
- an increase in copper loss of the motor 3 due to the presence of the harmonic component may be a problem.
- the reduction of the harmonic current component becomes a problem.
- the current flowing through the motor 3 is a value obtained by dividing the voltage by the impedance, and the impedance Z is substantially determined by the inductance L of the motor 3. That is, Z ⁇ 2 ⁇ fL, and the current is inversely proportional to the frequency f.
- each harmonic component is a multiplication value of each harmonic voltage component and each harmonic current component, and each addition value of the multiplication value is the first harmonic value.
- the switching phase may be obtained as a two function Y (thi). In this case, it is possible to reduce the sum of the respective harmonic power components.
- the second function Y1 (thi) can be applied not only to the third embodiment but also to the first and second embodiments, and the same effect can be obtained.
- FIG. 14 is a diagram showing an internal configuration of the gate signal generation unit 16A according to the fourth embodiment. Other configurations are the same as those of the first embodiment.
- the gate signal generation unit 16A generates switching patterns corresponding to the modulation rate m from the modulation rate calculator 11 and the pulse number Pnum from the pulse number determination unit 13 from the switching pattern determination unit 12. Reading and generating a gate signal 17 for driving the switching element 6 on and off based on the switching pattern.
- the switching leg 8a uses only the switching pattern for the switching leg 8a (hereinafter referred to as the switching pattern for the a leg), and the switching leg 8b uses the switching pattern for the switching leg 8b (hereinafter referred to as the b leg). If the switching operation is continued using only the switching pattern), the ON / OFF time and the flowing current differ depending on the load current and the switching phase. Prone to deterioration and switching variations.
- the gate signal generation unit 16A includes a switching pattern replacement unit 161 and a gate signal generation unit 162.
- the switching pattern switching unit 161 changes the switching pattern of the switching legs 8a and 8b based on the output voltage phase th, the load current and the element current, and the element temperature so that the load between the two switching legs 8a and 8b is equalized. Replace at a predetermined cycle.
- the gate signal generation unit 162 generates the gate signal 17 based on the switching pattern replaced by the switching pattern replacement unit 161.
- FIG. 15 is a diagram illustrating a procedure example for determining the switching frequency of the switching patterns of the two switching legs 8a and 8b.
- a flow for determining the replacement cycle NN, which is the switching pattern replacement frequency, will be described below with reference to FIG.
- the replacement cycle NN is represented by the number of cycles at the inverter operating frequency.
- the load current is detected by the current sensor 19, and the effective value Rms of the load current is calculated (ST1).
- the load current effective value Rms and the switching frequency determination threshold value Ca are compared to determine the switching frequency based on the load current (ST2).
- FIG. 16 shows an example of the output voltage Vs and load current of the single-phase five-level inverter 4 in step ST2.
- Waveforms 71a and 71b indicate a single-phase load current
- waveform 71ar indicates a current effective value (Rms) of the load current (waveform 71a)
- waveform 71br indicates a current effective value (Rms) of the load current (waveform 71b)
- waveform Reference numeral 71 represents a switching frequency determination threshold value Ca converted to a phase current.
- step ST2 when the detected load current is in the state shown in the waveforms 71b and 71br, that is, when the effective value Rms of the load current is equal to or less than the determination threshold value Ca, the switching pattern replacement cycle NN is 4 (4 cycles at the inverter operating frequency). And This is to increase the switching pattern replacement period NN to lower the replacement frequency (ST3).
- step ST2 when the detected load current is in the state shown in the waveforms 71a and 71ar, that is, when the effective value Rms of the load current is higher than the determination threshold value Ca, the two switching legs 8a of the inverter 4 are detected by the element current / temperature sensor 18. The element currents of the plurality of switching elements 6 every 8b are detected, and the average current Ie is calculated (ST4). Next, a value obtained by multiplying the switching element average current Ie for each switching leg 8a, 8b by the switching leg ON time is compared with a determination threshold Cb determined in advance by design (ST5). Sets the switching pattern replacement period NN to 2 (ST6).
- step ST5 when the value obtained by multiplying the switching element average current Ie for each switching leg 8a, 8b by the ON time of the switching leg is higher than the determination threshold Cb, the element current / temperature sensor 18 causes the switching leg 8a, 8b to The element temperatures of the plurality of switching elements 6 are detected, and the average temperature THe is calculated (ST7).
- the average temperature THe of the switching elements for each of the switching legs 8a and 8b is compared with a determination threshold value Cc determined in advance by design (ST8). If it is equal to or less than the determination threshold value Cc, the process proceeds to step ST6.
- the replacement cycle NN is set to 2.
- step ST8 when the average temperature THe of the switching elements for each switching leg 8a, 8b is higher than the determination threshold Cc, the switching pattern replacement period NN is set to 1 (ST9).
- the switching leg 8a performs switching using the leg 8a pattern (th1a), which is its own switching pattern.
- the switching leg 8a performs switching using the leg 8b pattern (th1b) which is a switching pattern for the switching leg 8b.
- the switching leg 8b performs switching by alternately using its own leg 8b pattern and leg 8a pattern every two periods.
- the phase of switching pattern replacement is 0 ° for each phase.
- the switching patterns of the two switching legs 8a and 8b are exchanged within one period at the inverter operating frequency.
- the switching leg 8a switches between 0 to (1/2) ⁇ and ⁇ to (3/2) ⁇ using the leg 8b switching pattern (th1b), and (1 / 2) Switching between ⁇ to ⁇ and (3/2) ⁇ to 2 ⁇ is performed by using the switching pattern (th1a) for the leg 8a.
- the switching is performed using the switching pattern for the leg 8a (th1a) between 0 to (1/2) ⁇ and ⁇ to (3/2) ⁇ .
- the switching leg 8b performs switching using a switching pattern that is not used by the switching leg 8a.
- the switching pattern replacement cycle is switched based on the detected values of the load current, the element current, and the element temperature.
- the present invention is not limited to this.
- the switching pattern is switched based on one or more types of detection values among the load current, element current, and element temperature, and the configuration related to switching is simplified. Also good.
- the number of harmonic order types to be reduced is not directly limited by the number of pulses. Therefore, even if the number of pulses is relatively small, the output voltage level Further, it is possible to reduce harmonic voltage components or harmonic current components in which the number of types of orders is greater than the total number of pulses.
- the gate signal generation unit 16A includes a switching pattern switching unit 161 and a gate signal generation unit 162, and generates the gate signal 17 so that the switching patterns of the switching legs 8a and 8b are switched at a predetermined period. As a result, the load on both switching legs 8a and 8b can be made uniform, and the life of the device is extended accordingly.
- FIG. 20 and 21 are circuit diagrams showing the overall configuration of the power conversion device according to Embodiment 5 of the present invention.
- FIG. 20 shows the configuration of the inverter 4 as the main circuit in detail
- FIG. 21 shows the configuration of the control unit 10 in detail.
- the voltage of the DC voltage source 1 is divided into two to equalize the voltages of the positive-side capacitor 5a and the negative-side capacitor 5b that supply the DC voltage to the switching legs 8a and 8b.
- a measure that eliminates the difference between the positive and negative output voltages is adopted.
- Other configurations and operations are the same as those in the first embodiment, and operations related to harmonic reduction are also the same.
- the configuration and operation related to the above-described measures will be mainly described.
- the power converter 2 includes a neutral point voltage sensor 22a, 22b, 22c that detects a voltage difference between the positive side capacitor 5a and the negative side capacitor 5b as a neutral point voltage, and a positive side capacitor.
- Neutral point current sensors 21a, 21b, and 21c that detect currents ica, icb, and icc that flow into the connection point between 5a and the negative electrode side capacitor 5b as neutral point currents are provided.
- the neutral point voltage is indicated by using the reference numerals 22a, 22b, and 22c of the neutral point voltage sensor.
- FIG. 22 is an internal block diagram of the gate signal generator 16B.
- the gate signal generation unit 16B includes a pulse correction unit 163 that corrects the switching pattern, and a gate signal generation unit 164 that generates the gate signal 17 based on the corrected switching pattern.
- the pulse correction unit 163 corrects the switching pattern read from the switching pattern determination unit 12 according to the detection outputs of the neutral point voltage sensors 22a, 22b, and 22c or the neutral point current sensors 21a, 21b, and 21c.
- FIG. 23 is a diagram for explaining a procedure for correcting the voltage imbalance between the positive-side capacitor 5a and the negative-side capacitor 5b by the pulse correction unit 163.
- the voltage of the positive electrode side capacitor 5a is higher than the voltage of the negative electrode side capacitor 5b, and this is detected, and this difference is reduced by correcting the switching pattern of the U-phase switching leg 8a.
- the switching phase to be corrected is the phase of the central pulse closest to ⁇ / 2, (3/2) ⁇ , in which the pulse waveform does not change, and the phase at which switching is turned on. Or only the phase at which switching is turned off.
- correction amount “shift” may be changed stepwise depending on the voltage difference (vcua ⁇ vcub) between the positive electrode side capacitor 5a and the negative electrode side capacitor 5b or the neutral point current (ica). Furthermore, an optimal correction amount may be calculated by so-called feedback control so that the voltage difference between the capacitors 5a and 5b becomes zero. Further, the frequency of correction may be changed according to the voltage difference and the neutral point current.
- FIG. FIG. 24 is a circuit diagram showing the overall configuration of the power conversion device according to Embodiment 6 of the present invention.
- the overall configuration of the power conversion device 2 is the same as that shown in the first embodiment, but in this case, the internal configuration of the switching pattern determination unit 12B in the control unit 10 is different. Other configurations are the same as those of the first embodiment.
- the determination of the switching pattern according to the sixth embodiment will be briefly described below with reference to FIG.
- the central pulse 211 that is a partial waveform of the output voltage waveform.
- the central pulse 211 is generated by the phases th3a and th3b, and is constituted by a central pulse train obtained by adding the central pulse 211a of the output voltage VLa of the switching leg 8a and the central pulse 211b of the output voltage VLb of the switching leg 8b.
- a desired fundamental wave is secured and each harmonic component is reduced.
- FIG. 26 is a diagram showing an internal configuration of the switching pattern determination unit 12B according to the sixth embodiment.
- the switching pattern determination unit 12B includes a modulation factor securing unit 121A, a harmonic reduction unit 122A, a function synthesis unit 123, a switching phase calculation unit 124, and a switching pattern storage unit 125.
- the modulation factor securing unit 121A includes a pulse fundamental wave securing unit 201, a center pulse ratio determining unit 202, and a center pulse fundamental wave securing unit 203.
- the first function is a basic first function (function f) and an auxiliary function. A first function (function fc) is set.
- the pulse fundamental wave securing unit 201 is a function for securing the modulation rate, and relates the fundamental wave component of the output voltage half cycle of the inverter 4 and the modulation rate based on the modulation rate, the number of pulses, and the number of switching leg stages.
- a function f is generated as a basic first function.
- the function f is the same function as the function f in the first embodiment.
- the center pulse ratio determination unit 202 determines the ratio j to the modulation rate in the fundamental wave component (partial fundamental wave component) of the center pulse 211 in the output voltage half cycle based on the modulation rate, the number of pulses, and the number of switching leg stages.
- the center pulse fundamental wave securing unit 203 generates a function fc as an auxiliary first function that relates the fundamental wave component of the center pulse 211 and the modulation rate based on the ratio j determined by the center pulse ratio determining unit 202.
- the harmonic reduction unit 122A includes a pulse harmonic reduction unit 204, a central pulse harmonic level determination unit 205, and a central pulse harmonic reduction unit 206, and a basic second function (function Y) as a second function. And an auxiliary second function (function Yc) is set.
- the pulse harmonic reduction unit 204 is a function for reducing the harmonic component of the output waveform of the inverter 4, and is based on the number of harmonic components of the output voltage half cycle of the inverter 4 based on the number of pulses and the number of switching leg stages.
- a function Y is generated as a basic second function that is an added value of each determined harmonic component.
- the function Y is the same function as the function Y in the first embodiment.
- the central pulse harmonic level determination unit 205 determines a harmonic level threshold value i (amplitude threshold value of the harmonic component) in the harmonic component of the central pulse 211 in the output voltage half cycle based on the modulation factor, the number of pulses, and the number of switching leg stages. decide. Based on the threshold value i determined by the central pulse harmonic level determination unit 205, the central pulse harmonic reduction unit 206 adds the added value of each harmonic element determined by each harmonic component of the central pulse 211, and the harmonic level.
- a function Yc is generated as an auxiliary second function that relates the threshold value i.
- the function synthesis unit 123 sets an evaluation function X that is a third function including a function f and a function fc that are first functions, a function Y and a function Yc that are second functions, and one or more additional variables.
- the switching phase calculation unit 124 calculates a switching phase that secures the modulation rate by minimizing the evaluation function X with respect to the switching phase and the additional variable and reduces the added value of each harmonic component.
- the switching pattern storage unit 125 stores a switching pattern determined by the switching phase calculated by the switching phase calculation unit 124 for each modulation factor and each number of pulses.
- first function basic first function f and auxiliary first function fc
- second function basic second function Y and auxiliary second function Yc
- evaluation function X Five functions shown in Expression (21) to Expression (25) are defined.
- the functions f and fc defined by the above equations (21) and (22) are generated by the pulse fundamental wave securing unit 201 and the central pulse fundamental wave securing unit 203 in the modulation factor securing unit 121A.
- the pulse fundamental wave securing unit 201 displays all switching phases (th1a, th2a, th3a, th1b, th2b, th3b: hereinafter referred to as thi) in order to ensure the modulation factor m obtained by connecting both switching legs 8a and 8b in series. )
- a function f (thi) that defines each switching phase thi as a variable is defined as shown in Expression (21). Equation (21) is the same as Equation (5) representing the function f (thi) in the first embodiment.
- two modulation factors m1 and m2 that satisfy m1 ⁇ m2 are set as reference values, a region of modulation factor m that satisfies m ⁇ m1 is a low modulation factor region, and a modulation factor m that satisfies m1 ⁇ m ⁇ m2. Is the medium modulation rate region, and the region of the modulation rate m satisfying m2 ⁇ m is the high modulation rate region.
- the ratio j of the fundamental wave amplitude of the central pulse 211 to the modulation rate is set.
- the ratios j1, j2, and j3 may be changed according to the number of pulses and the number of stages of the switching leg.
- the fundamental wave amplitude of the central pulse 211 determined by the product of the switching phases th3a and th3b and the modulation factor m and the ratio j
- a function fc (th3a, th3b) with the switching phases th3a and th3b as variables is defined as shown in Expression (22).
- the function Y (thi) and the function Yc (th3a, th3b) defined by the above equations (23) and (24) are the pulse harmonic reduction unit 204 and the central pulse harmonic reduction in the harmonic reduction unit 122A. Generated by the unit 206.
- the pulse harmonic reduction unit 204 adds each switching phase thi and each harmonic component to each harmonic voltage component of the output waveform of the inverter 4 as an added value of each harmonic element.
- Expression (23) is the same as Expression (6) representing the function Y (thi) in the first embodiment. That is, in Equation (23), k represents the harmonic order to be reduced, and here, the fifth order,... is not.
- the definition and setting method of the weighting coefficient w (k) here are the same as those in the first embodiment.
- the central pulse harmonic level determination unit 205 determines the threshold of the harmonic level in the harmonic component of the central pulse 211 in the half cycle of the output voltage, that is, the threshold i of the harmonic amplitude as shown in FIG.
- two modulation factors m3 and m4 satisfying m3 ⁇ m4 are set as reference values, a region of the modulation factor m satisfying m ⁇ m3 is a low modulation factor region, and a modulation factor m satisfying m3 ⁇ m ⁇ m4. Is the medium modulation rate region, and the region of the modulation rate m satisfying m4 ⁇ m is the high modulation rate region.
- the threshold value i of the harmonic amplitude of the center pulse 211 with respect to a modulation factor is set.
- the harmonic level is defined by the square root of the square sum of the harmonic voltages of the respective orders of the central pulse 211.
- the harmonic level thresholds i1, i2, and i3 may be changed according to the number of pulses and the number of stages of the switching leg.
- a function Yc (th3a, th3b) with the switching phases th3a and th3b as variables is defined as shown in Expression (24).
- k represents the harmonic order to be reduced as in the equation (23), and here, the fifth order,...
- the switching phase at which the sum of squares of the fifth to thirteenth harmonic components in equation (24) is less than or equal to the square of the threshold value i of the harmonic level is The purpose is to get.
- the function synthesizer 123 corresponds to the degrees of freedom of the function f, the function fc, the function Y, and the function Yc (the number of switching phases thi as variables is equivalent to six variables here).
- an evaluation function X having additional degrees of freedom by adding additional variables. This evaluation function X secures the modulation factor with the output waveform of the inverter 4, reduces the sum of squares of each harmonic voltage component, and obtains the fundamental wave of the center pulse 211 by the product of the modulation factor m and the ratio j.
- the center pulse fundamental wave amplitude is secured, and the sum of squares of the respective harmonic voltages of the center pulse 211 is defined to be equal to or less than the determined threshold value (i 2 ).
- Yc (th3a, th3b) is a sum of values obtained by multiplying weighting variables ⁇ , ⁇ , ⁇ , respectively, and an evaluation function X (thi, ⁇ , ⁇ ) with each switching phase thi and weighting variables ⁇ , ⁇ , ⁇ as variables. , ⁇ ).
- the switching phase calculation unit 124 takes partial differentials of the nine variables ⁇ , ⁇ , ⁇ , th1a to th3b of the evaluation function X (thi, ⁇ , ⁇ , ⁇ ) and sets them to 0 or 0 or less.
- a nine-element simultaneous equation shown in equation (26) is created. Then, by solving this nine-element simultaneous equation using, for example, the Newton method, the required modulation factor m is ensured, the total value of many harmonic voltage components is minimized, and the center A switching pattern in which the ratio of the fundamental amplitude of the pulse 211 to the modulation factor m and the harmonic voltage components of many orders of the central pulse 211 are set appropriately based on the modulation factor can be obtained.
- the modulation factor securing unit 121A in the switching pattern determination unit 12B has the basic first function (function f) and the auxiliary first function as the first function. (Function fc) is set, and the harmonic reduction unit 122A sets the basic second function (function Y) and the auxiliary second function (function Yc) as the second function. Then, a switching pattern is determined using an evaluation function X obtained from these functions and additional variables. Thereby, in addition to the effects described in the first embodiment, the ratio of the fundamental wave amplitude of the central pulse 211 to the modulation factor m and the harmonic voltage components of many orders of the central pulse 211 are determined based on the modulation factor.
- a switching pattern that can be obtained can be obtained. Further, as a waveform of a partial section of the output voltage half cycle of the inverter 4, a center pulse 211 sandwiching the phases (1/2) ⁇ and (3/2) ⁇ is used. The center pulse 211 is a portion that greatly contributes to and influences the output voltage waveform, and a desired switching pattern can be effectively obtained.
- the modulation factor reference values m1 and m2 in the central pulse ratio determination unit 202 and the modulation factor reference values m3 and m4 in the central pulse harmonic level determination unit 205 may be the same or different. Good. Further, the number of reference values of each modulation rate used in the central pulse ratio determining unit 202 and the central pulse harmonic level determining unit 205 is not limited to two, and may be three or more.
- the number of harmonic orders k to be reduced is four as shown in the equation (24), but the same order type as the pulse harmonic reduction unit 204, that is, the fifth to 25th. The next eight may be used, or more types may be targeted for reduction.
- the center pulse 211 is used as the waveform of a partial section of the output voltage half cycle of the inverter 4, but this is not restrictive.
- the phase range of a partial section for setting the ratio of the fundamental wave amplitude to the modulation factor m may be set freely.
- FIG. 29 is a diagram showing an internal configuration of the switching pattern determination unit 12C according to the seventh embodiment. Other configurations are the same as those in the first embodiment.
- the switching pattern determination unit 12C determines the switching pattern as follows.
- each switching leg 8a, 8b The fundamental wave of the entire output waveform of each switching leg 8a, 8b is secured, and the amplitude difference between the fundamental waves of the central pulse train 212 of the switching leg 8a, 8b is reduced.
- each harmonic component of the entire output waveform of the five-level inverter 4 is reduced, and each harmonic component in the central pulse train 212 of each switching leg 8a, 8b is reduced.
- the switching pattern determination unit 12C includes a modulation factor securing unit 121B, a harmonic reduction unit 122B, a function synthesis unit 123, a switching phase calculation unit 124, and a switching pattern storage unit 125.
- the modulation factor securing unit 121B includes each leg pulse fundamental wave securing unit 221 and each leg center pulse fundamental wave amplitude difference securing unit 222.
- As a first function a basic first function for each switching leg 8a, 8b ( A function fa, a function fb) and a balance function (function fd) are set.
- the functions fa and fb are set in the same manner as in the fourth embodiment.
- Each leg pulse fundamental wave securing unit 221 is a function for securing the same modulation rate for each switching leg 8a, 8b, and based on the modulation rate, the number of pulses, and the number of switching leg stages, the output voltage half cycle of the inverter 4
- the function fa and the function fb are generated for each switching leg 8a and 8b as a basic first function that relates the fundamental wave component and the modulation factor.
- Each leg center pulse fundamental wave amplitude difference securing unit 222 determines the amplitude difference between the fundamental wave components of the center pulse train 212 of the two switching legs 8a and 8b in the half cycle of the output voltage based on the modulation rate, the number of pulses, and the number of switching leg stages.
- the function fd is generated as a balance function that relates the preset upper limit value.
- the harmonic reduction unit 122B includes a pulse harmonic reduction unit 223 and each leg center pulse harmonic reduction unit 224.
- the basic second function (function Y) and the switching legs 8a and 8b are provided.
- the auxiliary second function (function Yca, function Ycb) is set.
- the pulse harmonic reduction unit 223 is a function for reducing the harmonic component of the output waveform of the inverter 4, and based on the number of pulses and the number of switching leg stages, each harmonic component of the output voltage half cycle of the inverter 4
- a function Y is generated as a basic second function that is an added value of each determined harmonic component.
- the function Y is the same function as the function Y in the first embodiment.
- Each leg center pulse harmonic reduction unit 224 includes an addition value of each harmonic component determined by each harmonic component of the center pulse train 212 of each switching leg 8a, 8b and a harmonic set in advance according to the modulation rate.
- a function Yca and a function Ycb are generated for each switching leg 8a and 8b.
- the function synthesis unit 123 is an evaluation that is a third function including the function fa, the function fb, and the function fd that are the first function, the function Y and the function Yca that are the second function, the function Ycb, and one or more additional variables.
- Set function X The switching phase calculation unit 124 calculates a switching phase that secures the modulation rate by minimizing the evaluation function X with respect to the switching phase and the additional variable and reduces the added value of each harmonic component.
- the switching pattern storage unit 125 stores a switching pattern determined by the switching phase calculated by the switching phase calculation unit 124 for each modulation factor and each number of pulses.
- the first function basic first functions fa and fb and balance function fd
- the second function basic second function Y and auxiliary second functions Yca and Ycb
- the evaluation function X is shown below.
- the first function is defined by the three functions shown in the equations (27) to (29)
- the second function is defined by the three functions shown in the equations (30) to (32)
- the evaluation function is defined by the function shown in ().
- Each leg pulse fundamental wave securing unit 221 in the modulation rate securing unit 121B equally shares the output modulation rate m between the switching legs 8a and 8b in order to equalize the load on the switching legs 8a and 8b.
- a function fa and a function fb with each switching phase as a variable are defined as shown in equations (27) and (28). That is, the function fa is a function that defines the relationship between the switching phase (th1a, th2a, th3a, th4a, th5a) of the switching leg 8a and the modulation factor m, and uses the switching phase of the switching leg 8a as a variable.
- the function fb is a function that defines the relationship between the switching phase (th1b, th2b, th3b, th4b, th5b) of the switching leg 8b and the modulation factor m and uses the switching phase of the switching leg 8b as a variable.
- each leg center pulse fundamental wave amplitude difference securing unit 222 in the modulation factor securing unit 121B obtains an amplitude difference between fundamental wave components of the center pulse train 212 of the two switching legs 8a and 8b and a preset upper limit value difflim.
- a function fd to be related is defined as shown in Expression (29). That is, the function fd is the fundamental wave amplitude of the central pulse train 212a defined by the switching phase (th3a, th4a, th5a) in the switching leg 8a and the central pulse train 212b defined by the switching phase (th3b, th4b, th5b) in the switching leg 8b.
- the pulse harmonic reduction unit 223 in the harmonic reduction unit 122B reduces the harmonics by switching each phase of the output waveform of the inverter 4 (th1a to th5a, th1b to th5b: hereinafter referred to as thi) and each harmonic.
- thi each phase of the output waveform of the inverter 4
- Each switching that defines the relationship with the sum of squares of values obtained by multiplying each harmonic voltage component of the output waveform of the inverter 4 by each weighting coefficient w (k) (k k1 to kj) as an added value of the element
- a function Y (thi) having the phase thi as a variable is defined as shown in Expression (30).
- Expression (30) is set in the same manner as Expression (6) representing the function Y (thi) in the first embodiment, but here, the number of types of harmonic orders to be reduced is 10. That is, in Expression (30), k represents the harmonic order to be reduced, and here, the fifth order,...
- the definition and setting method of the weighting coefficient w (k) here are the same as those in the first embodiment.
- each leg center pulse harmonic reduction unit 224 in the harmonic reduction unit 122B includes, for each switching leg 8a, 8b, an added value of each harmonic element of the center pulse train 212a, 212b and a threshold of the harmonic level.
- functions Yca and Ycb having the switching phases of the respective switching legs 8a and 8b as variables are defined as shown in equations (31) and (32). That is, the function Yca is defined with the switching phase (th3a, th4a, th5a) of the switching leg 8a as a variable, and the function Ycb is defined with the switching phase (th3b, th4b, th5b) of the switching leg 8b as a variable.
- a threshold value i of the harmonic amplitude which is a harmonic level defined by the square root of the square sum of each harmonic voltage component, is set in advance for each modulation factor.
- k represents the harmonic order to be reduced as in Expression (30).
- the function synthesis unit 123 corresponds to the degrees of freedom of the function fa, the function fb, the function fd, the function Y, the function Yca, and the function Ycb (the number of switching phases thi as variables).
- the evaluation function X is defined by adding additional variables to 10 variables) to increase the degree of freedom. This evaluation function X is set so that the modulation factor is equally shared by the output waveforms of the switching legs 8a and 8b of the inverter 4 to secure the fundamental wave component, and the square sum of each harmonic voltage component is reduced. Is done.
- the fundamental wave amplitude is ensured so that the difference between the fundamental wave amplitudes of the central pulse trains 212a and 212b of the two switching legs 8a and 8b is equal to or less than the upper limit value, and the respective higher harmonics of the central pulse trains 212a and 212b.
- the sum of squares of the wave voltage is defined to be equal to or less than the determined threshold value (i 2 ).
- the switching phase calculation unit 124 takes partial differentials of 15 variables ⁇ 1, ⁇ 2, ⁇ , ⁇ , ⁇ , th1a to th5b of the evaluation function X (thi, ⁇ 1, ⁇ 2, ⁇ , ⁇ , ⁇ ), A 15-way simultaneous equation shown in Expression (34) is created by setting them to 0 or 0 or less. Then, a desired switching pattern can be obtained by solving the 15-way simultaneous equations using, for example, a Newton method. That is, each switching leg 8a, 8b can secure the required modulation factor m by an equal burden, and can minimize the total value of harmonic voltages components of many orders.
- a switching pattern can be obtained in which the difference between the fundamental wave amplitudes of the central pulse trains 212a and 212b of the two switching legs 8a and 8b can be reduced, and the higher-order harmonic voltage components of the central pulse trains 212a and 212b can be reduced.
- the modulation factor securing unit 121B in the switching pattern determining unit 12C has the basic first function for each switching leg 8a, 8b ( The function fa, the function fb) and the balance function (function fd) are set, and the harmonic reduction unit 122B uses the basic second function (function Y) and the auxiliary second for each switching leg 8a, 8b as the second function. Functions (function Yca, function Ycb) are set. Then, a switching pattern is determined using an evaluation function X obtained from these functions and additional variables.
- the burden on the switching legs 8a and 8b can be made uniform, and the difference between the fundamental wave amplitudes of the central pulse trains 212a and 212b of the two switching legs 8a and 8b can be reduced.
- each harmonic voltage component of each central pulse train 212a, 212b can be reduced.
- switching loss can be reduced and not only the life of the element can be lengthened, but also switching with reduced switching loss and motor loss due to harmonics can be realized.
- the exchange sequence becomes complicated as the number of stages of the switching legs increases. Since the cycle becomes longer, it is difficult to eliminate imbalance between switching legs.
- this embodiment since the harmonic loss of each switching leg is suppressed in advance and the switching pattern in which each loss imbalance is reduced is determined and used, this embodiment is effective even when the number of switching leg stages is large.
- the upper limit value difflim for the difference between the fundamental wave amplitudes of the central pulse trains 212a and 212b of the switching legs 8a and 8b may be set for each modulation factor.
- the upper limit value difflim may be set in advance in a stepwise manner for the modulation rate and determined.
- a threshold value i corresponding to the modulation factor may be provided in advance for the threshold value i of the harmonic amplitude that is the harmonic level.
- a central pulse harmonic level determination unit 205 similar to that of the sixth embodiment may be provided, and may be set stepwise according to the modulation rate as shown in FIG.
- Embodiment 8 FIG. Next, a power conversion device according to embodiment 8 of the present invention will be described.
- the overall configuration of the power conversion apparatus is the same as that shown in FIGS. 1 and 2 of the first embodiment. In this case, the operation of the pulse number determination unit 13 in the control unit 10 is different.
- the inverter 4 of the power converter 2 when the number of stages of the three level switching legs 8a and 8b connected in series increases, the voltage level that can be output from the inverter 4 increases.
- the number of pulses output from each switching leg 8a, 8b in the fundamental wave half cycle is increased, the number of times of switching is also increased by a quarter cycle (increase in the number of pulses ⁇ number of stages).
- the pulse number determination unit 13 determines the pulse number Pnum per fundamental wave half cycle in PWM control. This is to reduce the number of times of switching at high speed operation so that switching can follow even a large capacity inverter having a low switching speed.
- the pulse number determination unit 13 determines the number of pulses for each of the plurality of switching legs 8a and 8b in accordance with the output frequency command value Fc of the inverter 4 and the modulation rate, and combines the combination of the pulse numbers. Shall be output.
- FIG. 32 is a diagram for explaining the operation of the pulse number determination unit 13 in this embodiment, and shows an example of the pulse number determination condition.
- the combination of the number of pulses of the switching legs 8a and 8b depends on the output frequency command value Fc (horizontal axis) of the inverter 4 and the output voltage amplitude value Vp (vertical axis) corresponding to the modulation factor. It is determined.
- the reference values F1, F2, F3, and F4 of the frequency command value Fc and the reference value Vp1 of the voltage amplitude value Vp are set, and nine combinations of the number of pulses are determined depending on the combination of the conditions.
- the frequency command value Fc is based on which of the five regions, that is, Fc ⁇ F1, F1 ⁇ Fc ⁇ F2, F2 ⁇ Fc ⁇ F3, F3 ⁇ Fc ⁇ F4, and F4 ⁇ Fc.
- the basic pulse numbers are 9, 7, 5, 3, 1 in order.
- whether the number of pulses of each switching leg 8a, 8b is the same or different is determined depending on whether the voltage amplitude value Vp is greater than or less than Vp1.
- a combination of a basic pulse number and a pulse number that is two less than the basic pulse number is used.
- FIG. 33 is a diagram illustrating an output voltage waveform for a single phase of the five-level inverter 4 when the combination of the pulse numbers determined by the pulse number determination unit 13 is 5 pulses + 3 pulses.
- the number of pulses of the switching leg 8a is 3
- the number of pulses of the switching leg 8b is 5, the output voltage waveform for a single phase of the 5-level inverter 4, and the two switching legs 8a and 8b connected in series
- FIG. 33 is a diagram illustrating an output voltage waveform for a single phase of the five-level inverter 4 when the combination of the pulse numbers determined by the pulse number determination unit 13 is 5 pulses + 3 pulses.
- the number of pulses of the switching leg 8a is 3
- the number of pulses of the switching leg 8b is 5
- the output voltage waveform for a single phase of the 5-level inverter 4 is 5
- the modulation factor securing unit 121 functions as a first function that defines the relationship between the switching phase and the modulation factor for each of the switching legs 8a and 8b.
- fa th1a, th2a, th3a
- function fb th1b, th2b, th3b, th4b, th5b.
- the function fa and the function fb are set so that the modulation rate m to be output is equally divided between both the switching legs 8a and 8b.
- the harmonic reduction unit 122 reduces each harmonic of the output waveform of the inverter 4 as an addition value of each switching phase thi and each harmonic element in order to reduce harmonics.
- k represents the harmonic order to be reduced, and here, the fifth order,..., 31st order, which is a total of 10 types of orders, is limited to this. Absent.
- the function synthesizing unit 123 secures the modulation rate and reduces the above-mentioned square sum related to each harmonic voltage component, so that the first function fa, fb and the second function Y
- An evaluation function X is defined in which the number of degrees of freedom is increased by adding additional variables to the degree of freedom (the number of switching phases thi as a variable corresponds to eight variables in this case). Specifically, it is the sum of the function Y (thi) shown in Expression (37) and the values obtained by multiplying the functions fa and fb shown in Expression (35) and Expression (36) by weighting variables ⁇ 1 and ⁇ 2, respectively.
- the evaluation function X (thi, ⁇ 1, ⁇ 2) is defined with each switching phase thi and weighting variables ⁇ 1, ⁇ 2 as variables.
- the switching phase calculation unit 124 calculates partial differentials of the ten variables ⁇ 1, ⁇ 2, and th1a to th5b of the evaluation function X (thi, ⁇ 1, ⁇ 2), and sets all of them to 0 in the equation (39). Create the 10-element simultaneous equation shown. Then, the ten-way simultaneous equations are solved using, for example, a Newton method. As a result, the required modulation factor m is secured with a combination of different numbers of pulses, the load on the switching legs 8a and 8b becomes uniform, and the total value of the harmonic voltage components of many orders is minimized. A switching pattern can be obtained.
- the pulse number determination unit 13 determines the number of pulses for each of the plurality of switching legs 8a and 8b according to the output frequency command value Fc of the inverter 4 and the modulation rate, and performs pulse processing. A combination of numbers was output. For this reason, the combination of the number of pulses can be changed according to the modulation rate, and the variation in the number of switchings per unit output voltage within the same time is reduced. Can be reduced.
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Abstract
Description
そこで、少ないスイッチング回数を有効利用し、特定の低次の高調波を低減するタイミングでスイッチングを行う、低次高調波消去PWM制御方式がある(例えば、特許文献1、非特許文献1参照)。
そして、所望された変調率を満たすスイッチングパターンが複数存在する場合、その複数のスイッチングパターンの中から所望の次数の高調波成分を低減できるスイッチングパターンを選択することができる。
前記制御部は、前記直流電圧源の直流電圧と前記出力電圧指令値とに基づき前記インバータの変調率を演算する変調率演算器と、前記出力周波数指令値に基づき前記PWM制御における基本波半周期当たりのパルス数を決定するパルス数決定部と、前記変調率および前記パルス数に応じて前記スイッチング素子をオンオフ駆動するタイミングであるスイッチング位相を特定するスイッチングパターンを予め演算により求め前記変調率および前記パルス数毎に記憶するスイッチングパターン決定部と、前記変調率演算器からの前記変調率と前記パルス数決定部からの前記パルス数とに対応する前記スイッチングパターンを前記スイッチングパターン決定部から読み出し、当該スイッチングパターンに基づき前記スイッチング素子をオンオフ駆動するゲート信号を生成するゲート信号生成部とを備える。
前記スイッチングパターン決定部は、前記変調率を確保するための関数であって、前記インバータの出力波形の基本波成分と前記変調率とを関係づける、前記スイッチング位相を変数とする第1関数を生成する変調率確保部と、前記インバータの出力波形の高調波成分を低減するための関数であって、前記インバータの出力波形の各次高調波成分で決まる各次高調波要素の加算値である、前記スイッチング位相を変数とする第2関数を生成する高調波低減部と、前記第1関数と前記第2関数と1以上の追加変数とからなり、前記スイッチング位相および前記追加変数を変数とする第3関数を設定する関数合成部と、前記第3関数を前記スイッチング位相および前記追加変数について最小化することにより前記変調率を確保するとともに前記各次高調波要素の加算値を低減する前記スイッチング位相を算出するスイッチング位相算出部と、算出された前記スイッチング位相で特定される前記スイッチングパターンを前記各変調率および前記各パルス数毎に記憶するスイッチングパターン記憶部とを備えたものである。
図1は、この発明の実施の形態1における電力変換装置2の全体構成を示す回路図である。図1において、電力変換装置2は、インバータ4とインバータ4を制御する制御部10とを備え、U、V、W相の直流電圧源1a、1b、1cの直流電圧を可変電圧可変周波数の交流電圧に変換して負荷であるモータ3に出力する。また、図2はインバータ4の構成を示す回路図である。
変調率演算器11は、直流電圧源1a~1cの直流電圧Vdcとインバータ4の出力電圧指令値(相電圧振幅)Vpとに基づき、式(1)により変調率mを演算する。
大容量インバータのようなスイッチング速度の遅い素子を持つインバータ4では、出力周波数指令値Fcが高くなると半周期あたりのパルス数Pnumを段階的に少なくして、スイッチング回数を減らす必要がある。本実施の形態では、高速運転時はパルス数Pnumを1(半周期に1パルス)にする。
この演算は、要求される変調率mを実現し、かつ、高調波成分を低減するスイッチングパターンを求めるもので、この発明の要部を成し、当該スイッチングパターンおよびその演算の要領は後段で詳細に説明する。
図に示すように、インバータ4の各部の電圧、電流、素子温度等を検出するセンサ群(センサ18、19を含む)である検出部20からの情報に基づいて、プロセッサ301の演算処理により、インバータ4のスイッチング素子6をオンオフ駆動するゲート信号17が生成される。
図は、1周期(2π)にわたるパルス電圧波形を示し、5レベルインバータ4の単相出力電圧Vsと、スイッチングレグ8aの出力電圧VLaと、スイッチングレグ8bの出力電圧VLbとを示す。なお、スイッチングレグは省略形でレグと記載した。
図に示すように、2つのスイッチングレグ8a、8bの出力電圧VLa、VLbを加算することで、総パルス数=Pnum(3)×レグ直列段数(2)=6で動作する、5レベルインバータ4の単相出力電圧Vsが得られる。
即ち、スイッチングパターンは、これら6個のスイッチング位相th1a、th2a、th3a、th1b、th2b、th3bを特定するもので、このスイッチングパターンによりインバータ4の出力電圧波形が特定される訳である。
なお、上記特許文献2では、特に、制御の構成を示す図面に基づく説明はされていないが、ここでは、本願発明との対比を明確にするため、敢えて、この実施の形態1におけるスイッチングパターン決定部12に相当する制御構成を想定した比較例とする。また、インバータの構成は、この実施の形態1で用いる5レベルインバータ4と同様とする。
そして、式(2)の第1、第2段目の式では、変調率確保手段101によって、2つのスイッチングレグ8a、8bで出力する電圧振幅の配分が均等となるようスイッチングレグの段数毎に変調率(基本波振幅)の配分を設定したため、消去できる高調波次数の種別数は6-2=4となる。
スイッチング位相算出手段104は、変調率確保手段101が設定した、式(2)の第1、第2段目の式、および高調波消去手段103が設定した、式(2)の第3~第6段目の式とからなる、6元の連立方程式を解くことで、スイッチングパターンを特定する6個の変数、即ち、スイッチング位相(th1a~th3b)を算出する。
但し、図7(A)にあるように、変調率m1を中心とする領域mareaにおいて、一部の、同じスイッチング素子で互いに隣り合うスイッチング位相th1a、th2aの位相差が、主としてスイッチング速度性能の観点からスイッチング素子で許容される下限位相差thlim未満となっている。
図8において、スイッチングパターン決定部12は、変調率確保部121と、高調波低減部122と、関数合成部123と、スイッチング位相算出部124と、スイッチングパターン記憶部125とから構成される。なお、上述したように、スイッチングパターン決定部12はプロセッサ301にて実現されるものであるが、スイッチングパターン決定部12内のスイッチングパターン記憶部125についてはスイッチングパターン記憶装置303にて実現される。
式(6)において、kは低減対象の高調波次数を表し、ここでは、5次、・・・、25次の、合計8個の種別の次数を対象としているが、これらに限られることはない。なお、重み付け係数w(k)については更に後述する。
具体的には、式(6)に示す関数Y(thi)と、式(5)に示す関数f(thi)に、追加変数として重み付け変数αを乗算した値との和である、各スイッチング位相thiおよび重み付け変数αを変数とする評価関数X(thi、α)を定義している。
なお、評価関数Xは、第2関数Yにもさらなる追加変数を乗算した形にしてもよい。
図10は、パルス数Pnum=1の場合における、5レベルインバータ4の単相分の出力電圧波形と、直列接続された2つのスイッチングレグ8a、8bの出力電圧波形との関係を示したものである。
図は、1周期(2π)にわたるパルス電圧波形を示し、5レベルインバータ4の単相出力電圧Vsと、スイッチングレグ8aの出力電圧VLaと、スイッチングレグ8bの出力電圧VLbとを示す。図に示すように、2つのスイッチングレグ8a、8bの出力電圧VLa、VLbを加算することで、総パルス数=Pnum(1)×レグ直列段数(2)=2で動作する、5レベルインバータ4の単相出力電圧Vsが得られる。
即ち、スイッチングパターンは、これら2個のスイッチング位相th1a、th1bを特定するもので、このスイッチングパターンによりインバータ4の出力電圧波形が特定される。
高調波低減部122は、式(10)により、各スイッチング位相thiとインバータ4の出力波形の各次高調波電圧成分に各次重み付け係数w(k)を乗算した値の二乗和との関係を規定した、各スイッチング位相thiを変数とする第2関数Y(thi)を定義する。
ここでは、k=5、7、11、13次の4個の種別の次数を低減対象としているが、これらに限られることはない。
変調率確保部121は、変調率を確保するための関数であってインバータ4の出力波形の基本波成分と変調率とを関係づける、スイッチング位相thiを変数とする第1関数f(thi)を設定し、高調波低減部122は、インバータ4の出力波形の高調波成分を低減するための関数であってインバータ4の出力波形の各次高調波成分で決まる各次高調波要素の加算値である、スイッチング位相thiを変数とする第2関数Y(thi)を設定する。そして、関数合成部123は、第1関数f(thi)と第2関数Y(thi)と追加変数αとからなり、スイッチング位相thiおよび追加変数αを変数とする第3関数としての評価関数X(thi、α)=Y(thi)+α×f(thi)を設定する。更に、評価関数X(thi、α)をスイッチング位相thiおよび追加変数αについて偏微分を取りそれらをすべて0と置く連立方程式を解き評価関数X(thi、α)を最小化する。 これにより、変調率を確保するとともに各次高調波要素の加算値を低減するスイッチング位相thiをスイッチング位相算出部124にて算出でき、算出されたスイッチング位相thiで特定されるスイッチングパターンを各変調率および各パルス数毎にスイッチングパターン記憶部125に記憶する。このため、パルス数によって低減したい高調波の次数種別の数が直接制限されず、従って、比較的少ないパルス数であっても、出力電圧における、次数の種別数が総パルス数以上の高調波電圧成分または高調波電流成分をも低減することが出来る。
次に、この発明の実施の形態2における電力変換装置について説明する。電力変換装置2の全体構成は、先の実施の形態1の図1、図2で示したものと同様であるが、この場合、スイッチングパターン決定部の内部構成が異なる。
図13は、この実施の形態2によるスイッチングパターン決定部12Aの内部構成を示す図である。
スイッチング位相差限定部126は、スイッチング位相差の下限値(thlim)を設定するため、新たに、隣り合うスイッチング位相th1aとth2aとの位相差を規定する関数Pを設定する。
具体的には、この関数P(th1a、th2a)は、式(13)で定義する。
そして、領域mareaの変調率m1に関しては、評価関数Xの合計8個の変数α、β、th1a~th3bの偏微分を取り、それらを0または0以上と置く、式(15)に示す8元連立方程式を設定する。
従って、スイッチングパターン決定部12Aは、領域marea以外の変調率であるときは、上記実施の形態1と同様に、先の式(8)で求めたスイッチングパターンを記憶し、領域mareaの変調率に関しては、先の式(8)で求めたスイッチングパターンと置き換えて式(15)で求めたスイッチングパターンを記憶する。
次に、この発明の実施の形態3における電力変換装置について説明する。電力変換装置2の全体構成は、先の実施の形態1の図1、図2で示したものと同様である。この場合、スイッチングパターン決定部12内の変調率確保部121で設定する第1関数が上記実施の形態1と異なる。その他の構成は、上記実施の形態1と同様である。
モータ3に流れる電流は、電圧をインピーダンスで除した値となるが、そのインピーダンスZは、ほぼモータ3のインダクタンスLによって決定される。即ち、Z≒2πfLであり、電流は、周波数fに反比例する。
この際、各次数における電流高調波の二乗和をインバータ4およびインバータ4に接続されたモータの高調波損失総和が低減されるように、次数により重み付け係数w(k)を変更して合計した第2関数Y1(thi)を設定することで、インバータ4およびインバータ4に接続されたモータ3の高調波損失総和を低減することができる。
次に、この発明の実施の形態4における電力変換装置について説明する。電力変換装置2の全体構成は、先の実施の形態1の図1、図2で示したものと同様である。この場合、ゲート信号生成部の内部構成が上記実施の形態1と異なる。
図14は、この実施の形態4によるゲート信号生成部16Aの内部構成を示す図である。その他の構成は、上記実施の形態1と同様である。
ゲート信号生成部16Aは、上記実施の形態1と同様に、変調率演算器11からの変調率mとパルス数決定部13からのパルス数Pnumとに対応するスイッチングパターンをスイッチングパターン決定部12から読み出し、当該スイッチングパターンに基づきスイッチング素子6をオンオフ駆動するゲート信号17を生成するものである。
スイッチングパターン入れ替え部161は、2つのスイッチングレグ8aと8bとの負担が均一化するよう、出力電圧位相th、負荷電流や素子電流、更には素子温度に基づきスイッチングレグ8aと8bとのスイッチングパターンを所定の周期で入れ替える。ゲート信号発生部162は、スイッチングパターン入れ替え部161により入れ替えたスイッチングパターンに基づきゲート信号17を生成する。
まず、電流センサ19により負荷電流を検出し、負荷電流の実効値Rmsを計算する(ST1)。
次に、負荷電流実効値Rmsとスイッチング頻度の判定閾値Caとを比較して負荷電流によるスイッチング頻度判定を行う(ST2)。
波形71a、71bは単相の負荷電流を示し、波形71arは負荷電流(波形71a)の電流実効値(Rms)、波形71brは負荷電流(波形71b)の電流実効値(Rms)を示し、波形71は、スイッチング頻度の判定閾値Caを相電流に変換したものを示す。
ステップST2において、検出した負荷電流が、波形71b、71brに示す状態、即ち、負荷電流の実効値Rmsが判定閾値Ca以下の場合、スイッチングパターンの入れ替え周期NNを4(インバータ運転周波数における4周期)とする。これは、スイッチングパターンの入れ替え周期NNを大きくして入れ替え頻度を低くするものである(ST3)。
次に、スイッチングレグ8a、8b毎のスイッチング素子の平均電流IeとスイッチングレグのON時間を乗じた値を、設計で予め定めた判定閾値Cbと比較して(ST5)、判定閾値Cb以下の場合は、スイッチングパターンの入れ替え周期NNを2に設定する(ST6)。
次に、スイッチングレグ8a、8b毎のスイッチング素子の平均温度THeを、設計で予め定めた判定閾値Ccと比較して(ST8)、判定閾値Cc以下の場合は、ステップST6に進み、スイッチングパターンの入れ替え周期NNを2に設定する。
ステップST8において、スイッチングレグ8a、8b毎のスイッチング素子の平均温度THeが判定閾値Ccより高い場合、スイッチングパターンの入れ替え周期NNを1に設定する(ST9)。
図17に示すように、運転周波数の周期N=1、2の間は、スイッチングレグ8aは、自らのスイッチングパターンであるレグ8a用パターン(th1a)を用いてスイッチングを行う。そして、周期N=3、4の間は、スイッチングレグ8aは、スイッチングレグ8b用のスイッチングパターンであるレグ8b用パターン(th1b)を用いてスイッチングを行う。
スイッチングレグ8bも、同様にして、2周期毎に自らのレグ8b用パターンとレグ8a用パターンとを交互に用いてスイッチングを行う。スイッチングパターン入れ替えの位相はそれぞれ各相の0°とする。
周期N=1では、スイッチングレグ8aは、0~(1/2)πとπ~(3/2)πの間は、レグ8b用スイッチングパターン(th1b)を用いてスイッチングを行い、(1/2)π~πと(3/2)π~2πの間は、自らのレグ8a用スイッチングパターン(th1a)を用いてスイッチングを行う。
スイッチングレグ8bは、スイッチングレグ8aが使わない方のスイッチングパターンを用いてスイッチングを行う。
図20、図21は、この発明の実施の形態5における電力変換装置の全体構成を示す回路図である。特に、図20では主回路であるインバータ4の構成を詳細に示し、図21では制御部10の構成を詳細に示した。この実施の形態5では、直流電圧源1の電圧を2分して各スイッチングレグ8a、8bに直流電圧を供給する正極側コンデンサ5aと負極側コンデンサ5bとの電圧を均等化してインバータ4としての出力電圧の正極側と負極側との差をなくす方策を採用している。その他の構成および動作は、上記実施の形態1の場合と同様であり、また、高調波低減に係る動作も同様である。
以下、上記方策に係る構成および動作を中心に説明する。
その場合、この補正処理を簡単にするため、補正するスイッチング位相を、パルス波形が変化しない、π/2、(3/2)πに最も近い中央パルスの位相で、かつ、スイッチングをオンする位相のみ、もしくは、スイッチングをオフする位相のみに限定してもよい。
図24は、この発明の実施の形態6における電力変換装置の全体構成を示す回路図である。電力変換装置2の全体構成は、上記実施の形態1で示したものと同様であるが、この場合、制御部10におけるスイッチングパターン決定部12Bの内部構成が異なる。その他の構成は、上記実施の形態1と同様である。
図25は、上記実施の形態1の図5で示したものと同様に、パルス数Pnum=3の場合における、5レベルインバータ4の単相分の出力電圧波形と、直列接続された2つのスイッチングレグ8a、8bの出力電圧波形との関係を示したものである。この実施の形態6によるスイッチングパターンの決定について、図25を用いて、以下に簡単に説明する。
そして、この実施の形態では、出力波形全体の基本波振幅(=変調率)に占める中央パルス211の基本波振幅の比率jを決定し、さらに中央パルス211における高調波レベルの閾値iを設定して、スイッチングパターンを決定する。即ち、出力波形全体と中央パルス211との双方について、所望の基本波を確保すると共にそれぞれの各次高調波成分を低減する。
図に示すように、スイッチングパターン決定部12Bは、変調率確保部121Aと、高調波低減部122Aと、関数合成部123と、スイッチング位相算出部124と、スイッチングパターン記憶部125とから構成される。
変調率確保部121Aは、パルス基本波確保部201と、中央パルス比率決定部202と、中央パルス基本波確保部203とから構成され、第1関数として、基本第1関数(関数f)および補助第1関数(関数fc)を設定する。
中央パルス比率決定部202は、変調率、パルス数、スイッチングレグ段数に基づき、出力電圧半周期における中央パルス211の基本波成分(部分基本波成分)における変調率に対する比率jを決定する。中央パルス基本波確保部203は、中央パルス比率決定部202により決定した比率jに基づいて、中央パルス211の基本波成分と変調率とを関係づける補助第1関数としての関数fcを生成する。
パルス高調波低減部204は、インバータ4の出力波形の高調波成分を低減するための関数であって、パルス数およびスイッチングレグ段数に基づき、インバータ4の出力電圧半周期の各次高調波成分で決まる各次高調波要素の加算値である基本第2関数として関数Yを生成する。なお、この関数Yは上記実施の形態1における関数Yと同じ関数である。
中央パルス高調波レベル決定部205は、変調率、パルス数、スイッチングレグ段数に基づき、出力電圧半周期における中央パルス211の高調波成分における高調波レベルの閾値i(高調波成分の振幅閾値)を決定する。中央パルス高調波低減部206は、中央パルス高調波レベル決定部205により決定した閾値iに基づいて、中央パルス211の各次高調波成分で決まる各次高調波要素の加算値と、高調波レベルの閾値iとを関係づける補助第2関数としての関数Ycを生成する。
パルス基本波確保部201は、両スイッチングレグ8a、8bを直列にして得られる変調率mを確保するため、全スイッチング位相(th1a、th2a、th3a、th1b、th2b、th3b:以下、thiと表示する)と当該変調率mとの関係を規定した、各スイッチング位相thiを変数とする関数f(thi)を、式(21)に示すように定義する。なお、式(21)は、上記実施の形態1における関数f(thi)を表す式(5)と同一である。
図27に示すように、低変調率ほど出力波形全体の基本波振幅(=変調率)に占める中央パルスの基本波振幅の比率jが高くなるように設定している。これは、一般に高変調率の時は高負荷、低変調率の時は低負荷であるため、その条件のもとに設定したためである。即ち、低変調率では変調率の変動で出力電圧波形が変わり難く、制御が安定するように中央パルス211の基本波振幅を高くし、高変調率では負荷電流が中央パルス付近で高くなるため、損失を低減するために中央パルス211の基本波振幅を低くした。この比率j1、j2、j3はパルス数やスイッチングレグの段数によって変えてよい。
パルス高調波低減部204は、高調波を低減するため、各スイッチング位相thiと、各高調波要素の加算値として、インバータ4の出力波形の各次高調波電圧成分に各次重み付け係数w(k)(k=k1~kj)を乗算した値の二乗和との関係を規定した、各スイッチング位相thiを変数とする関数Y(thi)を、式(23)に示すように定義する。なお、式(23)は、上記実施の形態1における関数Y(thi)を表す式(6)と同一である。即ち、式(23)において、kは低減対象の高調波次数を表し、ここでは、5次、・・・・25次の、合計8個の種別の次数を対象としているが、これに限るものではない。ここでの重み付け係数w(k)の定義と設定方法は実施の形態1と同様である。
式(24)において、kは式(23)と同様に低減対象の高調波次数を表し、ここでは、5次、・・・・13次の、合計4個の種別の次数を対象としている。そして、後述する式(25)、式(26)において、式(24)での5次~13次の高調波成分の二乗和が高調波レベルの閾値iの二乗の値以下となるスイッチング位相を得ることを目的としている。
具体的には、式(23)に示す関数Y(thi)と、式(21)、式(22)、式(24)に示す、関数f(thi)、関数fc(th3a,th3b)、関数Yc(th3a,th3b)にそれぞれ重み付け変数α、β、γを乗算した値との和である、各スイッチング位相thiおよび重み付け変数α、β、γを変数とする評価関数X(thi、α、β、γ)を定義している。
また、インバータ4の出力電圧半周期の一部区間の波形として、位相(1/2)π、(3/2)πを挟む中央パルス211を用いた。中央パルス211は、出力電圧波形への貢献および影響が大きい部分であり、所望のスイッチングパターンが効果的に得られる。
次に、この発明の実施の形態7における電力変換装置について説明する。この実施の形態7では、上記実施の形態6と同様に、中央パルスに着目してスイッチングパターンを決定するものであり、複数のスイッチングレグの制御をバランスさせるものである。
図29は、この実施の形態7によるスイッチングパターン決定部12Cの内部構成を示す図である。その他の構成は上記実施の形態1と同様である。
また、図30は、変調率m、パルス数Pnum=5の場合における、1周期(2π)にわたる、出力電圧波形の例であり、5レベルインバータ4の単相分の出力電圧波形と、直列接続された2つのスイッチングレグ8a、8bの出力電圧波形との関係を示したものである。
この実施の形態では、スイッチングパターン決定部12Cが、以下のようにスイッチングパターンを決定する。各スイッチングレグ8a、8bの出力波形全体の基本波を確保すると共に、スイッチングレグ8a、8bの中央パルス列212の基本波の振幅差を低減する。同時に、5レベルインバータ4の出力波形全体の各次高調波成分を低減し、かつ各スイッチングレグ8a、8bの中央パルス列212における各次高調波成分を低減する。
変調率確保部121Bは、各レグパルス基本波確保部221と、各レグ中央パルス基本波振幅差確保部222とから構成され、第1関数として、各スイッチングレグ8a、8b毎の基本第1関数(関数fa、関数fb)とバランス関数(関数fd)とを設定する。なお、関数fa、関数fbは上記実施の形態4と同様に設定されるものである。
各レグ中央パルス基本波振幅差確保部222は、変調率、パルス数、スイッチングレグ段数に基づき、出力電圧半周期における、2つのスイッチングレグ8a、8bの中央パルス列212の基本波成分の振幅差と、予め設定した上限値とを関係づけるバランス関数として関数fdを生成する。
パルス高調波低減部223は、インバータ4の出力波形の高調波成分を低減するための関数であって、パルス数およびスイッチングレグ段数に基づき、インバータ4の出力電圧半周期の各次高調波成分で決まる各次高調波要素の加算値である基本第2関数として関数Yを生成する。なお、この関数Yは上記実施の形態1における関数Yと同じ関数である。
各レグ中央パルス高調波低減部224は、各スイッチングレグ8a、8bの中央パルス列212の各次高調波成分で決まる各次高調波要素の加算値と、変調率に応じて予め設定された高調波レベルの閾値iとを関係づける補助第2関数として、各スイッチングレグ8a、8b毎に関数Yca、関数Ycbを生成する。
なお、式(30)は、上記実施の形態1における関数Y(thi)を表す式(6)と同様に設定されるが、ここでは低減対象の高調波次数の種別数を10個としている。即ち、式(30)において、kは低減対象の高調波次数を表し、ここでは、5次、・・・・31次の、合計10個の種別の次数を対象としている。ここでの重み付け係数w(k)の定義と設定方法は実施の形態1と同様である。
式(31)、式(32)において、kは式(30)と同様に低減対象の高調波次数を表し、ここでは、5次、・・・・13次の、合計4個の種別の次数を対象としている。
次に、この発明の実施の形態8における電力変換装置について説明する。電力変換装置の全体構成は、上記実施の形態1の図1、図2で示したものと同様である。この場合、制御部10内のパルス数決定部13の動作が異なる。
ところで、電力変換装置2のインバータ4において、直列に接続される3レベルスイッチングレグ8a、8bの段数が増えると、インバータ4から出力できる電圧レベルが増える。基本波半周期での各スイッチングレグ8a、8bから出力されるパルス数を増やすと、スイッチング回数も1/4周期で(パルス数増加分×段数)分増える。例えば、基本波半周期で各スイッチングレグ8a、8bが出力する3レベル電圧のパルス数Pnumを3パルスから5パルス、あるいは5パルスから3パルスに変えると、1/4周期のインバータ4でのスイッチング回数はパルス増分×2段=4回増減する。つまり、パルス数の増減によりスイッチング回数の増減分はレグ段数に比例して増える。
この実施の形態8では、パルス数決定部13は、インバータ4の出力周波数指令値Fcと変調率とに応じて、複数のスイッチングレグ8a、8b毎にパルス数を決定してパルス数の組み合わせを出力するものとする。
図32に示すように、インバータ4の出力周波数指令値Fc(横軸)と、変調率に相当する出力電圧振幅値Vp(縦軸)に応じて、スイッチングレグ8a、8bのパルス数の組み合わせが決定される。この場合、周波数指令値Fcの基準値F1、F2、F3、F4と、電圧振幅値Vpの基準値Vp1を設定し、その条件の組み合わせにより、9通りのパルス数の組み合わせが決定される。
そして、上記5つの領域のそれぞれにおいて、電圧振幅値Vpが、Vp1以上か未満かにより、各スイッチングレグ8a、8bのパルス数が同じか異なるかが決定される。異なるパルス数の組み合わせとなる場合は、基本のパルス数と、基本のパルス数より2個少ないパルス数との組み合わせとなる。
図33は、パルス数決定部13で決定されるパルス数の組み合わせが、5パルス+3パルスである場合の、5レベルインバータ4の単相分の出力電圧波形を示す図である。この場合、スイッチングレグ8aのパルス数が3で、スイッチングレグ8bのパルス数が5であり、5レベルインバータ4の単相分の出力電圧波形と、直列接続された2つのスイッチングレグ8a、8bの出力電圧波形との関係が図33に示されている。
式(37)において、kは低減対象の高調波次数を表し、ここでは、5次、・・・、31次の、合計10個の種別の次数を対象としているが、これに限られることはない。
具体的には、式(37)に示す関数Y(thi)と、式(35)、式(36)に示す関数fa、fbに、それぞれ重み付け変数α1、α2を乗算した値との和である、各スイッチング位相thiおよび重み付け変数α1、α2を変数とする評価関数X(thi、α1、α2)を定義している。
Claims (18)
- スイッチング素子を備え直流電圧源の直流電圧を入力し可変電圧可変周波数の交流電圧に変換して負荷に出力するインバータと、出力電圧指令値と出力周波数指令値とに基づき前記スイッチング素子のオンオフ駆動をPWM制御する制御部とを備えた電力変換装置において、
前記制御部は、
前記直流電圧源の直流電圧と前記出力電圧指令値とに基づき前記インバータの変調率を演算する変調率演算器と、
前記出力周波数指令値に基づき前記PWM制御における基本波半周期当たりのパルス数を決定するパルス数決定部と、
前記変調率および前記パルス数に応じて前記スイッチング素子をオンオフ駆動するタイミングであるスイッチング位相を特定するスイッチングパターンを予め演算により求め前記変調率および前記パルス数毎に記憶するスイッチングパターン決定部と、
前記変調率演算器からの前記変調率と前記パルス数決定部からの前記パルス数とに対応する前記スイッチングパターンを前記スイッチングパターン決定部から読み出し、当該スイッチングパターンに基づき前記スイッチング素子をオンオフ駆動するゲート信号を生成するゲート信号生成部とを備え、
前記スイッチングパターン決定部は、
前記変調率を確保するための関数であって、前記インバータの出力波形の基本波成分と前記変調率とを関係づける、前記スイッチング位相を変数とする第1関数を生成する変調率確保部と、
前記インバータの出力波形の高調波成分を低減するための関数であって、前記インバータの出力波形の各次高調波成分で決まる各次高調波要素の加算値である、前記スイッチング位相を変数とする第2関数を生成する高調波低減部と、
前記第1関数と前記第2関数と1以上の追加変数とからなり、前記スイッチング位相および前記追加変数を変数とする第3関数を設定する関数合成部と、
前記第3関数を前記スイッチング位相および前記追加変数について最小化することにより前記変調率を確保するとともに前記各次高調波要素の加算値を低減する前記スイッチング位相を算出するスイッチング位相算出部と、
算出された前記スイッチング位相で特定される前記スイッチングパターンを前記各変調率および前記各パルス数毎に記憶するスイッチングパターン記憶部とを備えた、
電力変換装置。 - 前記各次高調波要素は、各次高調波電圧成分または各次高調波電流成分であり、該成分の各次2乗値の加算値を前記第2関数とした、
請求項1記載の電力変換装置。 - 前記各次高調波要素は、各次高調波電圧成分と各次高調波電流成分との乗算値であり、該乗算値の各次加算値を前記第2関数とした、
請求項1記載の電力変換装置。 - 前記PWM制御における基本波周波数を基準とする前記各次高調波要素の次数は、自然数nを用いると6n±1次である、
請求項1から請求項3のいずれか1項に記載の電力変換装置。 - 前記インバータを、各相毎に2レベルまたは3レベルのスイッチングレグを2以上直列に接続して前記変調率の電圧を出力する構成とした、
請求項1から請求項4のいずれか1項に記載の電力変換装置。 - 前記変調率確保部は、前記第1関数として、前記インバータの出力電圧半周期の基本波成分と前記変調率とを関係づける基本第1関数と、前記インバータの出力電圧半周期内の一部区間における部分基本波成分と前記変調率とを関係づける補助第1関数とを生成する、
請求項1から請求項5のいずれか1項に記載の電力変換装置。 - 前記高調波低減部は、前記第2関数として、前記インバータの出力電圧半周期における前記各次高調波要素の加算値である基本第2関数と、前記インバータの出力電圧半周期内の一部区間における前記各次高調波要素の加算値と高調波レベルの閾値とを関係づける補助第2関数とを生成する、
請求項1から請求項6のいずれか1項に記載の電力変換装置。 - 前記変調率確保部は、前記第1関数として、前記複数のスイッチングレグ毎に出力電圧半周期の基本波成分と前記変調率とを関係づける複数の基本第1関数と、前記複数のスイッチングレグにおける出力電圧半周期内の一部区間における部分基本波成分の振幅差と該振幅差の上限値とを関係づけるバランス関数とを生成する、
請求項5記載の電力変換装置。 - 前記高調波低減部は、前記第2関数として、前記インバータの出力電圧半周期における前記各次高調波要素の加算値である基本第2関数と、前記複数のスイッチングレグ毎に出力電圧半周期内の一部区間における前記各次高調波要素の加算値と高調波レベルの閾値とを関係づける複数の補助第2関数とを生成する、
請求項5または請求項8に記載の電力変換装置。 - 前記インバータの出力電圧半周期内の前記一部区間は、該出力電圧半周期内の中央区間であって、少なくとも1つの中央パルスを含む区間である、
請求項6から請求項9のいずれか1項に記載の電力変換装置。 - 前記パルス数決定部は、前記複数のスイッチングレグ毎にパルス数を決定して該パルス数の組み合わせを出力する、
請求項5、請求項8、請求項9のいずれか1項に記載の電力変換装置。 - 前記ゲート信号生成部は、前記直列に接続された各スイッチングレグの負担が均等化するように、前記各スイッチングレグのスイッチングパターンを予め定められた周期で入れ替えるスイッチングパターン入れ替え部を備えた、
請求項5、請求項8、請求項9、請求項11のいずれか1項に記載の電力変換装置。 - 前記スイッチングパターン入れ替え部は、前記負荷に出力される電流に応じて、前記スイッチングパターンを入れ替える前記周期を切り替える、
請求項12記載の電力変換装置。 - 前記スイッチング素子に流れる電流を検出する素子電流検出部を備え、前記スイッチングパターン入れ替え部は、前記素子電流検出部の出力に応じて前記スイッチングパターンを入れ替える前記周期を切り替える、
請求項12または請求項13に記載の電力変換装置。 - 前記スイッチング素子の温度を検出する素子温度検出部を備え、前記スイッチングパターン入れ替え部は、前記素子温度検出部の出力に応じて前記スイッチングパターンを入れ替える前記周期を切り替える、
請求項12から請求項14のいずれか1項に記載の電力変換装置。 - 前記直流電圧源が正極側コンデンサと負極側コンデンサとの直列接続体に接続され、
前記制御部は、前記正極側コンデンサの電圧に基づき前記交流電圧の正極側成分を出力し、前記負極側コンデンサの電圧に基づき前記交流電圧の負極側成分を出力するように前記インバータをPWM制御し、
前記ゲート信号生成部は、前記正極側コンデンサの電圧と前記負極側コンデンサの電圧とが均等化するように、前記スイッチングパターンで特定された前記スイッチング位相を補正するパルス補正部を備えた、
請求項1から請求項15のいずれか1項に記載の電力変換装置。 - 前記正極側コンデンサの電圧と前記負極側コンデンサの電圧との差を中性点電圧として検出する中性点電圧検出部を備え、前記パルス補正部は、前記中性点電圧検出部の出力に基づき前記スイッチング位相を補正する、
請求項16記載の電力変換装置。 - 前記正極側コンデンサと前記負極側コンデンサとの接続点に流入する電流を中性点電流として検出する中性点電流検出部を備え、前記パルス補正部は、前記中性点電流検出部の出力に基づき前記スイッチング位相を補正する、
請求項16記載の電力変換装置。
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