WO2016091222A1 - 玻璃基板上埋入无源元件的圆片级制造方法 - Google Patents

玻璃基板上埋入无源元件的圆片级制造方法 Download PDF

Info

Publication number
WO2016091222A1
WO2016091222A1 PCT/CN2015/098677 CN2015098677W WO2016091222A1 WO 2016091222 A1 WO2016091222 A1 WO 2016091222A1 CN 2015098677 W CN2015098677 W CN 2015098677W WO 2016091222 A1 WO2016091222 A1 WO 2016091222A1
Authority
WO
WIPO (PCT)
Prior art keywords
glass substrate
wafer
glass
passive
doped silicon
Prior art date
Application number
PCT/CN2015/098677
Other languages
English (en)
French (fr)
Inventor
尚金堂
马梦颖
Original Assignee
东南大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 东南大学 filed Critical 东南大学
Publication of WO2016091222A1 publication Critical patent/WO2016091222A1/zh
Priority to US15/619,525 priority Critical patent/US10321577B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0029—Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/301—Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/003—Coplanar lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021—Constructional details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

Definitions

  • the invention relates to the technical field of microelectronic mechanical system packaging, and in particular to a wafer level manufacturing method for embedding passive components on a glass substrate.
  • the manufacturing process of the single-element in the conventional RF MEMS system uses a surface processing technology.
  • the RF passive component prepared by the process has a short longitudinal extension, a large DC resistance, and a small electrical path, and belongs to a 2D planar device, usually adopting an adapter plate.
  • the 3D interconnection is realized by layer stacking, and the 3D RF MEMS system prepared by the process has the disadvantages of complicated and complicated process, high cost, and limited performance of the device due to 2D planar characteristics.
  • the new 3D RF MEMS uses a silicon substrate embedded with passive components (resistors, capacitors, inductors, etc.) for 3D interconnection.
  • the process is based on the first post-perforation electroplating process of conductive through silicon vias (TSV).
  • TSV conductive through silicon vias
  • the silicon substrate is dry etched to form a void embedded in the RF passive component, and then the dielectric dielectric is insulated by chemical deposition or silicon high temperature oxidation process.
  • the layer finally fills the voids in the silicon substrate by a process of chemically depositing the seed layer and plating the conductive metal to prepare a passive component embedded in the silicon substrate.
  • the silicon substrate has electrically conductive properties, and the denseness and thickness of the dielectric barrier layer are limited by the nanoscale size, causing the electrical isolation of the buried RF device to fail at high frequencies.
  • the process is simpler than stacking a 3D RF MEMS system, the process steps are still cumbersome, and after the dry etch process forms a void, it is necessary to deposit a seed layer and then perform electroplating of the conductive via.
  • the compactness, uniformity and adhesion to the substrate in the pore directly determine the filling effect of the plating metal. Therefore, a fine processing process is required to prepare an excellent seed layer, which is complicated and expensive to control.
  • the conventional processing process of embedding a glass substrate device continues the process of embedding the silicon substrate device.
  • the inner cavity of the glass is processed by sand blasting, HF wet etching, deep reactive ion etching (DRIE) or laser drilling, and then a conductive metal-filled buried glass device is prepared by an electroplating process.
  • the cavity made by sandblasting is tapered and the sidewalls are rough; the HF wet etching process is difficult to obtain a high aspect ratio glass cavity; DRIE requires a complicated mask processing process, and the etching speed is also very slow.
  • Laser drilling introduces residual stress and defects into the glass.
  • After the preparation of the cavity is completed, it is necessary to deposit a uniform and dense seed layer, and then the conductive metal is filled into the cavity by an electroplating process, which is complicated and expensive to control.
  • the object of the present invention is to provide a novel glass substrate with simple process, low cost and excellent transmission performance.
  • a wafer level manufacturing method for embedding a passive component on a glass substrate comprising the following steps:
  • Step 1 Dry etching a highly doped silicon wafer to form a highly doped silicon mold wafer (1), so that the highly doped silicon mold wafer (1) comprises a mold embedded with a passive device structure (2)
  • the groove array (3), the unetched silicon (4) between the groove arrays (3) is used for subsequent device separation;
  • Step 2 anodic bonding the glass wafer (5) with the highly doped silicon mold disc (1) obtained in the first step in a vacuum, so that the groove array (3) is sealed in the bonding wafer;
  • Step 3 The bonding wafer obtained in the second step is placed in air to be heated, the heating temperature is higher than the softening point temperature of the glass, and the temperature is kept until the molten glass is filled and filled with the groove array under the action of the pressure difference between the inside and the outside of the groove ( 3) inner voids, annealed, cooled to normal temperature, forming a bottom full-doped silicon substrate (6), a composite of a glass substrate buried in the passive device structure mold (2) and an unetched silicon (4) ( 7) a triple-returning reed of the upper all-glass substrate (8);
  • Step 4 completely grinding and polishing the all-glass substrate (8) of the reflowed wafer obtained in the third step, so that the upper surface of the embedded passive device structure mold (2) is exposed on the upper surface of the glass substrate;
  • Step 5 dry etching a passive device structure mold buried in the glass substrate (2);
  • Step 6 using a full-height doped silicon substrate (6) as a seed layer, electroplating copper filled with a passive structure of the glass substrate (2) a hollow structure left after etching, and electroplating copper to form a buried glass lining Bottom passive component (10);
  • Step 7 Wet etching the unetched silicon (4) between the fully-doped silicon substrate (6) and the groove array (3) to obtain a glass that is free of cutting and self-separating buried passive components (10). a plurality of substrates (11);
  • Step 8 Surface processing Step 7
  • the obtained glass substrate is deposited with a metal adhesion layer (12), a plated metal conductive layer (13), used as a passive component unit, or a 3D integrated glass adapter plate.
  • the shape of the buried passive device structure mold (2) in the first step includes a cylindrical shape, a ring-shaped column shape, a coaxial column shape, or a polygonal line column, a square spiral column, a hexagonal spiral column, an octagonal spiral column, Round spiral column, or double cuboid, coaxial double ring column.
  • the highly doped silicon wafer is doped with phosphorus (P) or arsenic (As), the resistivity is 0.001-0.005 ⁇ cm, and the thickness is 300-600 um; the dry etching is a deep reaction Ion etching, the etching depth is less than the thickness of the highly doped silicon wafer of 100um or more.
  • the glass wafer (5) is borosilicate glass with a thickness of 300-500 um; and the vacuum anodic bonding process conditions are: temperature 400 ° C, voltage 800 V, and vacuum degree less than 10 -3 Pa.
  • the heating process conditions in the third step are: heating temperature is 900-1100 ° C, heating and holding time is 6-10 h; annealing process conditions are: annealing temperature 510-560 ° C, annealing holding time 30 min; cooling to normal temperature conditions for natural cooling.
  • Step 4 grinding and polishing: using an automatic grinding and polishing machine, first performing a grinding and thinning process on the all-glass substrate (8) to substantially remove the all-glass substrate (8), and then polishing the surface of the glass with a cerium oxide polishing solution.
  • the upper surface of the passive device structure mold (2) is exposed on the upper surface of the smooth glass substrate.
  • the dry etching is deep reactive ion etching; the etching stop discrimination method is to completely etch the passive device structure mold (2), or completely etch the passive device structure mold (2) and etch the bottom
  • the fully high doped silicon substrate (6) is no more than 20 um.
  • the process conditions for electroplating copper in step 6 are: acid sulfate electroplating copper plating solution, CuSO 4 ⁇ 5H 2 O content 85 g / L, H 2 SO 4 content 200 g / L, Cl - content 79 mg / L, current density is 30 mA/cm 2 .
  • the process conditions of the wet etching in step 7 are: the etching solution is a 40 wt% potassium hydroxide solution, and the etching temperature is 70 °C.
  • step 8 the deposited metal adhesion layer (12) is Ti or Cr, and the electroplated metal conductive layer (13) is Au or Cu.
  • the present invention firstly uses a dry etching process to etch a passive device structure mold on a highly doped silicon wafer, which has a high verticality and low roughness, and the process is a planar size and thickness of the engraved structure.
  • a highly configurable process that makes the design of buried passive components more likely.
  • the dry etching process can produce a cylindrical, a ring column and a coaxial column, etc., for preparing a cylindrical conductive through hole, a ring-shaped conductive through hole and a coaxial cylindrical conductive through hole embedded in the glass substrate;
  • Columns, square spiral columns, hexagonal spiral columns, octagonal spiral columns and circular spiral columns, etc., are used to prepare embedded glass substrate inductors; double cuboids and coaxial double ring columns can be fabricated for preparation of buried Glass substrate capacitor.
  • the present invention uses a dry etching process to form a groove array on a highly doped silicon mold wafer containing a buried passive device structure mold, the groove array will be filled with glass to form a glass substrate, and the silicon between the groove arrays Each glass substrate is separated, and each glass substrate can be released and separated by a silicon etching process without an additional cutting process.
  • the invention adopts a highly doped silicon wafer as a manufacturing mold for embedding a passive component on a glass substrate, the silicon-based semiconductor process is mature, and the precision of the mold is high; by using the highly doped silicon wafer and the glass wafer Anodic bonding
  • the silicon wafer can be used as a protective carrier for polishing and polishing glass wafers, and no additional bonding process is needed to make a new carrier-abrasive composite structure; the highly doped silicon wafer can be reused for subsequent copper plating.
  • the seed layer of the time does not need to additionally deposit an adhesion layer and a seed layer to ensure the progress of the copper plating process.
  • the high-doped silicon wafer has a three-purpose, shortening process steps and reducing cost.
  • the invention adopts an insulating glass substrate instead of a conductive silicon substrate, the thermal expansion coefficient of the glass is lower than that of silicon, and the thermal stability is better; the glass is a good dielectric material, no additional preparation of the dielectric insulating layer, the biocompatibility of the glass and Chemical stability allows glass-based RF MEMS to be implanted in living organisms for RF monitoring and RF transmission; glass transparency also provides advantages for internal device and interconnect reliability monitoring.
  • the borosilicate glass is used as the glass substrate embedded in the passive component.
  • the Pyrex 7740 model glass of Corning Company of the United States has a low thermal expansion coefficient and is matched with the thermal expansion coefficient of the silicon, and the anodic bonding of the glass wafer and the silicon wafer can be performed. High vacuum and low stress sealing of the microcavity.
  • the invention adopts an anodic bonding process to seal and bond a highly doped conductive silicon wafer to a glass wafer, and a Si-O bond is formed in the bonding region, and the chemical bond can maintain a high bonding strength at a high temperature during high temperature reflow.
  • the gas leakage is less likely to occur, and the pressure inside and outside the groove of the silicon wafer is the same, so that the molten glass cannot fill the groove.
  • a temperature of 400 ° C and a current voltage of 800 V anodic bonding can achieve a better sealing effect.
  • the invention adopts a high-temperature reflow process to form a glass substrate containing a mold embedded in a passive device structure, and the high temperature is 900-1100 ° C, and the holding time is 6-10 h.
  • the process step is simple, and the added temperature ensures the glass and the height.
  • the doped silicon material does not suffer from temperature-induced material modification or mutual penetration, reaction, etc.
  • the thermal expansion coefficient of the glass and the highly doped silicon material are matched, and excessive internal stress is not generated to cause defects in the structure, and the high-temperature reflow process can be manufactured.
  • the glass reflow process is used to replace the conventional dry-drying method to etch the structure voids, and then the adhesion layer, the barrier layer and the seed layer are deposited, and the metal conductive structure is electroplated to prepare the semiconductor process of embedding the device, thereby reducing production time, reducing cost, and obtaining high. Density, buried passive components covered by holes in the glass substrate.
  • the present invention employs an annealing process to eliminate internal stresses formed during glass reflow, thereby increasing structural strength.
  • the annealing temperature is 510-560 ° C, the holding time is 30 min, and then slowly and naturally cooled to room temperature.
  • the temperature treatment can effectively eliminate residual stress in the structure and ensure that the shape of the structure is not changed.
  • the invention adopts a grinding process to remove the upper full glass substrate, and then polishes the glass surface with a cerium oxide polishing solution, so that the middle portion composed of the composite structure of the glass substrate embedded in the passive device structure mold and the unetched silicon composite is exposed.
  • the microscopically convex portion of the glass surface is preferentially dissolved in the cerium oxide polishing liquid, thereby obtaining a rough surface. Low-gloss, bright, flat glass surface.
  • the invention adopts a grinding and polishing process to expose the upper surface of the mold embedded in the passive device structure to the surface of the glass, and the exposed area is the corrosion window opened by the subsequent etching of the passive device structure mold, and the chemical stability of the bonded glass Strong, thick, and dense, effectively protect the bottom silicon from corrosion, no additional deposition etching mask and windowing process.
  • the invention adopts a dry etching process to remove a passive device structure mold embedded in a glass substrate.
  • the process has good anisotropy, high selection ratio, no pollution introduction during the treatment process, high cleanliness and skillful process.
  • the invention adopts an electroplating process using a residual silicon substrate as a seed layer to prepare a copper material passive component embedded in a glass substrate, the silicon substrate being a seed layer with high flatness, good compactness and excellent structure, and electroplated copper
  • the filling rate is high and the compactness is good, no additional seed layer is needed, and the process steps and costs are reduced.
  • the invention adopts a silicon wet etching process to remove the connecting silicon between the residual silicon substrate and the glass substrate, and obtains a glass substrate embedded with copper passive components without cutting or self-separation, and the process step is simple and the selection ratio is high. It can be batched without additional cutting process.
  • the invention adopts a method of depositing a metal adhesion layer and then plating a metal conductive layer to surface-process the glass substrate, preparing a buried passive component unit, or preparing a buried passive component glass adapter plate for use in a 3D system package,
  • the metal adhesion layer enhances the adhesion between the conductive metal and the glass substrate, and has an anti-stripping effect.
  • the passive component of the embedded glass substrate prepared by the invention has a 3D structure, the buried component shortens the interconnect length, saves the substrate surface space for more system component integration, and surface assembly and layer stacking. Compared with the 3D system packaging method, the invention has the advantages of simple preparation process, low cost, and smaller package.
  • FIG. 1 is a cross-sectional view of a groove array in which a highly doped silicon mold wafer is etched with a mold containing a buried passive device structure.
  • FIG. 2 is a cross-sectional view of a bonding wafer after a high doped silicon mold wafer is bonded to a glass wafer anodic.
  • Figure 3 is a cross-sectional view of a reflowed wafer after heating under reflux and annealing.
  • Figure 4 is a cross-sectional view of the reflowed wafer after grinding and polishing.
  • Figure 5 is a cross-sectional view of a reflowed wafer after dry etching a passive device structure mold.
  • Figure 6 is a cross-sectional view of a reflowed wafer in which passive components of copper material are buried.
  • Figure 7 is a cross-sectional view of a glass substrate embedded in a passive component from a wet etched silicon.
  • Figure 8 is a cross-sectional view of a glass substrate subjected to a surface processing process.
  • Figure 9 is a perspective view of a conductive via, a fold line inductor, and a coplanar waveguide embedded in a glass substrate.
  • Figure 10 is a perspective view of a spiral inductor embedded in a glass substrate.
  • Figure 11 is a perspective view of a buried capacitor on a glass substrate.
  • a wafer level manufacturing method for embedding a passive component on a glass substrate comprising the following steps:
  • Step 1 Dry etching the highly doped silicon wafer to form the highly doped silicon mold wafer 1 so that the highly doped silicon mold wafer 1 includes the groove array 3 containing the passive device structure mold 2; As shown in Figure 1, the unetched silicon 4 between the array of trenches 3 is used for subsequent device isolation.
  • the highly doped silicon wafer is doped with phosphorus (P), has a resistivity of 0.001 ⁇ cm, and a thickness of 500 um.
  • the dry etching is deep reactive ion etching with an etching depth of 200 um.
  • the shape of the buried passive device structure mold 2 includes a cylinder, a ring column, a coaxial column, a 3-row ⁇ 2 column cylindrical array for interconnecting the coplanar waveguide, and is used to prepare six columns of the buried-type line inductance. Array. .
  • Step 2 The glass wafer 5 and the highly doped silicon mold disc 1 obtained in the first step are anodic bonded under a vacuum degree of less than 10 -3 Pa, a temperature of 400 ° C, and a voltage of 800 V, so that the groove array 3 is sealed. Inside the bond wafer, as shown in Figure 2.
  • the glass wafer 5 was Pyrex 7740 glass and had a thickness of 300 ⁇ m.
  • Step 3 The bonding wafer obtained in the second step is placed in air to be heated, the heating temperature is 900 ° C, and the temperature is kept for 6 h until the molten glass is reflowed to fill the gaps in the groove array 3 under the action of the pressure difference between the inside and the outside of the groove. And annealing at 560 ° C for 30 min, naturally cooled to normal temperature, forming a bottom full-doped silicon substrate 6, a glass substrate buried in the passive device structure mold 2 and a composite structure 7 of unetched silicon 4, the upper all-glass A triple-structured reflow wafer of substrate 8 is shown in FIG.
  • Step 4 using an automatic grinding and polishing machine, first performing a grinding and thinning process on the all-glass substrate 8 to substantially remove the all-glass substrate 8, and then polishing the surface of the glass with a cerium oxide polishing solution to embed the passive device structure mold 2 The upper surface is exposed on the smooth glass substrate surface as shown in FIG.
  • Step 5 Deep reactive ion etching is performed on the passive device structure mold 2 embedded in the glass substrate, as shown in FIG.
  • the etching depth is 200um.
  • Step 6 using a full-height doped silicon substrate 6 as a seed layer, electroplating copper fills the hollow structure of the passive device structure in the glass substrate, and the hollow structure left after being etched, the electroplated copper forms a passive embedded in the glass substrate Element 10 is shown in Figure 6.
  • the process conditions of the electroplating copper are: acid sulfate electroplating copper plating solution, CuSO 4 ⁇ 5H 2 O content 85g / L, H 2 SO 4 content 200g / L, Cl - content 79mg / L, current density is 30mA / Cm 2 .
  • Step 7 wet etching the unetched silicon 4 between the fully-doped silicon substrate 6 and the groove array 3 to obtain a plurality of glass substrates 11 embedded in the passive component 10 without cutting and self-separating, as shown in FIG. 7 Shown.
  • the process conditions of the wet etching are as follows: the etching solution is a 40 wt% potassium hydroxide solution, and the etching temperature is 70 °C.
  • Step 8 The glass substrate 11 obtained by the surface processing step 7 is deposited with a metal adhesion layer 12Ti or Cr, and the metal conductive layer 13Au or Cu is plated, as shown in FIG. 8, as a passive component unit, or a 3D integrated glass transfer. Board.
  • the cylindrical, ring-shaped, coaxial cylindrical embedded passive device structure mold 2 is used for preparing a cylindrical conductive via 14 for a buried glass substrate applied to a 3D device interconnection, a ring-shaped conductive via 15 and
  • the coaxial cylindrical conductive vias 16, such as interconnectable coplanar waveguides 17, or applied to fabricate a semi-embedded glass substrate fold line inductor 18, are shown in FIG.
  • the waveguide wire is connected to the lower surface of the cylinder, and two waveguide wires are respectively connected to the upper surface of each column of the cylinder to form a coplanar waveguide 17 structure of the copper pillar interconnection.
  • the waveguide wire preparation method is: Depositing a metal adhesion layer 12Ti or Cr, plating a metal conductive layer 13Au; for six cylindrical arrays, preparing a wire covering the upper surface of the first cylinder, preparing five wires respectively connecting the lower surfaces of the first and second cylinders, the second And the upper surface of the third cylinder, the lower surface of the third and fourth cylinders, the upper surfaces of the fourth and fifth cylinders, and the lower surfaces of the fifth and sixth cylinders, the wire is formed to cover the upper surface of the sixth cylinder, forming The inductor 18 is folded, and the wire is prepared by depositing a metal adhesion layer 12Ti or Cr and plating a metal conductive layer 13Cu.
  • Different kinds of coplanar waveguides and fold line inductances can be formed by increasing the number of copper pillars and preparing wires of different shapes.
  • Step 1 Dry etching the highly doped silicon wafer to form the highly doped silicon mold wafer 1 so that the highly doped silicon mold wafer 1 includes the groove array 3 containing the passive device structure mold 2; As shown in Figure 1, the unetched silicon 4 between the array of trenches 3 is used for subsequent device isolation.
  • the highly doped silicon wafer is doped with arsenic (As), has a resistivity of 0.003 ⁇ cm, and has a thickness of 600 um.
  • the dry etching is deep reactive ion etching with an etching depth of 300 um.
  • the shape of the buried passive device structure mold 2 includes a polygonal line column, a square spiral column, a hexagonal spiral column, an octagonal spiral column, a circular spiral column, or a double cuboid, a coaxial double ring column.
  • Step 2 The glass wafer 5 and the highly doped silicon mold disc 1 obtained in the first step are anodic bonded under a vacuum degree of less than 10 -3 Pa, a temperature of 400 ° C, and a voltage of 800 V, so that the groove array 3 is sealed. Inside the bond wafer, as shown in Figure 2.
  • the glass wafer 5 was Pyrex 7740 glass and had a thickness of 500 ⁇ m.
  • Step 3 The bonding wafer obtained in the second step is placed in air to be heated, the heating temperature is 1000 ° C, and the temperature is kept for 6 hours until the molten glass is reflowed to fill the gaps in the groove array 3 under the action of the pressure difference between the inside and the outside of the groove, and At 560 ° C Annealing for 30 minutes, naturally cooling to normal temperature, forming a bottom full-doped silicon substrate 6, a glass substrate buried in the passive device structure mold 2 and a composite structure 7 of unetched silicon 4, the upper all-glass substrate 8
  • the triple-structured reflow wafer is shown in Figure 3.
  • Step 4 using an automatic grinding and polishing machine, first performing a grinding and thinning process on the all-glass substrate 8 to substantially remove the all-glass substrate 8, and then polishing the surface of the glass with a cerium oxide polishing solution to embed the passive device structure mold 2 The upper surface is exposed on the smooth glass substrate surface as shown in FIG.
  • Step 5 Deep reactive ion etching is performed on the passive device structure mold 2 embedded in the glass substrate, as shown in FIG.
  • the etching depth is 300 um.
  • Step 6 using a full-height doped silicon substrate 6 as a seed layer, electroplating copper fills the hollow structure of the passive device structure in the glass substrate, and the hollow structure left after being etched, the electroplated copper forms a passive embedded in the glass substrate Element 10 is shown in Figure 6.
  • the process conditions of the electroplating copper are: acid sulfate electroplating copper plating solution, CuSO 4 ⁇ 5H 2 O content 85g / L, H 2 SO 4 content 200g / L, Cl - content 79mg / L, current density is 30mA / Cm 2 .
  • Step 7 wet etching the unetched silicon 4 between the fully-doped silicon substrate 6 and the groove array 3 to obtain a plurality of glass substrates 11 embedded in the passive component 10 without cutting and self-separating, as shown in FIG. 7 Shown.
  • the process conditions of the wet etching are as follows: the etching solution is a 40 wt% potassium hydroxide solution, and the etching temperature is 70 °C.
  • Step 8 The glass substrate 11 obtained by the surface processing step 7 is deposited with a metal adhesion layer 12Ti or Cr, and the metal conductive layer 13Au is plated, as shown in FIG. 8, as a passive component unit, or a 3D integrated glass adapter plate. , as shown in Figure 11.
  • the polygonal line column, the square spiral column, the hexagonal spiral column, the octagonal spiral column, and the circular spiral column are used for preparing a polygonal spiral inductor 19, a square spiral inductor 20, and a hexagonal spiral embedded in the glass substrate.
  • the inductor 21, the octagonal spiral inductor 22, and the circular spiral inductor 23 are as shown in FIG.
  • the double cuboid is used to prepare a plate type capacitor 24 that is fully embedded in a glass substrate, and the coaxial double ring column is used to prepare a ring capacitor 25 that is completely embedded in the glass substrate.
  • the inductor and capacitor can form components such as filters, amplifiers, etc. through surface metal interconnections.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种玻璃基板上埋入无源元件的圆片级制造方法，干法刻蚀高掺杂硅圆片形成高掺杂硅模具圆片（1），其内含埋入无源器件结构模具（2）的凹槽阵列（3）；将玻璃圆片（5）与其在真空中阳极键合；加热键合圆片使玻璃熔融填充满凹槽阵列（3）内空隙，退火，冷却，形成回流圆片；完全研磨和抛光回流圆片的上部全玻璃衬底（8）；完全刻蚀埋入玻璃衬底的无源器件结构模具（2）；电镀铜填充满玻璃衬底内无源器件结构模具（2）被刻蚀后留下的中空结构；刻蚀全高掺杂硅衬底（6）与凹槽阵列（3）之间的未刻蚀硅（4），得到埋入无源元件（10）的玻璃衬底若干个；沉积金属粘附层（12），电镀金属导电层（13），用作无源元件单元件，或3D集成的玻璃转接板。本方法步骤简单，成本低廉，制备的无源元件性能优越。

Description

玻璃基板上埋入无源元件的圆片级制造方法 技术领域
本发明涉及微电子机械系统封装技术领域，具体涉及一种玻璃基板上埋入无源元件的圆片级制造方法。
背景技术
传统射频微机电系统中单元件的制造工艺使用表面加工工艺，该工艺制备的射频无源元件纵向延伸较短，直流电阻较大，电通路较小，属于2D平面型器件，通常采用转接板层层堆叠的方式实现3D互连，使用该工艺制备3D射频微机电系统具有工艺繁琐复杂、成本昂贵、器件性能受到2D平面型特性的限制等缺点。
更高级3D系统封装形式采用埋入型基板实现。新型3D射频微机电系统采用埋入无源元件(电阻、电容、电感等)的硅基板实现3D互连。该工艺借鉴于导电硅通孔(TSV)的先打孔后电镀工艺，首先干法刻蚀硅基板形成埋入射频无源元件的空隙，然后通过化学沉积或硅高温氧化工艺制备绝缘的介质绝缘层，最后通过化学沉积种子层和电镀导电金属的工艺填充满硅基板内的空隙，制备出埋入硅基板的无源元件。然而，硅基材具有导电特性，而介电阻挡层的致密性与厚度受到纳米级尺寸的制约，致使埋入射频器件的电隔离在高频情况下失效。该工艺虽然比堆叠形成3D射频微机电系统的方式更简单，但工艺步骤仍较繁琐，并且，干法刻蚀工艺形成空隙后，需要淀积种子层，再进行导电通孔的电镀。孔内种子层的致密性、均匀性以及与基板的粘附性直接决定了电镀金属的填充效果，因此，需要精细的加工工艺来制备优良的种子层，该工艺控制较复杂、昂贵。
传统的埋入玻璃基板器件的加工工艺延续埋入硅基板器件的加工工艺。首先，通过喷砂、HF湿法腐蚀、深反应离子刻蚀(DRIE)或激光钻孔等方法加工出玻璃内空腔，然后利用电镀工艺制备出导电金属填充的埋入玻璃器件。然而，喷砂制成的空腔呈锥形，且侧壁粗糙；HF湿法腐蚀工艺难以得到高深宽比的玻璃内空腔；DRIE需要复杂的掩膜加工工艺，其刻蚀速度也非常慢；激光钻孔会给玻璃引入残余应力与缺陷。空腔制备完成后，需要淀积均匀、致密的种子层，再通过电镀工艺使导电金属填充空腔，该工艺控制较复杂、昂贵。
发明内容
本发明目的是提供一种工艺简单、成本低、传输性能优良的新型玻璃基板上埋入无 源元件的圆片级制造方法，以解决上述问题。
本发明采用以下技术方案：
一种玻璃基板上埋入无源元件的圆片级制造方法，包括如下步骤：
步骤一、干法刻蚀高掺杂硅圆片形成高掺杂硅模具圆片(1)，使高掺杂硅模具圆片(1)上包含内含埋入无源器件结构模具(2)的凹槽阵列(3)，凹槽阵列(3)之间的未刻蚀硅(4)用于后续器件分离；
步骤二、将玻璃圆片(5)与步骤一得到的高掺杂硅模具圆片(1)在真空中阳极键合，使得凹槽阵列(3)密封于键合圆片内；
步骤三、将步骤二得到的键合圆片放置在空气中加热，加热温度高于玻璃的软化点温度，并保温，直至熔融玻璃在凹槽内外压强差的作用下回流填充满凹槽阵列(3)内空隙，退火，冷却至常温，形成底部全高掺杂硅衬底(6)，中间埋入无源器件结构模具(2)的玻璃衬底和未刻蚀硅(4)的复合结构(7)，上部全玻璃衬底(8)的三重结构的回流圆片；
步骤四、完全研磨和抛光步骤三得到的回流圆片的全玻璃衬底(8)，使埋入无源器件结构模具(2)的上表面裸露在玻璃衬底上表面；
步骤五、干法刻蚀埋入玻璃衬底的无源器件结构模具(2)；
步骤六、以全高掺杂硅衬底(6)为种子层，电镀铜填充满玻璃衬底内无源器件结构模具(2)被刻蚀后留下的中空结构，电镀铜形成埋入玻璃衬底的无源元件(10)；
步骤七、湿法刻蚀全高掺杂硅衬底(6)与凹槽阵列(3)之间的未刻蚀硅(4)，得到免切割自分离的埋入无源元件(10)的玻璃基板(11)若干个；
步骤八、表面加工步骤七得到的玻璃基板，沉积金属粘附层(12)，电镀金属导电层(13)，用作无源元件单元件，或3D集成的玻璃转接板。
步骤一所述埋入无源器件结构模具(2)的形状包括圆柱形、环柱形、同轴柱形，或折线形柱、方形螺旋柱、六边形螺旋柱、八边形螺旋柱、圆形螺旋柱，或双长方体、同轴双环形柱。
步骤一所述高掺杂硅圆片所掺杂质为磷(P)或砷(As)，电阻率为0.001～0.005Ω·cm，厚度为300～600um；所述干法刻蚀为深反应离子刻蚀，刻蚀深度小于高掺杂硅圆片厚度100um以上。
步骤二所述玻璃圆片(5)为硼硅玻璃，厚度300～500um；所述真空阳极键合工艺 条件为：温度400℃，电压800V，真空度小于10-3Pa。
步骤三所述加热工艺条件为：加热温度为900～1100℃，加热保温时间6～10h；退火工艺条件为：退火温度510～560℃，退火保温时间30min；冷却至常温条件为自然冷却。
步骤四所述研磨和抛光为：采用自动研磨抛光机，首先对全玻璃衬底(8)实施研磨减薄工艺至基本去除全玻璃衬底(8)，再利用氧化铈抛光液抛光玻璃表面，至玻璃衬底裸露，此时埋入无源器件结构模具(2)的上表面裸露在光滑的玻璃衬底上表面。
步骤五所述干法刻蚀为深反应离子刻蚀；刻蚀停止判别方法为正好完全刻蚀无源器件结构模具(2)，或完全刻蚀无源器件结构模具(2)并刻蚀底部全高掺杂硅衬底(6)不大于20um。
步骤六所述电镀铜的工艺条件为：酸性硫酸盐电镀铜镀液中，CuSO4·5H2O含量85g/L，H2SO4含量200g/L，Cl-含量79mg/L，电流密度为30mA/cm2。
步骤七所述湿法刻蚀的工艺条件为：刻蚀液为40wt％的氢氧化钾溶液，刻蚀温度70℃。
步骤八所述沉积金属粘附层(12)为Ti或Cr，所述电镀金属导电层(13)为Au或Cu。
本发明的有益效果：
1.本发明首先采用干法刻蚀工艺在高掺杂硅圆片上刻蚀形成无源器件结构模具，所刻结构垂直度高，粗糙度低，本工艺是一种所刻结构平面尺寸与厚度尺寸可设计性强的工艺,，使得埋入无源单元件的设计有更多可能性。本干法刻蚀工艺可制作圆柱、环柱和同轴柱等，用于制备埋入玻璃基板圆柱形导电通孔、环柱形导电通孔和同轴柱形导电通孔；可制作折线形柱、方形螺旋柱、六边形螺旋柱、八边形螺旋柱和圆形螺旋柱等，用于制备埋入玻璃基板电感；可制作双长方体和同轴双环形柱等，用于制备埋入玻璃基板电容。
2.本发明采用干法刻蚀工艺形成高掺杂硅模具圆片上的内含埋入无源器件结构模具的凹槽阵列，凹槽阵列将被玻璃填充形成玻璃基板，凹槽阵列间的硅分隔各玻璃基板，通过硅刻蚀工艺可将各玻璃基板释放、分离，无需额外切割工艺。
3.本发明采用高掺杂硅圆片作为玻璃基板上埋入无源元件的制作模具，硅基半导体工艺成熟，所做模具精准度高；通过将该高掺杂硅圆片与玻璃圆片阳极键合，该高掺 杂硅圆片可作为玻璃圆片研磨和抛光时的保护用载片，无需额外使用粘结工艺制作新的载片-研磨片复合结构；该高掺杂硅圆片可重复利用为后续铜电镀时的种子层，无需额外沉积粘附层和种子层来保证铜电镀工艺的进行，本高掺杂硅圆片具有一片三用，缩短工艺步骤和降低成本等优点。
4.本发明采用绝缘玻璃基板代替有导电性的硅基板，玻璃的热膨胀系数比硅更低，热稳定性更好；玻璃是良介电材料，无需额外制备介质绝缘层，玻璃的生物兼容性与化学稳定性使玻璃基射频微机电系统可植入于生物体内以进行射频监测与射频传输；玻璃的透明性也给内部器件与互连可靠性监测提供了有利条件。采用硼硅玻璃作为埋入无源元件的玻璃基板，例如采用美国Corning公司的Pyrex7740型号玻璃，其热膨胀系数低，且与硅热膨胀系数匹配，将玻璃圆片和硅圆片进行阳极键合时可对微腔进行高真空和低应力密封。
5.本发明采用阳极键合工艺将高掺杂导电硅圆片与玻璃圆片密封粘结，键合区域形成Si-O键，高温时该化学键仍能保持高结合强度，在高温回流过程中不易发生气体泄漏而使硅片凹槽内外压强相同，致使熔融玻璃不能填充凹槽的情况。在温度400℃，电流电压为800V的条件下，阳极键合能够达到更好的密封效果。
6.本发明采用高温回流工艺形成内含埋入无源器件结构模具的玻璃衬底，所加高温为900～1100℃，保温时间6～10h，该工艺步骤简单，所加温度保证玻璃和高掺杂硅材料不会发生温度引起的材料改性或相互渗透、反应等后果，玻璃和高掺杂硅材料热膨胀系数匹配，不会产生过大内应力从而使结构产生缺陷，高温回流工艺可制造出无孔洞包覆的埋入射频器件结构模具的玻璃衬底。采用玻璃回流工艺代替传统的先干法刻蚀出结构空隙，后沉积粘附层、阻挡层和种子层，再电镀金属导电结构制备埋入器件的半导体工艺，缩减生产时间，降低成本，获得高致密性、被玻璃基板无孔洞包覆的埋入无源元件。
7.本发明采用退火工艺消除玻璃回流过程中形成的内应力，从而增加结构强度。退火温度为510～560℃，保温时间为30min，然后缓慢自然冷却至室温，该温度处理既能有效消除结构内残余应力，又能保证不改变结构形状。
8.本发明采用研磨工艺去除上部全玻璃衬底，再利用氧化铈抛光液抛光玻璃表面，使得由埋入无源器件结构模具的玻璃衬底和未刻蚀硅的复合结构组成的中间部分裸露，抛光时玻璃表面微观凸出的部分较凹部分优先在氧化铈抛光液中溶解，从而得到表面粗 糙度低、光亮、平整的玻璃面。
9.本发明采用研磨和抛光工艺使埋入无源器件结构模具的上表面裸露在玻璃表面，裸露区即为后续腐蚀埋入无源器件结构模具所开的腐蚀窗口，键合玻璃化学稳定性强，厚度大，致密性好，有效保护底部硅不被腐蚀，无需额外进行沉积腐蚀掩膜和开窗口工艺。
10.本发明采用干法刻蚀工艺去除埋入玻璃衬底的无源器件结构模具，该工艺各向异性好，选择比高，处理过程无污染引入，洁净度高，工艺纯熟。
11.本发明采用以剩余硅衬底为种子层的电镀工艺制备埋入玻璃基板的铜材料无源元件，该硅衬底是平整度高、致密性好、结构优良的种子层，所电镀铜填充率高，致密性好，无需额外制备种子层，缩减工艺步骤与成本。
12.本发明采用硅湿法腐蚀工艺去除残余硅衬底与玻璃基板之间的连接硅，得到免切割、自分离的埋入铜无源元件的玻璃基板，该工艺步骤简单，选择比高，可批量化进行，无需额外切割工艺。
13.本发明采用先沉积金属粘附层后电镀金属导电层对玻璃基板进行表面加工，制备埋入无源元件单元件，或制备应用于3D系统封装的埋入无源元件玻璃转接板，金属粘附层增强导电金属和玻璃基板之间的粘附性，具有防剥离作用。
14.本发明所制备的埋入玻璃基板的无源元件本身就具备3D结构，埋入式元件缩短互连线长度，节省基板表面空间用于更多系统元件集成，与表面组装和层层堆叠的3D系统封装方式相比，具有制备工艺简单，成本低廉，封装更小型化等优点。
附图说明
图1是高掺杂硅模具圆片上刻蚀有内含埋入无源器件结构模具的凹槽阵列截面图。
图2是高掺杂硅模具圆片与玻璃圆片阳极键合后的键合圆片截面图。
图3是加热回流与退火后的回流圆片截面图。
图4是研磨抛光后的回流圆片截面图。
图5是干法刻蚀无源器件结构模具后的回流圆片截面图。
图6是埋入铜材料无源元件的回流圆片截面图。
图7是湿法刻蚀硅后自分离的埋入无源元件的玻璃基板截面图。
图8是经过表面加工工艺的玻璃基板截面图。
图9是玻璃基板上埋入导电通孔、折线电感和共面波导透视图。
图10是玻璃基板上埋入螺旋电感透视图。
图11是玻璃基板上埋入电容透视图。
具体实施方式
下面结合实施例和附图对本发明做更进一步的解释。下列实施例仅用于说明本发明，但并不用来限定本发明的实施范围。
实施例1
一种玻璃基板上埋入无源元件的圆片级制造方法，包括如下步骤：
步骤一、干法刻蚀高掺杂硅圆片形成高掺杂硅模具圆片1，使高掺杂硅模具圆片1上包含内含埋入无源器件结构模具2的凹槽阵列3，如图1所示，凹槽阵列3之间的未刻蚀硅4用于后续器件分离。所述高掺杂硅圆片所掺杂质为磷(P)，电阻率为0.001Ω·cm，厚度为500um。所述干法刻蚀为深反应离子刻蚀，刻蚀深度为200um。所述埋入无源器件结构模具2的形状包括圆柱、环柱、同轴柱，用于互连共面波导的3排×2列圆柱阵列，用于制备埋入型折线电感的6个圆柱阵列。。
步骤二、将玻璃圆片5与步骤一得到的高掺杂硅模具圆片1在真空度小于10-3Pa、温度400℃，电压800V条件下进行阳极键合，使得凹槽阵列3密封于键合圆片内，如图2所示。所述玻璃圆片5为Pyrex7740玻璃，厚度300um。
步骤三、将步骤二得到的键合圆片放置在空气中加热，加热温度为900℃，并保温6h，直至熔融玻璃在凹槽内外压强差的作用下回流填充满凹槽阵列3内空隙，并在560℃下退火30min，自然冷却至常温，形成底部全高掺杂硅衬底6，中间埋入无源器件结构模具2的玻璃衬底和未刻蚀硅4的复合结构7，上部全玻璃衬底8的三重结构的回流圆片，如图3所示。
步骤四、采用自动研磨抛光机，首先对全玻璃衬底8实施研磨减薄工艺至基本去除全玻璃衬底8，再利用氧化铈抛光液抛光玻璃表面，至埋入无源器件结构模具2的上表面裸露在光滑的玻璃衬底上表面，如图4所示。
步骤五、深反应离子刻蚀埋入玻璃衬底的无源器件结构模具2，如图5所示。刻蚀深度为200um。
步骤六、以全高掺杂硅衬底6为种子层，电镀铜填充满玻璃衬底内无源器件结构模具2被刻蚀后留下的中空结构，电镀铜形成埋入玻璃衬底的无源元件10，如图6所示。所述电镀铜的工艺条件为：酸性硫酸盐电镀铜镀液中，CuSO4·5H2O含量85g/L，H2SO4 含量200g/L，Cl-含量79mg/L，电流密度为30mA/cm2。
步骤七、湿法刻蚀全高掺杂硅衬底6与凹槽阵列3之间的未刻蚀硅4，得到免切割自分离的埋入无源元件10的玻璃基板11若干个，如图7所示。所述湿法刻蚀的工艺条件为：刻蚀液为40wt％的氢氧化钾溶液，刻蚀温度70℃。
步骤八、表面加工步骤七得到的玻璃基板11，沉积金属粘附层12Ti或Cr，电镀金属导电层13Au或Cu，如图8所示，用作无源元件单元件，或3D集成的玻璃转接板。所述圆柱形、环柱形、同轴柱形埋入无源器件结构模具2用于制备应用于3D器件互连的埋入玻璃基板圆柱形导电通孔14、环柱形导电通孔15和同轴柱形导电通孔16，如可互连共面波导17，或者应用于制备半埋入玻璃基板折线电感18，如图9所示。对于3排×2列铜圆柱阵列，制备波导线连接圆柱下表面，制备两条波导线分别连接每列圆柱的上表面，形成铜柱互连的共面波导17结构，波导线制备方法为：沉积金属粘附层12Ti或Cr，电镀金属导电层13Au；对于6个圆柱阵列，制备导线覆盖第1个圆柱的上表面，制备5条导线分别连接第1和第2圆柱的下表面，第2和第3圆柱的上表面，第3和第4圆柱的下表面，第4和第5圆柱的上表面，第5和第6圆柱的下表面，制备导线覆盖第6个圆柱的上表面，形成折现电感18，导线制备方法为：沉积金属粘附层12Ti或Cr，电镀金属导电层13Cu。可通过增加铜柱个数和制备不同形状导线形成不同种共面波导，折线电感。
实施例2
步骤一、干法刻蚀高掺杂硅圆片形成高掺杂硅模具圆片1，使高掺杂硅模具圆片1上包含内含埋入无源器件结构模具2的凹槽阵列3，如图1所示，凹槽阵列3之间的未刻蚀硅4用于后续器件分离。所述高掺杂硅圆片所掺杂质为砷(As)，电阻率为0.003Ω·cm，厚度为600um。所述干法刻蚀为深反应离子刻蚀，刻蚀深度为300um。所述埋入无源器件结构模具2的形状包括折线形柱、方形螺旋柱、六边形螺旋柱、八边形螺旋柱、圆形螺旋柱，或双长方体、同轴双环形柱。
步骤二、将玻璃圆片5与步骤一得到的高掺杂硅模具圆片1在真空度小于10-3Pa、温度400℃，电压800V条件下进行阳极键合，使得凹槽阵列3密封于键合圆片内，如图2所示。所述玻璃圆片5为Pyrex7740玻璃，厚度500um。
步骤三、将步骤二得到的键合圆片放置在空气中加热，加热温度为1000℃，保温6h，直至熔融玻璃在凹槽内外压强差的作用下回流填充满凹槽阵列3内空隙，并在560℃ 下退火30min，自然冷却至常温，形成底部全高掺杂硅衬底6，中间埋入无源器件结构模具2的玻璃衬底和未刻蚀硅4的复合结构7，上部全玻璃衬底8的三重结构的回流圆片，如图3所示。
步骤四、采用自动研磨抛光机，首先对全玻璃衬底8实施研磨减薄工艺至基本去除全玻璃衬底8，再利用氧化铈抛光液抛光玻璃表面，至埋入无源器件结构模具2的上表面裸露在光滑的玻璃衬底上表面，如图4所示。
步骤五、深反应离子刻蚀埋入玻璃衬底的无源器件结构模具2，如图5所示。刻蚀深度为300um。
步骤六、以全高掺杂硅衬底6为种子层，电镀铜填充满玻璃衬底内无源器件结构模具2被刻蚀后留下的中空结构，电镀铜形成埋入玻璃衬底的无源元件10，如图6所示。所述电镀铜的工艺条件为：酸性硫酸盐电镀铜镀液中，CuSO4·5H2O含量85g/L，H2SO4含量200g/L，Cl-含量79mg/L，电流密度为30mA/cm2。
步骤七、湿法刻蚀全高掺杂硅衬底6与凹槽阵列3之间的未刻蚀硅4，得到免切割自分离的埋入无源元件10的玻璃基板11若干个，如图7所示。所述湿法刻蚀的工艺条件为：刻蚀液为40wt％的氢氧化钾溶液，刻蚀温度70℃。
步骤八、表面加工步骤七得到的玻璃基板11，沉积金属粘附层12Ti或Cr，电镀金属导电层13Au，如图8所示，用作无源元件单元件，或3D集成的玻璃转接板，如图11所示。所述折线形柱、方形螺旋柱、六边形螺旋柱、八边形螺旋柱、圆形螺旋柱用于制备全埋入玻璃基板的折线形螺旋电感19、方形螺旋电感20、六边形螺旋电感21、八边形螺旋电感22、圆形螺旋电感23，如图10所示。所述双长方体用于制备全埋入玻璃基板的板型电容24，同轴双环形柱用于制备全埋入玻璃基板的环形电容25。所述电感电容可通过表面金属互连形成滤波器、放大器等元件。

Claims (11)

  1. 一种玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，包括如下步骤：
    步骤一、干法刻蚀高掺杂硅圆片形成高掺杂硅模具圆片(1)，使高掺杂硅模具圆片(1)上包含内含埋入无源器件结构模具(2)的凹槽阵列(3)，凹槽阵列(3)之间的未刻蚀硅(4)用于后续器件分离；
    步骤二、将玻璃圆片(5)与步骤一得到的高掺杂硅模具圆片(1)在真空中阳极键合，使得凹槽阵列(3)密封于键合圆片内；
    步骤三、将步骤二得到的键合圆片放置在空气中加热，加热温度高于玻璃的软化点温度，并保温，直至熔融玻璃在凹槽内外压强差的作用下回流填充满凹槽阵列(3)内空隙，退火，冷却至常温，形成底部全高掺杂硅衬底(6)，中间埋入无源器件结构模具(2)的玻璃衬底和未刻蚀硅(4)的复合结构(7)，上部全玻璃衬底(8)的三重结构的回流圆片；
    步骤四、完全研磨和抛光步骤三得到的回流圆片的全玻璃衬底(8)，使埋入无源器件结构模具(2)的上表面裸露在玻璃衬底上表面；
    步骤五、干法刻蚀埋入玻璃衬底的无源器件结构模具(2)；
    步骤六、以全高掺杂硅衬底(6)为种子层，电镀铜填充满玻璃衬底内无源器件结构模具(2)被刻蚀后留下的中空结构，电镀铜形成埋入玻璃衬底的无源元件(10)；
    步骤七、湿法刻蚀全高掺杂硅衬底(6)与凹槽阵列(3)之间的未刻蚀硅(4)，得到免切割自分离的埋入无源元件(10)的玻璃基板(11)若干个；
    步骤八、表面加工步骤七得到的玻璃基板，沉积金属粘附层(12)，电镀金属导电层(13)，用作无源元件单元件，或3D集成的玻璃转接板。
  2. 根据权利要求1所述的玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，步骤一所述埋入无源器件结构模具(2)的形状包括圆柱形、环柱形、同轴柱形，或折线形柱、方形螺旋柱、六边形螺旋柱、八边形螺旋柱、圆形螺旋柱，或双长方体。
  3. 根据权利要求1或2所述的玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，步骤一所述高掺杂硅圆片所掺杂质为磷(P)或砷(As)，电阻率为0.001～0.005Ω·cm，厚度为300～600um；所述干法刻蚀为深反应离子刻蚀，刻蚀深度小于高掺杂硅圆片厚度100um以上。
  4. 根据权利要求1或2所述的玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，步骤二所述玻璃圆片(5)为硼硅玻璃，厚度300～500um；所述真空阳极键合 工艺条件为：温度400℃，电压800V，真空度小于10-3Pa。
  5. 根据权利要求1或2所述的玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，步骤三所述加热工艺条件为：加热温度为900～1100℃，加热保温时间6～10h；退火工艺条件为：退火温度510～560℃，退火保温时间30min；冷却至常温条件为自然冷却。
  6. 根据权利要求1或2所述的玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，步骤四所述研磨和抛光为：采用自动研磨抛光机，首先对全玻璃衬底(8)实施研磨减薄工艺至基本去除全玻璃衬底(8)，再利用氧化铈抛光液抛光玻璃表面，至玻璃衬底裸露，此时埋入无源器件结构模具(2)的上表面裸露在光滑的玻璃衬底上表面。
  7. 根据权利要求1或2所述的玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，步骤五所述干法刻蚀为深反应离子刻蚀；刻蚀停止判别方法为正好完全刻蚀无源器件结构模具(2)，或完全刻蚀无源器件结构模具(2)并刻蚀底部全高掺杂硅衬底(6)不大于20um。
  8. 根据权利要求1或2所述的玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，步骤六所述电镀铜的工艺条件为：酸性硫酸盐电镀铜镀液中，CuSO4·5H2O含量85g/L，H2SO4含量200g/L，Cl-含量79mg/L，电流密度为30mA/cm2。
  9. 根据权利要求1或2所述的玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，步骤七所述湿法刻蚀的工艺条件为：刻蚀液为40wt％的氢氧化钾溶液，刻蚀温度70℃。
  10. 根据权利要求1或2所述的玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，步骤八所述沉积金属粘附层(12)为Ti或Cr，所述电镀金属导电层(13)为Au或Cu。
  11. 根据权利要求2所述的玻璃基板上埋入无源元件的圆片级制造方法，其特征在于，所述同轴柱形为同轴双环形柱。
PCT/CN2015/098677 2014-12-11 2015-12-24 玻璃基板上埋入无源元件的圆片级制造方法 WO2016091222A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/619,525 US10321577B2 (en) 2014-12-11 2017-06-11 Wafer-level manufacturing method for embedding passive element in glass substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410765689.7 2014-12-11
CN201410765689.7A CN104401934B (zh) 2014-12-11 2014-12-11 玻璃基板上埋入无源元件的圆片级制造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/619,525 Continuation-In-Part US10321577B2 (en) 2014-12-11 2017-06-11 Wafer-level manufacturing method for embedding passive element in glass substrate

Publications (1)

Publication Number Publication Date
WO2016091222A1 true WO2016091222A1 (zh) 2016-06-16

Family

ID=52639623

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/098677 WO2016091222A1 (zh) 2014-12-11 2015-12-24 玻璃基板上埋入无源元件的圆片级制造方法

Country Status (3)

Country Link
US (1) US10321577B2 (zh)
CN (1) CN104401934B (zh)
WO (1) WO2016091222A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113839163A (zh) * 2021-09-28 2021-12-24 西安理工大学 一种采用tsv技术的面对面结构小型化三维发夹滤波器

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104401934B (zh) * 2014-12-11 2016-02-24 东南大学 玻璃基板上埋入无源元件的圆片级制造方法
CN106564856A (zh) * 2016-10-27 2017-04-19 东南大学 复合型基板及其制备方法
CN105399050B (zh) * 2015-12-18 2017-01-25 东南大学 集成芯片散热结构和无源器件的玻璃基板的圆片级制备方法
US10335978B2 (en) 2016-05-31 2019-07-02 Honeywell International Inc. Fabrication of three-dimensional structures using reflowed molding
DE102017127920A1 (de) * 2017-01-26 2018-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Erhöhte Durchkontaktierung für Anschlüsse auf unterschiedlichen Ebenen
CN107994008A (zh) * 2017-11-30 2018-05-04 杭州电子科技大学 一种运用螺线管式硅通孔电感的新型低通滤波器
US10622302B2 (en) 2018-02-14 2020-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Via for semiconductor device connection and methods of forming the same
KR102406488B1 (ko) 2018-02-28 2022-06-08 레이던 컴퍼니 적층 제조 기술 낮은 프로파일 신호 분배기
CN108645397B (zh) * 2018-04-03 2020-08-14 北京航天控制仪器研究所 一种石英盘式谐振微机械陀螺谐振子的制造方法
DE102018126130B4 (de) 2018-06-08 2023-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und -verfahren
CN109928359B (zh) * 2019-03-25 2021-08-27 机械工业仪器仪表综合技术经济研究所 微结构封装方法及封装器件
CN110676541B (zh) * 2019-05-10 2020-10-09 西安电子科技大学 一种基于玻璃通孔的三维集成滤波器
CN110577186A (zh) * 2019-09-12 2019-12-17 南通大学 一种mems红外探测器三维封装结构及其制作方法
CN110854019A (zh) * 2019-11-26 2020-02-28 上海华力集成电路制造有限公司 半导体制造方法
CN111244049B (zh) * 2020-01-20 2021-08-03 北京大学 内嵌散热腔的低损耗射频垂直电连接结构和制作方法
CN111574035A (zh) * 2020-05-08 2020-08-25 东南大学 一种玻璃基板上v型槽的制备方法
CN112312654B (zh) * 2020-08-14 2021-09-17 珠海越亚半导体股份有限公司 一种嵌埋在玻璃介质中的无源器件结构及其制造方法
CN112996282B (zh) * 2021-02-10 2023-12-22 福建世卓电子科技有限公司 选择性化学镀与电镀交叉生产柔性线路板的工艺
CN113488431A (zh) * 2021-05-24 2021-10-08 北京大学 一种包括高深宽比通孔的玻璃基板的制备方法
CN113880429A (zh) * 2021-09-28 2022-01-04 彩虹显示器件股份有限公司 一种无碱基板玻璃及其减薄方法
CN115784624B (zh) * 2022-11-23 2023-11-17 湖南邵虹特种玻璃股份有限公司 一种玻璃蚀刻加工台的夹持座及其操作方法
CN116106591B (zh) * 2023-01-10 2023-09-19 佛山市蓝箭电子股份有限公司 一种微波探针的制作方法及微波探针

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5624870A (en) * 1995-03-16 1997-04-29 United Microelectronics Corporation Method of contact planarization
JP2002134659A (ja) * 2000-10-24 2002-05-10 Tateyama Kagaku Kogyo Kk 電子素子用基板とその製造方法並びに電子素子とその製造方法
CN103413780A (zh) * 2013-08-20 2013-11-27 厦门大学 一种基于熔融玻璃骨架的三维通孔互联结构制作方法
CN104401934A (zh) * 2014-12-11 2015-03-11 东南大学 玻璃基板上埋入无源元件的圆片级制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101259951A (zh) * 2008-04-11 2008-09-10 东南大学 圆片级玻璃微腔的制造方法
JP2012205256A (ja) * 2011-03-28 2012-10-22 Seiko Instruments Inc パッケージの製造方法、圧電振動子、発振器、電子機器及び電波時計
CN102276167A (zh) * 2011-04-27 2011-12-14 中国科学院微电子研究所 一种把金属材料插入玻璃的方法及装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5624870A (en) * 1995-03-16 1997-04-29 United Microelectronics Corporation Method of contact planarization
JP2002134659A (ja) * 2000-10-24 2002-05-10 Tateyama Kagaku Kogyo Kk 電子素子用基板とその製造方法並びに電子素子とその製造方法
CN103413780A (zh) * 2013-08-20 2013-11-27 厦门大学 一种基于熔融玻璃骨架的三维通孔互联结构制作方法
CN104401934A (zh) * 2014-12-11 2015-03-11 东南大学 玻璃基板上埋入无源元件的圆片级制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113839163A (zh) * 2021-09-28 2021-12-24 西安理工大学 一种采用tsv技术的面对面结构小型化三维发夹滤波器

Also Published As

Publication number Publication date
CN104401934B (zh) 2016-02-24
US20170280566A1 (en) 2017-09-28
US10321577B2 (en) 2019-06-11
CN104401934A (zh) 2015-03-11

Similar Documents

Publication Publication Date Title
WO2016091222A1 (zh) 玻璃基板上埋入无源元件的圆片级制造方法
CN103193193B (zh) Mems器件及其形成方法
US8987137B2 (en) Method of fabrication of through-substrate vias
KR101475108B1 (ko) 집적 회로 디자인으로의 얕은 트렌치 격리 및 관통 기판 비아의 일체화
CN112864026B (zh) 激光结合hf湿刻蚀加工tgv通孔的工艺
CN108389847A (zh) 一种基于同轴硅通孔阵列的三维电容器及其制作方法
CN102208363A (zh) 一种形成穿透硅通孔的方法
CN109928359B (zh) 微结构封装方法及封装器件
CN103474394B (zh) 免金属cmp的tsv工艺方法
CN102881644B (zh) 一种圆片级芯片封装方法
CN109637970A (zh) 一种偏心式真空辅助旋涂垂直深孔内壁绝缘层制作方法
CN103474365A (zh) 一种半导体封装方法
CN105070682B (zh) 一种高效制备硅转接板的方法
TW201336041A (zh) 用於電子元件之三維封裝之方法
CN103700643A (zh) 一种基于tsv工艺的转接板深槽电容及其制造方法
Dixit et al. Via technologies for MEMS
CN109037149A (zh) 无缺陷穿硅通孔结构的制备方法
CN104952720A (zh) 一种高度可控的导电柱背部露头的形成方法
CN208127200U (zh) 一种基于同轴硅通孔阵列的三维电容器
CN111081632A (zh) 一种减小热应力的硅通孔结构及其制造方法
CN107994023B (zh) 超细孔结构的制成工艺
CN105140174A (zh) 一种tsv通孔侧壁的平坦化方法
CN114477779B (zh) 一种基于异质键合的多层玻璃基板工艺和结构
KR101582612B1 (ko) 동축 관통 실리콘 비아 구조체 및 그 제조방법
US20130134600A1 (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15866574

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15866574

Country of ref document: EP

Kind code of ref document: A1