WO2016072280A1 - 信号処理装置、撮像素子、並びに電子機器 - Google Patents
信号処理装置、撮像素子、並びに電子機器 Download PDFInfo
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- WO2016072280A1 WO2016072280A1 PCT/JP2015/079819 JP2015079819W WO2016072280A1 WO 2016072280 A1 WO2016072280 A1 WO 2016072280A1 JP 2015079819 W JP2015079819 W JP 2015079819W WO 2016072280 A1 WO2016072280 A1 WO 2016072280A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/186—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedforward mode, i.e. by determining the range to be selected directly from the input signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/56—Input signal compared with linear ramp
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Definitions
- the present technology relates to a signal processing device, an imaging device, and an electronic device, and more particularly, to a signal processing device, an imaging device, and an electronic device that can suppress an increase in cost.
- This A / D conversion is generally performed by comparing a signal read from a pixel having a light receiving unit with a reference voltage such as a ramp wave and measuring the time until the comparison result changes.
- a reference voltage such as a ramp wave
- Patent Document 1 two types of reference voltages having different inclinations are prepared, and a determination unit for determining the magnitude of the pixel output signal is newly provided, and one of the two reference voltages is selected according to the determination result.
- miniaturization of circuits has been advanced for the purpose of miniaturization and reduction of power consumption.
- the distance between signal wirings becomes shorter, and parasitic capacitance may occur.
- a control circuit for selecting a reference voltage is formed in the vicinity of the input terminal of the comparison unit that compares the signal read from the pixel with the reference voltage, and a parasitic circuit is formed between the wiring in the control circuit and the input terminal. Capacity may occur.
- the input terminal of the comparison unit that is connected in series and becomes a floating node is subjected to coupling due to signal transition of the wiring in the control circuit.
- the signal level of the signal transmitted through the wiring in the control circuit differs between the reset period of the correlated double sampling and the signal readout period, and the input terminal of the comparison unit
- the coupling voltage fluctuation amount received during the reset period and the coupling voltage fluctuation quantity received during the signal readout period are different from each other.
- an error may occur in the result of correlated double sampling due to the difference in the fluctuation quantity, and A / D conversion may not be performed correctly. It was.
- This technology has been proposed in view of such a situation, and an object thereof is to suppress an increase in cost.
- One aspect of the present technology is a comparison unit that compares a signal level of an analog signal and a signal level of a reference signal, a selection unit that selects a reference signal to be supplied to the comparison unit from a plurality of reference signals, A switching unit capable of switching a signal line connected to the input terminal of the comparison unit so as to connect a signal line through which the reference signal selected by the selection unit is transmitted to the input terminal of the comparison unit;
- the comparison unit includes an input terminal of a floating node, the selection unit includes a signal line in which a parasitic capacitance is generated between the input unit and the input terminal of the floating node of the comparison unit, and the signal line of the selection unit is
- the signal processing device transmits signals having the same signal level in the comparison performed a plurality of times by the comparison unit.
- the comparison unit sequentially compares a signal level of a reset signal read from the unit pixel and a signal level of each of a plurality of reference signals, and the selection unit responds to a signal level of the pixel signal read from the unit pixel. Selecting one of the plurality of reference signals, and the switching unit connects a signal line on which the reference signal selected by the selection unit is transmitted to an input terminal of the comparison unit, The signal line connected to the input terminal of the comparison unit is switched as necessary, and the comparison unit further compares the signal level of the pixel signal with the signal level of the reference signal selected by the selection unit.
- the signal line of the selection unit compares the signal level of the reset signal with the signal level of the reference signal selected by the selection unit and the pixel signal of the pixel signal. In both the comparison between No. level and signal level of the reference signal, it is possible to signal level transmit signals are identical to each other.
- the signal level of the signal transmitted through the signal line of the selection unit may indicate a reference signal selected by the selection unit.
- the comparison unit initializes and sequentially compares the signal level of the reset signal read from the unit pixel and the signal level of each of the plurality of reference signals, and the signal level of the pixel signal read from the unit pixel and a predetermined reference
- the selection unit compares the signal level with a signal level of the pixel signal based on a result of comparison between the signal level of the pixel signal and the signal level of a predetermined reference signal by the comparison unit.
- the switching unit is connected to the input terminal of the comparison unit so as to connect a signal line on which the reference signal selected by the selection unit is transmitted to the input terminal of the comparison unit.
- the signal line to be switched is switched as necessary, the comparison unit further compares the signal level of the pixel signal and the signal level of the reference signal selected by the selection unit,
- the signal lines of the selection unit are signals having the same signal level in both the initialization of the comparison unit and the comparison between the signal level of the pixel signal and the signal level of a predetermined reference signal by the comparison unit. Can be transmitted.
- the signal level of the signal transmitted through the signal line of the selection unit may indicate a reference signal selected by the selection unit.
- the selection unit can select a reference signal to be supplied to the comparison unit from a plurality of reference signals based on a result of the comparison performed by the comparison unit.
- the comparison unit can compare the signal level of the analog signal read from the unit pixel belonging to the unit pixel group assigned to the pixel array with the signal level of the reference signal.
- One aspect of the present technology also includes a pixel array in which unit pixels are arranged in a matrix, and a comparison unit that compares a signal level of an analog signal read from the unit pixel of the pixel array with a signal level of a reference signal
- a selection unit that selects a reference signal to be supplied to the comparison unit from a plurality of reference signals, and a signal line that transmits the reference signal selected by the selection unit is connected to an input terminal of the comparison unit.
- a switching unit capable of switching a signal line connected to the input terminal of the comparison unit, the comparison unit has an input terminal of a floating node, and the selection unit is the floating node of the comparison unit And a signal line in which parasitic capacitance is generated between the input terminal and the signal line of the selection unit in the comparison performed by the comparison unit a plurality of times.
- An image pickup element for transmitting a certain signal.
- One aspect of the present technology further includes an imaging unit that images a subject, and an image processing unit that performs image processing on image data obtained by imaging by the imaging unit, and the imaging unit includes unit pixels arranged in a matrix.
- a selection unit that selects a reference signal and a signal line that is connected to the input terminal of the comparison unit are switched so that a signal line that transmits the reference signal selected by the selection unit is connected to the input terminal of the comparison unit.
- the comparator has a floating node input terminal, and the selector has a parasitic capacitance between the input terminal of the comparator and the floating node. It has a signal line occurs, the signal line of the selection unit, in the comparison to be performed a plurality of times by the comparison unit is an electronic device signal level to transmit the signals are identical to each other.
- Another aspect of the present technology is a comparison unit that compares a signal level of an analog signal and a signal level of a reference signal, a selection unit that selects a reference signal to be supplied to the comparison unit from a plurality of reference signals, A switching unit capable of switching a signal line connected to the comparison unit so that a signal line on which a reference signal selected by the selection unit is transmitted is connected to the comparison unit, and a result of the comparison by the comparison unit Included in a signal output from the mixing unit and transmitted via a single signal line, and a mixing unit that mixes a signal indicating the reference signal selected by the selection unit and a signal indicating the reference signal selected by the selection unit Measuring the time until the value of the signal indicating the result of the comparison by the unit changes, and outputting the measurement result as an A / D conversion result of the analog signal; output from the mixing unit; Via signal line Included in the signal, based on a signal indicating a reference signal selected by the selection unit, a signal processing device and a control unit for
- the mixing unit may transmit a signal indicating a comparison result by the comparison unit and a signal indicating the reference signal selected by the selection unit via the single signal line in different periods. it can.
- the comparison unit sequentially compares the signal level of the reset signal read from the unit pixel and the signal level of each of the plurality of reference signals, and the signal level of the pixel signal read from the unit pixel and the signal of the predetermined reference signal
- the selection unit selects any one of the plurality of reference signals, and the switching unit selects a signal line through which the reference signal selected by the selection unit is transmitted.
- the signal line connected to the comparison unit is switched as necessary to connect to the comparison unit, and the comparison unit further includes a signal level of the pixel signal and a signal level of the reference signal selected by the selection unit.
- the mixing unit is a signal indicating a result of the comparison in a period in which the comparison unit compares the signal level of the reset signal with the signal level of each reference signal.
- the indicated signal can be transmitted through the single signal line.
- the comparison unit includes a signal comparison unit that compares the signal level of the analog signal and the signal level of the reference signal, a logic negation unit that inverts the result of the comparison by the signal comparison unit, and a logic negation unit
- a negative logical product unit for obtaining a negative logical product of the output and a predetermined control signal, wherein the mixing unit mixes the output of the negative logical product unit and a signal indicating the reference signal selected by the selection unit can do.
- the comparison unit includes a signal comparison unit that compares the signal level of the analog signal and the signal level of the reference signal, and a logic negation unit that inverts the result of the comparison by the signal comparison unit, and the mixing unit Is a logical product part for obtaining a logical product of the output of the logical negation part and a predetermined control signal, a negative logical sum of the output of the logical product part and a signal indicating the reference signal selected by the selection part. And a negative OR part to be obtained.
- the selection unit can select a reference signal to be supplied to the comparison unit from a plurality of reference signals according to the result of the comparison by the comparison unit.
- the comparison unit can compare the signal level of the analog signal read from the unit pixel belonging to the unit pixel group assigned to the pixel array with the signal level of the reference signal.
- the comparison unit, the selection unit, the switching unit, and the mixing unit, and the measurement unit and the control unit may be formed on different semiconductor substrates.
- Another aspect of the present technology also provides a comparison between a pixel array in which unit pixels are arranged in a matrix and a signal level of an analog signal read from the unit pixel of the pixel array and a signal level of a reference signal.
- a comparison unit to perform a selection unit that selects a reference signal to be supplied to the comparison unit from among a plurality of reference signals, and a signal line that transmits the reference signal selected by the selection unit is connected to the comparison unit
- a switching unit that can switch a signal line connected to the comparison unit, a signal that indicates the result of the comparison by the comparison unit, and a signal that indicates the reference signal selected by the selection unit And measuring the time until the value of the signal indicating the result of the comparison by the comparing unit included in the signal output from the mixing unit and transmitted via a single signal line changes.
- Another aspect of the present technology further includes an imaging unit that images a subject, and an image processing unit that performs image processing on image data obtained by imaging by the imaging unit, and the imaging unit includes unit pixels in a matrix form
- a comparison unit that compares a signal level of an analog signal read from the unit pixel of the pixel array with a signal level of a reference signal, and the comparison unit among a plurality of reference signals
- the signal line connected to the comparison unit can be switched so that the selection unit for selecting the reference signal to be supplied to the signal line and the signal line on which the reference signal selected by the selection unit is transmitted are connected to the comparison unit.
- a switching unit a mixing unit that mixes a signal indicating the result of the comparison by the comparison unit, and a signal indicating the reference signal selected by the selection unit, and a single signal line output from the mixing unit Through A measurement unit that measures a time until a value of a signal indicating the result of the comparison by the comparison unit changes, included in the transmitted signal, and outputs the measurement result as an A / D conversion result of the analog signal; A control unit for controlling measurement of the measurement unit based on a signal indicating a reference signal selected by the selection unit included in a signal output from the mixing unit and transmitted via a single signal line Is an electronic device.
- a comparison unit that compares a signal level of an analog signal and a signal level of a reference signal, a selection unit that selects a reference signal to be supplied to the comparison unit from a plurality of reference signals, and a selection A switching unit capable of switching a signal line connected to the input terminal of the comparison unit so as to connect a signal line on which the reference signal selected by the unit is transmitted to the input terminal of the comparison unit. Is provided with a floating node input terminal, and the signal level is the same in the comparison performed several times by the comparison unit via a signal line in which the selection unit has a parasitic capacitance with the input terminal of the comparison unit. Is transmitted.
- a comparison unit that compares the signal level of the analog signal and the signal level of the reference signal, a selection unit that selects a reference signal to be supplied to the comparison unit from a plurality of reference signals, A switching unit capable of switching a signal line connected to the comparison unit so as to connect a signal line to which the reference signal selected by the selection unit is transmitted to the comparison unit, and a signal indicating a result of comparison by the comparison unit;
- a mixing unit that mixes the signal indicating the reference signal selected by the selection unit, and a signal that indicates the result of the comparison by the comparison unit that is included in the signal that is output from the mixing unit and transmitted via a single signal line Measure the time until the value changes, and output the measurement result as an analog signal A / D conversion result and included in the signal transmitted from the mixing unit and transmitted via a single signal line Selected by the selector Based on the signal indicating the reference signal, it is provided a control unit for controlling the measurement of the measuring unit.
- the signal can be processed. Moreover, according to this technique, the increase in cost can be suppressed.
- 6 is a timing chart illustrating an example of A / D conversion.
- 6 is a timing chart illustrating an example of A / D conversion. It is a timing chart explaining the example of the internal signal of a switch control part.
- 6 is a timing chart illustrating an example of A / D conversion. It is a figure which shows the main structural examples of a column A / D conversion part. It is a figure which shows the main structural examples of a column A / D conversion part. It is a figure which shows the main structural examples of a column A / D conversion part. It is a figure which shows the main structural examples of a comparison part. It is a timing chart explaining the example of the mode of mixing. It is a figure which shows the main structural examples of a column A / D conversion part. It is a figure which shows the example of the physical structure of an image sensor. It is a figure which shows the main structural examples of an imaging device.
- First Embodiment> ⁇ Parasitic capacitance and coupling voltage fluctuation>
- a light receiving unit such as a photodiode
- a / D Analog / Digital
- This A / D conversion is generally performed by comparing a signal read from a pixel having a light receiving unit with a reference voltage such as a ramp wave and measuring the time until the comparison result changes.
- An increase in gradation of an image sensor is one of the performances required for high image quality.
- high gradation in a low illuminance region greatly contributes to image quality.
- the gradation is enlarged, high speed, area, and power consumption are sacrificed.
- the gradation is high, the number of A / D conversions increases, which may impair the high speed.
- parallel processing is performed using a plurality of A / D conversion units in order to maintain high speed, there is a risk of increasing the area and power consumption.
- the area of the A / D conversion portion increases, the semiconductor substrate becomes large and the manufacturing cost may increase.
- the increase in the area of the A / D conversion unit makes the design more difficult and may increase the development cost.
- FIG. 1 is a block diagram showing a main configuration example of an A / D conversion unit that performs A / D conversion by such a method.
- the comparison unit 11 uses a reference signal Vref1 or a reference signal Vref2 (also referred to as a reference voltage) that changes the voltage of the signal Vx, which is an analog signal, within a predetermined range such as a ramp wave. ).
- the counter 12 counts the time (for example, the number of clocks) from the start of counting until the value of the comparison result changes.
- This count value indicates the time (number of clocks) until the signal level of the reference signal Vref1 or the reference signal Vref2 reaches the signal level of the signal Vx from the minimum value or the maximum value. That is, this count value is digital data indicating the signal level of the signal Vx. Therefore, the counter 12 outputs the count value Do as an A / D conversion result of the signal Vx.
- a capacitor 13 is connected in series to an input terminal to which the signal Vx of the comparison unit 11 is input.
- a capacitor 14 is connected in series to an input terminal to which the reference signal Vref1 or reference signal Vref2 of the comparison unit 11 is input. That is, each input terminal of the comparison unit 11 forms a floating node.
- a switching unit 15 that can switch a reference signal input to the comparison unit 11 is connected to the capacitor 14 in series.
- the switching unit 15 includes a switch that controls connection between a signal line that transmits the reference signal Vref1 and a signal line that is connected to the capacitor 14, and a signal line that transmits the reference signal Vref2 and a signal line that is connected to the capacitor 14.
- the switching unit 15 performs such switching operation based on the control of the switch control unit 16, that is, based on the values of the control signal SWR1 and the control signal SWR2 from the switch control unit 16.
- the switch control unit 16 determines the values of the control signal SWR1 and the control signal SWR2 based on the predetermined control signal SWSQ, the control signal ADP, and the value of the predetermined signal Vin, and supplies the control signal SWR1 and the control signal SWR2.
- the switching unit 15 is controlled.
- the signal Vx is input to the switch control unit 16 as the signal Vin, and the switching unit 15 is controlled according to the magnitude of the signal level of the signal Vx (that is, the reference signal Is selected).
- the reference signal Vref1 and the reference signal Vref2 are different from each other in speed at which the voltage changes (that is, the slope of the signal). Therefore, the A / D converter as shown in FIG. 1 uses these reference signals according to the signal level (ie, illuminance) of the signal Vx (switches the accuracy of the reference signal), thereby maintaining the gradation in the high illuminance region.
- the gradation in the low illuminance region can be expanded while maintaining the above.
- the reference signal is switched by the switching unit, it is not necessary to perform parallel processing using a plurality of A / D conversion units, so that an increase in area and power consumption can be suppressed.
- the comparison unit 11 has a configuration such as the example shown in FIG. As shown in FIG. 2, a capacitor 13 is connected in series to an input terminal Vxin to which a signal Vx is input, and a capacitor is connected to an input terminal Vrefin to which a reference signal Vref1 and a reference signal Vref2 are input. 14 are connected in series. Therefore, the input terminal Vxin and the input terminal Vrefin are floating nodes.
- the switch control unit 16 has a configuration like the example shown in FIG.
- the values of the control signal SWR1 and the control signal SWR2 are determined as in the example shown in FIG. 3B according to the control signal ADP and the control signal SWSQ. More specifically, when the control signal ADP is “1”, the value of the control signal SWR1 is the value of the signal SWFB, and the value of the control signal SWR2 is the value of the signal SWFB.
- This signal SWFB is an internal signal of the switch control unit 16 and is determined by the signal Vin as shown in FIG. More specifically, the signal SWFB is the negation of the signal Vin latched at a predetermined timing controlled by the signal ⁇ fb.
- the distance between the signal lines in the circuit becomes shorter.
- the distance between the comparison unit 11 and the switch control unit 16 is shortened, and the floating node (Vrefin and Vxin) of the comparison unit 11 and the switch control as in the example shown in FIG. 4.
- a parasitic capacitance is generated between the signal line transmitting the signal SWFB of the unit 16.
- the floating node of the comparator may be coupled due to signal transition of the value of the signal SWFB (for example, the illuminance determination result).
- the A / D conversion unit of FIG. 1 performs a step in the reset period of correlated double sampling (also referred to as CDS (Correlated Double Sampling)) as shown in the timing chart of FIG.
- a / D conversion (N1) of signal Vx using reference voltage Vref1 with adjustment accuracy D1 and A / D conversion (N2) of signal Vx (reset signal) using reference voltage Vref2 with gradation accuracy D2 Thereafter, the signal level of the signal Vx is determined, and in the signal readout period of the CDS, based on the determination result, A / D conversion (S1) of the signal Vx (pixel signal) using the reference voltage Vref1 or the reference voltage Vref2 is determined.
- One of the A / D conversions (S2) of the used signal Vx (pixel signal) is performed.
- a shield wiring is provided between the signal line for transmitting the signal SWFB and the floating node of the comparison unit 11, or the layout is made so that the distance is sufficiently spoken.
- a method for reducing the capacity is conceivable.
- ⁇ Control of signal SWFB> Therefore, a signal line that is included in a selection unit that selects a reference signal to be supplied to the comparison unit from among a plurality of reference signals, and in which a parasitic capacitance is generated between the input terminal of the floating node of the comparison unit, In each of the comparisons performed a plurality of times by the comparison unit, signals having the same signal level are transmitted. For example, when A / D conversion is performed as in the example of FIG. 5, as shown in FIG. 6, the values of the signal SWFB are the same in comparison in both the CDS reset period and the signal readout period. To do.
- FIG. 6A shows an example of the signal SWFB when the high gain slope reference signal Vref1 and the signal Vx are compared in the signal readout period.
- the value of the signal SWFB is “H” both in the comparison between the reference signal Vref1 and the signal Vx in the reset period and in the comparison between the reference signal Vref1 and the signal Vx in the signal readout period.
- FIG. 6B shows an example of the signal SWFB when the low gain slope reference signal Vref2 and the signal Vx are compared in the signal readout period.
- the value of the signal SWFB is “L” both in the comparison between the reference signal Vref2 and the signal Vx in the reset period and in the comparison between the reference signal Vref2 and the signal Vx in the signal readout period.
- the signals SWFB that transmit the signal lines in which the parasitic capacitance is generated between the input terminal of the floating node of the comparison unit 11 are set to the same potential. Since the fluctuation amount of the coupling voltage is uniform, the error of the correlated double sampling result can be reduced. That is, it is possible to reduce the error without increasing the circuit area of the A / D conversion unit and perform A / D conversion more correctly. Therefore, an increase in development and manufacturing costs can be suppressed. Furthermore, an increase in power consumption can be suppressed.
- FIG. 7 shows a main configuration example of an image sensor which is an embodiment of an image sensor (signal processing device) to which the present technology is applied.
- An image sensor 100 shown in FIG. 7 is a device that photoelectrically converts light from a subject and outputs it as image data.
- the image sensor 100 is configured as a CMOS image sensor using CMOS (Complementary Metal Oxide Semiconductor), a CCD image sensor using CCD (Charge Coupled Device), or the like.
- CMOS Complementary Metal Oxide Semiconductor
- CCD Charge Coupled Device
- the image sensor 100 includes a pixel array 111, an A / D conversion unit 112, and a horizontal transfer unit 113.
- the image sensor 100 includes a control timing generation unit 121, a pixel scanning unit 122, and an A / D conversion control unit 123. Further, the image sensor 100 includes a reference voltage generation unit 131 and a reference voltage generation unit 132.
- the pixel array 111 is a pixel region in which pixel configurations (unit pixels) having photoelectric conversion elements such as photodiodes are arranged in a planar shape or a curved shape.
- the unit pixels 141 are arranged in a matrix (array).
- the arrangement of the unit pixels 141 is arbitrary, and may be an arrangement other than a matrix, such as a so-called honeycomb structure.
- a vertical signal line is formed for each column (column) of the unit pixel 141 (hereinafter also referred to as a unit pixel column). Each vertical signal line is connected to each unit pixel of a column (unit pixel column) corresponding to itself, and transmits a signal (for example, pixel signal Vx) read from each unit pixel to the A / D converter 112. .
- a control line is formed for each row of unit pixels 141 (hereinafter also referred to as a unit pixel row). Each control line is connected to each unit pixel in the unit pixel row corresponding to itself, and transmits a control signal supplied from the pixel scanning unit 122 to each unit pixel.
- the unit pixel 141 is connected to the vertical signal line assigned to the column (unit pixel column) to which the unit pixel 141 belongs and the control line assigned to the unit pixel row to which the unit pixel 141 belongs. Driving is performed based on the supplied control signal, and an electric signal obtained by itself is supplied to the A / D conversion unit 112 via the vertical signal line.
- the reference voltage generator 131 generates a reference signal Vref1 (also referred to as a reference voltage Vref1) that serves as a reference signal for A / D conversion with a predetermined gradation accuracy by the A / D converter 112.
- the waveform of the reference signal Vref1 is arbitrary.
- the reference signal Vref1 may be a ramp wave (sawtooth wave).
- a case where a ramp wave (Ramp) is used as the reference signal Vref1 will be described as an example.
- the reference voltage generation unit 131 includes, for example, a D / A conversion unit, and generates a reference signal (Ramp) by the D / A conversion unit. This reference signal (Ramp) is supplied to the A / D converter 112 via a reference signal line.
- the reference voltage generator 132 generates a reference signal Vref2 (also referred to as a reference voltage Vref2) that is a reference signal for A / D conversion with a predetermined gradation accuracy by the A / D converter 112.
- the reference signal Vref2 is a reference signal for A / D conversion with gradation accuracy different from that of the reference signal Vref1.
- the waveform of the reference signal Vref2 is arbitrary as long as it is the same type as the reference signal Vref1. For example, when the reference signal Vref1 is a ramp wave (sawtooth wave), the reference signal Vref2 is also a ramp wave (sawtooth wave). However, the slopes are different from each other.
- the reference voltage generator 132 includes, for example, a D / A converter, and generates a reference signal (Ramp) by the D / A converter. This reference signal (Ramp) is supplied to the A / D converter 112 via a reference signal line.
- reference signal Vref1 and reference signal Vref2 are ramp waves (Ramp)
- reference signal Vref1 is a reference signal for A / D conversion of low gain (high accuracy) determination with a high gain slope
- reference signal Vref2 Is a reference signal for A / D conversion of high illuminance (low accuracy) determination with a low gain slope (that is, a reference signal having a steeper slope than the reference signal Vref1).
- the A / D converter 112 uses the reference signal to A / D convert the signal Vx, which is an analog signal (read from each unit pixel) transmitted from the pixel array 111 via the vertical signal line.
- the digital data (digital output DO) is output to the horizontal transfer unit 113.
- the A / D converter 112 includes a column A / D converter 151-1, a column A / D converter 151-2, a column A / D converter 151-3,... Shown in FIG. A column A / D converter 151 is provided for each column (unit pixel column) of the pixel array 111.
- Each column A / D converter 151 is connected to a column vertical signal line corresponding to itself, a reference signal line to which the reference signal Vref1 is transmitted, and a reference signal line to which the reference signal Vref2 is transmitted. Each column A / D converter 151 performs A / D conversion on the column signal Vx corresponding to itself using the reference signal Vref1 or the reference signal Vref2.
- a signal line connected to the horizontal transfer unit 113 is connected to each column A / D conversion unit 151.
- Each column A / D conversion unit 151 supplies digital output DO, which is digital data indicating the A / D conversion result obtained by itself, to the horizontal transfer unit 113 via the signal line.
- the horizontal transfer unit 113 transfers the digital data supplied from the A / D conversion unit 112 to the outside of the image sensor 100 (output OUT).
- the control timing generation unit 121 supplies predetermined clock signals to the pixel scanning unit 122, the A / D conversion control unit 123, the reference voltage generation unit 131, the reference voltage generation unit 132, and the horizontal transfer unit 113, and their drive timings. To control.
- the pixel scanning unit 122 controls the operation of the transistor of each unit pixel 141 by supplying a control signal to each unit pixel row of the pixel array 111 via a control line.
- the A / D conversion control unit 123 controls the operation of the A / D conversion unit 112 (each column A / D conversion unit 151) by supplying a control signal via the control line.
- each control line is shown as a single line, but each control line may be composed of a plurality of control lines.
- FIG. 8 is a diagram illustrating an example of a main configuration of the circuit configuration of the unit pixel 141.
- the unit pixel 141 includes a photodiode (PD) 161, a transfer transistor 162, a reset transistor 163, an amplification transistor 164, and a select transistor 165.
- PD photodiode
- the photodiode (PD) 161 photoelectrically converts the received light into a photocharge (here, photoelectrons) having a charge amount corresponding to the light quantity, and accumulates the photocharge. The accumulated photocharge is read out at a predetermined timing.
- the anode electrode of the photodiode (PD) 161 is connected to the ground (pixel ground) of the pixel region, and the cathode electrode is connected to the floating diffusion (FD) via the transfer transistor 162.
- the cathode electrode of the photodiode (PD) 161 is connected to the power supply (pixel power supply) in the pixel region, the anode electrode is connected to the floating diffusion (FD) via the transfer transistor 162, and the photocharge is read out as a photohole. It is good also as a system.
- the transfer transistor 162 controls reading of the photocharge from the photodiode (PD) 161.
- the transfer transistor 162 has a drain electrode connected to the floating diffusion and a source electrode connected to the cathode electrode of the photodiode (PD) 161.
- a transfer control line (TRG) for transmitting a transfer control signal supplied from the pixel scanning unit 122 is connected to the gate electrode of the transfer transistor 162. That is, this transfer control line (TRG) is included in the control lines shown in FIG.
- the reset transistor 163 resets the potential of the floating diffusion (FD).
- the reset transistor 163 has a drain electrode connected to the power supply potential and a source electrode connected to the floating diffusion (FD).
- a reset control line (RST) that transmits a reset control signal supplied from the pixel scanning unit 122 is connected to the gate electrode of the reset transistor 163. That is, this reset control line (RST) is included in the control lines shown in FIG.
- the amplification transistor 164 amplifies the potential change of the floating diffusion (FD) and outputs it as an electric signal (analog signal).
- the amplification transistor 164 has a gate electrode connected to the floating diffusion (FD), a drain electrode connected to the source follower power supply voltage, and a source electrode connected to the drain electrode of the select transistor 165.
- the amplification transistor 164 outputs the potential of the floating diffusion (FD) reset by the reset transistor 163 to the select transistor 165 as a reset signal (reset level). Further, the amplification transistor 164 outputs the potential of the floating diffusion (FD) to which the photocharge has been transferred by the transfer transistor 162 to the select transistor 165 as a light accumulation signal (signal level).
- the select transistor 165 controls the output of the electrical signal supplied from the amplification transistor 164 to the vertical signal line (VSL) (that is, the A / D conversion unit 112).
- the select transistor 165 has a drain electrode connected to the source electrode of the amplification transistor 164 and a source electrode connected to the vertical signal line (VSL).
- a select control line (SEL) for transmitting a select control signal supplied from the pixel scanning unit 122 is connected to the gate electrode of the select transistor 165. That is, this select control line (SEL) is included in the control lines shown in FIG.
- the amplification transistor 164 and the vertical signal line (VSL) are electrically disconnected. Therefore, in this state, no reset signal, pixel signal, or the like is output from the unit pixel 141.
- the select control line (SEL) is in the on state
- the unit pixel 141 is in the selected state. That is, the amplification transistor 164 and the vertical signal line (VSL) are electrically connected, and a signal output from the amplification transistor 164 is supplied to the vertical signal line (VSL) as an analog signal read from the unit pixel 141. Is done. That is, a reset signal, a pixel signal, and the like are read from the unit pixel 141.
- the column A / D conversion unit 151 includes a comparison unit 171 and a counter 172.
- the comparison unit 171 is an aspect of the signal processing device to which the present technology is applied, selects one of the reference signal Vref1 and the reference signal Vref2, and sets the signal level of the signal Vx to the signal level of the selected reference signal. Compare. The comparison unit 171 performs such comparison multiple times. The comparison unit 171 supplies a signal Vco indicating the comparison result to the counter 172 for each comparison.
- the counter 172 counts the time (number of clocks) from the start of comparison by the comparison unit 171 until the comparison result (the value of the signal Vco) changes. This count value (digital data) becomes the A / D conversion result of the signal Vx which is an analog signal. The counter 172 supplies this count value to the horizontal transfer unit 113 as a digital output DO.
- the comparison unit 171 includes a comparison unit 181, a selection unit 182, a switching unit 183, a capacitor 184, and a capacitor 185.
- a capacitor 184 is connected to the input terminal Vrefin of the comparator 181 and a capacitor 185 is connected to the input terminal Vxin. That is, the input terminal Vrefin and the input terminal Vxin of the comparison unit 181 form a floating node.
- the input / output of the comparator 181 is short-circuited to remove the error and initialize, and the level at the time of initialization is set to the floating node of the series capacitance. Can be stored.
- the comparison unit 181 determines the signal level of the signal Vx (analog signal read from the pixel array 111) input to the input terminal Vxin, and the reference signal (reference signal Vref1 or reference signal Vref2) input to the input terminal Vrefin. Compared with the signal level, a signal Vco indicating the comparison result is supplied to the selection unit 182 and the counter 172. The comparison unit 181 performs such a comparison a plurality of times, and supplies a signal Vco indicating the comparison result to the selection unit 182 and the counter 172 for each comparison.
- the selection unit 182 selects a reference signal to be supplied to the comparison unit 181 based on the control pulse supplied from the A / D conversion control unit 123 and the signal indicating the comparison result output from the comparison unit 181.
- the selection unit 182 supplies control signals (control signal SW1 and control signal SW2) that cause the switching unit 183 to appropriately switch the connection so as to supply the selected reference signal (reference signal Vref1 or reference signal Vref2) to the comparison unit 181. This is supplied to the switching unit 183.
- the switching unit 183 selects one of the reference signal Vref1 and the reference signal Vref2 based on the control of the selection unit 182, ie, the control signal SW1 and the control signal SW2 supplied from the selection unit 182, and the selected reference signal Is supplied to the capacitor 184.
- the switching unit 183 includes a switch that controls the connection between the reference signal line that transmits the reference signal Vref1 and the capacitor 184, and a switch that controls the connection between the reference signal line that transmits the reference signal Vref2 and the capacitor 184.
- a switch for controlling the connection between the reference signal line for transmitting the reference signal Vref1 and the capacitor 184 is controlled by a control signal SW1 supplied from the selection unit 182.
- a switch for controlling the connection between the reference signal line for transmitting the reference signal Vref2 and the capacitor 184 is controlled by a control signal SW2 supplied from the selection unit 182.
- the switching unit 183 connects the reference signal line to the capacitor 184 by turning on a switch between a desired reference signal line and the capacitor 184 according to the values of the control signals, and other references. By turning off the other switch between the signal line and the capacitor 184, the other reference signal lines are disconnected (disconnected) from the capacitor 184.
- the capacitor 184 is provided between the switching unit 183 and the input terminal Vrefin of the comparison unit 181.
- the capacitor 185 is provided between the vertical signal line VSL (pixel array 111) of the pixel array 111 and the input terminal Vxin of the comparison unit 181.
- the selection unit 182 includes a determination unit 191 and a switch control unit 192.
- the determination unit 191 determines which reference signal to select based on the control pulse supplied from the A / D conversion control unit 123 and the signal indicating the comparison result output from the comparison unit 181.
- the determination unit 191 supplies a signal indicating the determination result, that is, a signal SWFB indicating the reference signal selected by the selection unit 182 to the switch control unit 192 via a predetermined signal line.
- the switch control unit 192 determines the values of the control signal SW1 and the control signal SW2 according to the signal SWFB supplied through the signal line.
- the switch control unit 192 controls the operation of the switching unit 183 by supplying the control signal SW1 and the control signal SW2 whose values are determined to the switching unit 183.
- such a selection unit 182 is formed closer to the comparison unit 181, and the signal line for transmitting the signal SWFB of the selection unit 182 and the floating node of the comparison unit 181 are used.
- Parasitic capacitance occurs between an input terminal Vrefin and an input terminal Vxin.
- the comparison unit 181 may be configured such that only one of the input terminal Vrefin and the input terminal Vxin is a floating node.
- the comparison unit 181 When the comparison unit 181 performs signal level comparison a plurality of times, the signal levels of the signal SWFB are set to be the same in each comparison. By doing so, it is possible to reduce the influence of the coupling voltage variation due to the parasitic capacitance on the comparison result by the comparison unit 181.
- the determination unit 191 of the selection unit 182 includes a NOT gate 201, a latch 202, and a switch 203.
- the NOT gate 201 inverts the output Vco of the comparison unit 181 that is 1-bit digital data.
- the latch 202 holds the output of the NOT gate 201 at a timing according to the control signal ⁇ fb supplied from the A / D conversion control unit 123, and outputs the held value (JUD).
- the switch 203 is one of the output JUD of the latch 202 and the signal SWSQ supplied from the A / D conversion control unit 123 according to the value of the control signal ADP supplied from the A / D conversion control unit 123. Select. For example, when the value of the control signal ADP is “1”, the switch 203 selects the output JUD of the latch 202. For example, when the value of the control signal ADP is “0”, the switch 203 selects the signal SWSQ. The switch 203 supplies the signal thus selected to the switch control unit 192 as the signal SWFB.
- the switch control unit 192 includes an amplifier 204 and a NOT gate 205.
- the amplifier 204 amplifies the signal SWFB and supplies it to the switching unit 183 as the control signal SW1.
- the NOT gate 205 inverts the signal SWFB, which is 1-bit digital data, and supplies the inverted signal SWFB to the switching unit 183 as the control signal SW2.
- the column A / D conversion unit 151 performs A / D conversion according to the flow shown in the timing chart shown in FIG. That is, the column A / D conversion unit 151 first performs A / D conversion of the reset signal read from the unit pixel 141 using the high gain slope reference signal Vref1 during the reset period of the CDS, and outputs the signal N1. (HG) is obtained (high precision noise output).
- the column A / D conversion unit 151 performs A / D conversion of the reset signal read from the unit pixel 141 using the low gain slope reference signal Vref2 in the reset period of the CDS, and generates a signal N2 ( LG) (low precision noise output).
- the column A / D conversion unit 151 determines the signal level of the pixel signal read from the unit pixel 141 (determination).
- the column A / D converter 151 selects the reference signal Vref1 or the reference signal Vref2 according to the determination result, and is read from the unit pixel 141 using the selected reference signal in the CDS signal readout period.
- a / D conversion of the signal level of the pixel signal is performed to obtain signal S1 (HG) or signal S2 (LG) (signal output).
- the values of the control signal SW1 and the control signal SW2 are determined by the value of the control signal SWSQ. That is, in the CDS reset period, the value of the control signal SWSQ is sequentially “1” and “0”, so that the reference signal Vref1 and the reference signal Vref2 are sequentially selected, and the high gain slope A / D conversion and low Gain slope A / D conversion is performed sequentially.
- the signal SWFB is sequentially set to the value “1” and the value “0” in the same manner as the control signal SW1.
- the output Vco of the comparison unit 181 in the determination period is latched by the pulse of the control signal ⁇ fb.
- the value of the control signal ADP becomes “1”, and the values of the control signal SW1 and the control signal SW2 are determined by the value of the output JUD of the latch 202. That is, in the signal readout period of the CDS, the reference signal Vref1 or the reference signal Vref2 is selected according to the output JUD of the latch 202, that is, the determination result of the signal level of the pixel signal in the determination period, and the selected reference signal is The A / D conversion used (high gain slope A / D conversion or low gain slope A / D conversion) is performed.
- the signal SWFB becomes the value “1” or the value “0” (a value corresponding to the determination result of the signal level of the pixel signal in the determination period), like the control signal SW1. That is, when low illuminance (A / D conversion with high gain slope) is selected, the value of the signal SWFB is “1”, and when high illuminance (A / D conversion with low gain slope) is selected, the signal SWFB The value of “0” is “0”.
- the difference in the coupling voltage fluctuation amount between the signal S1 and the signal N1 (or the signal S2 and the signal N2) can be suppressed, and an error due to the coupling voltage fluctuation can be suppressed by subtracting both. be able to.
- the column A / D converter 151 causes both the high gain slope reference signal Vref1 and the low gain slope reference signal Vref2 to fluctuate (sweep) in the voltage decreasing direction.
- either one or both of the reference signals may be changed in the voltage increasing direction.
- the low gain slope reference signal Vref2 may be varied in the voltage increasing direction. This case is the same as the case of FIG. 11 except for the sweep direction of the reference signal.
- the error of the correlated double sampling result (S1-N1 or S2-N2) is reduced without increasing the circuit area of the A / D converter, so that A / D conversion is performed more correctly. can do. Therefore, an increase in development and manufacturing costs can be suppressed. Furthermore, an increase in power consumption can be suppressed.
- Second Embodiment> ⁇ Comparison part initialization and judgment>
- suppression of an error caused by a change in coupling voltage fluctuation amount has been described in comparison of a reset signal and pixel signal.
- the amount of fluctuation in the coupling voltage received by the floating node of the comparison unit 11 changes between the completion of the initialization of the comparison unit 11 and the signal level determination of the pixel signal, this may cause a determination error. was there.
- a signal line included in a selection unit that selects a reference signal to be supplied to the input terminal of the floating node of the comparison unit from a plurality of reference signals, and there is a parasitic capacitance between the selection signal and the input terminal of the floating node of the comparison unit.
- the resulting signal line transmits signals having the same signal level both in the initialization of the comparison unit and in the comparison between the signal level of the pixel signal by the comparison unit and the signal level of the predetermined reference signal.
- both the initialization of the comparison unit and the comparison between the signal level of the pixel signal and the signal level of the predetermined reference signal by the comparison unit are parasitic between the input terminal of the floating node of the comparison unit.
- the column A / D conversion unit 151 may perform A / D conversion as in the timing chart shown in FIG.
- the column A / D conversion unit 151 initializes the comparison unit 181 and then performs A / D conversion as in the example of FIG.
- the value of the control signal ADP is “0” during the initialization period (initialization) of the comparison unit 181 and the period during which the signal level of the pixel signal is determined (determination). . Therefore, during these periods, the values of the control signal SW1 and the control signal SW2 are determined by the value of the control signal SWSQ. That is, during these periods, the value of the signal SWFB is determined by the value of the control signal SWSQ.
- the value of the control signal SWSQ is the same in both the initialization period (initialization) of the comparison unit 181 and the period (determination) in which the signal level of the pixel signal is determined. ("1"). Therefore, during these periods, the value of the signal SWFB is also the same (“1”).
- the potential (signal SWFB) of the signal line of the selection unit 182 in which parasitic capacitance is generated between the input terminal Vrefin and the input terminal Vxin which are the floating nodes of the comparison unit 181 is the same as when the initialization of the comparison unit is completed. The same potential is obtained when the signal level determination is completed.
- the difference in coupling voltage fluctuation between the initialization result (Vini) of the comparison unit and the signal level determination result (Vjud) of the pixel signal can be suppressed, and the coupling can be reduced by subtracting both. Errors due to voltage fluctuations can be suppressed. That is, it is possible to reduce the error of the illuminance determination result (Vjud ⁇ Vini) without increasing the circuit area of the A / D conversion unit, and to perform A / D conversion more correctly. Therefore, an increase in development and manufacturing costs can be suppressed. Furthermore, an increase in power consumption can be suppressed.
- the difference in the coupling voltage fluctuation between the initialization result of the comparison unit and the signal level determination result of the pixel signal is suppressed, and the signal S1 and the signal N1 (or the signal S2 and the signal N2) is also suppressed, but only the difference in the coupling voltage variation between the initialization result of the comparison unit and the signal level determination result of the pixel signal is suppressed. It may be. Further, the column A / D conversion unit 151 varies (sweeps) both the high gain slope reference signal Vref1 and the low gain slope reference signal Vref2 in the voltage decreasing direction, as in the example of FIG. However, either one or both of the reference signals may be changed in the voltage increasing direction. Also in this embodiment, as in the case of the first embodiment, only one of the input terminal Vrefin and the input terminal Vxin of the comparison unit 181 may be a floating node. Good.
- the column A / D conversion unit 151 includes a latch 301 and a latch 302.
- the latch 301 is a simplified illustration of the selector 182 (FIG. 9).
- the output Vco of the comparison unit 181 in the signal level determination period of the pixel signal is latched by the latch 301, and control signals (control signal SW1 and control signal SW2) corresponding to the value are supplied to the switching unit 183.
- the latch 301 supplies an identification signal FLAG for identifying a slope gain for controlling the value of the counter 172 to the latch 302 based on the latched output Vco of the comparison unit 181.
- the latch 302 latches the identification signal FLAG, and at a predetermined timing, according to the value of the identification signal FLAG, a control signal that matches the count speed (for example, magnification) of the counter 172 with the slope signal of the reference signal is counter 172. To supply.
- the column A / D converter 151 is configured as shown in FIG.
- the column A / D conversion unit 151 includes a latch 311 and a latch 312 instead of the latch 301 and the latch 302 of FIG. 15.
- the latch 311 latches the output Vco of the comparison unit 181 in the signal level determination period of the pixel signal, and supplies control signals (control signal SW1 and control signal SW2) corresponding to the value to the switching unit 183. However, no signal is supplied to the latch 312.
- the latch 312 acquires and latches the output Vco of the comparator 181 from the vicinity of the counter 172 of the signal line between the comparator 181 and the counter 172 without latching the identification signal FLAG.
- the latch 312 supplies the counter 172 with a control signal that matches the count speed (eg, magnification) of the counter 172 with the slope signal of the reference signal in accordance with the value of the output Vco.
- connection portion bump or the like
- an increase in the number of connection portions can be suppressed as compared with the configuration example of FIG.
- an increase in circuit area can be suppressed as compared with the configuration example of FIG.
- the latch 311 and the latch 312 may have different capture timings of determination results (the capture timing may be shifted). Due to the difference in the capture timing, the data latched by the latch 311 and the data latched by the latch 312 are different from each other, and there is a possibility that the calculation may fail.
- the mixing unit mixes the signal indicating the comparison result by the comparison unit and the signal indicating the reference signal selected by the selection unit, and the measurement unit outputs the single signal line from the mixing unit. Measure the time until the value of the signal indicating the comparison result by the comparison unit changes, and output the measurement result as an A / D conversion result of the analog signal.
- the measurement of the measurement unit is controlled based on the signal indicating the reference signal selected by the selection unit, which is included in the signal output from the mixing unit and transmitted via the single signal line.
- a mixing unit that mixes a signal indicating the result of comparison by the comparison unit and a signal indicating the reference signal selected by the selection unit, and is output from the mixing unit and transmitted via a single signal line. Measure the time until the value of the signal indicating the comparison result by the comparison unit changes, included in the signal, and output the measurement result as an A / D conversion result of the analog signal, and output from the mixing unit, And a control unit that controls measurement of the measurement unit based on a signal indicating a reference signal selected by the selection unit, which is included in a signal transmitted via a single signal line.
- a signal indicating the result of comparison by the comparison unit and a signal indicating the reference signal selected by the selection unit can be transmitted from the comparison unit to the measurement unit via a single signal line. Therefore, an increase in circuit area can be suppressed. In addition, since an increase in the number of connection portions can be suppressed, an increase in circuit area can be suppressed even when the comparison portion and the measurement portion are formed on different semiconductor substrates.
- the configuration of the image sensor 100 in this case is basically the same as that in each embodiment described above. In the following description, only the part that should be described for the configuration and operation of the image sensor 100 will be described, and the description in each of the above embodiments can be applied to the part that will not be described, or any configuration And the operation can be applied.
- FIG. 17 shows a main configuration example of the column A / D conversion unit 151 in this case.
- the column A / D conversion unit 151 includes a latch 321, a multiplexer 322, an electrode 323, and a latch 324 instead of the latch 301 and the latch 302 of FIG.
- the latch 321 is a simplified illustration of the selector 182 (FIG. 9), similar to the latch 301.
- the output Vco of the comparison unit 181 in the signal level determination period of the pixel signal is latched by the latch 321, and control signals (control signal SW 1 and control signal SW 2) corresponding to the value are supplied to the switching unit 183.
- the latch 321 supplies an identification signal FLAG for identifying a slope gain for controlling the value of the counter 172 to the multiplexer 322 based on the latched output Vco of the comparison unit 181.
- the multiplexer (MUX) 322 mixes the output Vco of the comparison unit 181 and the identification signal FLAG during the signal level determination period of the pixel signal, and supplies the mixed signal to the counter 172.
- the multiplexer 322 mixes the output Vco of the comparison unit 181 and the control signal FLAG so as to be transmitted through a single signal line in different periods. Details of mixing will be described later.
- the electrode 323 is, for example, a connection part such as a bump (BUMP) or a via (VIA).
- the counter 172 and the latch 324 are formed on a semiconductor substrate different from the structure shown on the left side of the multiplexer 322 and the multiplexer 322 in FIG.
- the electrode 323 is a connection part for connecting a circuit between a plurality of semiconductors in this way. Note that the counter 172 and the latch 324 may be formed on the same semiconductor substrate as that shown on the left side of the multiplexer 322 and the multiplexer 322 in FIG. In that case, the electrode 323 can be omitted.
- the latch 324 obtains a mixed signal from the vicinity of the counter 172 of the signal line between the comparison unit 181 and the counter 172 (at least on the counter 172 side from the electrode 323), and is included in the mixed signal.
- Latch control signal FLAG The latch 312 supplies the counter 172 with a control signal that matches the count speed (eg, magnification) of the counter 172 with the slope signal of the reference signal in accordance with the value of the output Vco.
- the counter 172 counts according to the control signal.
- Comparison unit 181 A main configuration example of the comparison unit 181 in this case is shown in FIG.
- the comparison unit 181 is configured as shown in FIG. 18 using, for example, a comparison unit 331, a NOT gate 332, and a NAND gate 333.
- the logical negation by the NOT gate 332 of the comparison result between the analog signal VSL read from the unit pixel 141 by the comparison unit 331 and the reference signal DAC is determined by the NAND gate 333 at the timing controlled by the control signal STB. It is output to the multiplexer 322. That is, the output timing of the output Vco of the comparison unit 181 can be controlled using the control signal STB.
- the image sensor 100 (column A / D converter 151) performs A / D conversion in the same manner as in the above-described embodiments. Then, as shown in FIG. 19, the multiplexer 322 outputs the output Vco of the comparison unit 181 in the CDS reset period (P phase and P phase 2) and the signal readout period (D phase), and the signal level of the pixel signal
- the control signal FLAG is output during the determination period.
- the counter 172 does not count during the determination period, and the latch 324 latches the control signal FLAG before the CDS signal readout period. Accordingly, the multiplexer 322 mixes the output Vco of the comparison unit 181 and the control signal FLAG as in the example of FIG. 19, so that the counter 172 and the latch 324 respectively acquire necessary signals from a single signal line. be able to.
- the latch 324 can latch the control signal FLAG generated by the latch 321 and can control the counter 172 based on the control signal FLAG. Therefore, the column A / D conversion unit 151 can make the determination timings of the latches 321 and 324 the same, and the data latched by each can always be the same. Thereby, the failure of calculation can be suppressed.
- most of the signal lines between the comparison unit 181 and the counter 172 may be one. And an increase in circuit area can be suppressed. Further, since the increase in the number of electrodes 323 formed in one portion of the signal line can be suppressed, even when the comparison unit 181 and the counter 172 are formed on different semiconductor substrates, An increase in the area of the circuit can be suppressed.
- the column A / D conversion unit 151 (that is, the image sensor 100) can suppress an increase in the area of the circuit and suppress an increase in development and manufacturing costs while suppressing the failure of calculation. Furthermore, an increase in power consumption can be suppressed.
- the multiplexer 322 may be provided for the next output. For example, before the comparison result of the reset signal is output from the comparison unit 181 (timing before the “P phase” of the “output” stage in FIG. 19 is started), the multiplexer 322 outputs the output Vco of the comparison unit 181. May be selected and output (“VCO” to the left of “FLAG” in the “MUX selection” stage in FIG. 19 is started). Further, for example, the multiplexer 322 controls the control signal from before the determination result of the signal level of the pixel signal is output from the comparison unit 181 (timing before “determination” in the “output” stage in FIG. 19 is started).
- FLAG may be selected and output (“FLAG” at the “MUX selection” stage in FIG. 19 is started). Furthermore, for example, before the comparison result of the pixel signal is output from the comparison unit 181 (timing before the “D phase” of the “output” stage in FIG. 19 is started), the multiplexer 322 includes the comparison unit 181. The output Vco may be selected and output (“VCO” to the right of “FLAG” in the “MUX selection” stage in FIG. 19 is started).
- the signal comparison unit compares the signal level of the analog signal with the signal level of the reference signal
- the logical negation unit logically negates (inverts) the result of the comparison by the signal comparison unit
- the logical product unit The logical product of the output of the logical negation part and a predetermined control signal is obtained
- the negative logical sum part obtains the negative logical sum of the output of the logical product part and the signal indicating the reference signal selected by the selection part. It may be.
- FIG. 20 shows a main configuration example of the column A / D conversion unit 151 in that case.
- the column A / D conversion unit 151 basically has the same configuration as the configuration example shown in FIGS. 17 and 18, but the latch 321, the multiplexer 322, and the comparison unit Instead of the 181 NAND gate 333, a latch 342, an AND gate 343, and a NOR gate 344 are provided. That is, the column A / D converter 151 has a composite gate including an AND gate 343 and a NOR gate 344 instead of the NAND gate 333 and the multiplexer 322.
- the latch 342 latches the output of the NOT gate 332 of the comparison unit 181 (internal signal of the comparison unit 181).
- the latch 342 supplies a control signal (control signal SW1 and control signal SW2) corresponding to the value to the switching unit 183.
- the latch 342 generates a logical negation of the identification signal FLAG for identifying the slope gain for controlling the value of the counter 172 from the latched signal based on the control signal LATEN, and decodes the signal as a decoding gate (NOR gate 344). ).
- the AND gate 343 of the composite gate supplies the output of the NOT gate 332 of the comparison unit 181 (internal signal of the comparison unit 181) to the NOR gate 344 of the composite gate at a timing according to the control of the control signal VCOEN.
- the NOR gate 344 of the composite gate is an output of the NOT gate 332 of the comparison unit 181 (that is, a logic negation of the output VCO of the comparison unit 181) or a logic negation of a logic negation of the control signal FLAG, that is, an output VCO of the comparison unit 181 or A control signal FLAG is supplied to the counter 172 via a single signal line.
- the output VCO of the comparison unit 181 and the control signal FLAG can be transmitted to the counter 172 and the latch 324 through a common (mostly single) signal line. Further, since the increase in the number of electrodes 323 formed in one portion of the signal line can be suppressed, even when the comparison unit 181 and the counter 172 are formed on different semiconductor substrates, An increase in the area of the circuit can be suppressed.
- the column A / D converter 151 (that is, the image sensor 100) suppresses an increase in the area of the circuit and suppresses the development and manufacturing costs while suppressing the failure of the calculation, as in the example of FIG. Can be suppressed. Furthermore, an increase in power consumption can be suppressed.
- the two-stage configuration of the NAND gate 333 and the multiplexer 322 of the comparison unit 181 is replaced with a single-stage mixed gate as in the examples of FIGS.
- the power supply fluctuation due to the inversion of the comparison unit 331 can suppress the influence of noise caused by the power supply as compared with the case where a large number of logic circuits are connected in the subsequent stage, and the LATCH signal is also Can be acquired.
- an imaging element to which the present technology is applied can be realized, for example, as a package (chip) in which a semiconductor substrate is sealed, a module in which the package (chip) is installed on a circuit board, or the like.
- the imaging element in the package (chip) may be configured by a single semiconductor substrate, or may be configured by a plurality of semiconductor substrates superimposed on each other. It may be.
- FIG. 21 is a diagram illustrating an example of a physical configuration of the image sensor 100 which is an image sensor to which the present technology is applied.
- An image sensor 400 shown in FIG. 21 is an image sensor that captures a subject and obtains digital data of a captured image, as with each image sensor 100 described above in each embodiment.
- the image sensor 400 includes two semiconductor substrates (a laminated substrate (a pixel substrate 401 and a circuit substrate 402)) that are superposed on each other. That is, in the image sensor 400, the above-described circuit configuration of the image sensor 100 is formed on the multilayer substrate (the pixel substrate 401 and the circuit substrate 402).
- a pixel region 411 in which a plurality of unit pixels including a photoelectric conversion element that photoelectrically converts incident light is arranged is formed on the pixel substrate 401. Further, a peripheral circuit region 412 in which a peripheral circuit for processing a signal read from the pixel region 411 is formed is formed on the circuit board 402.
- the pixel substrate 401 and the circuit substrate 402 overlap each other to form a multilayer structure (laminated structure).
- Each pixel in the pixel region 411 formed on the pixel substrate 401 and a peripheral circuit in the peripheral circuit region 412 formed on the circuit substrate 402 are through vias formed in the via region (VIA) 413 and the via region (VIA) 414 ( VIA) etc. are electrically connected to each other.
- the number (number of layers) of the semiconductor substrates is arbitrary, and may be, for example, three or more layers.
- the plurality of semiconductor substrates on which the configuration of the image sensor 100 is arranged may not form a stacked structure.
- these semiconductor substrates may be arranged next to each other.
- the column A / D conversion unit 151 has been described as performing A / D conversion on a signal read from the unit pixel 141 of a single column.
- the signal A / D converted by the A / D converter 151 may be read from the unit pixel 141 belonging to an arbitrary unit pixel group assigned to itself.
- signals read from the unit pixels 141 of a plurality of columns of the pixel array 111 may be A / D converted.
- the column A / D conversion unit 151 may perform A / D conversion on a signal read from the unit pixel 141 belonging to the partial region of the pixel array 111 assigned to itself.
- the column A / D conversion unit 151 may perform A / D conversion on signals sequentially supplied from the unit pixels of all columns. That is, the present technology can also be applied to the A / D conversion unit 112.
- the present technology can be applied to devices other than the image sensor.
- the column A / D conversion unit 151 described above may be applied to any device other than the image sensor.
- the column A / D converter 151 may be an embodiment of a signal processing device to which the present technology is applied. That is, the analog signal that the column A / D conversion unit 151 performs A / D conversion is arbitrary, and the column A / D conversion unit 151 performs A / D conversion on signals other than the signal read from the unit pixel 141. It may be.
- the counter 172 may be configured in another device (for example, another semiconductor substrate). That is, the comparison unit 171 may be an embodiment of a signal processing device to which the present technology is applied.
- FIG. 22 is a block diagram illustrating a main configuration example of an imaging apparatus as an example of an electronic apparatus to which the present technology is applied.
- An imaging apparatus 600 shown in FIG. 22 is an apparatus that images a subject and outputs an image of the subject as an electrical signal.
- the imaging apparatus 600 includes an optical unit 611, a CMOS image sensor 612, an image processing unit 613, a display unit 614, a codec processing unit 615, a storage unit 616, an output unit 617, a communication unit 618, and a control unit 621. , An operation unit 622, and a drive 623.
- the optical unit 611 includes a lens that adjusts the focal point to the subject and collects light from the focused position, an aperture that adjusts exposure, a shutter that controls the timing of imaging, and the like.
- the optical unit 611 transmits light (incident light) from the subject and supplies the light to the CMOS image sensor 612.
- the CMOS image sensor 612 photoelectrically converts incident light, A / D converts a signal for each pixel (pixel signal), performs signal processing such as CDS, and supplies the processed captured image data to the image processing unit 613. .
- the image processing unit 613 performs image processing on the captured image data obtained by the CMOS image sensor 612. More specifically, the image processing unit 613 performs, for example, color mixture correction, black level correction, white balance adjustment, demosaic processing, matrix processing, gamma correction, on the captured image data supplied from the CMOS image sensor 612. And various image processing such as YC conversion.
- the image processing unit 613 supplies captured image data subjected to image processing to the display unit 614.
- the display unit 614 is configured as a liquid crystal display or the like, for example, and displays an image of captured image data (for example, an image of a subject) supplied from the image processing unit 613.
- the image processing unit 613 further supplies the captured image data subjected to the image processing to the codec processing unit 615 as necessary.
- the codec processing unit 615 subjects the captured image data supplied from the image processing unit 613 to encoding processing of a predetermined method, and supplies the obtained encoded data to the storage unit 616. Further, the codec processing unit 615 reads the encoded data recorded in the storage unit 616, decodes it to generate decoded image data, and supplies the decoded image data to the image processing unit 613.
- the image processing unit 613 performs predetermined image processing on the decoded image data supplied from the codec processing unit 615.
- the image processing unit 613 supplies the decoded image data subjected to the image processing to the display unit 614.
- the display unit 614 is configured as a liquid crystal display, for example, and displays an image of the decoded image data supplied from the image processing unit 613.
- the codec processing unit 615 supplies the encoded data obtained by encoding the captured image data supplied from the image processing unit 613 or the encoded data of the captured image data read from the storage unit 616 to the output unit 617. You may make it output outside the imaging device 600.
- the codec processing unit 615 supplies captured image data before encoding or decoded image data obtained by decoding encoded data read from the storage unit 616 to the output unit 617, and outputs the image data to the outside of the imaging device 600. You may make it output to.
- the codec processing unit 615 may transmit the captured image data, the encoded data of the captured image data, or the decoded image data to another device via the communication unit 618. Further, the codec processing unit 615 may acquire captured image data and encoded data of the image data via the communication unit 618. The codec processing unit 615 appropriately encodes and decodes the captured image data acquired through the communication unit 618 and the encoded data of the image data. The codec processing unit 615 supplies the obtained image data or encoded data to the image processing unit 613 as described above, or outputs it to the storage unit 616, the output unit 617, and the communication unit 618. May be.
- the storage unit 616 stores encoded data supplied from the codec processing unit 615 and the like.
- the encoded data stored in the storage unit 616 is read out and decoded by the codec processing unit 615 as necessary.
- the captured image data obtained by the decoding process is supplied to the display unit 614, and a captured image corresponding to the captured image data is displayed.
- the output unit 617 has an external output interface such as an external output terminal, and outputs various data supplied via the codec processing unit 615 to the outside of the imaging apparatus 600 via the external output interface.
- the communication unit 618 supplies various types of information such as image data and encoded data supplied from the codec processing unit 615 to another device that is a communication partner of predetermined communication (wired communication or wireless communication). Further, the communication unit 618 acquires various types of information such as image data and encoded data from another device that is a communication partner of predetermined communication (wired communication or wireless communication), and supplies the acquired information to the codec processing unit 615. .
- the control unit 621 controls the operation of each processing unit (each processing unit indicated by a dotted line 620, the operation unit 622, and the drive 623) of the imaging apparatus 600.
- the operation unit 622 includes, for example, an arbitrary input device such as a jog dial (trademark), a key, a button, or a touch panel.
- the operation unit 622 receives an operation input by a user or the like and supplies a signal corresponding to the operation input to the control unit 621. To do.
- the drive 623 reads information stored in a removable medium 624 attached to the drive 623 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory.
- the drive 623 reads various information such as programs and data from the removable medium 624 and supplies the information to the control unit 621.
- the drive 623 stores various information such as image data and encoded data supplied through the control unit 621 in the removable medium 624 when the writable removable medium 624 is attached to the drive 623. be able to.
- the present technology described above in each embodiment is applied.
- the image sensor 100 described above is used as the CMOS image sensor 612.
- the CMOS image sensor 612 can be more easily downsized, and an increase in development and manufacturing costs can be suppressed. Furthermore, an increase in power consumption can be suppressed.
- the CMOS image sensor 612 can be further reduced in size, and thus the imaging apparatus 600 can be easily reduced in size. it can.
- the CMOS image sensor 612 is downsized, design and manufacture become easier, and further, the cost of the CMOS image sensor 612 is reduced. Therefore, an increase in the cost of development and manufacturing of the imaging device 600 can be suppressed. . Furthermore, an increase in power consumption can be suppressed by reducing the power consumption of the CMOS image sensor 612.
- the series of processes described above can be executed by hardware or software.
- a program constituting the software is installed from a network or a recording medium.
- this recording medium includes a removable medium 624 on which the program is recorded, which is distributed to distribute the program to the user, separately from the apparatus main body.
- the removable medium 624 includes a magnetic disk (including a flexible disk) and an optical disk (including a CD-ROM and a DVD). Further, magneto-optical disks (including MD (Mini-Disc)) and semiconductor memories are also included.
- the program can be installed in the storage unit 616 by attaching the removable medium 624 to the drive 623.
- This program can also be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting. In that case, the program can be received by the communication unit 618 and installed in the storage unit 616.
- a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.
- the program can be received by the communication unit 618 and installed in the storage unit 616.
- this program can be installed in advance in a ROM (Read Only Memory) or the like in the storage unit 616 or the control unit 621.
- the program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.
- the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.
- each step described above can be executed in each device described above or any device other than each device described above.
- the device that executes the process may have the functions (functional blocks and the like) necessary for executing the process described above.
- Information necessary for processing may be transmitted to the apparatus as appropriate.
- the system means a set of a plurality of components (devices, modules (parts), etc.), and it does not matter whether all the components are in the same housing. Accordingly, a plurality of devices housed in separate housings and connected via a network and a single device housing a plurality of modules in one housing are all systems. .
- the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units).
- the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit).
- a configuration other than that described above may be added to the configuration of each device (or each processing unit).
- a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). .
- the present technology can take a configuration of cloud computing in which one function is shared by a plurality of devices via a network and is jointly processed.
- each step described in the above flowchart can be executed by one device or can be shared by a plurality of devices.
- the plurality of processes included in the one step can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.
- the present technology is not limited to this, and any configuration mounted on such a device or a device constituting the system, for example, a processor as a system LSI (Large Scale Integration), a module using a plurality of processors, a plurality of It is also possible to implement as a unit using other modules, a set obtained by further adding other functions to the unit (that is, a partial configuration of the apparatus), and the like.
- a processor as a system LSI (Large Scale Integration)
- a module using a plurality of processors a plurality of It is also possible to implement as a unit using other modules, a set obtained by further adding other functions to the unit (that is, a partial configuration of the apparatus), and the like.
- this technique can also take the following structures.
- a comparison unit that compares the signal level of the analog signal with the signal level of the reference signal;
- a selection unit that selects a reference signal to be supplied to the comparison unit from a plurality of reference signals;
- a switching unit capable of switching a signal line connected to the input terminal of the comparison unit so as to connect a signal line to which the reference signal selected by the selection unit is transmitted to the input terminal of the comparison unit;
- the comparison unit has an input terminal of a floating node,
- the selection unit has a signal line in which parasitic capacitance is generated between the input unit of the floating node of the comparison unit,
- the signal line of the selection unit transmits signals having the same signal level in the comparison performed a plurality of times by the comparison unit.
- the comparison unit sequentially compares the signal level of the reset signal read from the unit pixel and the signal levels of the plurality of reference signals,
- the selection unit selects any one of the plurality of reference signals according to a signal level of a pixel signal read from the unit pixel,
- the switching unit switches a signal line connected to the input terminal of the comparison unit as necessary so that a signal line through which the reference signal selected by the selection unit is transmitted is connected to the input terminal of the comparison unit.
- the comparison unit further compares the signal level of the pixel signal with the signal level of the reference signal selected by the selection unit,
- the signal line of the selection unit compares the signal level of the reset signal with the signal level of the reference signal selected by the selection unit by the comparison unit, and the signal level of the pixel signal and the signal of the reference signal.
- the comparison unit initializes and sequentially compares the signal level of the reset signal read from the unit pixel and the signal level of each of the plurality of reference signals, and the signal level of the pixel signal read from the unit pixel Compare with the signal level of a given reference signal,
- the selection unit selects any one of the plurality of reference signals based on a result of comparison between a signal level of the pixel signal and a signal level of a predetermined reference signal by the comparison unit,
- the switching unit switches a signal line connected to the input terminal of the comparison unit as necessary so that a signal line through which the reference signal selected by the selection unit is transmitted is connected to the input terminal of the comparison unit.
- the comparison unit further compares the signal level of the pixel signal with the signal level of the reference signal selected by the selection unit,
- the signal lines of the selection unit have the same signal level both in the initialization of the comparison unit and in the comparison between the signal level of the pixel signal and the signal level of a predetermined reference signal by the comparison unit.
- the signal processing device according to any one of (1) to (3), which transmits a signal.
- the signal processing device according to (4), wherein a signal level of a signal transmitted through the signal line of the selection unit indicates a reference signal selected by the selection unit.
- the selection unit selects a reference signal to be supplied to the comparison unit from a plurality of reference signals based on a result of the comparison performed by the comparison unit.
- a signal processing device (1) to (5) A signal processing device according to 1. (7) It further includes a measurement unit that measures a time until the result of the comparison performed by the comparison unit changes, and outputs the measurement result as an A / D conversion result of the analog signal (1) to (6) The signal processing device according to any one of the above. (8) The comparison unit compares the signal level of the analog signal read from the unit pixel belonging to the unit pixel group assigned to the pixel array with the signal level of the reference signal. ) To (7).
- (9) a pixel array in which unit pixels are arranged in a matrix;
- a comparison unit that compares a signal level of an analog signal read from the unit pixel of the pixel array with a signal level of a reference signal;
- a selection unit that selects a reference signal to be supplied to the comparison unit from a plurality of reference signals;
- a switching unit capable of switching a signal line connected to the input terminal of the comparison unit so as to connect a signal line to which the reference signal selected by the selection unit is transmitted to the input terminal of the comparison unit;
- the comparison unit has an input terminal of a floating node,
- the selection unit has a signal line in which parasitic capacitance is generated between the input unit of the floating node of the comparison unit,
- the signal line of the selection unit transmits signals having the same signal level in the comparison performed a plurality of times by the comparison unit.
- an imaging unit for imaging a subject An image processing unit that performs image processing on image data obtained by imaging by the imaging unit,
- the imaging unit A pixel array in which unit pixels are arranged in a matrix;
- a comparison unit that compares a signal level of an analog signal read from the unit pixel of the pixel array with a signal level of a reference signal;
- a selection unit that selects a reference signal to be supplied to the comparison unit from a plurality of reference signals;
- a switching unit capable of switching a signal line connected to the input terminal of the comparison unit so as to connect a signal line to which the reference signal selected by the selection unit is transmitted to the input terminal of the comparison unit;
- the comparison unit has an input terminal of a floating node,
- the selection unit has a signal line in which parasitic capacitance is generated between the input unit of the floating node of the comparison unit,
- the signal line of the selection unit transmits electronic signals having the same signal level in the comparison performed a plurality of times by the comparison unit.
- a comparison unit that compares the signal level of the analog signal with the signal level of the reference signal
- a selection unit that selects a reference signal to be supplied to the comparison unit from a plurality of reference signals
- a switching unit capable of switching a signal line connected to the comparison unit so as to connect a signal line on which a reference signal selected by the selection unit is transmitted to the comparison unit
- a mixing unit that mixes a signal indicating the result of the comparison by the comparison unit and a signal indicating the reference signal selected by the selection unit; Measure the time until the value of the signal indicating the result of the comparison by the comparison unit changes, included in the signal output from the mixing unit and transmitted via a single signal line, A measurement unit that outputs the analog signal as an A / D conversion result;
- a control unit for controlling the measurement of the measurement unit based on a signal indicating the reference signal selected by the selection unit included in a signal output from the mixing unit and transmitted through a single signal line;
- a signal processing apparatus comprising: (12) The mixing unit transmits a signal indicating
- the signal processing device (11). (13)
- the comparison unit sequentially compares the signal level of the reset signal read from the unit pixel with the signal level of each of the plurality of reference signals, and the signal level of the pixel signal read from the unit pixel and a predetermined reference Compare with the signal level of the signal,
- the selection unit selects any one of the plurality of reference signals;
- the switching unit switches the signal line connected to the comparison unit as necessary so as to connect the signal line on which the reference signal selected by the selection unit is transmitted to the comparison unit,
- the comparison unit further compares the signal level of the pixel signal with the signal level of the reference signal selected by the selection unit,
- the mixing unit includes: In the period in which the comparison unit compares the signal level of the reset signal and the signal level of each reference signal, a signal indicating the result of the comparison is transmitted via the single signal line, In a period in which the comparison unit compares the signal level of the pixel signal with the signal level of a predetermined reference signal, a signal indicating the reference signal selected by the
- the comparison unit includes: A signal comparison unit that compares the signal level of the analog signal with the signal level of the reference signal; A logic negation unit for inverting the result of the comparison by the signal comparison unit; A negative logical product part for obtaining a negative logical product of the output of the logical negative part and a predetermined control signal, and The signal processing apparatus according to any one of (11) to (13), wherein the mixing unit mixes an output of the NAND circuit and a signal indicating a reference signal selected by the selection unit.
- the comparison unit includes: A signal comparison unit that compares the signal level of the analog signal with the signal level of the reference signal; A logic negation unit for inverting the result of the comparison by the signal comparison unit,
- the mixing unit includes: A logical product unit for obtaining a logical product of the output of the logical negation unit and a predetermined control signal;
- the signal processing device according to any one of (11) to (14), further comprising: a negative logical sum unit that obtains a negative logical sum of an output of the logical product unit and a signal indicating the reference signal selected by the selection unit .
- the selection unit selects a reference signal to be supplied to the comparison unit from a plurality of reference signals according to a result of the comparison performed by the comparison unit. Signal processing equipment.
- the comparison unit compares the signal level of the analog signal read from the unit pixel belonging to the unit pixel group assigned to the pixel array with the signal level of the reference signal.
- the signal processing device according to any one of (16).
- the comparison unit, the selection unit, the switching unit, and the mixing unit, and the measurement unit and the control unit are formed on different semiconductor substrates. (11) to (17) The signal processing apparatus as described.
- a pixel array in which unit pixels are arranged in a matrix;
- a comparison unit that compares the signal level of the analog signal read from the unit pixel of the pixel array with the signal level of the reference signal;
- a selection unit that selects a reference signal to be supplied to the comparison unit from a plurality of reference signals;
- a switching unit capable of switching a signal line connected to the comparison unit so as to connect a signal line on which a reference signal selected by the selection unit is transmitted to the comparison unit;
- a mixing unit that mixes a signal indicating the result of the comparison by the comparison unit and a signal indicating the reference signal selected by the selection unit; Measure the time until the value of the signal indicating the result of the comparison by the comparison unit changes, included in the signal output from the mixing unit and transmitted via a single signal line, A measurement unit that outputs the analog signal as an A / D conversion result;
- a control unit for controlling the measurement of the measurement unit based on a signal indicating the reference signal selected by the selection unit included in a signal output from the mixing
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Abstract
Description
1.第1の実施の形態(イメージセンサ)
2.第2の実施の形態(イメージセンサ)
3.第3の実施の形態(イメージセンサ)
4.第4の実施の形態(イメージセンサ)
5.第5の実施の形態(撮像装置)
<寄生容量とカップリング電圧変動>
従来、一般的なイメージセンサでは、例えばフォトダイオード等の受光部に蓄積された電荷が信号として読み出され、A/D(Analog / Digital)変換されていた。このA/D変換は、一般的に、受光部を有する画素から読み出された信号がランプ波等の参照電圧と比較され、その比較結果が変化するまでの時間を計測することにより行われる。
そこで、複数の参照信号の中から比較部に供給する参照信号を選択する選択部が有する信号線であって、比較部のフローティングノードの入力端子との間に寄生容量が生じる信号線が、その比較部により複数回行われる比較の各回において、信号レベルが互いに同一である信号を伝送するようにする。例えば、図5の例のようにA/D変換を行う場合、図6に示されるように、CDSのリセット期間と信号読み出し期間の両方における比較において、信号SWFBの値が互いに同一となるようにする。
このような本技術を適用した撮像素子(信号処理装置)の一実施の形態であるイメージセンサの主な構成例を、図7に示す。図7に示されるイメージセンサ100は、被写体からの光を光電変換して画像データとして出力するデバイスである。例えば、イメージセンサ100は、CMOS(Complementary Metal Oxide Semiconductor)を用いたCMOSイメージセンサ、CCD(Charge Coupled Device)を用いたCCDイメージセンサ等として構成される。
図8は、単位画素141の回路構成の主な構成の例を示す図である。図8に示されるように、単位画素141は、フォトダイオード(PD)161、転送トランジスタ162、リセットトランジスタ163、増幅トランジスタ164、およびセレクトトランジスタ165を有する。
次に、図9を参照して、カラムA/D変換部151の構成例について説明する。図9に示されるように、カラムA/D変換部151は、比較部171およびカウンタ172を有する。
選択部182の主な構成例を図10に示す。図10に示されるように選択部182の判定部191は、NOTゲート201、ラッチ202、およびスイッチ203を有する。NOTゲート201は、1ビットのデジタルデータである比較部181の出力Vcoを反転する。ラッチ202は、そのNOTゲート201の出力を、A/D変換制御部123から供給される制御信号Φfbに応じたタイミングで保持し、その保持した値を出力する(JUD)。
次に、このカラムA/D変換部151によるA/D変換の例について説明する。カラムA/D変換部151は、図11に示されるタイミングチャートのような流れでA/D変換を行う。つまり、カラムA/D変換部151は、まず、CDSのリセット期間において、高ゲインスロープの参照信号Vref1を用いて、単位画素141から読み出されたリセット信号のA/D変換を行い、信号N1(HG)を得る(高精度ノイズ出力)。次に、カラムA/D変換部151は、CDSのリセット期間において、低ゲインスロープの参照信号Vref2を用いて、単位画素141から読み出されたリセット信号のA/D変換を行い、信号N2(LG)を得る(低精度ノイズ出力)。次に、カラムA/D変換部151は、単位画素141から読み出された画素信号の信号レベルを判定する(判定)。カラムA/D変換部151は、その判定結果に応じて参照信号Vref1若しくは参照信号Vref2を選択し、CDSの信号読み出し期間において、その選択した参照信号を用いて、単位画素141から読み出された画素信号の信号レベルのA/D変換を行い、信号S1(HG)若しくは信号S2(LG)を得る(信号出力)。
<比較部初期化と判定時>
第1の実施の形態においては、リセット信号の比較と画素信号の比較とにおいて、カップリング電圧変動量が変化することにより生じる誤差の抑制について説明した。同様に、比較部11の初期化完了時と画素信号の信号レベル判定完了時とにおいて、比較部11のフローティングノードが受けるカップリング電圧変動量が変化すると、それが判定誤差要因となってしまうおそれがあった。
そこで、複数の参照信号の中から比較部のフローティングノードの入力端子に供給する参照信号を選択する選択部が有する信号線であって、比較部のフローティングノードの入力端子との間に寄生容量が生じる信号線が、その比較部の初期化と、その比較部による画素信号の信号レベルと所定の参照信号の信号レベルとの比較との両方において、信号レベルが互いに同一である信号を伝送するようにする。例えば、図5の例のようにA/D変換を行う場合、図13に示されるように、初期化の期間(コンパレータ初期化)と、画素信号の信号レベル判定の期間(照度判定)の両方において、信号SWFBの値が互いに同一となるようにする。
このようにする場合、カラムA/D変換部151が、図14に示されるタイミングチャートのようにA/D変換を行うようにすればよい。
<比較部とカウンタとの接続>
上述した各実施の形態においては、説明の便宜上、比較部171(比較部181)とカウンタ172との間の信号線を1本の線で接続するように示したが、実際には、比較部171(比較部181)とカウンタ172とは、例えば、図15の例のように、複数本の信号線で接続される。
そこで、混合部が、比較部による比較の結果を示す信号と、選択部により選択された参照信号を示す信号とを混合し、計測部が、その混合部から出力され、単一の信号線を介して伝送される信号に含まれる、比較部による比較の結果を示す信号の値が変化するまでの時間を計測し、その計測結果をアナログ信号のA/D変換結果として出力し、制御部が、混合部から出力され、単一の信号線を介して伝送される信号に含まれる、選択部により選択された参照信号を示す信号に基づいて、計測部の計測を制御するようにする。
この場合のイメージセンサ100の構成は、基本的に、上述した各実施の形態の場合と同様である。以下においてはイメージセンサ100の構成や動作について説明すべき部分についてのみ説明を行い、説明を省略する部分については、以上の各実施の形態における説明を適用することができるか、若しくは、任意の構成や動作を適用することができるものとする。
この場合の比較部181の主な構成例を図18に示す。比較部181は、例えば、比較部331、NOTゲート332、およびNANDゲート333を用いて、図18に示されるように構成される。
イメージセンサ100(カラムA/D変換部151)は、この場合も、上述した各実施の形態の場合と同様にA/D変換を行う。そして、マルチプレクサ322は、図19に示されるように、CDSのリセット期間(P相およびP相2)と信号読み出し期間(D相)において比較部181の出力Vcoを出力し、画素信号の信号レベルの判定期間において制御信号FLAGを出力する。
以上においては、図18に示されるような構成の比較部181のNANDゲート333の出力を制御信号FLAGと混合するように説明したが、カラムA/D変換部151の構成例はこの例に限定されない。
<イメージセンサの物理構成>
なお、本技術を適用する撮像素子は、例えば、半導体基板が封止されたパッケージ(チップ)やそのパッケージ(チップ)が回路基板に設置されたモジュール等として実現することができる。例えば、パッケージ(チップ)として実現する場合、そのパッケージ(チップ)において撮像素子が、単一の半導体基板により構成されるようにしてもよいし、互いに重畳される複数の半導体基板により構成されるようにしてもよい。
<撮像装置>
例えば、撮像装置のような、撮像素子を有する装置(電子機器等)に本技術を適用するようにしてもよい。図22は、本技術を適用した電子機器の一例としての撮像装置の主な構成例を示すブロック図である。図22に示される撮像装置600は、被写体を撮像し、その被写体の画像を電気信号として出力する装置である。
(1) アナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部の入力端子に接続するように、前記比較部の入力端子に接続する信号線を切り替えることができる切替部と
を備え、
前記比較部は、フローティングノードの入力端子を有し、
前記選択部は、前記比較部の前記フローティングノードの入力端子との間に寄生容量が生じる信号線を有し、
前記選択部の前記信号線は、前記比較部により複数回行われる前記比較において、信号レベルが互いに同一である信号を伝送する
信号処理装置。
(2) 前記比較部は、単位画素から読み出されるリセット信号の信号レベルと複数の参照信号のそれぞれの信号レベルとの比較を順次行い、
前記選択部は、前記単位画素から読み出される画素信号の信号レベルに応じて前記複数の参照信号のうちのいずれか1つを選択し、
前記切替部は、前記選択部により選択された参照信号が伝送される信号線を前記比較部の入力端子に接続するように、前記比較部の入力端子に接続する信号線を必要に応じて切り替え、
前記比較部は、さらに、前記画素信号の信号レベルと前記選択部により選択された前記参照信号の信号レベルとの比較を行い、
前記選択部の前記信号線は、前記比較部による、前記リセット信号の信号レベルと前記選択部により選択される参照信号の信号レベルとの比較と、前記画素信号の信号レベルと前記参照信号の信号レベルとの比較との両方において、信号レベルが互いに同一である信号を伝送する
(1)に記載の信号処理装置。
(3) 前記選択部の前記信号線を介して伝送される信号の信号レベルは、前記選択部により選択される参照信号を示す
(2)に記載の信号処理装置。
(4) 前記比較部は、初期化し、単位画素から読み出されるリセット信号の信号レベルと複数の参照信号のそれぞれの信号レベルとの比較を順次行い、前記単位画素から読み出される画素信号の信号レベルと所定の参照信号の信号レベルとの比較を行い、
前記選択部は、前記比較部による、前記画素信号の信号レベルと所定の参照信号の信号レベルとの比較の結果に基づいて、前記複数の参照信号のうちのいずれか1つを選択し、
前記切替部は、前記選択部により選択された参照信号が伝送される信号線を前記比較部の入力端子に接続するように、前記比較部の入力端子に接続する信号線を必要に応じて切り替え、
前記比較部は、さらに、前記画素信号の信号レベルと前記選択部により選択された前記参照信号の信号レベルとの比較を行い、
前記選択部の前記信号線は、前記比較部の初期化と、前記比較部による前記画素信号の信号レベルと所定の参照信号の信号レベルとの比較との両方において、信号レベルが互いに同一である信号を伝送する
(1)乃至(3)のいずれかに記載の信号処理装置。
(5) 前記選択部の前記信号線を介して伝送される信号の信号レベルは、前記選択部により選択される参照信号を示す
(4)に記載の信号処理装置。
(6) 前記選択部は、前記比較部により行われる前記比較の結果に基づいて、複数の参照信号の中から前記比較部に供給する参照信号を選択する
(1)乃至(5)のいずれかに記載の信号処理装置。
(7) 前記比較部により行われる前記比較の結果が変化するまでの時間を計測し、計測結果を前記アナログ信号のA/D変換結果として出力する計測部をさらに備える
(1)乃至(6)のいずれかに記載の信号処理装置。
(8) 前記比較部は、画素アレイの、自身に割り当てられた単位画素群に属する単位画素から読み出された前記アナログ信号の信号レベルと、前記参照信号の信号レベルとの比較を行う
(1)乃至(7)のいずれかに記載の信号処理装置。
(9) 単位画素が行列状に配置される画素アレイと、
前記画素アレイの前記単位画素から読み出されるアナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部の入力端子に接続するように、前記比較部の入力端子に接続する信号線を切り替えることができる切替部と
を備え、
前記比較部は、フローティングノードの入力端子を有し、
前記選択部は、前記比較部の前記フローティングノードの入力端子との間に寄生容量が生じる信号線を有し、
前記選択部の前記信号線は、前記比較部により複数回行われる前記比較において、信号レベルが互いに同一である信号を伝送する
撮像素子。
(10) 被写体を撮像する撮像部と、
前記撮像部による撮像により得られた画像データを画像処理する画像処理部と
を備え、
前記撮像部は、
単位画素が行列状に配置される画素アレイと、
前記画素アレイの前記単位画素から読み出されるアナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部の入力端子に接続するように、前記比較部の入力端子に接続する信号線を切り替えることができる切替部と
を備え、
前記比較部は、フローティングノードの入力端子を有し、
前記選択部は、前記比較部の前記フローティングノードの入力端子との間に寄生容量が生じる信号線を有し、
前記選択部の前記信号線は、前記比較部により複数回行われる前記比較において、信号レベルが互いに同一である信号を伝送する
電子機器。
(11) アナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部に接続するように、前記比較部に接続する信号線を切り替えることができる切替部と、
前記比較部による前記比較の結果を示す信号と、前記選択部により選択された参照信号を示す信号とを混合する混合部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記比較部による前記比較の結果を示す信号の値が変化するまでの時間を計測し、計測結果を前記アナログ信号のA/D変換結果として出力する計測部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記選択部により選択された参照信号を示す信号に基づいて、前記計測部の計測を制御する制御部と
を備える信号処理装置。
(12) 前記混合部は、前記比較部による比較の結果を示す信号と、前記選択部により選択された参照信号を示す信号とを、互いに異なる期間に、前記単一の信号線を介して伝送させる
(11)に記載の信号処理装置。
(13) 前記比較部は、単位画素から読み出されるリセット信号の信号レベルと複数の参照信号のそれぞれの信号レベルとの比較を順次行い、前記単位画素から読み出される画素信号の信号レベルと所定の参照信号の信号レベルとの比較を行い、
前記選択部は、前記複数の参照信号のうちのいずれか1つを選択し、
前記切替部は、前記選択部により選択された参照信号が伝送される信号線を前記比較部に接続するように、前記比較部に接続する信号線を必要に応じて切り替え、
前記比較部は、さらに、前記画素信号の信号レベルと前記選択部により選択された前記参照信号の信号レベルとの比較を行い、
前記混合部は、
前記比較部が前記リセット信号の信号レベルと各参照信号の信号レベルとの比較を行う期間において、前記比較の結果を示す信号を前記単一の信号線を介して伝送させ、
前記比較部が前記画素信号の信号レベルと所定の参照信号の信号レベルとの比較を行う期間において、前記選択部により選択された参照信号を示す信号を前記単一の信号線を介して伝送させ、
前記比較部が前記画素信号の信号レベルと前記選択部により選択された前記参照信号の信号レベルとの比較を行う期間において、前記比較の結果を示す信号を前記単一の信号線を介して伝送させる
(12)に記載の信号処理装置。
(14) 前記比較部は、
前記アナログ信号の信号レベルと前記参照信号の信号レベルとの比較を行う信号比較部と、
前記信号比較部による前記比較の結果を反転させる論理否定部と、
前記論理否定部の出力と所定の制御信号との否定論理積を求める否定論理積部と
を備え、
前記混合部は、前記否定論理積部の出力と、前記選択部により選択された参照信号を示す信号とを混合する
(11)乃至(13)のいずれかに記載の信号処理装置。
(15) 前記比較部は、
前記アナログ信号の信号レベルと前記参照信号の信号レベルとの比較を行う信号比較部と、
前記信号比較部による前記比較の結果を反転させる論理否定部と
を備え、
前記混合部は、
前記論理否定部の出力と所定の制御信号との論理積を求める論理積部と、
前記論理積部の出力と、前記選択部により選択された参照信号を示す信号との否定論理和を求める否定論理和部と
を備える(11)乃至(14)のいずれかに記載の信号処理装置。
(16) 前記選択部は、前記比較部による前記比較の結果に応じて、複数の参照信号の中から前記比較部に供給する参照信号を選択する
(11)乃至(15)のいずれかに記載の信号処理装置。
(17) 前記比較部は、画素アレイの、自身に割り当てられた単位画素群に属する単位画素から読み出された前記アナログ信号の信号レベルと参照信号の信号レベルとの比較を行う
(11)乃至(16)のいずれかに記載の信号処理装置。
(18) 前記比較部、前記選択部、前記切替部、および前記混合部と、前記計測部および前記制御部とが、互いに異なる半導体基板に形成される
(11)乃至(17)のいずれかに記載の信号処理装置。
(19) 単位画素が行列状に配置される画素アレイと、
前記画素アレイの前記単位画素から読み出されたアナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部に接続するように、前記比較部に接続する信号線を切り替えることができる切替部と、
前記比較部による前記比較の結果を示す信号と、前記選択部により選択された参照信号を示す信号とを混合する混合部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記比較部による前記比較の結果を示す信号の値が変化するまでの時間を計測し、計測結果を前記アナログ信号のA/D変換結果として出力する計測部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記選択部により選択された参照信号を示す信号に基づいて、前記計測部の計測を制御する制御部と
を備える撮像素子。
(20) 被写体を撮像する撮像部と、
前記撮像部による撮像により得られた画像データを画像処理する画像処理部と
を備え、
前記撮像部は、
単位画素が行列状に配置される画素アレイと、
前記画素アレイの前記単位画素から読み出されたアナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部に接続するように、前記比較部に接続する信号線を切り替えることができる切替部と、
前記比較部による前記比較の結果を示す信号と、前記選択部により選択された参照信号を示す信号とを混合する混合部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記比較部による前記比較の結果を示す信号の値が変化するまでの時間を計測し、計測結果を前記アナログ信号のA/D変換結果として出力する計測部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記選択部により選択された参照信号を示す信号に基づいて、前記計測部の計測を制御する制御部と
を備える電子機器。
Claims (20)
- アナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部の入力端子に接続するように、前記比較部の入力端子に接続する信号線を切り替えることができる切替部と
を備え、
前記比較部は、フローティングノードの入力端子を有し、
前記選択部は、前記比較部の前記フローティングノードの入力端子との間に寄生容量が生じる信号線を有し、
前記選択部の前記信号線は、前記比較部により複数回行われる前記比較において、信号レベルが互いに同一である信号を伝送する
信号処理装置。 - 前記比較部は、単位画素から読み出されるリセット信号の信号レベルと複数の参照信号のそれぞれの信号レベルとの比較を順次行い、
前記選択部は、前記単位画素から読み出される画素信号の信号レベルに応じて前記複数の参照信号のうちのいずれか1つを選択し、
前記切替部は、前記選択部により選択された参照信号が伝送される信号線を前記比較部の入力端子に接続するように、前記比較部の入力端子に接続する信号線を必要に応じて切り替え、
前記比較部は、さらに、前記画素信号の信号レベルと前記選択部により選択された前記参照信号の信号レベルとの比較を行い、
前記選択部の前記信号線は、前記比較部による、前記リセット信号の信号レベルと前記選択部により選択される参照信号の信号レベルとの比較と、前記画素信号の信号レベルと前記参照信号の信号レベルとの比較との両方において、信号レベルが互いに同一である信号を伝送する
請求項1に記載の信号処理装置。 - 前記選択部の前記信号線を介して伝送される信号の信号レベルは、前記選択部により選択される参照信号を示す
請求項2に記載の信号処理装置。 - 前記比較部は、初期化し、単位画素から読み出されるリセット信号の信号レベルと複数の参照信号のそれぞれの信号レベルとの比較を順次行い、前記単位画素から読み出される画素信号の信号レベルと所定の参照信号の信号レベルとの比較を行い、
前記選択部は、前記比較部による、前記画素信号の信号レベルと所定の参照信号の信号レベルとの比較の結果に基づいて、前記複数の参照信号のうちのいずれか1つを選択し、
前記切替部は、前記選択部により選択された参照信号が伝送される信号線を前記比較部の入力端子に接続するように、前記比較部の入力端子に接続する信号線を必要に応じて切り替え、
前記比較部は、さらに、前記画素信号の信号レベルと前記選択部により選択された前記参照信号の信号レベルとの比較を行い、
前記選択部の前記信号線は、前記比較部の初期化と、前記比較部による前記画素信号の信号レベルと所定の参照信号の信号レベルとの比較との両方において、信号レベルが互いに同一である信号を伝送する
請求項1に記載の信号処理装置。 - 前記選択部の前記信号線を介して伝送される信号の信号レベルは、前記選択部により選択される参照信号を示す
請求項4に記載の信号処理装置。 - 前記選択部は、前記比較部により行われる前記比較の結果に基づいて、複数の参照信号の中から前記比較部に供給する参照信号を選択する
請求項1に記載の信号処理装置。 - 前記比較部により行われる前記比較の結果が変化するまでの時間を計測し、計測結果を前記アナログ信号のA/D変換結果として出力する計測部をさらに備える
請求項1に記載の信号処理装置。 - 前記比較部は、画素アレイの、自身に割り当てられた単位画素群に属する単位画素から読み出された前記アナログ信号の信号レベルと、前記参照信号の信号レベルとの比較を行う
請求項1に記載の信号処理装置。 - 単位画素が行列状に配置される画素アレイと、
前記画素アレイの前記単位画素から読み出されるアナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部の入力端子に接続するように、前記比較部の入力端子に接続する信号線を切り替えることができる切替部と
を備え、
前記比較部は、フローティングノードの入力端子を有し、
前記選択部は、前記比較部の前記フローティングノードの入力端子との間に寄生容量が生じる信号線を有し、
前記選択部の前記信号線は、前記比較部により複数回行われる前記比較において、信号レベルが互いに同一である信号を伝送する
撮像素子。 - 被写体を撮像する撮像部と、
前記撮像部による撮像により得られた画像データを画像処理する画像処理部と
を備え、
前記撮像部は、
単位画素が行列状に配置される画素アレイと、
前記画素アレイの前記単位画素から読み出されるアナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部の入力端子に接続するように、前記比較部の入力端子に接続する信号線を切り替えることができる切替部と
を備え、
前記比較部は、フローティングノードの入力端子を有し、
前記選択部は、前記比較部の前記フローティングノードの入力端子との間に寄生容量が生じる信号線を有し、
前記選択部の前記信号線は、前記比較部により複数回行われる前記比較において、信号レベルが互いに同一である信号を伝送する
電子機器。 - アナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部に接続するように、前記比較部に接続する信号線を切り替えることができる切替部と、
前記比較部による前記比較の結果を示す信号と、前記選択部により選択された参照信号を示す信号とを混合する混合部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記比較部による前記比較の結果を示す信号の値が変化するまでの時間を計測し、計測結果を前記アナログ信号のA/D変換結果として出力する計測部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記選択部により選択された参照信号を示す信号に基づいて、前記計測部の計測を制御する制御部と
を備える信号処理装置。 - 前記混合部は、前記比較部による比較の結果を示す信号と、前記選択部により選択された参照信号を示す信号とを、互いに異なる期間に、前記単一の信号線を介して伝送させる
請求項11に記載の信号処理装置。 - 前記比較部は、単位画素から読み出されるリセット信号の信号レベルと複数の参照信号のそれぞれの信号レベルとの比較を順次行い、前記単位画素から読み出される画素信号の信号レベルと所定の参照信号の信号レベルとの比較を行い、
前記選択部は、前記複数の参照信号のうちのいずれか1つを選択し、
前記切替部は、前記選択部により選択された参照信号が伝送される信号線を前記比較部に接続するように、前記比較部に接続する信号線を必要に応じて切り替え、
前記比較部は、さらに、前記画素信号の信号レベルと前記選択部により選択された前記参照信号の信号レベルとの比較を行い、
前記混合部は、
前記比較部が前記リセット信号の信号レベルと各参照信号の信号レベルとの比較を行う期間において、前記比較の結果を示す信号を前記単一の信号線を介して伝送させ、
前記比較部が前記画素信号の信号レベルと所定の参照信号の信号レベルとの比較を行う期間において、前記選択部により選択された参照信号を示す信号を前記単一の信号線を介して伝送させ、
前記比較部が前記画素信号の信号レベルと前記選択部により選択された前記参照信号の信号レベルとの比較を行う期間において、前記比較の結果を示す信号を前記単一の信号線を介して伝送させる
請求項12に記載の信号処理装置。 - 前記比較部は、
前記アナログ信号の信号レベルと前記参照信号の信号レベルとの比較を行う信号比較部と、
前記信号比較部による前記比較の結果を反転させる論理否定部と、
前記論理否定部の出力と所定の制御信号との否定論理積を求める否定論理積部と
を備え、
前記混合部は、前記否定論理積部の出力と、前記選択部により選択された参照信号を示す信号とを混合する
請求項11に記載の信号処理装置。 - 前記比較部は、
前記アナログ信号の信号レベルと前記参照信号の信号レベルとの比較を行う信号比較部と、
前記信号比較部による前記比較の結果を反転させる論理否定部と
を備え、
前記混合部は、
前記論理否定部の出力と所定の制御信号との論理積を求める論理積部と、
前記論理積部の出力と、前記選択部により選択された参照信号を示す信号との否定論理和を求める否定論理和部と
を備える請求項11に記載の信号処理装置。 - 前記選択部は、前記比較部による前記比較の結果に応じて、複数の参照信号の中から前記比較部に供給する参照信号を選択する
請求項11に記載の信号処理装置。 - 前記比較部は、画素アレイの、自身に割り当てられた単位画素群に属する単位画素から読み出された前記アナログ信号の信号レベルと参照信号の信号レベルとの比較を行う
請求項11に記載の信号処理装置。 - 前記比較部、前記選択部、前記切替部、および前記混合部と、前記計測部および前記制御部とが、互いに異なる半導体基板に形成される
請求項11に記載の信号処理装置。 - 単位画素が行列状に配置される画素アレイと、
前記画素アレイの前記単位画素から読み出されたアナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部に接続するように、前記比較部に接続する信号線を切り替えることができる切替部と、
前記比較部による前記比較の結果を示す信号と、前記選択部により選択された参照信号を示す信号とを混合する混合部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記比較部による前記比較の結果を示す信号の値が変化するまでの時間を計測し、計測結果を前記アナログ信号のA/D変換結果として出力する計測部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記選択部により選択された参照信号を示す信号に基づいて、前記計測部の計測を制御する制御部と
を備える撮像素子。 - 被写体を撮像する撮像部と、
前記撮像部による撮像により得られた画像データを画像処理する画像処理部と
を備え、
前記撮像部は、
単位画素が行列状に配置される画素アレイと、
前記画素アレイの前記単位画素から読み出されたアナログ信号の信号レベルと参照信号の信号レベルとの比較を行う比較部と、
複数の参照信号の中から前記比較部に供給する参照信号を選択する選択部と、
前記選択部により選択された参照信号が伝送される信号線を前記比較部に接続するように、前記比較部に接続する信号線を切り替えることができる切替部と、
前記比較部による前記比較の結果を示す信号と、前記選択部により選択された参照信号を示す信号とを混合する混合部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記比較部による前記比較の結果を示す信号の値が変化するまでの時間を計測し、計測結果を前記アナログ信号のA/D変換結果として出力する計測部と、
前記混合部から出力され、単一の信号線を介して伝送される信号に含まれる、前記選択部により選択された参照信号を示す信号に基づいて、前記計測部の計測を制御する制御部と
を備える電子機器。
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