WO2016063608A1 - Cellule solaire à contact arrière à hétérojonction et son procédé de fabrication - Google Patents

Cellule solaire à contact arrière à hétérojonction et son procédé de fabrication Download PDF

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Publication number
WO2016063608A1
WO2016063608A1 PCT/JP2015/073572 JP2015073572W WO2016063608A1 WO 2016063608 A1 WO2016063608 A1 WO 2016063608A1 JP 2015073572 W JP2015073572 W JP 2015073572W WO 2016063608 A1 WO2016063608 A1 WO 2016063608A1
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type amorphous
film
amorphous semiconductor
semiconductor film
back contact
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PCT/JP2015/073572
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English (en)
Japanese (ja)
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親扶 岡本
正道 小林
田所　宏之
健 稗田
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a hetero back contact solar cell and a method for manufacturing the same.
  • FIG. 37 shows a schematic cross-sectional view of the solar cell described in Patent Document 1.
  • an i-type amorphous semiconductor layer 112i made of i-type amorphous silicon containing hydrogen and hydrogen are applied to a part of the back surface 100b of the semiconductor substrate 100 made of n-type single crystal silicon.
  • An IN stacked body 112 with an n-type amorphous semiconductor layer 112n made of n-type amorphous silicon is provided.
  • An insulating layer 118 made of silicon oxide, silicon nitride, silicon oxynitride, or the like is provided over the n-type amorphous semiconductor layer 112n.
  • an i-type amorphous film made of i-type amorphous silicon containing hydrogen so as to cover the non-formation surface of the IN stacked body 112 on the back surface 100 b of the semiconductor substrate 100 and the stacked body of the insulating layer 118 on the IN stacked body 112.
  • the first conductive layer 119a, the second conductive layer 119b, and the third conductive layer 119c are formed so as to cover the non-formation surface of the insulating layer 118 on the surface of the n-type amorphous semiconductor layer 112n and the IP stacked body 113.
  • a conductive layer stack 119 is formed by sequentially stacking the fourth conductive layer 119d.
  • a groove 120 extending to the surface of the insulating layer 118 is formed in the stacked body 119 of the conductive layer, whereby an n electrode 114 on the IN stacked body 112 and a p electrode 115 on the IP stacked body 113 are formed. It is separated.
  • an i-type amorphous semiconductor layer 117i made of i-type amorphous silicon containing hydrogen and an n-type amorphous semiconductor layer made of n-type amorphous silicon containing hydrogen.
  • 117n and an insulating layer 116 made of silicon oxide, silicon nitride, silicon oxynitride, or the like are provided.
  • the embodiment disclosed herein includes a step of forming a dielectric film containing nitrogen and silicon so as to be in contact with the first surface of the semiconductor substrate, and a second surface opposite to the first surface of the semiconductor substrate. Forming a first conductive type amorphous semiconductor film and a second conductive type amorphous semiconductor film on the surface side, forming a first electrode on the first conductive type amorphous semiconductor film, Forming a second electrode on the second conductive type amorphous semiconductor film.
  • a method for manufacturing a heterojunction back contact cell is a method for manufacturing a heterojunction back contact cell.
  • the embodiment disclosed herein is a dielectric film containing a semiconductor substrate of a first conductivity type or a second conductivity type, and nitrogen and silicon provided in contact with the first surface of the semiconductor substrate.
  • a first conductivity type amorphous semiconductor film and a second conductivity type amorphous semiconductor film provided on a second surface side opposite to the first surface of the semiconductor substrate, and a first conductivity type amorphous semiconductor A heterojunction back contact cell comprising a first electrode on a porous semiconductor film and a second electrode on a second conductive amorphous semiconductor film.
  • FIG. 3 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 1.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • 6 is a schematic cross-sectional view of a heterojunction back contact cell of Embodiment 2.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example.
  • FIG. 1 is a schematic cross-sectional view of a solar cell described in Patent Document 1.
  • FIG. 1 is a schematic cross-sectional view of a solar cell described in Patent Document 1.
  • FIG. 1 is a schematic cross-sectional view of the heterojunction back contact cell of the first embodiment.
  • the heterojunction back contact cell of Embodiment 1 has a semiconductor substrate 1 which is an n-type single crystal silicon substrate.
  • the first surface 1a (light-receiving surface) of the semiconductor substrate 1 has an uneven shape, and a dielectric film 6 containing nitrogen (N) and silicon (Si) is in contact with the first surface 1a. Is provided.
  • the dielectric film 6 containing N and Si for example, a film containing silicon nitride can be used.
  • the dielectric film 6 may contain one or more atoms selected from the group consisting of oxygen (O), carbon (C), and fluorine (F) in addition to N and Si.
  • the composition of the dielectric film 6 is, for example, SiN x C y O z F w H v (0 ⁇ x, 0 ⁇ y, 0 ⁇ z, 0 ⁇ w and 0 ⁇ v) (hereinafter, “SiN x C y O z Fw Hv ”)).
  • SiN x C y O z Fw Hv the composition of the dielectric film 6 can be expressed by the formula “SiN x ”.
  • the composition of the dielectric film 6 can be expressed by the formula “SiN x O z ”.
  • the composition of the dielectric film 6 can be obtained by measuring the content of each atom of the dielectric film 6 by secondary ion mass spectrometry (SIMS).
  • the thickness of the dielectric film 6 is not particularly limited, but can be, for example, 60 nm or more and 150 nm or less.
  • a natural oxide film of silicon may exist in at least a part of the region between the first surface 1a and the dielectric film 6.
  • the thickness of the natural oxide film is, for example, 5 nm or less, preferably 1 nm or less.
  • each of the first i-type amorphous semiconductor film 2 and the second i-type amorphous semiconductor film 4 is an i-type amorphous silicon film.
  • i-type means not only a completely intrinsic state but also a sufficiently low concentration (the n-type impurity concentration is less than 1 ⁇ 10 15 / cm 3 and the p-type impurity concentration is 1 ⁇ (Less than 10 15 / cm 3 ) is meant to include n-type or p-type impurities.
  • n-type means a state where the n-type impurity concentration is 1 ⁇ 10 15 / cm 3 or more
  • p-type means that the p-type impurity concentration is 1 ⁇ 10 15 / cm 3 or more. Means the state.
  • the n-type impurity concentration and the p-type impurity concentration can be measured by, for example, secondary ion mass spectrometry.
  • amorphous silicon includes not only amorphous silicon in which the dangling bonds of silicon atoms are not terminated with hydrogen, but also dangling bonds of silicon atoms such as hydrogenated amorphous silicon. In which is terminated with hydrogen.
  • a first conductive type amorphous semiconductor film 3 which is a p-type amorphous silicon film in contact with the first i-type amorphous semiconductor film 2 is provided.
  • a second conductive amorphous semiconductor film 5 which is an n-type amorphous silicon film in contact with the second i-type amorphous semiconductor film 4, is provided. Is provided.
  • the end of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductivity-type amorphous semiconductor film 5 is the first i-type amorphous semiconductor film 2 and the first conductivity-type amorphous.
  • the edge part of the laminated body 51 with the quality semiconductor film 3 is covered. Therefore, the end of the second i-type amorphous semiconductor film 4 is located between the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5.
  • the end of the second i-type amorphous semiconductor film 4 is in contact with both the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5.
  • the first conductive amorphous semiconductor film 3 and the second conductive amorphous semiconductor film 5 are separated by the second i-type amorphous semiconductor film 4.
  • first electrode 7 in contact with the first conductive type amorphous semiconductor film 3 is provided on the first conductive type amorphous semiconductor film 3.
  • a second electrode 8 that is in contact with the second conductive type amorphous semiconductor film 5 is provided on the second conductive type amorphous semiconductor film 5.
  • the first electrode 7 and the second electrode 8 aluminum, silver, or the like can be used.
  • an uneven shape is formed on the first surface 1 a serving as the light receiving surface of the semiconductor substrate 1.
  • the uneven shape of the first surface 1a can be formed, for example, by texture-etching the first surface 1a of the semiconductor substrate 1 after forming a texture mask over the entire second surface 1b of the semiconductor substrate 1. it can.
  • silicon nitride or silicon oxide can be used as the texture mask.
  • an etchant used for texture etching for example, an alkaline solution capable of dissolving silicon can be used.
  • a dielectric film 6 is formed so as to be in contact with the entire surface of the first surface 1 a of the semiconductor substrate 1.
  • the dielectric film 6 can be formed, for example, by a plasma CVD (Chemical Vapor Deposition) method.
  • SiH 4 can be used as the Si source gas, and at least one of N 2 and NH 3 can be used as the N source gas.
  • SiN x O z film is formed as the dielectric film 6, SiH 4 as Si source gas, at least one of N 2 and NH 3 as N source gas, and oxygen source gas O 2 gas can be used.
  • Each of C, O, and F in the dielectric film 6 may be intentionally introduced using a source gas containing these atoms, or may be introduced unavoidably without using the source gas. Also good.
  • the dielectric film 6 can be formed, for example, at 400 ° C. or more and 600 ° C. or less. Thereby, in the etching process described later, the dielectric film 6 can function as a protective film having etching resistance of the first surface 1a of the semiconductor substrate 1. Therefore, in the etching process described later, the first surface 1a side It is not necessary to form a protective film. For this reason, it is possible to reduce the number of manufacturing steps, thereby reducing the manufacturing cost.
  • the insulating layer 116 is formed at about 100 ° C. to 200 ° C. This is because, when the temperature at which the insulating layer 116 is formed is increased (for example, 450 ° C. or higher), hydrogen in the amorphous semiconductor layer already formed on the semiconductor substrate 100 is excessively removed, and thus amorphous. This is because the quality of the quality semiconductor layer deteriorates. Since the insulating layer formed at such a low temperature has low etching resistance, it is necessary to provide a protective film over the insulating layer 116 in preparation for an etching process described later.
  • a first i-type amorphous semiconductor film 2 is formed on the entire second surface 1 b of the semiconductor substrate 1.
  • the method for forming the first i-type amorphous semiconductor film 2 is not particularly limited, and for example, a plasma CVD method can be used.
  • an i-type amorphous silicon film can be preferably used, but is not limited to an i-type amorphous silicon film.
  • a quality semiconductor film can also be used.
  • a first conductivity type amorphous semiconductor film 3 is formed on the first i-type amorphous semiconductor film 2.
  • the formation method of the 1st conductivity type amorphous semiconductor film 3 is not specifically limited, For example, plasma CVD method can be used.
  • the first conductive type amorphous semiconductor film 3 a p-type amorphous silicon film can be preferably used.
  • the first conductive type amorphous semiconductor film 3 is not limited to a p-type amorphous silicon film.
  • a semiconductor film can also be used.
  • boron can be used as the p-type impurity.
  • a stacked body of the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 is formed on the first conductive-type amorphous semiconductor film 3.
  • An etching mask 31 such as a photoresist having an opening at a portion to be etched in the thickness direction is formed.
  • the stacked body 51 of the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is etched in the thickness direction using the etching mask 31 as a mask. As a result, a part of the second surface 1b of the semiconductor substrate 1 is exposed.
  • a second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the semiconductor substrate 1 and the first conductive amorphous semiconductor film 3.
  • the method for forming the second i-type amorphous semiconductor film 4 is not particularly limited, and for example, a plasma CVD method can be used.
  • an i-type amorphous silicon film can be suitably used, but is not limited to an i-type amorphous silicon film.
  • a conventionally known i-type amorphous silicon film is used.
  • a quality semiconductor film can also be used.
  • a second conductivity type amorphous semiconductor film 5 is formed on the second i-type amorphous semiconductor film 4.
  • the formation method of the 2nd conductivity type amorphous semiconductor film 5 is not specifically limited, For example, plasma CVD method can be used.
  • an n-type amorphous silicon film can be preferably used, but is not limited to an n-type amorphous silicon film.
  • a conventionally known n-type amorphous silicon film is used.
  • a semiconductor film can also be used.
  • phosphorus can be used as the n-type impurity.
  • a photoresist is formed only on a portion where the stacked body of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is left on the back surface of the semiconductor substrate 1.
  • Etching mask 32 is formed.
  • a part of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 is etched in the thickness direction using the etching mask 32 as a mask.
  • the etching mask 32 is completely removed.
  • the first electrode 7 is formed so as to be in contact with the first conductive amorphous semiconductor film 3, and the second electrode is in contact with the second conductive amorphous semiconductor film 5. 8 is formed.
  • the formation method of the 1st electrode 7 and the 2nd electrode 8 is not specifically limited, For example, a vapor deposition method etc. can be used.
  • the solar cell described in Patent Document 1 is manufactured by simultaneously forming an i-type amorphous semiconductor layer 117i on the light receiving surface 100a and an i-type amorphous semiconductor layer 112i on the back surface 100b. This is because the i-type amorphous semiconductor layer 117i and the i-type amorphous semiconductor layer 112i are essential for improving the passivation of the light receiving surface 100a and the back surface 100b of the semiconductor substrate 100, respectively, and it is more efficient to form them simultaneously. It was because it was thought to be the target.
  • the present inventors in the solar cell described in Patent Document 1, the i-type amorphous semiconductor layer 117i on the light receiving surface 100a of the semiconductor substrate 100 emits light in a short wavelength region (wavelength of 300 nm or more and 500 nm or less). It has been found that it is easy to absorb and this does not increase the short circuit current density as expected.
  • an amorphous semiconductor film is not provided between the first surface 1a of the semiconductor substrate 1 and the dielectric film 6, and the first surface 1a and the dielectric are not provided. It has a structure in contact with the film 6. Thereby, the absorption of light in the short wavelength region by the amorphous semiconductor film on the light receiving surface side can be suppressed and the amount of light incident on the semiconductor substrate 1 can be increased, so that the heterojunction back contact cell of Embodiment 1 is Compared with the solar cell described in Patent Document 1, the short-circuit current density can be improved.
  • the difference between the refractive index of the semiconductor substrate 1 and the refractive index of the dielectric film 6 is preferably 1.0 or less, and preferably 0.8 or less. More preferred. Thereby, the dielectric film 6 can have higher passivation property.
  • the refractive index means an absolute refractive index.
  • FIG. 13 is a schematic cross-sectional view of the heterojunction back contact cell of the second embodiment.
  • the heterojunction back contact cell of Embodiment 2 is characterized by having a first dielectric film 6a in contact with the first surface 1a and a second dielectric film 6b provided on the first dielectric film 6a. There is.
  • the first dielectric film 6a and the second dielectric film 6b are each a dielectric film containing N and Si, and the content of Si in the second dielectric film 6b is the same as that in the first dielectric film 6a. Less than Si content. That is, in the dielectric film 6, the Si content is gradually reduced as the distance from the first surface 1 a of the semiconductor substrate 1 increases. As a result, the refractive index decreases in the order of the semiconductor substrate 1, the first dielectric film 6a, and the second dielectric film 6b.
  • the ratio of the flow rate of the Si source gas to the source material gas can be set lower than the ratio of the flow rate of the Si source gas to the N source gas.
  • the refractive index of the dielectric film 6 can be reduced stepwise as the distance from the first surface 1a of the semiconductor substrate 1 increases.
  • the antireflection function of the film 6 can be enhanced.
  • the difference between the refractive index of the semiconductor substrate 1 and the refractive index of the first dielectric film 6a is 1.0 or less, particularly 0.8 or less, the semiconductor substrate 1 is formed by the first dielectric film 6a.
  • the passivation property of the 1st surface 1a can be improved.
  • the dielectric film 6 includes the first dielectric film 6a and the second dielectric film 6b has been described.
  • the present invention is not limited to this, and the dielectric film 6 is a dielectric film having three or more layers. May be configured to be stacked.
  • the heterojunction back contact cell of Embodiment 3 is characterized in that the Si content in the dielectric film 6 is continuously reduced as the distance from the first surface 1a of the semiconductor substrate 1 increases.
  • the heterojunction back contact cell of Embodiment 3 is obtained by continuously decreasing the ratio of the flow rate of the Si source gas to the N source gas, for example, in the plasma CVD method when forming the dielectric film 6. Can be manufactured.
  • Embodiment 3 other than the above is the same as that of Embodiment 1 and Embodiment 2, and therefore description thereof will not be repeated.
  • a concavo-convex shape is formed on the first surface 1a which becomes the light receiving surface of the semiconductor substrate 1.
  • a first i-type amorphous semiconductor film 2 is formed on the entire second surface 1 b of the semiconductor substrate 1.
  • a first conductivity type amorphous semiconductor film 3 is formed on the first i-type amorphous semiconductor film 2.
  • an etching mask 31 is formed on the first conductive type amorphous semiconductor film 3.
  • the stacked body 51 of the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is etched in the thickness direction using the etching mask 31 as a mask. As a result, a part of the second surface 1b of the semiconductor substrate 1 is exposed.
  • the second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the second surface 1 b of the semiconductor substrate 1 and the first conductive type amorphous semiconductor film 3. Form.
  • a second conductivity type amorphous semiconductor film 5 is formed on the second i-type amorphous semiconductor film 4.
  • etching mask 32 is formed only on the substrate.
  • a part of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 is etched in the thickness direction using the etching mask 32 as a mask.
  • the etching mask 32 is completely removed.
  • a dielectric film 6 is formed so as to be in contact with the entire surface of the first surface 1a of the semiconductor substrate 1.
  • the dielectric film 6 is preferably formed by setting the temperature of the semiconductor substrate 1 to 100 ° C. or more and 200 ° C. or less. This is because when the temperature of the semiconductor substrate 1 is set higher than 200 ° C. and the dielectric film 6 is formed, excessive escape of hydrogen from each amorphous semiconductor film provided on the second surface 1b side. This is because.
  • the first electrode 7 is formed so as to be in contact with the first conductive type amorphous silicon film 3, and the second electrode is formed so as to be in contact with the second conductive type amorphous silicon film 5. 8 is formed.
  • the process performed after forming the dielectric film 6 is a process of forming the first electrode 7 and a process of forming the second electrode 8. There is no need to provide a protective film having etching resistance. Therefore, according to the manufacturing method of Embodiment 4, the manufacturing process can be simplified, thereby reducing the manufacturing cost.
  • the dielectric film 6 is a single layer has been described.
  • the present invention is not limited to this, and the content of Si in the dielectric film 6 gradually increases as the distance from the first surface 1a of the semiconductor substrate 1 increases.
  • the dielectric film 6 may be formed after each film on the second surface 1b side is formed.
  • a concavo-convex shape was formed on the first surface 1a serving as the light receiving surface of the semiconductor substrate 1 which is an n-type single crystal silicon substrate after removal of slice damage.
  • the uneven shape of the first surface 1a is obtained by forming a texture mask on the entire second surface 1b of the semiconductor substrate 1 and then performing texture etching using an alkaline solution on the first surface 1a of the semiconductor substrate 1. Was formed. Then, after removing the texture mask from the semiconductor substrate 1, the semiconductor substrate 1 was cleaned.
  • a dielectric film 6 was formed so as to be in contact with the entire surface of the first surface 1 a of the semiconductor substrate 1.
  • the dielectric film 6, by a plasma CVD method, a laminate by laminating a the SiN x film of the SiN x film and the refractive index 1.8 of the refractive index 2.0 in this order from the first surface 1a side of the semiconductor substrate 1 Formed as. Thereafter, the semiconductor substrate 1 was cleaned.
  • a first i-type amorphous semiconductor film 2 made of an i-type amorphous silicon film was formed on the entire second surface 1b of the semiconductor substrate 1 by plasma CVD.
  • a first conductive type amorphous semiconductor film 3 made of an i type amorphous silicon film is formed on the entire surface of the first i type amorphous semiconductor film 2 by plasma CVD. .
  • a stacked body of the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 is formed on the first conductive-type amorphous semiconductor film 3.
  • An etching mask 31 made of a photoresist having an opening at a portion to be etched in the thickness direction was formed.
  • the first i-type amorphous semiconductor film 2 and the dielectric film 6 on the light receiving surface of the semiconductor substrate 1 and the etching mask 31 on the back surface of the semiconductor substrate 1 are used as masks.
  • a portion of the second surface 1b of the semiconductor substrate 1 was exposed by etching the stacked body 51 with the first conductive type amorphous semiconductor film 3 in the thickness direction. Then, after removing the etching mask 31, the semiconductor substrate 1 was cleaned.
  • the second surface made of the i-type amorphous silicon film is formed by plasma CVD so as to cover the exposed surface of the semiconductor substrate 1 and the first conductive type amorphous semiconductor film 3.
  • An i-type amorphous semiconductor film 4 was formed.
  • a second conductive amorphous semiconductor film 5 made of an n-type amorphous silicon film is formed on the second i-type amorphous semiconductor film 4 by plasma CVD. did.
  • a photoresist is formed only on a portion where the stacked body of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is left on the back surface of the semiconductor substrate 1.
  • An etching mask 32 made of is formed.
  • a laminate of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 By etching a part of 52 in the thickness direction, a part of the first conductive type amorphous semiconductor film 3 was exposed as shown in FIG. Thereafter, as shown in FIG. 12, the etching mask 32 was completely removed. Thereafter, the semiconductor substrate 1 was cleaned.
  • a metal film made of silver is deposited on the entire surface of the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5, and an opening is formed at a location where the metal film is etched in the thickness direction.
  • the metal film was etched using the dielectric film 6 on the light-receiving surface of the semiconductor substrate 1 and the etching mask on the back surface of the semiconductor substrate 1 as a mask in a state where an etching mask made of a photoresist was formed on the metal film. .
  • the first electrode 7 in contact with the first conductive type amorphous semiconductor film 3 is formed, and the second electrode 8 is set in contact with the second conductive type amorphous semiconductor film 5. Formed.
  • the etching mask on the back surface of the semiconductor substrate 1 was removed.
  • the heterojunction back contact cell of the example was completed.
  • a concavo-convex shape is formed on the first surface 1a serving as the light-receiving surface of the semiconductor substrate 1 which is the n-type single crystal silicon substrate after removing the slice damage, After removing the texture mask from the substrate 1, the semiconductor substrate 1 was cleaned.
  • an i-type amorphous silicon film and n are formed from the side of the semiconductor substrate 1 so as to be in contact with the entire surface of the first surface 1a serving as the light receiving surface of the semiconductor substrate 1.
  • Type amorphous silicon films are deposited in this order by plasma CVD, and as shown in the schematic cross-sectional view of FIG. 24, an i-type amorphous silicon film and an n-type amorphous silicon film A laminate 61 made of was formed.
  • the first i-type amorphous semiconductor film 2 and the first conductivity-type amorphous semiconductor film 3 are formed on the entire surface of the second surface 1b which is the back surface of the semiconductor substrate 1.
  • the layers were sequentially deposited by the plasma CVD method (see FIG. 25).
  • a stacked body of the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 is formed on the first conductive-type amorphous semiconductor film 3.
  • An etching mask 31 made of a photoresist having an opening at a portion to be etched in the thickness direction was formed (see FIG. 26).
  • the etching mask 31 is also formed on the stacked body 61 of the i-type amorphous silicon film and the n-type amorphous silicon film on the light receiving surface of the semiconductor substrate 1.
  • the etching mask 31 as a mask, the stacked body of the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is etched in the thickness direction. As a result, a part of the second surface 1b of the semiconductor substrate 1 was exposed (see FIG. 27). Then, after removing the etching masks 31 on the light receiving surface and the back surface of the semiconductor substrate 1, the semiconductor substrate 1 was cleaned.
  • the second surface made of the i-type amorphous silicon film is formed by plasma CVD so as to cover the exposed surface of the semiconductor substrate 1 and the first conductive type amorphous semiconductor film 3.
  • An i-type amorphous semiconductor film 4 is formed (see FIG. 28), and a second conductivity type non-crystalline film made of an n-type amorphous silicon film is formed on the second i-type amorphous semiconductor film 4 by plasma CVD.
  • a crystalline semiconductor film 5 was formed (see FIG. 29).
  • the photoresist is applied only to the portion where the stacked body of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is left on the back surface of the semiconductor substrate 1.
  • An etching mask 32 made of (see FIG. 30) was formed.
  • the etching mask 32 is also formed on the stacked body 61 on the light receiving surface of the semiconductor substrate 1.
  • a part of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 is etched in the thickness direction using the etching mask 32 as a mask.
  • a part of the first conductive type amorphous semiconductor film 3 was exposed (see FIG. 31). Then, after removing the etching masks 32 on the light receiving surface and the back surface of the semiconductor substrate 1, the semiconductor substrate 1 was cleaned.
  • plasma CVD is performed on a stacked body 61 of an i-type amorphous silicon film and an n-type amorphous silicon film on the light receiving surface of the semiconductor substrate 1.
  • SiN x film of the SiN x film and the refractive index 1.8 of the refractive index 2.0 by stacking of a stack 61 side in this order, the SiN x film and the refractive index of the refractive index 2.0 1.
  • a dielectric film 6 composed of a stack of 8 SiN x films was formed.
  • the first conductivity type amorphous film is formed with an etching mask 33 made of a photoresist formed on the entire surface of the dielectric film 6 on the light receiving surface of the semiconductor substrate 1.
  • a metal film 9 made of silver was deposited on the entire surface of the semiconductor film 3 and the second conductive type amorphous semiconductor film 5.
  • an etching mask 33 made of a photoresist having an opening at a location where the metal film 9 is etched in the thickness direction was formed on the metal film 9.
  • FIG. 34 an etching mask 33 made of a photoresist having an opening at a location where the metal film 9 is etched in the thickness direction was formed on the metal film 9.
  • the metal film 9 is etched using the etching mask 33 on the light receiving surface and the back surface of the semiconductor substrate 1 as a mask, so that the first conductivity type amorphous semiconductor film is obtained. 3 was formed, and the second electrode 8 was formed in contact with the second conductive type amorphous semiconductor film 5.
  • the etching masks 33 on the light receiving surface and the back surface of the semiconductor substrate 1 were removed after the first electrode 7 and the second electrode 8 were formed. Thus, the heterojunction back contact cell of the comparative example was completed.
  • FIG. 36 shows the spectral sensitivities of the light receiving surfaces of the heterojunction back contact cells of the example and the comparative example with respect to light having a wavelength of 300 nm to 500 nm, and the horizontal axis of FIG. 36 represents the wavelength [nm].
  • the vertical axis represents the external quantum efficiency (EQE) [%].
  • the external quantum efficiency means the ratio [%] of the number of carrier pairs (electron and hole pairs) generated for one photon of incident light.
  • the heterojunction back contact cell of the example has higher spectral sensitivity of light on the short wavelength side than the heterojunction back contact cell of the comparative example.
  • the external quantum efficiency of the heterojunction back contact cell of the example was about 80%
  • the external quantum efficiency of the heterojunction back contact cell of the comparative example was about 60%, there was a large difference of about 20%.
  • the SiN x C y O z F w H v film has the same physical properties as the SiN x film. , even in the case of forming a direct SiN x C y O z F w H v film on the light receiving surface of the semiconductor substrate 1 in place of the SiN x film, the same effect as in the case of forming a the SiN x film described above is obtained Conceivable.
  • a method for manufacturing a heterojunction back contact cell According to the method for manufacturing a heterojunction back contact cell of the embodiment disclosed herein, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the step of forming the dielectric film includes the first conductive type amorphous semiconductor film and the second conductive type on the second surface side. It is preferably performed before the step of forming the type amorphous semiconductor film.
  • the dielectric film can be used as a protective film having etching resistance, the step of forming the protective film having etching resistance before the etching process can be reduced, and thus the heterojunction back contact cell. The manufacturing cost can be reduced.
  • the step of forming a dielectric film includes a first conductive type amorphous semiconductor film and a second conductive type on the second surface side.
  • the step of forming the dielectric film is preferably performed at 450 ° C. or higher and 500 ° C. or lower. In this case, since the etching resistance of the dielectric film can be increased, it is not necessary to form a protective film for protecting the dielectric film in the manufacturing process. Therefore, since the manufacturing process can be simplified, the manufacturing cost of the heterojunction back contact cell can be reduced.
  • the step of forming the dielectric film includes the first conductive type amorphous semiconductor film and the second conductive type on the second surface side. It is preferably performed after the step of forming the type amorphous semiconductor film. In this case, since it is necessary to form a protective film having etching resistance after the dielectric film is formed, the manufacturing cost of the heterojunction back contact cell can be reduced.
  • the step of forming a dielectric film includes a first conductive type amorphous semiconductor film and a second conductive type on the second surface side.
  • the step of forming the dielectric film is preferably performed at 100 ° C. or higher and 200 ° C. or lower. Also in this case, the manufacturing cost can be reduced.
  • the dielectric content of the dielectric film decreases as the distance from the first surface increases. In this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the silicon content is preferably continuously reduced as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the silicon content is preferably reduced stepwise as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the dielectric film preferably further includes one or more atoms selected from the group consisting of oxygen, carbon, and fluorine. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the composition of the dielectric film is preferably represented by the formula of SiN x C y O z F w H v. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the step of forming the first conductive type amorphous semiconductor film and the second conductive type amorphous semiconductor film is performed on a semiconductor substrate. Forming a first i-type amorphous semiconductor film on the second surface side, forming a first conductivity-type amorphous semiconductor film on the first i-type amorphous semiconductor film, Removing a part of the stack of the first i-type amorphous semiconductor film and the first conductive amorphous semiconductor film, and forming the second i-type amorphous semiconductor film on the second surface side And a step of forming a second conductivity type amorphous semiconductor film on the second i-type amorphous semiconductor film. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the first i-type amorphous semiconductor film preferably contains i-type amorphous silicon. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the second i-type amorphous semiconductor film preferably contains i-type amorphous silicon. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the semiconductor substrate preferably includes n-type crystalline silicon. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • a heterojunction back contact cell includes a semiconductor substrate of a first conductivity type or a second conductivity type, and nitrogen provided in contact with a first surface of the semiconductor substrate.
  • a heterojunction back contact cell comprising a first electrode on the first conductive type amorphous semiconductor film and a second electrode on the second conductive type amorphous semiconductor film.
  • the dielectric film preferably has a silicon content that decreases as the distance from the first surface increases. In this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the silicon content is preferably continuously reduced as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the silicon content is reduced stepwise as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the dielectric film preferably further includes one or more selected from the group consisting of oxygen, carbon, and fluorine. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the composition of the dielectric film is preferably represented by the formula of SiN x C y O z F w H v. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • a heterojunction back contact cell includes a first i-type amorphous semiconductor film between a semiconductor substrate and a first conductive amorphous semiconductor film, a semiconductor substrate, It is preferable to further include a second i-type amorphous semiconductor film between the second conductive type amorphous semiconductor film. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the first i-type amorphous semiconductor film preferably includes i-type amorphous silicon. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the second i-type amorphous semiconductor film preferably contains i-type amorphous silicon. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the semiconductor substrate and the first i-type amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the semiconductor substrate and the second i-type amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the first i-type amorphous semiconductor film and the first conductive amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the second i-type amorphous semiconductor film and the second conductive amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the second i-type amorphous semiconductor film is interposed between the first conductive amorphous semiconductor film and the second conductive amorphous semiconductor film.
  • the end of the semiconductor film is preferably located. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the end of the second i-type amorphous semiconductor film is formed of the first conductive type amorphous semiconductor film and the second conductive type amorphous semiconductor. It is preferable to be in contact with each of the crystalline semiconductor films. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the semiconductor substrate preferably contains n-type crystalline silicon. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the embodiment disclosed herein can be suitably used for a heterojunction back contact cell and a manufacturing method thereof.
  • 1,100 semiconductor substrate 1a first surface, 1b second surface, 2nd first i-type amorphous semiconductor film, 3rd first conductivity type amorphous semiconductor film, 4th second i-type amorphous Semiconductor film, 5 Second conductive type amorphous semiconductor film, 6 Dielectric film, 6a First dielectric film, 6b Second dielectric film, 7 First electrode, 8 Second electrode, 9 Metal film, 31, 32 33, etching mask, 51, 52, 61 laminate, 100a light receiving surface, 100b back surface, 112 IN laminate, 112i, 113i, 117i, 121, 124 i-type amorphous semiconductor layer, 112n, 117n, 122 n-type non-layer Crystalline semiconductor layer, 113 IP stack, 113p, 125 p-type amorphous semiconductor layer, 114 n-side electrode, 115 p-side electrode, 116, 118, 123 insulating layer, 119 stack, 119a, 119b, 1 9c, 119

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Abstract

L'invention porte sur un procédé de fabrication d'une cellule à contact arrière à hétérojonction, qui comprend : une étape consistant à former un film diélectrique (6) de manière à ce qu'il soit en contact avec une première surface (1a) d'un substrat semi-conducteur (1), ledit film diélectrique (6) contenant de l'azote et du silicium; une étape consistant à former un film semi-conducteur amorphe (3) d'un premier type de conductivité et un film semi-conducteur amorphe (5) d'un second type de conductivité sur une seconde surface (1b) du substrat semi-conducteur (1), ladite seconde surface (1b) étant à l'opposé de la première surface (1a); une étape consistant à former une première électrode (7) sur le film semi-conducteur amorphe (3) du premier type de conductivité; et une étape consistant à former une seconde électrode (8) sur le film semi-conducteur amorphe (5) du second type de conductivité.
PCT/JP2015/073572 2014-10-21 2015-08-21 Cellule solaire à contact arrière à hétérojonction et son procédé de fabrication WO2016063608A1 (fr)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006128258A (ja) * 2004-10-27 2006-05-18 Sharp Corp 太陽電池および太陽電池の製造方法
JP2009515336A (ja) * 2005-11-08 2009-04-09 エルジー・ケム・リミテッド 高効率の太陽電池及びその調製方法
JP2009520369A (ja) * 2005-12-16 2009-05-21 ビーピー・コーポレーション・ノース・アメリカ・インコーポレーテッド バックコンタクト太陽電池
WO2009096539A1 (fr) * 2008-01-30 2009-08-06 Kyocera Corporation Élément de batterie solaire et procédé de fabrication d'élément de batterie solaire
JP2010524254A (ja) * 2007-04-12 2010-07-15 サンパワー コーポレイション 太陽電池の酸窒化物パッシベーション
JP2010177264A (ja) * 2009-01-27 2010-08-12 Kyocera Corp 太陽電池素子および太陽電池素子の製造方法
JP2011518422A (ja) * 2007-12-14 2011-06-23 サンパワー コーポレイション 裏面コンタクト太陽電池用の高光吸収層を有する反射防止膜
JP2011233657A (ja) * 2010-04-27 2011-11-17 Sharp Corp 裏面電極型太陽電池、および裏面電極型太陽電池の製造方法
WO2013145008A1 (fr) * 2012-03-29 2013-10-03 三菱電機株式会社 Elément photovoltaïque, procédé de fabrication de celui-ci et module à cellules solaires

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4363877B2 (ja) * 2003-01-17 2009-11-11 三洋電機株式会社 光起電力装置およびその製造方法
KR20100015622A (ko) * 2007-03-16 2010-02-12 비피 코포레이션 노쓰 아메리카 인코포레이티드 태양 전지
US7749917B1 (en) * 2008-12-31 2010-07-06 Applied Materials, Inc. Dry cleaning of silicon surface for solar cell applications
CN102074599B (zh) * 2009-09-07 2014-10-29 Lg电子株式会社 太阳能电池及其制造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006128258A (ja) * 2004-10-27 2006-05-18 Sharp Corp 太陽電池および太陽電池の製造方法
JP2009515336A (ja) * 2005-11-08 2009-04-09 エルジー・ケム・リミテッド 高効率の太陽電池及びその調製方法
JP2009520369A (ja) * 2005-12-16 2009-05-21 ビーピー・コーポレーション・ノース・アメリカ・インコーポレーテッド バックコンタクト太陽電池
JP2010524254A (ja) * 2007-04-12 2010-07-15 サンパワー コーポレイション 太陽電池の酸窒化物パッシベーション
JP2011518422A (ja) * 2007-12-14 2011-06-23 サンパワー コーポレイション 裏面コンタクト太陽電池用の高光吸収層を有する反射防止膜
WO2009096539A1 (fr) * 2008-01-30 2009-08-06 Kyocera Corporation Élément de batterie solaire et procédé de fabrication d'élément de batterie solaire
JP2010177264A (ja) * 2009-01-27 2010-08-12 Kyocera Corp 太陽電池素子および太陽電池素子の製造方法
JP2011233657A (ja) * 2010-04-27 2011-11-17 Sharp Corp 裏面電極型太陽電池、および裏面電極型太陽電池の製造方法
WO2013145008A1 (fr) * 2012-03-29 2013-10-03 三菱電機株式会社 Elément photovoltaïque, procédé de fabrication de celui-ci et module à cellules solaires

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