WO2016061885A1 - 玻璃面板和用于制造所述面板的方法 - Google Patents

玻璃面板和用于制造所述面板的方法 Download PDF

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Publication number
WO2016061885A1
WO2016061885A1 PCT/CN2014/093985 CN2014093985W WO2016061885A1 WO 2016061885 A1 WO2016061885 A1 WO 2016061885A1 CN 2014093985 W CN2014093985 W CN 2014093985W WO 2016061885 A1 WO2016061885 A1 WO 2016061885A1
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WIPO (PCT)
Prior art keywords
line
glass panel
scan line
charge sharing
mask
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PCT/CN2014/093985
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English (en)
French (fr)
Inventor
黄世帅
张天豪
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深圳市华星光电技术有限公司
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Priority to US14/416,805 priority Critical patent/US20160111443A1/en
Publication of WO2016061885A1 publication Critical patent/WO2016061885A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of manufacturing liquid crystal display panels, and more particularly to a glass panel and a method for manufacturing the same.
  • step a a film is coated on a glass substrate.
  • step b a photoresist material is applied over the plated layer.
  • step c the glass plate coated with the photoresist material is illuminated under the masking of the mask 105.
  • step d development is carried out.
  • step e etching is performed.
  • step f the photoresist is removed from the treated glass sheet by removing the photoresist 106. A patterned coating can then be obtained and then recycled to step a for the next plating treatment. Steps a through f are continuously cycled until a desired glass panel with multiple plating layers is obtained.
  • a "five mask” process is commonly used to fabricate glass panels for array substrates of liquid crystal displays.
  • the “five masks” are mainly repeated five times in the process steps shown in Fig. 1, and five layers on the glass substrate are formed by five different masks 105.
  • Figure 2 shows a cross-sectional view of a glass panel manufactured by the "five mask” process.
  • the glass substrate 1 is located at the lowermost layer.
  • the gate 2 (which is located in the first metal layer M1) is formed by the first mask by the method shown in FIG. 1, and then the insulating layer 3 is covered.
  • a second mask is used to fabricate an active layer, for example composed of different semiconductor materials 4 and 5.
  • a source 6 and a drain 7 located in the second metal layer M2 are fabricated using a third mask.
  • Via layer An ITO layer 9 serving as an electrode was fabricated through a fifth mask.
  • Fig. 3 shows a liquid crystal pixel unit in the prior art.
  • a low color shift design is usually performed. For example, by increasing the domain of a pixel unit, one pixel unit can be divided into four pixel domains. If one pixel unit is further divided into the main area 21 and the sub-area 22, it can be increased to 8 pixel areas to achieve the purpose of improving the viewing angle and improving the color shift.
  • FIG. 4 shows an equivalent circuit diagram of a common pixel cell with a low color shift design.
  • One pixel unit is divided into a main area and a sub area.
  • the scanning lines of the liquid crystal capacitance 11 is opened in the main area of the thin film transistor and the thin film transistor T main sub-zone located T sub turned on, electric signals are supplied from the data line 13 is in pixel units of the main and sub-region And storage capacitors.
  • the sharing thin film transistor Tcs When the scan line 11 is turned off and the charge sharing line 12 is turned on, the sharing thin film transistor Tcs is turned on, and a part of the voltage in the liquid crystal capacitor Clc sub and the storage capacitor CST sub located in the sub-region is released into the sharing capacitor Cb. In this way, a potential difference is exhibited between the sub-region and the main region of the pixel unit, and supplemented by regulation, the purpose of reducing the color shift can be achieved.
  • the scan line 11 and the charge share line 12 are independent of each other, and a low color shift design is required to be achieved by controlling the switches of the scan line 11 and the charge share line 12, respectively.
  • the scanning line 11 and the charge sharing line 12 are independent of each other as described above, it is necessary to consume a large amount of flip chip (COF) in the manufacturing and packaging processes.
  • COF flip chip
  • Another low color shift design is to turn on the charge sharing line 12 in the previous group through the scan line 11 that is turned on later.
  • the n+p scan lines 11 open the charge sharing line 12 in the nth group, which is called the n+p type low color. Partial design. The benefit of this design is to reduce the amount of flip chip used.
  • Figure 5 shows the signal diagram and circuit diagram of the n+2 low color-off structure.
  • the commonly used "five mask” manufacturing method if you want to convert the manufacturing type, from n+1 type to n+2 type, you need to completely replace the five mask pattern design from beginning to end to change the glass panel. Structure. This severely reduces production efficiency during the type conversion of different low color-offset design, requires extensive adjustment of process conditions, and requires high mask manufacturing costs.
  • the glass panel includes: a first metal layer for forming a scan line and a charge sharing line, wherein one scan line and one corresponding charge sharing line collectively correspond to one row of pixel units; and a wiring metal layer for forming a connection wiring
  • the connection wiring is capable of connecting the scan line and the charge sharing line, wherein the connection wiring has a via portion, and the connection wiring is connected to the via hole in the via portion through the via hole Scan lines and/or the charge sharing lines.
  • the charge sharing line in the previous group can be opened by the scan line that is turned on later, and the amount of the flip chip is reduced in the manufacturing and packaging process.
  • each of the connecting wires includes a trunk portion extending in a straight line, and an elongated first via portion, a second via portion, and a third via portion extending perpendicular to the trunk portion, wherein The second via portion is located between the first via portion and the third via portion.
  • an n+2 type low color shift structure is formed, the n+2 type low color shift structure is calculated from one end of the glass panel, and the nth charge sharing line is started by the n+2th scan line.
  • n is a positive integer.
  • the first via portion is connected to the nth charge sharing line through a via
  • the third via portion is connected to the n+2th scan line through the via hole
  • the second via portion is suspended.
  • an n+1 type low color shift structure is formed, the n+1 type low color shift structure is calculated from one end of the glass panel, and the nth charge sharing line is activated by the n+1th scan line.
  • n is a positive integer.
  • the first via portion is suspended, the second via portion is connected to the nth charge sharing line through a via, and the third via portion passes through the via Connect to the n+1th scan line.
  • the n+1 or n+2 low color shift design structure effectively reduces the color shift of the display while saving the flip chip that is consumed during manufacturing and packaging. Further reducing manufacturing costs.
  • the rest of the masks can be the same set, and only the mask pattern of the first metal layer M1 needs to be changed. This greatly saves the material cost and process cost of manufacturing the mask.
  • the wiring metal layer is in the same layer as the second metal layer for forming the source drain of the thin film transistor. This simplifies the process and reduces the number of masks.
  • the pixel unit includes a main area and a sub-area respectively provided with different pixel electrodes, the sub-area additionally provided with a shared thin film transistor and a sharing capacitor, and the pixel electrode of the sub-area is connected to the sharing film a source of the transistor, a drain of the shared thin film transistor is connected to the sharing capacitor, and a gate of the sharing thin film transistor is connected to the charge sharing line.
  • the shared thin film transistor is turned on, and the liquid crystal capacitor and the storage capacitor of the sub-area are A portion of the voltage enters the sharing capacitor through the shared thin film transistor, causing a potential difference between the main region and the sub-region.
  • the potential difference can be adjusted by the regulating mechanism to adjust the color of the display screen and reduce the color shift.
  • the scan line simultaneously controls pixel electrodes in the main and sub-regions of the pixel unit through a plurality of charge thin film transistors.
  • the present invention also proposes a method for manufacturing a glass panel according to the present invention, which is manufactured by a five-mask method in which a first mask is used to fabricate a first metal layer on a glass substrate. And then covering the insulating layer, using a second mask on the insulating layer to fabricate the active layer, using a third mask over the active layer to fabricate the second metal layer, and manufacturing the fourth layer through the fourth mask a via layer thereon, the electrode layer is formed through the fifth mask over the via layer, wherein the positional relationship between the scan line and the charge sharing line is changed only by changing the pattern of the first mask Thereby, conversion between the n+1 type low color shift structure and the n+2 type low color shift structure is realized.
  • the remaining masks can adopt the same set, and only the first metal layer M1 The mask pattern needs to be changed. This greatly saves the material cost and process cost of manufacturing the mask.
  • the n+1 or n+2 low color shift design structure it effectively reduces the color shift of the display while saving the flip chip that is consumed in the manufacturing and packaging process. Further reducing manufacturing costs.
  • Figure 1 shows a prior art process step for fabricating a glass panel
  • Figure 2 shows a prior art "five mask” method for fabricating a glass panel
  • FIG. 3 is a schematic view showing the structure of a pixel unit using a low color shift structure
  • Figure 4 shows a circuit diagram of a pixel unit employing a low color shift structure
  • Figure 5 shows the signal diagram and circuit diagram of the n+2 type low color shift structure
  • FIG. 6 is a structural view showing a glass panel according to the present invention using an n+2 type low color shift structure
  • Fig. 7 is a view showing the structure of a glass panel according to the present invention in which a n+1 type low color shift structure is employed.
  • the present invention proposes a glass panel.
  • Fig. 6 is a view showing the structure of a glass panel according to the present invention in which an n+2 type low color shift structure is employed.
  • a glass panel according to the present invention includes a first metal layer M1 for forming a scan line 11 and a charge sharing line 12.
  • One of the scan lines 11 and a corresponding charge share line 12 collectively correspond to a row of pixel cells on the glass panel.
  • the first metal layer M1 is completed by the first mask. That is, the position of the scan line 11 and the charge sharing line 12 is determined by the pattern of the first mask. A common line 14 may also be included in the metal layer M1.
  • the glass panel according to the present invention further includes a wiring metal layer for forming the connection wiring 15.
  • the connection wiring 15 can connect the scanning line 11 and the charge sharing line 12.
  • the connection wiring 15 may have a via portion, and the connection wiring 15 is connected to the scan line 11 and/or the charge sharing line 12 through the via hole 18 in the via portion.
  • the enlarged structure of the via portion is shown on the right side of Fig. 6.
  • the via portion connects the wiring metal layer and the first metal layer M1 through the via holes 18.
  • an ITO layer 17 is also overlaid on top of the two metal layers (of course, it is not necessarily adjacent to the metal layer).
  • each of the connecting wires 15 includes a trunk portion extending in a straight line.
  • the trunk portion extends in the longitudinal direction (up and down direction in the drawing).
  • the connection wiring 15 further includes a first via portion 31, a second via portion 32, and a third via portion 33 that extend perpendicularly to the main line portion.
  • the first via portion 31, the second via portion 32, and the third via portion 33 are both elongated and extend in the lateral direction (left-right direction in the drawing).
  • the second via portion 32 is located between the first via portion 31 and the third via portion 33.
  • the glass panel according to the present invention forms an n+2 type low color shift structure.
  • the n+2 type low color shift structure that is, calculated from one end of the glass panel, the nth charge sharing line 12 is activated by the n+2th scan line 11, where n is a positive integer.
  • the first via portion 31 is connected to the nth charge sharing line 12 through the via 18, and the third via portion 33 is connected to the n+2th scan line 11 through the via 18.
  • the second via portion 32 is suspended and is not connected to any line. In this way, a structure is realized in which a scanning line 11 and a charge sharing line 12 connected by the connection wiring 15 are separated by a scanning line and a charge sharing line, and it can be known that the nth charge sharing line 12 is nth. +2 scan lines 11 are activated.
  • the glass panel can be fabricated by a "five mask” method, and the wiring metal layer can be designed to be in the same layer as the second metal layer M2 for forming the source drain of the thin film transistor. This can reduce the number of masks and shorten the manufacturing process.
  • one pixel unit may include a main region 21 and a sub-region 22 each provided with a different pixel electrode.
  • the sub-region 22 is additionally provided with a shared thin film transistor Tcs and a shared capacitor Cb.
  • the pixel electrode of the sub-region 22 (as shown in FIG.
  • the pixel electrode of the sub-region 22 includes, for example, a liquid crystal capacitor Clc sub and a storage capacitor CST sub ) is connected to the source of the shared thin film transistor Tcs, and the drain connection of the shared thin film transistor Tcs To the sharing capacitor Cb, the gate of the shared thin film transistor Tcs is connected to the charge sharing line 12.
  • the scan line 11 simultaneously controls the pixel electrodes in the main region 21 and the sub-region 22 of the pixel unit through the plurality of charge thin film transistors T main and T sub .
  • the scanning lines 11 are respectively connected to the gate of the thin film transistor gate charging and charging sub-area of the main region 21 of the thin film transistor T main T sub 22 to thereby control the charging and the thin film transistor T main region 21 of the main sub-region The on/off of the charging thin film transistor T sub of 22.
  • the charging film 21 to open the main area of the sub-region and the transistor T main charging the thin film transistor T sub 22 such that the electric signal from the data line 13 may be introduced into the liquid crystal capacitor Clc main storage capacitor CST and the main region 21
  • the liquid crystal capacitor Clc sub of the main and sub-region 22 and the storage capacitor CST sub are the liquid crystal capacitor Clc sub of the main and sub-region 22 and the storage capacitor CST sub .
  • the liquid crystal capacitor Clc sub and the storage capacitor CST sub of the sub -region 22 are respectively connected to the source of the shared thin film transistor Tcs, and the drain of the shared thin film transistor Tcs is connected to the sharing capacitor Cb, and the gate of the shared thin film transistor Tcs is connected to the charge. Share line 12.
  • the share thin film transistor Tcs is turned on, the liquid crystal capacitor Clc sub and a part of the storage capacitor CST sub
  • the voltage enters the sharing capacitor Cb through the sharing thin film transistor Tcs, thereby causing a potential difference between the main region 21 and the sub-region 22. And the potential difference can be adjusted by the regulating mechanism to adjust the color of the display screen and reduce the color shift.
  • the glass panel according to the present invention can also form an n+1 type low color shift structure.
  • the n+1 type low color shift structure that is, calculated from one end of the glass panel, the nth charge sharing line 12 is activated by the n+1th scan line 11, where n is a positive integer.
  • the first via portion 31 is suspended, and the second via portion 32 is connected to the nth charge sharing line 12 through the via hole, and the third via hole
  • the portion 33 is connected to the n+1th scanning line through a via.
  • the glass panel is fabricated by a "five mask” method, it may be designed such that the wiring metal layer is in the same layer as the second metal layer M2 used to form the source drain of the thin film transistor. This can reduce the number of masks and shorten the manufacturing process.
  • one pixel unit may include a main region 21 and a sub-region 22 each provided with a different pixel electrode.
  • the sub-region 22 is additionally provided with a shared thin film transistor Tcs and a shared capacitor Cb.
  • the pixel electrode of the sub-region 22 (as shown in FIG.
  • the pixel electrode of the sub-region 22 includes, for example, a liquid crystal capacitor Clc sub and a storage capacitor CST sub ) is connected to the source of the shared thin film transistor Tcs, and the drain connection of the shared thin film transistor Tcs To the sharing capacitor Cb, the gate of the shared thin film transistor Tcs is connected to the charge sharing line 12.
  • the scanning line 11 simultaneously controls the pixel electrodes in the main region 21 and the sub-region 22 of the pixel unit through the plurality of charging thin film transistors T main and T sub .
  • the scanning lines 11 are respectively connected to the gate of the thin film transistor gate charging and charging sub-area of the main region 21 of the thin film transistor T main T sub 22 to thereby control the charging and the thin film transistor T main region 21 of the main sub-region The on/off of the charging thin film transistor T sub of 22.
  • the charging film 21 to open the main area of the sub-region and the transistor T main charging the thin film transistor T sub 22 such that the electric signal from the data line 13 may be introduced into the liquid crystal capacitor Clc main storage capacitor CST and the main region 21
  • the liquid crystal capacitor Clc sub of the main and sub-region 22 and the storage capacitor CST sub are the liquid crystal capacitor Clc sub of the main and sub-region 22 and the storage capacitor CST sub .
  • the liquid crystal capacitor Clc sub and the storage capacitor CST sub of the sub -region 22 are respectively connected to the source of the shared thin film transistor Tcs, and the drain of the shared thin film transistor Tcs is connected to the sharing capacitor Cb, and the gate of the shared thin film transistor Tcs is connected to the charge. Share line 12.
  • the share thin film transistor Tcs is turned on, the liquid crystal capacitor Clc sub and a part of the storage capacitor CST sub
  • the voltage enters the sharing capacitor Cb through the sharing thin film transistor Tcs, thereby causing a potential difference between the main region 21 and the sub-region 22. And the potential difference can be adjusted by the regulating mechanism to adjust the color of the display screen and reduce the color shift.
  • the invention also proposes a method for manufacturing a glass panel according to the invention.
  • the glass panel is produced by a five masking method, namely:
  • An electrode layer is fabricated through a fifth mask over the via layer.
  • the positional relationship between the scan line and the charge sharing line is changed only by changing the pattern of the first mask, thereby realizing the n+1 type low color shift structure and the n+2 type low. Conversion between color-shifted structures.
  • the remaining masks can adopt the same set, and only the first metal layer M1 The mask pattern needs to be changed. This greatly saves the material cost and process cost of manufacturing the mask.
  • the n+1 or n+2 low color shift design structure it effectively reduces the color shift of the display while saving the flip chip that is consumed in the manufacturing and packaging process. Further reducing manufacturing costs.

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Abstract

一种玻璃面板，包括：用于形成扫描线（11）和电荷分享线（12）的第一金属层（M1）；用于形成连接配线（15）的配线金属层，其中，连接配线（15）具有过孔部，连接配线（15）在过孔部中通过过孔（18）连接到扫描线（11）和/或电荷分享线（12）。还提供了相应的制造方法。该玻璃面板可以通过后开启的扫描线（11）来打开前一组中的电荷分享线（12），在制造和封装的工艺中，减少了覆晶薄膜的使用量。

Description

玻璃面板和用于制造所述面板的方法
相关申请的交叉引用
本申请要求享有于2014年10月20日提交的名称为“玻璃面板和用于制造所述面板的掩膜”的中国专利申请CN201410559637.4的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示面板制造领域，尤其涉及一种玻璃面板和用于制造所述面板的方法。
背景技术
在现有技术中，通常采用如图1所示的工艺步骤来制造薄膜晶体管液晶显示器的阵列基板。参照图1，在步骤a中，在玻璃基板上镀膜。在步骤b中，在所镀的膜层上涂布光阻材料。在步骤c中，在掩膜105的遮蔽下，对涂布光阻材料后的玻璃板进行光照。在步骤d中，进行显影。在步骤e中，进行刻蚀。在步骤f中，通过去光阻液106对所处理的玻璃板去除光阻。之后可得到具有图形的镀层，而后循环至步骤a，进行下一次镀层的处理。不断循环步骤a至f，直至得到具有多个镀层的所需的玻璃面板。
现有技术中，常用“五道掩膜”工艺来制造用于液晶显示器的阵列基板的玻璃面板。“五道掩膜”，主要重复进行五次如图1所示的工艺步骤，通过五道不同的掩膜105，来形成玻璃基板上的五个层。
图2显示了“五道掩膜”工艺所制造的玻璃面板的横截面剖视图。参照图2，位于最下层的为玻璃基板1。在玻璃基板1上通过图1所示的方法，用第一道掩膜来制造栅极2(其位于第一金属层M1中)，而后覆盖绝缘层3。在绝缘层3之上，用第二道掩膜来制造例如由不同半导体材料4和5构成的有源层。在有源层4和5之上，用第三道掩膜来制造源极6和漏极7(位于第二金属层M2中)。位于其之上的为具有过孔8的过孔层，过孔层通过第四道掩膜来制造。在过孔层 之上通过第五道掩膜来制造用作电极的ITO层9。
图3显示了现有技术中的液晶像素单元。为了提高视角、降低色偏，在大尺寸的面板中，通常会做低色偏的设计。例如通过增加像素单元的域，可以将一个像素单元分成4个像素域。如果将一个像素单元进一步分割为主区21和副区22，则可以增加到8个像素域，以达到提高视角、改善色偏的目的。
像素单元的主区21和副区22通常通过两个或更多不同的薄膜晶体管来供电。图4所示为一种常见的带有低色偏设计的像素单元的等效电路图。一个像素单元分为主区和副区。在扫描线11打开时，位于主区的薄膜晶体管Tmain和位于副区的薄膜晶体管Tsub导通，分别将来自数据线13的电信号送至位于像素单元的主区和副区的液晶电容和存储电容中。当扫描线11关闭、电荷分享线12打开时，分享薄膜晶体管Tcs导通，将位于副区的液晶电容Clcsub和存储电容CSTsub中的部分电压释放到分享电容Cb中。这样像素单元的副区和主区之间就会呈现出电位差，再辅以调控，可以达到降低色偏的目的。
在通常的设计中，扫描线11和电荷分享线12是相互独立的，在显示时需要通过分别控制扫描线11和电荷分享线12的开关来实现低色偏设计。但是由于上述方法扫描线11和电荷分享线12相互独立，在制造和封装的工艺中，需要消耗较多的覆晶薄膜(COF)。
另一种低色偏设计方案是通过后开启的扫描线11来打开前一组中的电荷分享线12。例如从面板的一端计算，第n条扫描线对应第n行像素单元时，通过第n+p条扫描线11打开第n组中的电荷分享线12，即称作n+p型的低色偏设计。这种设计的好处是减少了覆晶薄膜的使用量。图5即显示了n+2型低色偏结构的信号图和电路图。
然而目前在现有技术中，对于n+1型、n+2型甚至是n+p型的低色偏设计而言，每一种不同的结构设计都需要单独类型的掩膜来进行图1所示的处理步骤。制造工艺复杂度很高，大大推升了玻璃面板制造的成本，为相关产品的大规模生产带来很大障碍。
发明内容
目前在现有技术中，对于不同类型的低色偏设计结构而言(例如n+1型和n+2型)，每一种不同的结构设计都需要独特类型的掩膜来进行曝光、蚀刻等工艺步 骤。制造工艺非常繁琐。且转换制造类型时，必须更换全部的掩膜，成本高昂，不利于节省材料和工序。且不同的掩膜如果相互配合不当，容易造成误差。
例如通常采用的“五道掩膜”制造方法，如果想转换制造类型，从n+1型转换为n+2型，则需要从头到尾彻底更换五个掩膜的图案设计，以更改玻璃面板的结构。这在不同的低色偏结构设计的类型转换的过程中严重降低了生产效率，需要大力调整工艺条件步骤，同时需要承担高昂的掩膜制造成本。
针对上述问题，发明人提出了一种改进的玻璃面板。
所述玻璃面板包括：用于形成扫描线和电荷分享线的第一金属层，其中一条扫描线和一条相应的电荷分享线共同对应于一行像素单元；用于形成连接配线的配线金属层，所述连接配线能够将所述扫描线和所述电荷分享线连接起来，其中，所述连接配线具有过孔部，所述连接配线在过孔部中通过过孔连接到所述扫描线和/或所述电荷分享线。
以此方式，可以通过后开启的扫描线来打开前一组中的电荷分享线，在制造和封装的工艺中，减少了覆晶薄膜的使用量。
优选地，每条所述连接配线包括沿直线延伸的干线部分，和垂直于所述干线部分而延伸出来的狭长的第一过孔部、第二过孔部和第三过孔部，其中所述第二过孔部位于所述第一过孔部和所述第三过孔部之间。
采用此结构设计，仅通过改变第一道掩膜的图案来改变扫描线和电荷分享线之间的位置关系，由此实现n+1型低色偏结构和n+2型低色偏结构之间的转换。
优选地，形成n+2型低色偏结构，所述n+2型低色偏结构即从所述玻璃面板的一端开始计算，第n条电荷分享线由第n+2条扫描线启动，其中n为正整数。
优选地，在第n条连接配线中，所述第一过孔部通过过孔连接到第n条电荷分享线，所述第三过孔部通过过孔连接到第n+2条扫描线，所述第二过孔部悬空。
优选地，形成n+1型低色偏结构，所述n+1型低色偏结构即从所述玻璃面板的一端开始计算，第n条电荷分享线由第n+1条扫描线启动，其中n为正整数。
优选地，在第n条连接配线中，所述第一过孔部悬空，所述第二过孔部通过过孔连接到第n条电荷分享线，所述第三过孔部通过过孔连接到第n+1条扫描线。
通过n+1或n+2型的低色偏设计结构，有效在降低显示器的色偏状况的同时，节省了制造和封装过程中所消耗的覆晶薄膜。进一步降低了制造成本。
制造根据本发明的玻璃面板，采用n+1型低色偏结构和n+2型低色偏结构时， 其余的掩膜可采用同一套，只有第一金属层M1的掩膜图案需要改变。这大大节省了制造掩膜的材料成本和工序成本。
优选地，所述配线金属层与用于形成薄膜晶体管的源漏极的第二金属层位于同一层中。如此可以简化工序，减少掩膜数量。
优选地，所述像素单元包括分别配备有不同的像素电极的主区和副区，所述副区额外设置有分享薄膜晶体管和分享电容，且所述副区的像素电极连接到所述分享薄膜晶体管的源极，所述分享薄膜晶体管的漏极连接至所述分享电容，所述分享薄膜晶体管的栅极连接至所述电荷分享线。
如此地，当第n条扫描线关闭，而第n条电荷分享线由第n+1条或第n+2条扫描线启动时，分享薄膜晶体管被打开，副区的液晶电容和存储电容中的一部分电压会经过分享薄膜晶体管而进入到分享电容中，从而在主区和副区之间造成电位差。且通过调控机构可以调节该电位差，从而调节显示画面颜色，降低色偏。
优选地，所述扫描线通过多个充电薄膜晶体管同时控制所述像素单元的主区和副区中的像素电极。
本发明还提出了一种用于制造根据本发明所述的玻璃面板的方法，所述玻璃面板通过五道掩膜方法制造，在玻璃基板上用第一道掩膜来制造第一金属层，而后覆盖绝缘层，在绝缘层之上用第二道掩膜来制造有源层，在有源层之上用第三道掩膜来制造第二金属层，通过第四道掩膜来制造位于其之上的过孔层，在过孔层之上通过第五道掩膜来制造电极层，其中，仅通过改变第一道掩膜的图案来改变扫描线和电荷分享线之间的位置关系，由此实现n+1型低色偏结构和n+2型低色偏结构之间的转换。
采用根据本发明的方法来制造根据本发明的玻璃面板，采用n+1型低色偏结构和n+2型低色偏结构时，其余的掩膜可采用同一套，只有第一金属层M1的掩膜图案需要改变。这大大节省了制造掩膜的材料成本和工序成本。同时，通过n+1或n+2型的低色偏设计结构，有效在降低显示器的色偏状况的同时，节省了制造和封装过程中所消耗的覆晶薄膜。进一步降低了制造成本。
上述技术特征可以各种适合的方式组合或由等效的技术特征来替代，只要能够达到本发明的目的。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1显示了现有技术中的用于制造玻璃面板的工艺步骤；
图2显示了现有技术中的用于制造玻璃面板的“五道掩膜”方法；
图3显示了采用低色偏结构的像素单元的结构示意图；
图4显示了采用低色偏结构的像素单元的电路图；
图5显示了n+2型低色偏结构的信号图和电路图；
图6显示了根据本发明的玻璃面板采用n+2型低色偏结构时的结构示图；以及
图7显示了根据本发明的玻璃面板采用n+1型低色偏结构时的结构示图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
下面将结合附图对本发明作进一步说明。
本发明提出了一种玻璃面板。
图6显示了根据本发明的玻璃面板采用n+2型低色偏结构时的结构示图。参照图6，根据本发明的玻璃面板包括用于形成扫描线11和电荷分享线12的第一金属层M1。其中一条扫描线11和一条相应的电荷分享线12共同对应于玻璃面板上的一行像素单元。
在通过“五道掩膜”方法进行制造的过程中，第一金属层M1通过第一道掩膜来完成。也就是说，扫描线11和电荷分享线12的位置由第一道掩膜的图案决定。金属层M1中还可包括公共线14。
根据本发明的玻璃面板还包括用于形成连接配线15的配线金属层。连接配线15能够将扫描线11和电荷分享线12连接起来。具体地可以是，连接配线15具有过孔部，连接配线15在过孔部中通过过孔18连接到扫描线11和/或电荷分享线12。图6中右侧即显示了过孔部的放大结构示意图。从放大图中可看到，过孔部通过过孔18连接配线金属层和第一金属层M1。同时，在所述两个金属层之上还覆盖有ITO层17(当然，其未必与金属层紧紧相邻)。
由图6可看出，每条连接配线15包括沿直线延伸的干线部分。在图6中，干线部分沿纵向方向延伸(图中的上下方向)。连接配线15还包括垂直于干线部分而延伸出来的第一过孔部31、第二过孔部32和第三过孔部33。在图6中， 第一过孔部31、第二过孔部32和第三过孔部33均为狭长的，且沿横向方向延伸(图中的左右向)。在图6中，第二过孔部32位于第一过孔部31和第三过孔部33之间。
在图6所示的情况中，根据本发明的玻璃面板形成了n+2型低色偏结构。所述n+2型低色偏结构，即从玻璃面板的一端开始计算，第n条电荷分享线12由第n+2条扫描线11启动，其中n为正整数。
从图6中可看到，第一过孔部31通过过孔18连接到第n条电荷分享线12，而第三过孔部33部通过过孔18连接到第n+2条扫描线11，第二过孔部32悬空，未与任何线路相连。以此方式，实现了如下结构：通过连接配线15相连的扫描线11和电荷分享线12中间隔了一条扫描线、一条电荷分享线，即可知道，第n条电荷分享线12由第n+2条扫描线11启动。
在一个实施例中，如通过“五道掩膜”法制造玻璃面板，可以设计为配线金属层与用于形成薄膜晶体管的源漏极的第二金属层M2位于同一层中。如此可以降低掩膜数量，缩短制造工序。
再次参照图3。正如先前所介绍，在采用低色偏设计的玻璃面板中，一个像素单元可以包括分别配备有不同的像素电极的主区21和副区22。结合图4所示的电路图，可清楚地看出，副区22额外设置有分享薄膜晶体管Tcs和分享电容Cb。副区22的像素电极(如图4所示，副区22的像素电极例如包括液晶电容Clcsub和存储电容CSTsub)连接到分享薄膜晶体管Tcs的源极，而分享薄膜晶体管Tcs的漏极连接至分享电容Cb，分享薄膜晶体管Tcs的栅极连接至电荷分享线12。
扫描线11通过多个充电薄膜晶体管Tmain和Tsub同时控制像素单元的主区21和副区22中的像素电极。参照图4，扫描线11分别连接至主区21的充电薄膜晶体管Tmain的栅极和副区22的充电薄膜晶体管Tsub的栅极，从而控制主区21的充电薄膜晶体管Tmain和副区22的充电薄膜晶体管Tsub的通断。当扫描线11启动时，开启主区21的充电薄膜晶体管Tmain和副区22的充电薄膜晶体管Tsub，使得来自数据线13的电信号可以导入主区21的液晶电容Clcmain和存储电容CSTmain以及副区22的液晶电容Clcsub和存储电容CSTsub。
同时，副区22的液晶电容Clcsub和存储电容CSTsub分别连通至分享薄膜晶体管Tcs的源极，而分享薄膜晶体管Tcs的漏极连接至分享电容Cb，分享薄膜晶体管Tcs的栅极连接至电荷分享线12。如此地，当第n条扫描线11关闭，第n条 电荷分享线12由第n+2条扫描线11启动时，分享薄膜晶体管Tcs被打开，液晶电容Clcsub和存储电容CSTsub中的一部分电压会经过分享薄膜晶体管Tcs而进入到分享电容Cb中，从而在主区21和副区22之间造成电位差。且通过调控机构可以调节该电位差，从而调节显示画面颜色，降低色偏。
然而，除了上述n+2型低色偏结构，根据本发明的玻璃面板也可形成n+1型低色偏结构。所述n+1型低色偏结构，即从玻璃面板的一端开始计算，第n条电荷分享线12由第n+1条扫描线11启动，其中n为正整数。
从图7中可看到，在n+1型低色偏结构中，第一过孔部31悬空，第二过孔部32通过过孔连接到第n条电荷分享线12，第三过孔部33通过过孔连接到第n+1条扫描线。以此方式，实现了如下结构：通过相应的连接配线15相连的扫描线11和电荷分享线12相邻，即可知道，第n条电荷分享线12由第n+1条扫描线11启动。
在一个实施例中，如通过“五道掩膜”法制造玻璃面板，可以设计为配线金属层与用于形成薄膜晶体管的源漏极的所述第二金属层M2位于同一层中。如此可以降低掩膜数量，缩短制造工序。
再次参照图3。正如先前所介绍，在采用低色偏设计的玻璃面板中，一个像素单元可以包括分别配备有不同的像素电极的主区21和副区22。结合图4所示的电路图，可清楚地看出，副区22额外设置有分享薄膜晶体管Tcs和分享电容Cb。副区22的像素电极(如图4所示，副区22的像素电极例如包括液晶电容Clcsub和存储电容CSTsub)连接到分享薄膜晶体管Tcs的源极，而分享薄膜晶体管Tcs的漏极连接至分享电容Cb，分享薄膜晶体管Tcs的栅极连接至电荷分享线12。
扫描线11通过多个充电薄膜晶体管Tmain、Tsub同时控制像素单元的主区21和副区22中的像素电极。参照图4，扫描线11分别连接至主区21的充电薄膜晶体管Tmain的栅极和副区22的充电薄膜晶体管Tsub的栅极，从而控制主区21的充电薄膜晶体管Tmain和副区22的充电薄膜晶体管Tsub的通断。当扫描线11启动时，开启主区21的充电薄膜晶体管Tmain和副区22的充电薄膜晶体管Tsub，使得来自数据线13的电信号可以导入主区21的液晶电容Clcmain和存储电容CSTmain以及副区22的液晶电容Clcsub和存储电容CSTsub。
同时，副区22的液晶电容Clcsub和存储电容CSTsub分别连通至分享薄膜晶体管Tcs的源极，而分享薄膜晶体管Tcs的漏极连接至分享电容Cb，分享薄膜晶体 管Tcs的栅极连接至电荷分享线12。如此地，当第n条扫描线11关闭，而第n条电荷分享线12由第n+1条扫描线11启动，分享薄膜晶体管Tcs被打开，液晶电容Clcsub和存储电容CSTsub中的一部分电压会经过分享薄膜晶体管Tcs而进入到分享电容Cb中，从而在主区21和副区22之间造成电位差。且通过调控机构可以调节该电位差，从而调节显示画面颜色，降低色偏。
本发明还提出了一种用于制造根据本发明的玻璃面板的方法。
在根据本发明的方法中，玻璃面板通过五道掩膜方法制造，即：
在玻璃基板上用第一道掩膜来制造第一金属层，而后覆盖绝缘层；
在绝缘层之上用第二道掩膜来制造有源层；
在有源层之上用第三道掩膜来制造第二金属层；
通过第四道掩膜来制造位于其之上的过孔层；
在过孔层之上通过第五道掩膜来制造电极层。
而在根据本发明的方法中，仅通过改变第一道掩膜的图案来改变扫描线和电荷分享线之间的位置关系，由此实现n+1型低色偏结构和n+2型低色偏结构之间的转换。
采用根据本发明的方法来制造根据本发明的玻璃面板，采用n+1型低色偏结构和n+2型低色偏结构时，其余的掩膜可采用同一套，只有第一金属层M1的掩膜图案需要改变。这大大节省了制造掩膜的材料成本、工序成本。同时，通过n+1或n+2型的低色偏设计结构，有效在降低显示器的色偏状况的同时，节省了制造和封装过程中所消耗的覆晶薄膜。进一步降低了制造成本。
虽然已经参考优选实施例对本发明进行了描述，但在不脱离本发明的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (10)

  1. 一种玻璃面板，其中，包括：
    用于形成扫描线和电荷分享线的第一金属层，其中一条扫描线和一条相应的电荷分享线共同对应于一行像素单元；
    用于形成连接配线的配线金属层，所述连接配线能够将所述扫描线和所述电荷分享线连接起来，
    其中，所述连接配线具有过孔部，所述连接配线在过孔部中通过过孔连接到所述扫描线和/或所述电荷分享线。
  2. 根据权利要求1所述的玻璃面板，其中，每条所述连接配线包括沿直线延伸的干线部分，和垂直于所述干线部分而延伸出来的狭长的第一过孔部、第二过孔部和第三过孔部，其中所述第二过孔部位于所述第一过孔部和所述第三过孔部之间。
  3. 根据权利要求2所述的玻璃面板，其中，形成n+2型低色偏结构，所述n+2型低色偏结构即从所述玻璃面板的一端开始计算，第n条电荷分享线由第n+2条扫描线启动，其中n为正整数。
  4. 根据权利要求3所述的玻璃面板，其中，在第n条连接配线中，所述第一过孔部通过过孔连接到第n条电荷分享线，所述第三过孔部通过过孔连接到第n+2条扫描线，所述第二过孔部悬空。
  5. 根据权利要求2所述的玻璃面板，其中，形成n+1型低色偏结构，所述n+1型低色偏结构即从所述玻璃面板的一端开始计算，第n条电荷分享线由第n+1条扫描线启动，其中n为正整数。
  6. 根据权利要求5所述的玻璃面板，其中，在第n条连接配线中，所述第一过孔部悬空，所述第二过孔部通过过孔连接到第n条电荷分享线，所述第三过孔部通过过孔连接到第n+1条扫描线。
  7. 根据权利要求1所述的玻璃面板，其中，所述配线金属层与用于形成薄膜晶体管的源漏极的第二金属层位于同一层中。
  8. 根据权利要求1所述的玻璃面板，其中，所述像素单元包括分别配备有不同的像素电极的主区和副区，所述副区额外设置有分享薄膜晶体管和分享电容，且所述副区的像素电极连接到所述分享薄膜晶体管的源极，所述分享薄膜晶体管 的漏极连接至所述分享电容，所述分享薄膜晶体管的栅极连接至所述电荷分享线。
  9. 根据权利要求8所述的玻璃面板，其中，所述扫描线通过多个充电薄膜晶体管同时控制所述像素单元的主区和副区中的像素电极。
  10. 用于制造玻璃面板的方法，
    所述玻璃面板包括：
    用于形成扫描线和电荷分享线的第一金属层，其中一条扫描线和一条相应的电荷分享线共同对应于一行像素单元；
    用于形成连接配线的配线金属层，所述连接配线能够将所述扫描线和所述电荷分享线连接起来，
    其中，所述连接配线具有过孔部，所述连接配线在过孔部中通过过孔连接到所述扫描线和/或所述电荷分享线，
    所述玻璃面板通过五道掩膜方法制造，其中，在玻璃基板上用第一道掩膜来制造第一金属层，而后覆盖绝缘层，在绝缘层之上用第二道掩膜来制造有源层，在有源层之上用第三道掩膜来制造第二金属层，通过第四道掩膜来制造位于其之上的过孔层，在过孔层之上通过第五道掩膜来制造电极层，仅通过改变第一道掩膜的图案来改变扫描线和电荷分享线之间的位置关系，由此实现n+1型低色偏结构和n+2型低色偏结构之间的转换。
PCT/CN2014/093985 2014-10-20 2014-12-16 玻璃面板和用于制造所述面板的方法 WO2016061885A1 (zh)

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