WO2019237642A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2019237642A1
WO2019237642A1 PCT/CN2018/113782 CN2018113782W WO2019237642A1 WO 2019237642 A1 WO2019237642 A1 WO 2019237642A1 CN 2018113782 W CN2018113782 W CN 2018113782W WO 2019237642 A1 WO2019237642 A1 WO 2019237642A1
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Prior art keywords
metal layer
layer
electrode
gate
drain
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PCT/CN2018/113782
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English (en)
French (fr)
Inventor
周依芳
徐鉉植
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2019237642A1 publication Critical patent/WO2019237642A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate and a manufacturing method thereof.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • each pixel is electrically connected to a thin film transistor (TFT), the gate of the thin film transistor is connected to a horizontal scanning line, the drain is connected to a vertical data line, and the source (Source ) Is connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly performed by an external integrated circuit board (Integrated Circuit, IC) to complete, the external IC can control the progressive charging and discharging of the horizontal scanning lines at all levels.
  • IC Integrated Circuit
  • GOA technology Gate Driver on Array
  • the gate driving circuit can be fabricated on the TFT array substrate by using the array process of the liquid crystal display panel to realize the driving method of progressive scanning of the gate.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product costs, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • Common GOA circuits include a pull-up circuit, a pull-up control circuit, a pass-through circuit, a pull-down circuit, a pull-down hold circuit, and a rising circuit.
  • the pull-up circuit is mainly responsible for generating a scanning signal according to the input clock signal and outputting it to each subpixel. The gate of the thin film transistor is scanned progressively.
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit. Generally, the signal is transmitted by the upper GOA circuit.
  • the pull-down circuit is responsible for quickly pulling the scan signal to a low level after outputting the scan signal.
  • the pull-down holding circuit is responsible for keeping the scan signal and the signal of the switch node of the pull-up circuit in the off state during the non-working phase. In the rising circuit, the load raises the switching node potential of the pull-up circuit twice during the working phase to ensure the normal output of the scanning signal.
  • the rising circuit of the GOA circuit includes a boosting capacitor (boosting cap), which is used to perform the second lifting of the switching node potential of the pull-up circuit.
  • boosting capacitor boosting cap
  • the main purpose of the GOA technology applied to liquid crystal displays is to narrow or borderless Display products, but in the existing GOA circuit, the boosting capacitor (Boosting cap) is formed by the gate metal and the drain metal and the insulating layer between the gate metal and the drain metal.
  • the boost capacitor of this structure requires The large area is not conducive to the realization of narrow or borderless frames.
  • the object of the present invention is to provide an array substrate, which can reduce the area of the boost capacitor of the GOA circuit and realize narrow frame or frameless display.
  • the object of the present invention is also to provide a method for manufacturing an array substrate, which can reduce the area of the boost capacitor of the GOA circuit, and realize narrow-frame or frameless display.
  • the present invention provides an array substrate including a base substrate, a first metal layer provided on the base substrate, and a first insulation provided on the first metal layer and the base substrate. Layer, a second metal layer provided on the first insulating layer, a passivation layer covering the first insulating layer and the second metal layer, and a third metal layer provided on the passivation layer;
  • the base substrate includes a display area and a GOA area located outside the display area;
  • the first metal layer includes a first gate electrode
  • the second metal layer includes a first source electrode and a first drain electrode spaced apart
  • the third metal layer includes an auxiliary electrode.
  • the first gate and the first drain are at least partially overlapped
  • the auxiliary electrode is at least partially overlapped with the first drain
  • the auxiliary electrode is passed through the first pass through the passivation layer and the first insulating layer.
  • the via is electrically connected to the first gate.
  • the first metal layer includes: a second gate electrode and a gate line electrically connected to the second gate electrode; the second metal layer includes a second source electrode and A second drain electrode and a source line electrically connected to the second source electrode; the third metal layer includes a pixel electrode, and the pixel electrode passes through the second via hole penetrating the passivation layer and the first metal electrode; The two drains are electrically connected.
  • the array substrate further includes a semiconductor layer between the first insulating layer and the second metal layer.
  • the semiconductor layer includes a first semiconductor island on a first insulation layer above the first gate and a second semiconductor island on a first insulation layer above the second gate;
  • the first source electrode and the first drain electrode are in contact with both ends of the first semiconductor island, and the second source electrode and the second drain electrode are in contact with both ends of the second semiconductor island.
  • the materials of the first metal layer and the second metal layer are a combination of one or more of molybdenum, aluminum, copper, and titanium; and the materials of the first insulating layer and the passivation layer are silicon oxide and nitrogen One or a combination of silicon compounds; the material of the third metal layer is indium tin oxide.
  • the invention also provides a method for manufacturing an array substrate, which includes the following steps:
  • Step S1 A base substrate is provided.
  • the base substrate includes a display area and a GOA area located outside the display area.
  • Step S2 A first metal thin film is formed on the base substrate and a first metal layer is formed through a first photomask process.
  • the first metal layer includes a first gate formed in the GOA region.
  • Step S3 covering a first insulating layer on the first metal layer and the base substrate;
  • Step S4 forming a second metal thin film on the first insulating layer and forming a second metal layer through a second photomask process;
  • the second metal layer includes: a first source formed at intervals in the GOA region Electrode and first drain, the first gate and the first drain at least partially overlap;
  • Step S5 A passivation layer is covered on the second metal layer and the first insulating layer, and a first via hole is formed through a third photomask process, and the first via hole penetrates the passivation layer and the first insulating layer. And exposing a part of the first gate;
  • Step S6 A third metal thin film is formed on the passivation layer and a third metal layer is formed by a fourth photomask process.
  • the third metal layer includes an auxiliary electrode formed in the GOA region.
  • the auxiliary electrode It is electrically connected to the first gate through a first via hole, and the first drain of the auxiliary electrode at least partially overlaps.
  • the first metal layer further includes: a second gate formed in the display region and a gate line electrically connected to the second gate;
  • the second metal layer further includes a second source electrode and a second drain electrode formed at intervals in the display area, and a source line electrically connected to the second source electrode;
  • a second via hole is further formed in the step S5, the second via hole penetrates the passivation layer and exposes a part of the second drain electrode;
  • the third metal layer further includes a pixel electrode formed in the display area, and the pixel electrode is electrically connected to the second drain through a second via hole.
  • the step S4 further includes forming a semiconductor layer between the first insulating layer and the second metal layer.
  • the semiconductor layer includes a first semiconductor island on a first insulation layer above the first gate and a second semiconductor island on a first insulation layer above the second gate;
  • the first source electrode and the first drain electrode are in contact with both ends of the first semiconductor island, and the second source electrode and the second drain electrode are in contact with both ends of the second semiconductor island.
  • the materials of the first metal layer and the second metal layer are a combination of one or more of molybdenum, aluminum, copper, and titanium; and the materials of the first insulating layer and the passivation layer are silicon oxide and nitrogen.
  • the present invention also provides an array substrate, including: a base substrate, a first metal layer provided on the base substrate, a first insulating layer provided on the first metal layer and the base substrate, and A second metal layer on the first insulating layer, a passivation layer covering the first insulating layer and the second metal layer, and a third metal layer provided on the passivation layer, wherein the second metal layer
  • the material of the metal layer is copper;
  • the base substrate includes a display area and a GOA area located outside the display area;
  • the first metal layer includes a first gate electrode
  • the second metal layer includes a first source electrode and a first drain electrode spaced apart
  • the third metal layer includes an auxiliary electrode.
  • the first gate and the first drain are at least partially overlapped
  • the auxiliary electrode is at least partially overlapped with the first drain
  • the auxiliary electrode is passed through the first pass through the passivation layer and the first insulating layer.
  • the via is electrically connected to the first gate.
  • the first metal layer includes: a second gate electrode and a gate line electrically connected to the second gate electrode; the second metal layer includes a second source electrode and A second drain electrode and a source line electrically connected to the second source electrode; the third metal layer includes a pixel electrode, and the pixel electrode passes through the second via hole penetrating the passivation layer and the first metal electrode; The two drains are electrically connected.
  • the array substrate further includes a semiconductor layer between the first insulating layer and the second metal layer.
  • the semiconductor layer includes a first semiconductor island on a first insulation layer above the first gate and a second semiconductor island on a first insulation layer above the second gate;
  • the first source electrode and the first drain electrode are in contact with both ends of the first semiconductor island, and the second source electrode and the second drain electrode are in contact with both ends of the second semiconductor island.
  • the material of the first metal layer is a combination of one or more of molybdenum, aluminum, copper, and titanium; and the material of the first insulating layer and the passivation layer is one of silicon oxide and silicon nitride or A combination of the two; the material of the third metal layer is indium tin oxide.
  • the present invention provides an array substrate.
  • the array substrate includes a base substrate, a first metal layer provided on the base substrate, and the first metal layer and the base substrate.
  • the base substrate includes a display area and a GOA area located outside the display area; in the GOA area, the first metal layer includes a first gate, and the second metal layer includes spaced apart
  • the third metal layer includes an auxiliary electrode, the first gate electrode and the first drain electrode at least partially overlap, and the auxiliary electrode and the first drain electrode at least partially overlap
  • the auxiliary electrode is electrically connected to the first gate through a first via hole penetrating the passivation layer and the first insulating layer, and is common through the first gate, the first drain, and the auxiliary electrode.
  • Forming a sandwich capacitor as a step-up capacitor for the GOA circuit can reduce GOA electricity
  • the boosting capacitor area, to realize a narrow border or no border is displayed.
  • the invention also provides a method for manufacturing an array substrate, which can reduce the area of the boost capacitor of the GOA circuit, and realize narrow frame or frameless display.
  • FIG. 1 is a schematic diagram of an array substrate of the present invention
  • FIG. 2 is a schematic diagram of a base substrate in an array substrate of the present invention.
  • FIG. 3 is a schematic cross-sectional view of a GOA region in an array substrate of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a display area in an array substrate of the present invention.
  • FIG. 5 is a schematic top view of a display area in an array substrate of the present invention.
  • FIG. 6 is a flowchart of a method for manufacturing an array substrate according to the present invention.
  • the present invention provides an array substrate including: a base substrate 10, a first metal layer 20 provided on the base substrate 10, a first metal layer 20 provided on the base substrate 10, and a substrate.
  • the first insulating layer 30 of the base substrate 10, the second metal layer 40 provided on the first insulating layer 30, the passivation layer 50 covering the first insulating layer 30 and the second metal layer 40, and the The third metal layer 60 on the passivation layer 50 is described.
  • the base substrate 10 includes a display area 11 and a GOA area 12 located on the periphery of the display area 11.
  • the display area 11 is used to form each pixel of a display panel.
  • the GOA area 12 is used to form a GOA circuit that drives each pixel of the display panel to work.
  • the first metal layer 20 includes a first gate electrode 21, and the second metal layer 40 includes a first source electrode 41 and a first electrode disposed at intervals.
  • a drain electrode 42, the third metal layer 60 includes an auxiliary electrode 61, the first gate electrode 21 and the first drain electrode 42 at least partially overlap, and the auxiliary electrode 61 and the first drain electrode 42 at least partially Overlapping, the auxiliary electrode 61 is electrically connected to the first gate electrode 21 through a first via hole 71 penetrating the passivation layer 50 and the first insulating layer 30.
  • the first metal layer 20 includes a second gate 22 and a gate electrically connected to the second gate 22. Electrode line 23; the second metal layer 40 includes a second source electrode 43 and a second drain electrode 44 spaced apart, and a source electrode line 45 electrically connected to the second source electrode 43; the third metal layer 60 includes a pixel electrode 62, and the pixel electrode 62 is electrically connected to the second drain electrode 44 through the second via hole 72 penetrating the passivation layer 50.
  • a complete array substrate should also include a semiconductor layer 80 between the first insulating layer 30 and the second metal layer 40.
  • the semiconductor layer 80 includes a first semiconductor island 81 on the first insulating layer 30 above the first gate 21 and a second semiconductor island 81 on the first insulating layer 30 above the second gate 22.
  • Semiconductor island 82; the first source electrode 41 and the first drain electrode 42 are in contact with both ends of the first semiconductor island 81, and the second source electrode 43 and the second drain electrode 44 are respectively in contact with the second Both ends of the semiconductor island 82 are in contact.
  • the materials of the first metal layer 20 and the second metal layer 40 are a combination of one or more of molybdenum, aluminum, copper, and titanium;
  • the material is one or a combination of silicon oxide and silicon nitride;
  • the material of the third metal layer 60 is indium tin oxide.
  • the material of the semiconductor layer 80 may be amorphous silicon, polysilicon, or an oxide semiconductor.
  • an auxiliary electrode 61 is formed on the GOA region 12 by using the third metal layer 60 where the pixel electrode 62 is located, and the auxiliary electrode 61 and the auxiliary electrode 61 are connected through the first via hole 71.
  • the first gate 21 is electrically connected together, so that the auxiliary electrode 61, the first gate 21, and the first drain 42 together form a sandwich capacitor as a step-up capacitor of the GOA circuit.
  • the sandwich capacitor is under the same capacitance. With a smaller area, it can reduce the occupied area of the GOA circuit, reduce the frame size of the display panel, and realize narrow or borderless display.
  • the material of the second metal layer 40 of the array substrate of the present invention is preferably copper, in order to improve the conductivity of the second metal layer 40, and because the second drain of the present invention for forming a boost capacitor is The size of the electrode 42 is reduced, and the probability that the copper on the surface of the second metal layer 40 in contact with the passivation layer 50 is oxidized by the silicon oxide in the passivation layer 50 can be reduced, so as to avoid process defects.
  • the present invention provides a method for fabricating an array substrate, including the following steps:
  • a base substrate 10 is provided.
  • the base substrate 10 includes a display area 11 and a GOA area 12 located on the periphery of the display area 11.
  • Step S2 please refer to FIG. 1 and FIG. 3, forming a first metal thin film on the base substrate 10 and forming a first metal layer 20 through a first photomask process.
  • the first metal layer 20 includes: The first gate 21 in the GOA region 12.
  • the first metal layer 20 further includes a second gate electrode 22 formed in the display region 11 and a second gate electrode 22 formed in the display region 11.
  • the gate line 23 is electrically connected to the gate electrode 22.
  • the first gate 21, the second gate 22, and the gate line 23 are all formed at the same time through a first mask process.
  • a material of the first metal layer 20 is a combination of one or more of molybdenum, aluminum, copper, and titanium.
  • Step S3 Referring to FIG. 1, a first insulating layer 30 is covered on the first metal layer 20 and the base substrate 10.
  • the first insulating layer 30 is formed by a deposition process, and the material is one or a combination of silicon oxide and silicon nitride.
  • Step S4 forming a second metal thin film on the first insulating layer 30 and forming a second metal layer 40 through a second photomask process;
  • the second metal layer 40 includes: formed at intervals in the GOA region 12 A first source electrode 41 and a first drain electrode 42, the first gate electrode 21 and the first drain electrode 42 at least partially overlap.
  • the second metal layer 40 includes second source electrodes 43 and second drain electrodes 44 formed at intervals in the display area 11 and electrically connected to the second source electrode 43. Sexually connected source line 45.
  • the step S4 further includes: forming a semiconductor layer 80 between the first insulating layer 30 and the second metal layer 40.
  • the semiconductor layer 80 includes a first semiconductor island 81 on the first insulation layer 30 above the first gate 21 and a second semiconductor island on the first insulation layer 30 above the second gate 22 82; the first source electrode 41 and the first drain electrode 42 are in contact with both ends of the first semiconductor island 81, and the second source electrode 43 and the second drain electrode 44 are respectively in contact with the second semiconductor island The two ends of 82 are in contact.
  • the semiconductor layer 80 and the second metal layer 40 may be formed simultaneously using the same photomask or separately formed using different photomasks.
  • the step S4 includes: forming a semiconductor thin film on the first insulating layer 30 and patterning the same through a photomask.
  • a semiconductor layer 80 is obtained from the semiconductor thin film, a metal thin film is formed on the semiconductor layer 80 and the first insulating layer 30, and then the metal thin film is patterned through another photomask to form a second metal layer 40 .
  • the mask is preferably a half-tone mask or a grayscale mask.
  • the step S4 specifically includes: forming a semiconductor thin film on the first insulating layer 30, forming a metal thin film on the semiconductor thin film, and covering the metal thin film with a photoresist; Two photomasks are used to pattern the photoresist, removing and removing the photoresist corresponding to the first source 41, the first drain 42, the second source 43, the second drain 44, the source line 45, and the first semiconductor island.
  • the photoresistance in the channel region of 81 and the region other than the channel region of the second semiconductor island 82 is reserved for the first source 41, the first drain 42, the second source 43, the second drain 44, and
  • the photoresistance in the region of the source line 45, the channel region of the first semiconductor island 81, and the channel region of the second semiconductor island 82 makes the channel region corresponding to the first semiconductor island 81 and the second semiconductor island 82
  • the thickness of the photoresist in the channel region is smaller than the thickness of the photoresist in other regions. Then, a metal film and a semiconductor film that are not blocked by the photoresist are removed by a wet etching process and a dry etching process, respectively.
  • Channel region of a semiconductor island 81 and a second semiconductor island 82 Forming a photoresist on the channel region of the semiconductor device and thinning the photoresist on other regions, and then forming a metal film on the channel region corresponding to the first semiconductor island 81 and the channel region of the second semiconductor island 82 through a wet etching process.
  • the source electrode 43 and the drain electrode 45 are then etched through a dry etching process to form a channel in the channel region of the first semiconductor island 81 and the channel region of the second semiconductor island 82 to form a channel of the first semiconductor island 81.
  • the channel region of the second semiconductor island 82 and finally removing all remaining photoresist layers to form a second metal layer 40 and a semiconductor layer 80.
  • Step S5 Cover the passivation layer 50 on the second metal layer 40 and the first insulating layer 30, and form a first via hole 71 through a third mask process, and the first via hole 61 penetrates the passivation layer 50 and the first insulating layer 30 and expose a part of the first gate 21.
  • a second via hole 72 is further formed in the step S5, and the second via hole 72 penetrates the passivation layer 50 and exposes a part of the second drain electrode 44.
  • the material of the passivation layer 50 is one or a combination of silicon oxide and silicon nitride.
  • Step S6 A third metal thin film is formed on the passivation layer 50 and a third metal layer 60 is formed by a fourth photomask process.
  • the third metal layer 60 includes an auxiliary electrode 61 formed in the GOA region 12.
  • the auxiliary electrode 61 is electrically connected to the first gate electrode 21 through a first via hole 71 and the first drain electrode 42 of the auxiliary electrode 61 at least partially overlaps.
  • the third metal layer 60 further includes a pixel electrode 62 formed in the display area 11.
  • the pixel electrode 62 is electrically connected to the second drain electrode 44 through the second via hole 72. connection.
  • a material of the third metal layer 60 is indium tin oxide.
  • an auxiliary electrode 61 is formed on the GOA region 12 by using the third metal layer 60 where the pixel electrode 62 is located, and the auxiliary electrode 61 and the auxiliary electrode 61 are connected through the first via hole 71.
  • the first gate electrode 21 is electrically connected together, so that the auxiliary electrode 61, the first gate electrode 21, and the first drain electrode 42 together form a sandwich capacitor as a step-up capacitor of the GOA circuit.
  • the sandwich capacitor is under the same capacitance. With a smaller area, it can reduce the occupied area of the GOA circuit, reduce the frame size of the display panel, and realize narrow or borderless display.
  • the material of the second metal layer 40 of the array substrate of the present invention is preferably copper, in order to improve the conductivity of the second metal layer 40, and because the second drain of the present invention for forming a boost capacitor is The size of the electrode 42 is reduced, and the probability that the copper on the surface of the second metal layer 40 in contact with the passivation layer 50 is oxidized by the silicon oxide in the passivation layer 50 can be reduced, so as to avoid process defects.
  • the present invention provides an array substrate.
  • the array substrate includes a base substrate, a first metal layer provided on the base substrate, and a first metal layer provided on the first metal layer and the base substrate.
  • the base substrate includes a display area and a GOA area located at the periphery of the display area; in the GOA area, the first metal layer includes a first gate, and the second metal layer includes a first A source electrode and a first drain electrode, the third metal layer includes an auxiliary electrode, the first gate electrode at least partially overlaps the first drain electrode, and the auxiliary electrode at least partially overlaps the first drain electrode ,
  • the auxiliary electrode is electrically connected to the first gate through a first via hole penetrating the passivation layer and the first insulating layer, and is formed together by the first gate, the first drain,

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Abstract

一种阵列基板及其制作方法，阵列基板包括：衬底基板（10）、设于衬底基板（10）上的第一金属层（20）、设于第一金属层（20）及衬底基板（10）的第一绝缘层（30）、设于第一绝缘层（30）上的第二金属层（40）、覆盖第一绝缘层（30）及第二金属层（40）的钝化层（50）以及设于钝化层（50）上的第三金属层（60）；衬底基板（10）包括显示区（11）以及位于显示区（11）外围的GOA区（12）；在GOA区（12）内，第一金属层（20）包括第一栅极（21），第二金属层（40）包括间隔设置的第一源极（41）和第一漏极（42），第三金属层（60）包括辅助电极（61），第一栅极（21）与第一漏极（42）至少部分重叠，辅助电极（61）与第一漏极（42）至少部分重叠，辅助电极（61）通过贯穿钝化层（50）和第一绝缘层（30）的第一过孔（71）与第一栅极（21）电性连接，通过第一栅极（21）、第一漏极（42）及辅助电极（61）共同形成一电容作为GOA电路的升压电容，能够减少GOA电路的升压电容的面积。

Description

阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法。
 背景技术
液晶显示器（Liquid Crystal Display，LCD）具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理（PDA）、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管（TFT），薄膜晶体管的栅极（Gate）连接至水平扫描线，漏极（Drain）连接至垂直方向的数据线，源极（Source）则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板（Integrated Circuit，IC）来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA技术（Gate Driver on Array）即集成在阵列基板上的行扫描驱动技术，可以运用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接IC的焊接（bonding）工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
常见的GOA电路包括上拉电路、上拉控制电路、下传电路、下拉电路、下拉保持电路、以及上升电路，其中上拉电路主要负责根据输入的时钟信号产生扫描信号输出至各个子像素的驱动薄膜晶体管的栅极，进行逐行扫描。上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的信号作用，下拉电路负责在输出扫描信号后，快速地将扫描信号拉低为低电平。下拉保持电路负责在非工作阶段将扫描信号和上拉电路的开关节点的信号保持在关闭状态。上升电路则负载在工作阶段对上拉电路的开关节点电位的进行二次抬升，确保扫描信号的正常输出。
 技术问题
一般在GOA电路的上升电路包括一升压电容（Boosting cap），用于进行上拉电路的开关节点电位的进行二次抬升，GOA技术应用于液晶显示器最主要的目的是为了窄边框或无边框的显示产品，但现有的GOA电路中升压电容（Boosting cap）是由栅极金属和漏极金属以及栅极金属和漏极金属之间的绝缘层形成，这种结构的升压电容需要的面积较大，不利于窄边框或无边框的实现。
 技术解决方案
本发明的目的在于提供一种阵列基板，能够减少GOA电路的升压电容的面积，实现窄边框或无边框显示。
本发明的目的还在于提供一种阵列基板的制作方法，能够减少GOA电路的升压电容的面积，实现窄边框或无边框显示。
为实现上述目的，本发明提供了一种阵列基板，包括：衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板的第一绝缘层、设于所述第一绝缘层上的第二金属层、覆盖所述第一绝缘层及第二金属层的钝化层以及设于所述钝化层上的第三金属层；
所述衬底基板包括显示区以及位于所述显示区外围的GOA区；
在所述GOA区内，所述第一金属层包括第一栅极，所述第二金属层包括间隔设置的第一源极和第一漏极，所述第三金属层包括辅助电极，所述第一栅极与所述第一漏极至少部分重叠，所述辅助电极与所述第一漏极至少部分重叠，所述辅助电极通过贯穿所述钝化层和第一绝缘层的第一过孔与所述第一栅极电性连接。
在所述显示区内，所述第一金属层包括：第二栅极及与所述第二栅极电性连接的栅极线；所述第二金属层包括间隔设置的第二源极和第二漏极及与所述第二源极电性连接的源极线；所述第三金属层包括像素电极，所述像素电极通过所述贯穿所述钝化层的第二过孔与第二漏极电性连接。
所述阵列基板还包括：位于所述第一绝缘层与所述第二金属层之间的半导体层。
所述半导体层包括位于所述第一栅极上方的第一绝缘层上的第一半导体岛以及位于所述第二栅极上方的第一绝缘层上的第二半导体岛；
所述第一源极和第一漏极分别与所述第一半导体岛的两端接触，所述第二源极和第二漏极分别与所述第二半导体岛的两端接触。
所述第一金属层和第二金属层的材料均为钼、铝、铜及钛中的一种或多种的组合；所述第一绝缘层及钝化层的材料均为氧化硅及氮化硅中的一种或二者的组合；所述第三金属层的材料为氧化铟锡。
本发明还提供一种阵列基板的制作方法，包括如下步骤：
步骤S1、提供一衬底基板，所述衬底基板包括显示区以及位于所述显示区外围的GOA区；
步骤S2、在所述衬底基板上形成第一金属薄膜并通过第一道光罩制程形成第一金属层，所述第一金属层包括：形成于所述GOA区的第一栅极；
步骤S3、在所述第一金属层和衬底基板上覆盖第一绝缘层；
步骤S4、在所述第一绝缘层上形成第二金属薄膜并通过第二道光罩制程形成第二金属层；所述第二金属层包括：形成于所述GOA区内间隔设置的第一源极和第一漏极，所述第一栅极与所述第一漏极至少部分重叠；
步骤S5、在所述第二金属层和第一绝缘层上覆盖钝化层，通过第三道光罩制程形成第一过孔，所述第一过孔贯穿所述钝化层和第一绝缘层并暴露出所述第一栅极的一部分；
步骤S6、在所述钝化层上形成第三金属薄膜并通过第四道光罩制程形成第三金属层，所述第三金属层包括形成于所述GOA区内的辅助电极，所述辅助电极通过第一过孔与所述第一栅极电性连接且所述辅助电极所述第一漏极至少部分重叠。
所述步骤S2中，所述第一金属层还包括：形成于所述显示区内的第二栅极及与所述第二栅极电性连接的栅极线；
所述步骤S4中，所述第二金属层还包括形成于所述显示区内的间隔设置的第二源极和第二漏极及与所述第二源极电性连接的源极线；
所述步骤S5中还形成第二过孔，所述第二过孔贯穿所述钝化层并暴露出所述第二漏极的一部分；
所述步骤S6中，所述第三金属层还包括形成于所述显示区内的像素电极，所述像素电极通过第二过孔与第二漏极电性连接。
所述步骤S4还包括在所述第一绝缘层与所述第二金属层之间形成半导体层。
所述半导体层包括位于所述第一栅极上方的第一绝缘层上的第一半导体岛以及位于所述第二栅极上方的第一绝缘层上的第二半导体岛；
所述第一源极和第一漏极分别与所述第一半导体岛的两端接触，所述第二源极和第二漏极分别与所述第二半导体岛的两端接触。
所述第一金属层和第二金属层的材料均为钼、铝、铜及钛中的一种或多种的组合；所述第一绝缘层及钝化层的材料均为氧化硅及氮化硅中的一种或二者的组合；所述第三金属层的材料为氧化铟锡。
本发明还提供了一种阵列基板，包括：衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板的第一绝缘层、设于所述第一绝缘层上的第二金属层、覆盖所述第一绝缘层及第二金属层的钝化层以及设于所述钝化层上的第三金属层，其中，所述第二金属层的材料为铜；
所述衬底基板包括显示区以及位于所述显示区外围的GOA区；
在所述GOA区内，所述第一金属层包括第一栅极，所述第二金属层包括间隔设置的第一源极和第一漏极，所述第三金属层包括辅助电极，所述第一栅极与所述第一漏极至少部分重叠，所述辅助电极与所述第一漏极至少部分重叠，所述辅助电极通过贯穿所述钝化层和第一绝缘层的第一过孔与所述第一栅极电性连接。
在所述显示区内，所述第一金属层包括：第二栅极及与所述第二栅极电性连接的栅极线；所述第二金属层包括间隔设置的第二源极和第二漏极及与所述第二源极电性连接的源极线；所述第三金属层包括像素电极，所述像素电极通过所述贯穿所述钝化层的第二过孔与第二漏极电性连接。
所述阵列基板还包括：位于所述第一绝缘层与所述第二金属层之间的半导体层。
所述半导体层包括位于所述第一栅极上方的第一绝缘层上的第一半导体岛以及位于所述第二栅极上方的第一绝缘层上的第二半导体岛；
所述第一源极和第一漏极分别与所述第一半导体岛的两端接触，所述第二源极和第二漏极分别与所述第二半导体岛的两端接触。
所述第一金属层材料为钼、铝、铜及钛中的一种或多种的组合；所述第一绝缘层及钝化层的材料均为氧化硅及氮化硅中的一种或二者的组合；所述第三金属层的材料为氧化铟锡。
 有益效果
本发明的有益效果：本发明提供一种阵列基板，所述阵列基板包括：衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板的第一绝缘层、设于所述第一绝缘层上的第二金属层、覆盖所述第一绝缘层及第二金属层的钝化层以及设于所述钝化层上的第三金属层；所述衬底基板包括显示区以及位于所述显示区外围的GOA区；在所述GOA区内，所述第一金属层包括第一栅极，所述第二金属层包括间隔设置的第一源极和第一漏极，所述第三金属层包括辅助电极，所述第一栅极与所述第一漏极至少部分重叠，所述辅助电极与所述第一漏极至少部分重叠，所述辅助电极通过贯穿所述钝化层和第一绝缘层的第一过孔与所述第一栅极电性连接，通过所述第一栅极、第一漏极及辅助电极共同形成一夹层电容来作为GOA电路的升压电容，能够减少GOA电路的升压电容的面积，实现窄边框或无边框显示。本发明还提供一种阵列基板的制作方法，能够减少GOA电路的升压电容的面积，实现窄边框或无边框显示。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的阵列基板中的示意图；
图2为本发明的阵列基板中衬底基板的示意图；
图3为本发明的阵列基板中GOA区的剖面示意图；
图4为本发明的阵列基板中显示区的剖面示意图；
图5为本发明的阵列基板中显示区的俯视示意图；
图6为本发明的阵列基板的制作方法的流程图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1至图4，本发明提供一种阵列基板，包括：衬底基板10、设于所述衬底基板10上的第一金属层20、设于所述第一金属层20及衬底基板10的第一绝缘层30、设于所述第一绝缘层30上的第二金属层40、覆盖所述第一绝缘层30及第二金属层40的钝化层50以及设于所述钝化层50上的第三金属层60。
具体地，如图2所示，所述衬底基板10包括显示区11以及位于所述显示区11外围的GOA区12，所述显示区11用于形成显示面板的各个像素，所述GOA区12用于形成驱动显示面板的各个像素工作的GOA电路。
具体地，如图3所示，在所述GOA区12内，所述第一金属层20包括第一栅极21，所述第二金属层40包括间隔设置的第一源极41和第一漏极42，所述第三金属层60包括辅助电极61，所述第一栅极21与所述第一漏极42至少部分重叠，所述辅助电极61与所述第一漏极42至少部分重叠，所述辅助电极61通过贯穿所述钝化层50和第一绝缘层30的第一过孔71与所述第一栅极21电性连接。
进一步地，如图4所示及图5所示，在所述显示区11内，所述第一金属层20包括：第二栅极22及与所述第二栅极22电性连接的栅极线23；所述第二金属层40包括间隔设置的第二源极43和第二漏极44及与所述第二源极43电性连接的源极线45；所述第三金属层60包括像素电极62，所述像素电极62通过所述贯穿所述钝化层50的第二过孔72与第二漏极44电性连接。
当然，完整的阵列基板，还应当包括位于所述第一绝缘层30与所述第二金属层40之间的半导体层80。其中，所述半导体层80包括位于所述第一栅极21上方的第一绝缘层30上的第一半导体岛81以及位于所述第二栅极22上方的第一绝缘层30上的第二半导体岛82；所述第一源极41和第一漏极42分别与所述第一半导体岛81的两端接触，所述第二源极43和第二漏极44分别与所述第二半导体岛82的两端接触。
优选地，所述第一金属层20和第二金属层40的材料均为钼、铝、铜及钛中的一种或多种的组合；所述第一绝缘层30及钝化层50的材料均为氧化硅及氮化硅中的一种或二者的组合；所述第三金属层60的材料为氧化铟锡。所述半导体层80的材料可以为非晶硅、多晶硅或氧化物半导体。
需要说明的是，本发明的阵列基板中，利用像素电极62所在的第三金属层60在GOA区12上形成一个辅助电极61，并通过第一过孔71将所述辅助电极61与所述第一栅极21电性连接到一起，使得所述辅助电极61、第一栅极21及第一漏极42共同组成一个夹层电容作为GOA电路的升压电容，该夹层电容在相同的电容下具有更小的面积，能够减少GOA电路的占用面积，缩小显示面板的边框大小，实现窄边框或无边框显示。
值得一提是，本发明的阵列基板的第二金属层40的材料优选为铜，以提升所述第二金属层40的导电性能，同时由于本发明的用于形成升压电容的第二漏极42的尺寸得以减小，能够减小第二金属层40与钝化层50接触的表面的铜被钝化层50中的氧化硅氧化的机率，避免制程不良。
请参阅图1至图6，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤S1、请参阅图2，提供一衬底基板10，所述衬底基板10包括显示区11以及位于所述显示区11外围的GOA区12。
步骤S2、请参阅图1及图3，在所述衬底基板10上形成第一金属薄膜并通过第一道光罩制程形成第一金属层20，所述第一金属层20包括：形成于所述GOA区12内的第一栅极21。
具体地，请参阅图1、图4及图5，所述步骤S2中，所述第一金属层20还包括：形成于所述显示区11内的第二栅极22及与所述第二栅极22电性连接的栅极线23。
所述第一栅极21、第二栅极22及栅极线23均通过第一道光罩制程同时形成。优选地，所述第一金属层20的材料为钼、铝、铜及钛中的一种或多种的组合。
步骤S3、请参阅图1，在所述第一金属层20和衬底基板10上覆盖第一绝缘层30。
具体地，所述第一绝缘层30通过沉积工艺形成，材料为氧化硅及氮化硅中的一种或二者的组合。
步骤S4、在所述第一绝缘层30上形成第二金属薄膜并通过第二道光罩制程形成第二金属层40；所述第二金属层40包括：形成于所述GOA区12内间隔设置的第一源极41和第一漏极42，所述第一栅极21与所述第一漏极42至少部分重叠。
具体地，所述步骤S4中，所述第二金属层40包括形成于所述显示区11内的间隔设置的第二源极43和第二漏极44及与所述第二源极43电性连接的源极线45。
进一步地，所述步骤S4还包括：在所述第一绝缘层30与所述第二金属层40之间形成半导体层80。所述半导体层80包括位于所述第一栅极21上方的第一绝缘层30上的第一半导体岛81以及位于所述第二栅极22上方的第一绝缘层30上的第二半导体岛82；所述第一源极41和第一漏极42分别与所述第一半导体岛81的两端接触，所述第二源极43和第二漏极44分别与所述第二半导体岛82的两端接触。
可选地，所述半导体层80与所述第二金属层40可采用同一道光罩同时形成或采用不同的光罩的分别形成。
其中，所述半导体层80与所述第二金属层40采用不同光罩分别形成时，所述步骤S4包括：在所述第一绝缘层30形成一层半导体薄膜，并通过一道光罩图案化所述半导体薄膜，得到半导体层80，接着在所述半导体层80及第一绝缘层30上形成一层金属薄膜，接着再通过另一道光罩图案化所述金属薄膜，形成第二金属层40。
而当所述半导体层80与所述第二金属层40采用同一道光罩同时形成时，所述光罩优选为半色调光罩或灰阶光罩。所述步骤S4具体包括：在所述第一绝缘层30形成一层半导体薄膜，在所述半导体薄膜上形成一层金属薄膜，在所述金属薄膜上覆盖一层光阻；随后通过所述第二道光罩对所述光阻进行图案化，去除除开对应待形成第一源极41、第一漏极42、第二源极43、第二漏极44、源极线45、第一半导体岛81的沟道区及第二半导体岛82的沟道区以外的区域的光阻，保留对应待形成第一源极41、第一漏极42、第二源极43、第二漏极44、源极线45、第一半导体岛81的沟道区及第二半导体岛82的沟道区的区域上的光阻，并使得对应第一半导体岛81的沟道区及第二半导体岛82的沟道区上的光阻的厚度小于其他区域的光阻厚度，接着通过一道湿蚀刻制程和一道干蚀刻制程分别去除未被光阻遮挡的金属薄膜和半导体薄膜，然后通过灰化制程去除对应第一半导体岛81的沟道区及第二半导体岛82的沟道区上的光阻，同时减薄其他区域的光阻，接着通过一道湿蚀刻制程去除对应第一半导体岛81的沟道区及第二半导体岛82的沟道区上的金属薄膜形成源极43和漏极45，接着通过一道干蚀刻制程对待形成第一半导体岛81的沟道区及第二半导体岛82的沟道区中半导体层进行蚀刻，形成第一半导体岛81的沟道区及第二半导体岛82的沟道区，最后去除剩余的全部光阻层，形成第二金属层40和半导体层80。
步骤S5、在所述第二金属层40和第一绝缘层30上覆盖钝化层50，通过第三道光罩制程形成第一过孔71，所述第一过孔61贯穿所述钝化层50和第一绝缘层30并暴露出所述第一栅极21的一部分。
具体地，所述步骤S5中还形成第二过孔72，所述第二过孔72贯穿所述钝化层50并暴露出所述第二漏极44的一部分。优选地，所述钝化层50的材料为氧化硅及氮化硅中的一种或二者的组合。
步骤S6、在所述钝化层50上形成第三金属薄膜并通过第四道光罩制程形成第三金属层60，所述第三金属层60包括形成于所述GOA区12内的辅助电极61，所述辅助电极61通过第一过孔71与所述第一栅极21电性连接且所述辅助电极61所述第一漏极42至少部分重叠。
具体地，所述步骤S6中，所述第三金属层60还包括形成于所述显示区11内的像素电极62，所述像素电极62通过第二过孔72与第二漏极44电性连接。优选地，所述第三金属层60的材料为氧化铟锡。
需要说明的是，本发明的阵列基板中，利用像素电极62所在的第三金属层60在GOA区12上形成一个辅助电极61，并通过第一过孔71将所述辅助电极61与所述第一栅极21电性连接到一起，使得所述辅助电极61、第一栅极21及第一漏极42共同组成一个夹层电容作为GOA电路的升压电容，该夹层电容在相同的电容下具有更小的面积，能够减少GOA电路的占用面积，缩小显示面板的边框大小，实现窄边框或无边框显示。
值得一提是，本发明的阵列基板的第二金属层40的材料优选为铜，以提升所述第二金属层40的导电性能，同时由于本发明的用于形成升压电容的第二漏极42的尺寸得以减小，能够减小第二金属层40与钝化层50接触的表面的铜被钝化层50中的氧化硅氧化的机率，避免制程不良。
综上所述，本发明提供一种阵列基板，所述阵列基板包括：衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层及衬底基板的第一绝缘层、设于所述第一绝缘层上的第二金属层、覆盖所述第一绝缘层及第二金属层的钝化层以及设于所述钝化层上的第三金属层；所述衬底基板包括显示区以及位于所述显示区外围的GOA区；在所述GOA区内，所述第一金属层包括第一栅极，所述第二金属层包括间隔设置的第一源极和第一漏极，所述第三金属层包括辅助电极，所述第一栅极与所述第一漏极至少部分重叠，所述辅助电极与所述第一漏极至少部分重叠，所述辅助电极通过贯穿所述钝化层和第一绝缘层的第一过孔与所述第一栅极电性连接，通过所述第一栅极、第一漏极及辅助电极共同形成一夹层电容来作为GOA电路的升压电容，能够减少GOA电路的升压电容的面积，实现窄边框或无边框显示。本发明还提供一种阵列基板的制作方法，能够减少GOA电路的升压电容的面积，实现窄边框或无边框显示。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (15)

  1. 一种阵列基板，其包含：衬底基板（10）、设于所述衬底衬底基板（10）上的第一金属层（20）、设于所述第一金属层（20）及衬底基板（10）上的第一绝缘层（30）、设于所述第一绝缘层（30）上的第二金属层（40）、覆盖所述第一绝缘层（30）及第二金属层（40）上的钝化层（50）以及设于所述钝化层（50）上的第三金属层（60）；
    所述衬底基板（10）包括显示区（11）以及位于所述显示区（11）外围的GOA区（12）；
    在所述GOA区（12）内，所述第一金属层（20）包括第一栅极（21），所述第二金属层（40）包括间隔设置的第一源极（41）和第一漏极（42），所述第三金属层（60）包括辅助电极（61），所述第一栅极（21）与所述第一漏极（42）至少部分重叠，所述辅助电极（61）与所述第一漏极（42）至少部分重叠，所述辅助电极（61）通过贯穿所述钝化层（50）和第一绝缘层（30）的第一过孔（71）与所述第一栅极（21）电性连接。
  2. 如权利要求1所述的阵列基板，其中在所述显示区（11）内，所述第一金属层（20）还包括：第二栅极（22）及与所述第二栅极（22）电性连接的栅极线（23）；所述第二金属层（40）还包括间隔设置的第二源极（43）和第二漏极（44）及与所述第二源极（43）电性连接的源极线（45）；所述第三金属层（60）还包括像素电极（62），所述像素电极（62）通过所述贯穿所述钝化层（50）的第二过孔（72）与第二漏极（44）电性连接。
  3. 如权利要求2所述的阵列基板，其中所述阵列基板还包括：位于所述第一绝缘层（30）与所述第二金属层（40）之间的半导体层（80）。
  4. 如权利要求3所述的阵列基板，其中所述半导体层（80）包括位于所述第一栅极（21）上方的第一绝缘层（30）上的第一半导体岛（81）以及位于所述第二栅极（22）上方的第一绝缘层（30）上的第二半导体岛（82）；
    所述第一源极（41）和第一漏极（42）分别与所述第一半导体岛（81）的两端接触，所述第二源极（43）和第二漏极（44）分别与所述第二半导体岛（82）的两端接触。
  5. 如权利要求1所述的阵列基板，其中所述第一金属层（20）和第二金属层（40）的材料均为钼、铝、铜及钛中的一种或多种的组合；所述第一绝缘层（30）及钝化层（50）的材料均为氧化硅及氮化硅中的一种或二者的组合；所述第三金属层（60）的材料为氧化铟锡。
  6. 一种阵列基板的制作方法，其包含如下步骤：
    步骤S1、提供一衬底基板（10），所述衬底基板（10）包括显示区（11）以及位于所述显示区（11）外围的GOA区（12）；
    步骤S2、在所述衬底基板（10）上形成第一金属薄膜并通过第一道光罩制程形成第一金属层（20），所述第一金属层（20）包括：形成于所述GOA区（12）内的第一栅极（21）；
    步骤S3、在所述第一金属层（20）和衬底基板（10）上覆盖第一绝缘层（30）；
    步骤S4、在所述第一绝缘层（30）上形成第二金属薄膜并通过第二道光罩制程形成第二金属层（40）；所述第二金属层（40）包括：形成于所述GOA区（12）内间隔设置的第一源极（41）和第一漏极（42），所述第一栅极（21）与所述第一漏极（42）至少部分重叠；
    步骤S5、在所述第二金属层（40）和第一绝缘层（30）上覆盖钝化层（50），通过第三道光罩制程形成第一过孔（71），所述第一过孔（61）贯穿所述钝化层（50）和第一绝缘层（30）并暴露出所述第一栅极（21）的一部分；
    步骤S6、在所述钝化层（50）上形成第三金属薄膜并通过第四道光罩制程形成第三金属层（60），所述第三金属层（60）包括形成于所述GOA区（12）内的辅助电极（61），所述辅助电极（61）通过第一过孔（71）与所述第一栅极（21）电性连接且所述辅助电极（61）所述第一漏极（42）至少部分重叠。
  7. 如权利要求6所述的阵列基板的制作方法，其中所述步骤S2中，所述第一金属层（20）还包括：形成于所述显示区（11）内的第二栅极（22）及与所述第二栅极（22）电性连接的栅极线（23）；
    所述步骤S4中，所述第二金属层（40）还包括形成于所述显示区（11）内的间隔设置的第二源极（43）和第二漏极（44）及与所述第二源极（43）电性连接的源极线（45）；
    所述步骤S5中还形成第二过孔（72），所述第二过孔（72）贯穿所述钝化层（50）并暴露出所述第二漏极（44）的一部分；
    所述步骤S6中，所述第三金属层（60）还包括形成于所述显示区（11）内的像素电极（62），所述像素电极（62）通过第二过孔（72）与第二漏极（43）电性连接。
  8. 如权利要求7所述的阵列基板的制作方法，其中所述步骤S4还包括在所述第一绝缘层（30）与所述第二金属层（40）之间形成半导体层（80）。
  9. 如权利要求8所述的阵列基板的制作方法，其中所述半导体层（80）包括位于所述第一栅极（21）上方的第一绝缘层（30）上的第一半导体岛（81）以及位于所述第二栅极（22）上方的第一绝缘层（30）上的第二半导体岛（82）；
    所述第一源极（41）和第一漏极（42）分别与所述第一半导体岛（81）的两端接触，所述第二源极（43）和第二漏极（44）分别与所述第二半导体岛（82）的两端接触。
  10.    如权利要求6所述的阵列基板的制作方法，其中所述第一金属层（20）和第二金属层（40）的材料均为钼、铝、铜及钛中的一种或多种的组合；所述第一绝缘层（30）及钝化层（50）的材料均为氧化硅及氮化硅中的一种或二者的组合；所述第三金属层（60）的材料为氧化铟锡。
  11.    一种阵列基板，其包含：衬底基板（10）、设于所述衬底衬底基板（10）上的第一金属层（20）、设于所述第一金属层（20）及衬底基板（10）上的第一绝缘层（30）、设于所述第一绝缘层（30）上的第二金属层（40）、覆盖所述第一绝缘层（30）及第二金属层（40）上的钝化层（50）以及设于所述钝化层（50）上的第三金属层（60），其中所述第二金属层（40）的材料均为铜；
    所述衬底基板（10）包括显示区（11）以及位于所述显示区（11）外围的GOA区（12）；
    在所述GOA区（12）内，所述第一金属层（20）包括第一栅极（21），所述第二金属层（40）包括间隔设置的第一源极（41）和第一漏极（42），所述第三金属层（60）包括辅助电极（61），所述第一栅极（21）与所述第一漏极（42）至少部分重叠，所述辅助电极（61）与所述第一漏极（42）至少部分重叠，所述辅助电极（61）通过贯穿所述钝化层（50）和第一绝缘层（30）的第一过孔（71）与所述第一栅极（21）电性连接。
  12.    如权利要求11所述的阵列基板，其中在所述显示区（11）内，所述第一金属层（20）还包括：第二栅极（22）及与所述第二栅极（22）电性连接的栅极线（23）；所述第二金属层（40）还包括间隔设置的第二源极（43）和第二漏极（44）及与所述第二源极（43）电性连接的源极线（45）；所述第三金属层（60）还包括像素电极（62），所述像素电极（62）通过所述贯穿所述钝化层（50）的第二过孔（72）与第二漏极（44）电性连接。
  13.    如权利要求12所述的阵列基板，其中所述阵列基板还包括：位于所述第一绝缘层（30）与所述第二金属层（40）之间的半导体层（80）。
  14.    如权利要求13所述的阵列基板，其中所述半导体层（80）包括位于所述第一栅极（21）上方的第一绝缘层（30）上的第一半导体岛（81）以及位于所述第二栅极（22）上方的第一绝缘层（30）上的第二半导体岛（82）；
    所述第一源极（41）和第一漏极（42）分别与所述第一半导体岛（81）的两端接触，所述第二源极（43）和第二漏极（44）分别与所述第二半导体岛（82）的两端接触。
  15.    如权利要求11所述的阵列基板，其中所述第一金属层（20）的材料为钼、铝、铜及钛中的一种或多种的组合；所述第一绝缘层（30）及钝化层（50）的材料均为氧化硅及氮化硅中的一种或二者的组合；所述第三金属层（60）的材料为氧化铟锡。
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CN109459894A (zh) * 2018-12-24 2019-03-12 深圳市华星光电半导体显示技术有限公司 像素电极结构及其制作方法
CN110729308A (zh) * 2019-09-27 2020-01-24 深圳市华星光电技术有限公司 显示面板及显示装置
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080022245A (ko) * 2006-09-06 2008-03-11 삼성전자주식회사 게이트 구동회로 및 이를 갖는 표시 장치
CN103943634A (zh) * 2014-03-17 2014-07-23 京东方科技集团股份有限公司 阵列基板、显示装置及其电容结构
CN204314578U (zh) * 2014-12-23 2015-05-06 京东方科技集团股份有限公司 一种显示基板和显示装置
US20170343865A1 (en) * 2016-05-24 2017-11-30 Samsung Display Co., Ltd. Display substrate having gate driving circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080022245A (ko) * 2006-09-06 2008-03-11 삼성전자주식회사 게이트 구동회로 및 이를 갖는 표시 장치
CN103943634A (zh) * 2014-03-17 2014-07-23 京东方科技集团股份有限公司 阵列基板、显示装置及其电容结构
CN204314578U (zh) * 2014-12-23 2015-05-06 京东方科技集团股份有限公司 一种显示基板和显示装置
US20170343865A1 (en) * 2016-05-24 2017-11-30 Samsung Display Co., Ltd. Display substrate having gate driving circuit

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