CN103777423A - 液晶面板及其像素结构 - Google Patents

液晶面板及其像素结构 Download PDF

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CN103777423A
CN103777423A CN201410036809.XA CN201410036809A CN103777423A CN 103777423 A CN103777423 A CN 103777423A CN 201410036809 A CN201410036809 A CN 201410036809A CN 103777423 A CN103777423 A CN 103777423A
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control switch
pixel
pixel cell
discharge control
electrode
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CN103777423B (zh
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黄世帅
张天豪
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2015/071297 priority patent/WO2015110030A1/zh
Priority to US14/782,187 priority patent/US9620074B2/en
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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Abstract

本发明实施例公开了一种像素结构，其包括矩阵排列的多个像素单元。所述像素单元由相交的多条扫描线及数据线所定义。每一像素单元包括第一放电控制开关、第二放电控制开关以及相邻设置的主像素区及副像素区。所述主像素区包括主像素电极及主充电控制开关。所述副像素区包括副像素电极及副充电控制开关。所述主像素电极通过该主充电控制开关接收显示信号。所述副像素电极通过该副充电控制开关接收显示信号。所述第一放电控制开关连接传输本像素单元扫描信号的扫描线与位于上方像素单元的副像素电极。所述第二放电控制开关连接传输上一个像素单元扫描信号的扫描线与本像素单元的副像素电极。本发明实施例还公开了一种包括上述像素结构的液晶显示面板。

Description

液晶面板及其像素结构
技术领域
本发明涉及一种液晶面板及其像素结构。
背景技术
现有液晶显示面板的低色偏像素结构主要是通过增加扫描线，分别对同一像素的不同区域进行控制。然此种方法需要多一倍的覆晶薄膜(Chip On Film,COF)数量，导致成本增加。
因此，需要提供能够改善上述问题的液晶面板及其像素结构。
发明内容
为了解决上述技术问题，本发明实施例提供了一种像素结构，其包括矩阵排列的多个像素单元。所述像素单元由相交的多条扫描线及数据线所定义。每一像素单元包括第一放电控制开关、第二放电控制开关以及相邻设置的主像素区及副像素区。所述主像素区包括主像素电极及主充电控制开关。所述副像素区包括副像素电极及副充电控制开关。所述主像素电极通过该主充电控制开关接收显示信号。所述副像素电极通过该副充电控制开关接收显示信号。所述第一放电控制开关连接传输本像素单元扫描信号的扫描线与位于上方像素单元的副像素电极。所述第二放电控制开关连接传输上一个像素单元扫描信号的扫描线与本像素单元的副像素电极。
其中，所述第一放电控制开关的控制端连接至传输本像素单元扫描信号的扫描线。
其中，所述第一放电控制开关的一端连接至上两个像素单元的副像素电极。
其中，所述每一像素单元还包括一第一驱动线及一第二驱动线。所述每一像素单元的第一放电控制开关的控制端连接至所述第一驱动线。所述每一像素单元的第二放电控制开关的控制端连接所述第二驱动线。
其中，所述第一放电控制开关的一端连接至相邻的上一个像素单元的副像素电极。
其中，所述第二放电控制开关的控制端连接至传输本像素单元扫描信号的扫描线。
其中，所述主充电控制开关、副充电控制开关、第一放电控制开关及第二放电控制开关为薄膜晶体管。第一放电控制开关及第二放电控制开关的控制端为薄膜晶体管的栅极。
一种液晶显示面板，其包括上述的像素结构。
其中，进一步包括阵列基板、液晶层以及彩膜基板。所述阵列基板与彩膜基板相对设置，所述液晶层夹设在阵列基板与彩膜基板之间。
其中，所述阵列基板包括绝缘层、存储电容电极及设置在绝缘层上的多个具有所述像素结构、用于显示不同色彩的像素单元。所述存储电容电极对应设置在每个像素单元下，并由所述绝缘层所覆盖。所述彩膜基板包括一公共电极，所述公共电极设置在彩膜基板与阵列基板相对的下表面。
本发明所提供的液晶显示面板的像素结构可在不增加扫描线的前提下对副像素电极进行放电而实现低色偏的设计要求，而且所述像素结构可以兼容正向扫描和反向扫描，具有较大的应用领域。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例所提供的液晶显示面板的结构示意图。
图2是本发明第一实施例所提供的像素单元的结构示意图。
图3是本发明第二实施例所提供的像素单元的结构示意图。
图4是本发明第三实施例所提供的像素单元的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示，本发明第一实施例所提供的液晶显示面板1包括阵列基板10、液晶层20以及彩膜基板30。其中，阵列基板10与彩膜基板30相对设置，液晶层20夹设在阵列基板10和彩膜基板30之间。
所述阵列基板10包括绝缘层100、存储电容电极102及设置在绝缘层100上的多个结构相同、用于显示不同色彩的像素单元104。所述存储电容电极102对应设置在每个像素单元104下，并由所述绝缘层100所覆盖。
所述彩膜基板30包括一公共电极300。所述公共电极300设置在彩膜基板30与阵列基板10相对的下表面。
请一并参阅图1及图2，图2是本发明所提供的像素单元104的电路结构示意图。所述阵列基板10上设置有多条扫描线S1～SN以及多条数据线L1～LN。所述扫描线S1～SN横向设置以传输用于选中像素单元104的扫描信号。所述数据线L1～LN纵向设置以传输所选中像素单元104的显示信号。所述扫描线S1～SN和数据线L1～LN彼此垂直相交以定义出呈矩阵排列的像素单元104。在其他实施例中，扫描线S1～SN和数据线L1～LN也可以不垂直。
所述每一个像素单元104包括第一放电控制开关1041、第二放电控制开关1042以及相邻设置的主像素区1043和副像素区1044。所述主像素区1043与副像素区1044的下方分别对应设置有所述存储电容电极102。所述主像素区1043包括主像素电极1045及主充电控制开关1046。所述副像素区1044包括副像素电极1047及副充电控制开关1048。所述第一放电控制开关1041连接构成该像素单元104的下列扫描线Sn与位于上方的其他像素单元104中的副像素电极1047以在下列扫描线Sn的扫描信号的控制下对上方像素单元104的副像素电极1047进行放电。所述第二放电控制开关1042连接构成该像素单元104的上列扫描线Sn-1与该像素单元104的副像素电极1047以在上列扫描线Sn-1的扫描信号的控制下对该像素单元104的副像素电极1047进行放电。所述副像素电极1047在放电后与同一像素单元104内的主像素电极1045之间形成电位差，达到降低色偏的目的。在本实施例中，所述第一放电控制开关1041与相邻的上一个像素单元104中的副像素电极1047相连接。所述第二放电控制开关10421与相邻的下一个像素单元104中的副像素电极1047相连接。
所述主充电控制开关1046、副充电控制开关1048、第一放电控制开关1041及第二放电控制开关1042均优选为薄膜晶体管。所述主充电控制开关1046的栅极为控制端且连接至扫描线S1～SN上。所述主充电控制开关1046的源极连接至数据线上。所述主充电控制开关1046的漏极连接至主像素电极1045。所述副充电控制开关1048的栅极为控制端且连接至扫描线S1～SN上。所述副充电控制开关1048的源极连接至数据线L1～LN上。所述副充电控制开关1048的漏极连接至副像素电极1047。
所述第一放电控制开关1041的栅极为控制端。所述第一放电控制开关1041的栅极及源极共同连接至该像素单元104的下列扫描线Sn上。所述第一放电控制开关1041的漏极连接至上一个像素单元104的副像素电极1047。所述第二放电控制开关1042的栅极为控制端。所述第二放电控制开关1042的栅极及源极共同连接至该像素单元104的上列扫描线Sn-1上。所述第二放电控制开关1042的漏极连接至该像素单元104的副像素电极1047。
下面以图2中所示的第n像素单元104为例进行说明。
采用正向扫描方式，即扫描信号按照从第一条扫描线S1至第N条扫描线SN依次加载。当扫描信号沿第n条扫描线Sn传输时，第n像素单元104的主充电控制开关1046及副充电控制开关1048通过各自的栅极被扫描信号导通。第n像素单元104的显示信号沿第n条数据线Ln分别通过所述主充电控制开关1046及副充电控制开关1048对第n像素单元104的主像素电极1045及副像素电极1047充电。于此同时，与第n条扫描线Sn相连的第一放电控制开关1041被导通以使得第n-1像素单元104的副像素电极1047放电。因为在此之前扫描信号沿第n-1条扫描线Sn-1传输时，第n-1像素单元104内的主像素电极1045及副像素电极1047已被充电。所以，当第n-1像素单元104的副像素电极1047被第n像素单元104的第一放电控制开关1041放电后，所述第n-1像素单元104的主像素电极1045与副像素电极1047之间的电位不同，从而达到低色偏的设计要求。同理，当扫描信号沿下一列第n+1条扫描线Sn+1传输时，第n+1像素单元104的第一放电控制开关1041被导通而对第n像素单元104内的副像素电极1047进行放电，使得第n像素单元104的副像素电极1047具有与主像素电极1045不同的电位。虽然当扫描信号沿第n条扫描线传输时第n+1像素单元104的第二放电控制开关1042会被导通，但因为第n+1像素单元104的副像素电极1047在上一帧扫描周期内已被放电，所以此时不会再次放电。
采用反向扫描方式，即扫描信号按照从第N条扫描线SN至第一条扫描线S1依次加载。当扫描信号沿第n条扫描线Sn传输时，第n像素单元104的主充电控制开关1046及副充电控制开关1048通过各自的栅极被扫描信号导通。第n像素单元104的显示信号沿第n条数据线Ln分别通过所述主充电控制开关1046及副充电控制开关1048对第n像素单元104的主像素电极1045及副像素电极1047充电。于此同时，与第n条扫描线Sn相连的第n+1像素单元104的第二放电控制开关1042被导通以使得第n+1像素单元104的副像素电极1047放电。因为在此之前扫描信号沿第n+1条扫描线Sn+1传输时第n+1像素单元104内的主像素电极1045及副像素电极1047已被充电，所以当第n+1像素单元104的副像素电极1047被第n像素单元104的第二放电控制开关1042放电后，所述第n+1像素单元104的主像素电极1045与副像素电极1047之间的电位不同，从而达到低色偏的设计要求。同理，当扫描信号沿下一列第n-1条扫描线Sn-1传输时，第n像素单元104的第二放电控制开关1042被导通而对第n像素单元104内的副像素电极1047进行放电，使得第n像素单元104的副像素电极1047具有与主像素电极1045不同的电位。虽然当扫描信号沿第n条扫描线Sn传输时第n-1像素单元104的第一放电控制开关1041会被导通，但因为第n-1像素单元104的副像素在上一帧扫描周期内以被放电，所以此时不会再次放电。
因此，本发明所提供的液晶显示面板1的像素结构可在不增加扫描线的前提下对副像素电极1047进行放电而实现低色偏的设计要求，而且所述像素结构可以兼容正向扫描和反向扫描，具有较大的应用领域。
如图3所示，本发明第二实施例所提供的像素单元204的结构具有与第一实施例的像素单元104的结构基本相同的结构，其区别在于：第二实施例的像素单元204内的第一放电控制开关2041的漏极连接至上两个像素单元204的副像素电极2047。对应地，在采用正向扫描方式时，第n像素单元204的副像素电极2047在完成充电后需要在下两条扫描线Sn+2，即第n+2条扫描线Sn+2被选中时才会通过该条扫描线Sn+2上的第一放电控制开关2041进行放电，以实现与相同像素单元204内的主像素电极2045之间的电位差。
如图4所示，本发明第三实施例所提供的像素单元304的结构具有与第一实施例的像素单元104的结构基本相同的结构，其区别在于：第三实施例的像素单元304的还包括与扫描线垂直相交的第一驱动线P1及第二驱动线P2。每个像素单元304的第一放电控制开关3041的栅极均连接至该第一驱动线P1。每个像素单元304的第二放电控制开关3042的栅极均连接至该第二驱动线P2。采用正向扫描方式时，向第一驱动线P1输出驱动信号则每个像素单元304内的第一放电控制开关3041都被导通。此时当扫描信号沿第n条扫描线Sn传输时，扫描信号通过第n像素单元304内的第一放电控制开关3041传输至上一个的第n-1像素单元304的副像素电极3047以对第n-1像素单元304的副像素电极3047进行放电。在扫描信号沿下一列第n+1条扫描线Sn+1传输时，第n像素单元304的副像素电极3047通过导通的第n+1像素单元304的第一放电控制开关3041进行放电。因为在正向扫描时所述第二驱动线P2上未施加信号，所以每个像素单元304内的第二放电控制开关3042均未被导通，从而不会对与第二放电控制开关3042连接的副像素电极3047进行放电。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (10)

1.一种像素结构，其包括矩阵排列的多个像素单元(104)，所述像素单元(104)由相交的多条扫描线(S1～SN))及数据线(L1～LN)所定义，每一像素单元(104)包括第一放电控制开关(1041)、第二放电控制开关(1042)以及相邻设置的主像素区(1043)及副像素区(1044)，所述主像素区(1043)包括主像素电极(1045)及主充电控制开关(1046)，所述副像素区(1044)包括副像素电极(1047)及副充电控制开关(1048)，所述主像素电极(1045)通过该主充电控制开关(1046)接收显示信号，所述副像素电极(1047)通过该副充电控制开关(1048)接收显示信号，所述第一放电控制开关(1041)连接传输本像素单元(104)扫描信号的扫描线(sn)与位于上方像素单元(104)的副像素电极(1047)，所述第二放电控制开关(1042)连接传输上一个像素单元(104)扫描信号的扫描线(Sn-1)与本像素单元(104)的副像素电极(1047)。
2.如权利要求1所述的像素结构，其特征在于，所述第一放电控制开关(1041)的控制端连接至传输本像素单元(104)扫描信号的扫描线(Sn)。
3.如权利要求2所述的像素结构，其特征在于，所述第一放电控制开关(1041)的一端连接至上两个像素单元(104)的副像素电极(1047)。
4.如权利要求1所述的像素结构，其特征在于，所述每一像素单元(104)还包括一第一驱动线(P1)及一第二驱动线(P2)，所述每一像素单元(104)的第一放电控制开关(1041)的控制端连接至所述第一驱动线(P1)，所述每一像素单元(104)的第二放电控制开关(1042)的控制端连接所述第二驱动线(P2)。
5.如权利要求2或4中任一项所述的像素结构，其特征在于，所述第一放电控制开关(1041)的一端连接至相邻的上一个像素单元(104)的副像素电极(1047)。
6.如权利要求1所述的像素结构，其特征在于，所述第二放电控制开关(1042)的控制端连接至传输本像素单元(104)扫描信号的扫描线(sn)。
7.如权利要求1、2、4或6中任一项所述的像素结构，其特征在于，所述主充电控制开关(1046)、副充电控制开关(1048)、第一放电控制开关(1041)及第二放电控制开关(1042)为薄膜晶体管，第一放电控制开关(1041)及第二放电控制开关(1042)的控制端为薄膜晶体管的栅极。
8.一种液晶显示面板(1)，其特征在于：所述液晶面板包括如权利要求1、2、3、4或6中任一项所述的像素结构。
9.如权利要求8所述的液晶显示面板(1)，其特征在于，进一步包括阵列基板(10)、液晶层(20)以及彩膜基板(30)，所述阵列基板(10)与彩膜基板(30)相对设置，所述液晶层(20)夹设在阵列基板(10)与彩膜基板(30)之间。
10.如权利要求9所述的液晶显示面板(1)，其特征在于，所述阵列基板(10)包括绝缘层(100)、存储电容电极(102)及设置在绝缘层(100)上的用于显示不同色彩的像素单元(104)，所述存储电容电极(102)对应设置在每个像素单元(104)下，并由所述绝缘层(100)所覆盖，所述彩膜基板(3)0包括一公共电极(300)，所述公共电极(300)设置在彩膜基板(30)与阵列基板(10)相对的下表面。
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