WO2015110030A1 - 液晶面板及其像素结构 - Google Patents
液晶面板及其像素结构 Download PDFInfo
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- WO2015110030A1 WO2015110030A1 PCT/CN2015/071297 CN2015071297W WO2015110030A1 WO 2015110030 A1 WO2015110030 A1 WO 2015110030A1 CN 2015071297 W CN2015071297 W CN 2015071297W WO 2015110030 A1 WO2015110030 A1 WO 2015110030A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Definitions
- the invention relates to a liquid crystal panel and a pixel structure thereof.
- the low color-shifting pixel structure of the existing liquid crystal display panel mainly controls different regions of the same pixel by increasing the scanning lines.
- this method requires twice the number of Chip On Film (COF), resulting in an increase in cost.
- COF Chip On Film
- an embodiment of the present invention provides a pixel structure including a plurality of pixel units arranged in a matrix.
- the pixel unit is defined by a plurality of intersecting scan lines and data lines.
- Each of the pixel units includes a first discharge control switch, a second discharge control switch, and adjacently disposed main pixel regions and sub-pixel regions.
- the main pixel region includes a main pixel electrode and a main charge control switch.
- the sub-pixel region includes a sub-pixel electrode and a sub-charge control switch.
- the main pixel electrode receives a display signal through the main charge control switch.
- the sub-pixel electrode receives a display signal through the sub-charge control switch.
- the first discharge control switch is connected to a scan line that transmits a scan signal of the pixel unit and a sub-pixel electrode that is located at the upper pixel unit.
- the second discharge control switch is connected to the scan line transmitting the scan signal of the previous pixel unit and the sub-pixel electrode of the pixel unit.
- the control end of the first discharge control switch is connected to a scan line that transmits a scan signal of the pixel unit.
- one end of the first discharge control switch is connected to the sub-pixel electrode of the upper two pixel units.
- Each of the pixel units further includes a first driving line and a second driving line.
- a control end of the first discharge control switch of each of the pixel units is connected to the first driving line.
- the control end of the second discharge control switch of each pixel unit is connected to the second driving line.
- one end of the first discharge control switch is connected to a sub-pixel electrode of an adjacent previous pixel unit.
- the control end of the second discharge control switch is connected to a scan line that transmits a scan signal of the pixel unit.
- the main charging control switch, the sub charging control switch, the first discharging control switch and the second The discharge control switch is a thin film transistor.
- the control terminals of the first discharge control switch and the second discharge control switch are gates of the thin film transistor.
- a liquid crystal display panel includes an array substrate, a liquid crystal layer, and a color filter substrate, and the array substrate is disposed opposite to the color filter substrate.
- the liquid crystal layer is interposed between the array substrate and the color filter substrate.
- a plurality of pixel units arranged in a matrix are disposed on the array substrate.
- the pixel unit is defined by a plurality of intersecting scan lines and data lines.
- Each of the pixel units includes a first discharge control switch, a second discharge control switch, and adjacently disposed main pixel regions and sub-pixel regions.
- the main pixel region includes a main pixel electrode and a main charge control switch.
- the sub-pixel region includes a sub-pixel electrode and a sub-charge control switch.
- the main pixel electrode receives a display signal through the main charge control switch.
- the sub-pixel electrode receives a display signal through the sub-charge control switch.
- the first discharge control switch is connected to a scan line that transmits a scan signal of the pixel unit and a sub-pixel electrode that is located at the upper pixel unit.
- the second discharge control switch is connected to the scan line transmitting the scan signal of the previous pixel unit and the sub-pixel electrode of the pixel unit.
- the control end of the first discharge control switch is connected to a scan line that transmits a scan signal of the pixel unit.
- Each of the pixel units further includes a first driving line and a second driving line.
- a control end of the first discharge control switch of each of the pixel units is connected to the first driving line.
- the control end of the second discharge control switch of each pixel unit is connected to the second driving line.
- one end of the first discharge control switch is connected to a sub-pixel electrode of an adjacent previous pixel unit.
- the array substrate includes an insulating layer, a storage capacitor electrode, and a plurality of pixel units disposed on the insulating layer and having the pixel structure for displaying different colors.
- the storage capacitor electrode is disposed under each pixel unit and covered by the insulating layer.
- the color filter substrate includes a common electrode disposed on a lower surface of the color filter substrate opposite to the array substrate.
- the pixel structure of the liquid crystal display panel provided by the present invention can discharge the sub-pixel electrode without increasing the scanning line to achieve low color shift design requirements, and the pixel structure can be compatible with forward scanning and reverse scanning. Has a large application area.
- FIG. 1 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present invention.
- FIG. 2 is a schematic structural diagram of a pixel unit according to a first embodiment of the present invention.
- FIG. 3 is a schematic structural diagram of a pixel unit according to a second embodiment of the present invention.
- FIG. 4 is a schematic structural diagram of a pixel unit according to a third embodiment of the present invention.
- a liquid crystal display panel 1 includes an array substrate 10 , a liquid crystal layer 20 , and a color filter substrate 30 .
- the array substrate 10 is disposed opposite to the color filter substrate 30, and the liquid crystal layer 20 is interposed between the array substrate 10 and the color filter substrate 30.
- the array substrate 10 includes an insulating layer 100, a storage capacitor electrode 102, and a plurality of pixel units 104 having the same structure and displaying different colors disposed on the insulating layer 100.
- the storage capacitor electrode 102 is correspondingly disposed under each of the pixel units 104 and covered by the insulating layer 100.
- the color filter substrate 30 includes a common electrode 300.
- the common electrode 300 is disposed on a lower surface of the color filter substrate 30 opposite to the array substrate 10.
- FIG. 2 is a schematic diagram showing the circuit structure of the pixel unit 104 provided by the present invention.
- the array substrate 10 is provided with a plurality of scanning lines S1 to SN and a plurality of data lines L1 to LN.
- the scan lines S1 to SN are laterally disposed to transmit a scan signal for the selected pixel unit 104.
- the data lines L1 to LN are longitudinally arranged to transmit a display signal of the selected pixel unit 104.
- the scan lines S1 to SN and the data lines L1 to LN intersect perpendicularly to each other to define pixel units 104 arranged in a matrix. In other embodiments, the scan lines S1 to SN and the data lines L1 to LN may not be perpendicular.
- Each of the pixel units 104 includes a first discharge control switch 1041, a second discharge control switch 1042, and an adjacently disposed main pixel region 1043 and a sub-pixel region 1044.
- the storage capacitor electrode 102 is disposed corresponding to the lower side of the main pixel region 1043 and the sub-pixel region 1044.
- the main pixel region 1043 includes a main pixel electrode 1045 and a main charge control switch 1046.
- the sub-pixel region 1044 includes a sub-pixel electrode 1047 and a sub-charge control switch 1048.
- the first discharge control switch 1041 connects the following scan line Sn constituting the pixel unit 104 and the sub-pixel electrode in the other pixel unit 104 located above.
- the second discharge control switch 1042 is connected to the upper column scan line Sn-1 constituting the pixel unit 104 and the sub-pixel electrode 1047 of the pixel unit 104 to control the pixel under the control of the scan signal of the upper column scan line Sn-1.
- the sub-pixel electrode 1047 of the cell 104 is discharged.
- the sub-pixel electrode 1047 forms a potential difference between the main pixel electrode 1045 and the main pixel electrode 1045 in the same pixel unit 104 after discharge, thereby achieving the purpose of reducing color shift.
- the first discharge control switch 1041 is connected to the sub-pixel electrode 1047 in the adjacent previous pixel unit 104.
- the second discharge control switch 10421 is connected to the sub-pixel electrode 1047 in the adjacent next pixel unit 104.
- the main charge control switch 1046, the sub charge control switch 1048, the first discharge control switch 1041, and the second discharge control switch 1042 are each preferably a thin film transistor.
- the gate of the main charge control switch 1046 is a control terminal and is connected to the scan lines S1 to SN.
- the source of the primary charge control switch 1046 is coupled to the data line.
- the drain of the main charge control switch 1046 is connected to the main pixel electrode 1045.
- the gate of the secondary charging control switch 1048 is a control terminal and is connected to the scan lines S1 to SN.
- the source of the sub-charge control switch 1048 is connected to the data lines L1 to LN.
- the drain of the sub-charge control switch 1048 is connected to the sub-pixel electrode 1047.
- the gate of the first discharge control switch 1041 is a control terminal.
- the gate and the source of the first discharge control switch 1041 are commonly connected to the following scan line Sn of the pixel unit 104.
- the drain of the first discharge control switch 1041 is connected to the sub-pixel electrode 1047 of the previous pixel unit 104.
- the gate of the second discharge control switch 1042 is a control terminal.
- the gate and the source of the second discharge control switch 1042 are commonly connected to the upper column scan line Sn-1 of the pixel unit 104.
- the drain of the second discharge control switch 1042 is connected to the sub-pixel electrode 1047 of the pixel unit 104.
- the n-th pixel unit 104 shown in FIG. 2 will be described below as an example.
- the forward scanning mode is adopted, that is, the scanning signals are sequentially loaded from the first scanning line S1 to the Nth scanning line SN.
- the main charge control switch 1046 and the sub charge control switch 1048 of the nth pixel unit 104 are turned on by the respective gates.
- the display signal of the nth pixel unit 104 charges the main pixel electrode 1045 and the sub pixel electrode 1047 of the nth pixel unit 104 through the main charge control switch 1046 and the sub charge control switch 1048 along the nth data line Ln.
- the first discharge control switch 1041 connected to the nth scanning line Sn is turned on to discharge the sub-pixel electrode 1047 of the n-1th pixel unit 104. Since the scan signal is transmitted along the n-1th scan line Sn-1 before this, the main pixel electrode 1045 in the n-1th pixel unit 104 And the sub-pixel electrode 1047 has been charged. Therefore, after the sub-pixel electrode 1047 of the n-1th pixel unit 104 is discharged by the first discharge control switch 1041 of the nth pixel unit 104, the main pixel electrode 1045 and the sub-pixel electrode 1047 of the n-1th pixel unit 104 are The potentials are different to achieve low color shift design requirements.
- the first discharge control switch 1041 of the n+1th pixel unit 104 is turned on and the sub-pixel in the nth pixel unit 104 is turned on.
- the electrode 1047 is discharged such that the sub-pixel electrode 1047 of the n-th pixel unit 104 has a potential different from that of the main pixel electrode 1045.
- the second discharge control switch 1042 of the n+1th pixel unit 104 is turned on when the scan signal is transmitted along the nth scan line, the subpixel electrode 1047 of the n+1th pixel unit 104 is scanned in the previous frame. It has been discharged during the cycle, so it will not discharge again at this time.
- the reverse scanning mode is adopted, that is, the scanning signals are sequentially loaded from the Nth scanning line SN to the first scanning line S1.
- the main charge control switch 1046 and the sub charge control switch 1048 of the nth pixel unit 104 are turned on by the respective gates.
- the display signal of the nth pixel unit 104 charges the main pixel electrode 1045 and the sub pixel electrode 1047 of the nth pixel unit 104 through the main charge control switch 1046 and the sub charge control switch 1048 along the nth data line Ln.
- the second discharge control switch 1042 of the n+1th pixel unit 104 connected to the nth scan line Sn is turned on to discharge the subpixel electrode 1047 of the n+1th pixel unit 104. Since the main pixel electrode 1045 and the sub-pixel electrode 1047 in the n+1th pixel unit 104 have been charged when the scan signal is transmitted along the n+1th scan line Sn+1, the n+1th pixel unit 104 is charged. After the sub-pixel electrode 1047 is discharged by the second discharge control switch 1042 of the nth pixel unit 104, the potential between the main pixel electrode 1045 and the sub-pixel electrode 1047 of the n+1th pixel unit 104 is different, thereby achieving low color. Partial design requirements.
- the second discharge control switch 1042 of the nth pixel unit 104 is turned on and the sub-pixel electrode 1047 in the nth pixel unit 104 is turned on.
- the discharge is performed such that the sub-pixel electrode 1047 of the n-th pixel unit 104 has a potential different from that of the main pixel electrode 1045.
- the first discharge control switch 1041 of the n-1th pixel unit 104 is turned on when the scan signal is transmitted along the nth scan line Sn, since the sub-pixel of the n-1th pixel unit 104 is in the previous frame scan period The inside is discharged, so it will not discharge again at this time.
- the pixel structure of the liquid crystal display panel 1 provided by the present invention can discharge the sub-pixel electrode 1047 without increasing the scanning line to achieve a low color shift design requirement, and the pixel structure can be compatible with forward scanning and Reverse scanning has a large application area.
- the structure of the pixel unit 204 provided by the second embodiment of the present invention has the first
- the structure of the pixel unit 104 of the embodiment is substantially the same, except that the drain of the first discharge control switch 2041 in the pixel unit 204 of the second embodiment is connected to the sub-pixel electrode 2047 of the upper two pixel units 204.
- the sub-pixel electrode 2047 of the nth pixel unit 204 needs to be selected after the next two scanning lines Sn+2, that is, the n+2th scanning line Sn+2 is selected after the charging is completed.
- the discharge is performed by the first discharge control switch 2041 on the scan line Sn+2 to achieve a potential difference with the main pixel electrode 2045 in the same pixel unit 204.
- the structure of the pixel unit 304 provided by the third embodiment of the present invention has substantially the same structure as that of the pixel unit 104 of the first embodiment, and the difference is that the pixel unit 304 of the third embodiment Also included are a first drive line P1 and a second drive line P2 that intersect perpendicularly to the scan line.
- the gate of the first discharge control switch 3041 of each pixel unit 304 is connected to the first driving line P1.
- the gate of the second discharge control switch 3042 of each pixel unit 304 is connected to the second drive line P2.
- the driving signal is output to the first driving line P1, and the first discharging control switch 3041 in each pixel unit 304 is turned on.
- the scan signal is transmitted along the nth scan line Sn
- the scan signal is transmitted to the sub-pixel electrode 3047 of the n-1th pixel unit 304 of the previous one through the first discharge control switch 3041 in the nth pixel unit 304.
- the sub-pixel electrode 3047 of the n-1 pixel unit 304 is discharged.
- the sub-pixel electrode 3047 of the nth pixel unit 304 is discharged by the first discharge control switch 3041 of the turned-on n+1th pixel unit 304. Since no signal is applied to the second driving line P2 during forward scanning, the second discharging control switch 3042 in each pixel unit 304 is not turned on, so that the second discharging control switch 3042 is not connected.
- the sub-pixel electrode 3047 is discharged.
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Abstract
一种像素结构,包括矩阵排列的多个像素单元(104)。像素单元(104)由相交的多条扫描线及数据线所定义。每一像素单元(104)包括第一放电控制开关(1041)、第二放电控制开关(1042)以及相邻设置的主像素区(1043)及副像素区(1044)。主像素区(1043)包括主像素电极(1045)及主充电控制开关(1046)。副像素区(1044)包括副像素电极(1047)及副充电控制开关(1048)。主像素电极(1045)通过主充电控制开关(1046)接收显示信号。副像素电极(1047)通过副充电控制开关(1048)接收显示信号。第一放电控制开关(1041)连接传输本像素单元(104)扫描信号的扫描线与位于上方像素单元(104)的副像素电极(1047)。第二放电控制开关(1042)连接传输上一个像素单元(104)扫描信号的扫描线与本像素单元(104)的副像素电极(1047)。还公开了一种包括该像素结构的液晶显示面板(1)。
Description
本发明涉及一种液晶面板及其像素结构。
现有液晶显示面板的低色偏像素结构主要是通过增加扫描线,分别对同一像素的不同区域进行控制。然此种方法需要多一倍的覆晶薄膜(Chip On Film,COF)数量,导致成本增加。
因此,需要提供能够改善上述问题的液晶面板及其像素结构。
发明内容
为了解决上述技术问题,本发明实施例提供了一种像素结构,其包括矩阵排列的多个像素单元。所述像素单元由相交的多条扫描线及数据线所定义。每一像素单元包括第一放电控制开关、第二放电控制开关以及相邻设置的主像素区及副像素区。所述主像素区包括主像素电极及主充电控制开关。所述副像素区包括副像素电极及副充电控制开关。所述主像素电极通过该主充电控制开关接收显示信号。所述副像素电极通过该副充电控制开关接收显示信号。所述第一放电控制开关连接传输本像素单元扫描信号的扫描线与位于上方像素单元的副像素电极。所述第二放电控制开关连接传输上一个像素单元扫描信号的扫描线与本像素单元的副像素电极。
其中,所述第一放电控制开关的控制端连接至传输本像素单元扫描信号的扫描线。
其中,所述第一放电控制开关的一端连接至上两个像素单元的副像素电极。
其中,所述每一像素单元还包括一第一驱动线及一第二驱动线。所述每一像素单元的第一放电控制开关的控制端连接至所述第一驱动线。所述每一像素单元的第二放电控制开关的控制端连接所述第二驱动线。
其中,所述第一放电控制开关的一端连接至相邻的上一个像素单元的副像素电极。
其中,所述第二放电控制开关的控制端连接至传输本像素单元扫描信号的扫描线。
其中,所述主充电控制开关、副充电控制开关、第一放电控制开关及第二
放电控制开关为薄膜晶体管。第一放电控制开关及第二放电控制开关的控制端为薄膜晶体管的栅极。
一种液晶显示面板,其包括阵列基板、液晶层以及彩膜基板,所述阵列基板与彩膜基板相对设置。所述液晶层夹设在阵列基板与彩膜基板之间。所述阵列基板上设置有矩阵排列的多个像素单元。所述像素单元由相交的多条扫描线及数据线所定义。每一像素单元包括第一放电控制开关、第二放电控制开关以及相邻设置的主像素区及副像素区。所述主像素区包括主像素电极及主充电控制开关。所述副像素区包括副像素电极及副充电控制开关。所述主像素电极通过该主充电控制开关接收显示信号。所述副像素电极通过该副充电控制开关接收显示信号。所述第一放电控制开关连接传输本像素单元扫描信号的扫描线与位于上方像素单元的副像素电极。所述第二放电控制开关连接传输上一个像素单元扫描信号的扫描线与本像素单元的副像素电极。
其中,所述第一放电控制开关的控制端连接至传输本像素单元扫描信号的扫描线。
其中,所述每一像素单元还包括一第一驱动线及一第二驱动线。所述每一像素单元的第一放电控制开关的控制端连接至所述第一驱动线。所述每一像素单元的第二放电控制开关的控制端连接所述第二驱动线。
其中,所述第一放电控制开关的一端连接至相邻的上一个像素单元的副像素电极。
其中,所述阵列基板包括绝缘层、存储电容电极及设置在绝缘层上的多个具有所述像素结构、用于显示不同色彩的像素单元。所述存储电容电极对应设置在每个像素单元下,并由所述绝缘层所覆盖。所述彩膜基板包括一公共电极,所述公共电极设置在彩膜基板与阵列基板相对的下表面。
本发明所提供的液晶显示面板的像素结构可在不增加扫描线的前提下对副像素电极进行放电而实现低色偏的设计要求,而且所述像素结构可以兼容正向扫描和反向扫描,具有较大的应用领域。
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付
出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1是本发明实施例所提供的液晶显示面板的结构示意图。
图2是本发明第一实施例所提供的像素单元的结构示意图。
图3是本发明第二实施例所提供的像素单元的结构示意图。
图4是本发明第三实施例所提供的像素单元的结构示意图。
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
如图1所示,本发明第一实施例所提供的液晶显示面板1包括阵列基板10、液晶层20以及彩膜基板30。其中,阵列基板10与彩膜基板30相对设置,液晶层20夹设在阵列基板10和彩膜基板30之间。
所述阵列基板10包括绝缘层100、存储电容电极102及设置在绝缘层100上的多个结构相同、用于显示不同色彩的像素单元104。所述存储电容电极102对应设置在每个像素单元104下,并由所述绝缘层100所覆盖。
所述彩膜基板30包括一公共电极300。所述公共电极300设置在彩膜基板30与阵列基板10相对的下表面。
请一并参阅图1及图2,图2是本发明所提供的像素单元104的电路结构示意图。所述阵列基板10上设置有多条扫描线S1~SN以及多条数据线L1~LN。所述扫描线S1~SN横向设置以传输用于选中像素单元104的扫描信号。所述数据线L1~LN纵向设置以传输所选中像素单元104的显示信号。所述扫描线S1~SN和数据线L1~LN彼此垂直相交以定义出呈矩阵排列的像素单元104。在其他实施例中,扫描线S1~SN和数据线L1~LN也可以不垂直。
所述每一个像素单元104包括第一放电控制开关1041、第二放电控制开关1042以及相邻设置的主像素区1043和副像素区1044。所述主像素区1043与副像素区1044的下方分别对应设置有所述存储电容电极102。所述主像素区1043包括主像素电极1045及主充电控制开关1046。所述副像素区1044包括副像素电极1047及副充电控制开关1048。所述第一放电控制开关1041连接构成该像素单元104的下列扫描线Sn与位于上方的其他像素单元104中的副像素电极
1047以在下列扫描线Sn的扫描信号的控制下对上方像素单元104的副像素电极1047进行放电。所述第二放电控制开关1042连接构成该像素单元104的上列扫描线Sn-1与该像素单元104的副像素电极1047以在上列扫描线Sn-1的扫描信号的控制下对该像素单元104的副像素电极1047进行放电。所述副像素电极1047在放电后与同一像素单元104内的主像素电极1045之间形成电位差,达到降低色偏的目的。在本实施例中,所述第一放电控制开关1041与相邻的上一个像素单元104中的副像素电极1047相连接。所述第二放电控制开关10421与相邻的下一个像素单元104中的副像素电极1047相连接。
所述主充电控制开关1046、副充电控制开关1048、第一放电控制开关1041及第二放电控制开关1042均优选为薄膜晶体管。所述主充电控制开关1046的栅极为控制端且连接至扫描线S1~SN上。所述主充电控制开关1046的源极连接至数据线上。所述主充电控制开关1046的漏极连接至主像素电极1045。所述副充电控制开关1048的栅极为控制端且连接至扫描线S1~SN上。所述副充电控制开关1048的源极连接至数据线L1~LN上。所述副充电控制开关1048的漏极连接至副像素电极1047。
所述第一放电控制开关1041的栅极为控制端。所述第一放电控制开关1041的栅极及源极共同连接至该像素单元104的下列扫描线Sn上。所述第一放电控制开关1041的漏极连接至上一个像素单元104的副像素电极1047。所述第二放电控制开关1042的栅极为控制端。所述第二放电控制开关1042的栅极及源极共同连接至该像素单元104的上列扫描线Sn-1上。所述第二放电控制开关1042的漏极连接至该像素单元104的副像素电极1047。
下面以图2中所示的第n像素单元104为例进行说明。
采用正向扫描方式,即扫描信号按照从第一条扫描线S1至第N条扫描线SN依次加载。当扫描信号沿第n条扫描线Sn传输时,第n像素单元104的主充电控制开关1046及副充电控制开关1048通过各自的栅极被扫描信号导通。第n像素单元104的显示信号沿第n条数据线Ln分别通过所述主充电控制开关1046及副充电控制开关1048对第n像素单元104的主像素电极1045及副像素电极1047充电。于此同时,与第n条扫描线Sn相连的第一放电控制开关1041被导通以使得第n-1像素单元104的副像素电极1047放电。因为在此之前扫描信号沿第n-1条扫描线Sn-1传输时,第n-1像素单元104内的主像素电极1045
及副像素电极1047已被充电。所以,当第n-1像素单元104的副像素电极1047被第n像素单元104的第一放电控制开关1041放电后,所述第n-1像素单元104的主像素电极1045与副像素电极1047之间的电位不同,从而达到低色偏的设计要求。同理,当扫描信号沿下一列第n+1条扫描线Sn+1传输时,第n+1像素单元104的第一放电控制开关1041被导通而对第n像素单元104内的副像素电极1047进行放电,使得第n像素单元104的副像素电极1047具有与主像素电极1045不同的电位。虽然当扫描信号沿第n条扫描线传输时第n+1像素单元104的第二放电控制开关1042会被导通,但因为第n+1像素单元104的副像素电极1047在上一帧扫描周期内已被放电,所以此时不会再次放电。
采用反向扫描方式,即扫描信号按照从第N条扫描线SN至第一条扫描线S1依次加载。当扫描信号沿第n条扫描线Sn传输时,第n像素单元104的主充电控制开关1046及副充电控制开关1048通过各自的栅极被扫描信号导通。第n像素单元104的显示信号沿第n条数据线Ln分别通过所述主充电控制开关1046及副充电控制开关1048对第n像素单元104的主像素电极1045及副像素电极1047充电。于此同时,与第n条扫描线Sn相连的第n+1像素单元104的第二放电控制开关1042被导通以使得第n+1像素单元104的副像素电极1047放电。因为在此之前扫描信号沿第n+1条扫描线Sn+1传输时第n+1像素单元104内的主像素电极1045及副像素电极1047已被充电,所以当第n+1像素单元104的副像素电极1047被第n像素单元104的第二放电控制开关1042放电后,所述第n+1像素单元104的主像素电极1045与副像素电极1047之间的电位不同,从而达到低色偏的设计要求。同理,当扫描信号沿下一列第n-1条扫描线Sn-1传输时,第n像素单元104的第二放电控制开关1042被导通而对第n像素单元104内的副像素电极1047进行放电,使得第n像素单元104的副像素电极1047具有与主像素电极1045不同的电位。虽然当扫描信号沿第n条扫描线Sn传输时第n-1像素单元104的第一放电控制开关1041会被导通,但因为第n-1像素单元104的副像素在上一帧扫描周期内以被放电,所以此时不会再次放电。
因此,本发明所提供的液晶显示面板1的像素结构可在不增加扫描线的前提下对副像素电极1047进行放电而实现低色偏的设计要求,而且所述像素结构可以兼容正向扫描和反向扫描,具有较大的应用领域。
如图3所示,本发明第二实施例所提供的像素单元204的结构具有与第一
实施例的像素单元104的结构基本相同的结构,其区别在于:第二实施例的像素单元204内的第一放电控制开关2041的漏极连接至上两个像素单元204的副像素电极2047。对应地,在采用正向扫描方式时,第n像素单元204的副像素电极2047在完成充电后需要在下两条扫描线Sn+2,即第n+2条扫描线Sn+2被选中时才会通过该条扫描线Sn+2上的第一放电控制开关2041进行放电,以实现与相同像素单元204内的主像素电极2045之间的电位差。
如图4所示,本发明第三实施例所提供的像素单元304的结构具有与第一实施例的像素单元104的结构基本相同的结构,其区别在于:第三实施例的像素单元304的还包括与扫描线垂直相交的第一驱动线P1及第二驱动线P2。每个像素单元304的第一放电控制开关3041的栅极均连接至该第一驱动线P1。每个像素单元304的第二放电控制开关3042的栅极均连接至该第二驱动线P2。采用正向扫描方式时,向第一驱动线P1输出驱动信号则每个像素单元304内的第一放电控制开关3041都被导通。此时当扫描信号沿第n条扫描线Sn传输时,扫描信号通过第n像素单元304内的第一放电控制开关3041传输至上一个的第n-1像素单元304的副像素电极3047以对第n-1像素单元304的副像素电极3047进行放电。在扫描信号沿下一列第n+1条扫描线Sn+1传输时,第n像素单元304的副像素电极3047通过导通的第n+1像素单元304的第一放电控制开关3041进行放电。因为在正向扫描时所述第二驱动线P2上未施加信号,所以每个像素单元304内的第二放电控制开关3042均未被导通,从而不会对与第二放电控制开关3042连接的副像素电极3047进行放电。
以上所揭露的仅为本发明一种较佳实施例而已,当然不能以此来限定本发明之权利范围,因此依本发明权利要求所作的等同变化,仍属本发明所涵盖的范围。
Claims (16)
- 一种像素结构,其包括矩阵排列的多个像素单元,所述像素单元由相交的多条扫描线及数据线所定义,每一像素单元包括第一放电控制开关、第二放电控制开关以及相邻设置的主像素区及副像素区,所述主像素区包括主像素电极及主充电控制开关,所述副像素区包括副像素电极及副充电控制开关,所述主像素电极通过该主充电控制开关接收显示信号,所述副像素电极通过该副充电控制开关接收显示信号,所述第一放电控制开关连接传输本像素单元扫描信号的扫描线与位于上方像素单元的副像素电极,所述第二放电控制开关连接传输上一个像素单元扫描信号的扫描线与本像素单元的副像素电极。
- 如权利要求1所述的像素结构,其中,所述第一放电控制开关的控制端连接至传输本像素单元扫描信号的扫描线。
- 如权利要求2所述的像素结构,其中,所述第一放电控制开关的一端连接至上两个像素单元的副像素电极。
- 如权利要求1所述的像素结构,其中,所述每一像素单元还包括一第一驱动线及一第二驱动线,所述每一像素单元的第一放电控制开关的控制端连接至所述第一驱动线,所述每一像素单元的第二放电控制开关的控制端连接所述第二驱动线。
- 如权利要求2所述的像素结构,其中,所述第一放电控制开关的一端连接至相邻的上一个像素单元的副像素电极。
- 如权利要求4所述的像素结构,其中,所述第一放电控制开关的一端连接至相邻的上一个像素单元的副像素电极。
- 如权利要求1所述的像素结构,其中,所述第二放电控制开关的控制端连接至传输本像素单元扫描信号的扫描线。
- 如权利要求1所述的像素结构,其中,所述主充电控制开关、副充电控制开关、第一放电控制开关及第二放电控制开关为薄膜晶体管,第一放电控制开关及第二放电控制开关的控制端为薄膜晶体管的栅极。
- 如权利要求2所述的像素结构,其中,所述主充电控制开关、副充电控制开关、第一放电控制开关及第二放电控制开关为薄膜晶体管,第一放电控制开关及第二放电控制开关的控制端为薄膜晶体管的栅极。
- 如权利要求4所述的像素结构,其中,所述主充电控制开关、副充电控 制开关、第一放电控制开关及第二放电控制开关为薄膜晶体管,第一放电控制开关及第二放电控制开关的控制端为薄膜晶体管的栅极。
- 如权利要求6所述的像素结构,其中,所述主充电控制开关、副充电控制开关、第一放电控制开关及第二放电控制开关为薄膜晶体管,第一放电控制开关及第二放电控制开关的控制端为薄膜晶体管的栅极。
- 一种液晶显示面板,其包括阵列基板、液晶层以及彩膜基板,所述阵列基板与彩膜基板相对设置,所述液晶层夹设在阵列基板与彩膜基板之间,其中:所述阵列基板上设置有矩阵排列的多个像素单元,所述像素单元由相交的多条扫描线及数据线所定义,每一像素单元包括第一放电控制开关、第二放电控制开关以及相邻设置的主像素区及副像素区,所述主像素区包括主像素电极及主充电控制开关,所述副像素区包括副像素电极及副充电控制开关,所述主像素电极通过该主充电控制开关接收显示信号,所述副像素电极通过该副充电控制开关接收显示信号,所述第一放电控制开关连接传输本像素单元扫描信号的扫描线与位于上方像素单元的副像素电极,所述第二放电控制开关连接传输上一个像素单元扫描信号的扫描线与本像素单元的副像素电极。
- 如权利要求12所述的液晶显示面板,其中,所述第一放电控制开关的控制端连接至传输本像素单元扫描信号的扫描线。
- 如权利要求12所述的液晶显示面板,其中,所述每一像素单元还包括一第一驱动线及一第二驱动线,所述每一像素单元的第一放电控制开关的控制端连接至所述第一驱动线,所述每一像素单元的第二放电控制开关的控制端连接所述第二驱动线。
- 如权利要求14所述的液晶显示面板,其中,所述第一放电控制开关的一端连接至相邻的上一个像素单元的副像素电极。
- 如权利要求12所述的液晶显示面板,其中,所述阵列基板包括绝缘层、存储电容电极及设置在绝缘层上的用于显示不同色彩的像素单元,所述存储电容电极对应设置在每个像素单元下,并由所述绝缘层所覆盖,所述彩膜基板包括一公共电极,所述公共电极设置在彩膜基板与阵列基板相对的下表面。
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