WO2016060134A1 - Émetteur optique, câble optique actif, unité de réseau optique et procédé de transmission optique - Google Patents

Émetteur optique, câble optique actif, unité de réseau optique et procédé de transmission optique Download PDF

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Publication number
WO2016060134A1
WO2016060134A1 PCT/JP2015/078959 JP2015078959W WO2016060134A1 WO 2016060134 A1 WO2016060134 A1 WO 2016060134A1 JP 2015078959 W JP2015078959 W JP 2015078959W WO 2016060134 A1 WO2016060134 A1 WO 2016060134A1
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Prior art keywords
current
auxiliary
magnitude
signal
driver
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PCT/JP2015/078959
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English (en)
Japanese (ja)
Inventor
達夫 久保
菊池　修
田中　貴之
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株式会社フジクラ
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Priority to JP2016554088A priority Critical patent/JP6190072B2/ja
Publication of WO2016060134A1 publication Critical patent/WO2016060134A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
    • H01S5/062—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters

Definitions

  • the present invention relates to an optical transmitter and an optical transmission method for converting a data signal into an optical signal and transmitting it.
  • the present invention also relates to an active optical cable in which such an optical transmitter is incorporated in a connector, and an ONU in which such an optical transmitter is incorporated.
  • serial communication In serial communication according to SAS (Serial Attached SCSI) 2.0, negotiation using an OOB (Out Of Band) signal is performed before starting data transfer.
  • the OOB signal has a pattern including a DATA section in which a value (voltage) alternately takes a high level and a low level, and an IDLE section in which the value (voltage) continues to take an intermediate level between the high level and the low level.
  • PCIe PCI Express
  • the same signal is used for negotiation.
  • an IDLE section included in a signal transmitted / received at the time of negotiation is also referred to as an EI section (Electrical Idle).
  • the metal cable 101 includes a cable 104 and connectors 102 and 103 provided at both ends of the cable 104.
  • the cable 104 accommodates a metal wire 107 as a transmission medium, and the connectors 102 and 103 contain AC coupling capacitors 105 and 106.
  • the data signal includes an OOB signal or the like (a signal having a pattern composed of a DATA section and an EI section in PCIe 3.0, etc., the same signal as the OOB signal in SAS 2.0. Even in the same manner, a voltage signal having the same waveform as the data signal input to one connector 102 can be output from the other connector 103.
  • the active optical cable 201 includes a cable 204 and connectors 202 and 203 provided at both ends of the cable 204.
  • the cable 204 accommodates an optical fiber 211 that is a transmission medium.
  • the connector 202 includes an AC coupling capacitor 205, a transmission circuit 206, and an LD (Laser Diode) 207.
  • the connector 203 contains a PD (Photo Diode) 208, a receiving circuit 209, and an AC coupling capacitor 210.
  • As light-emitting element driving circuits that can be used as the transmission circuit 206 for example, those disclosed in Patent Documents 1 and 2 are known.
  • the magnitude of the drive current input to the LD 207 is fixed in the IDLE section in the connector 202, the magnitude of the photocurrent output from the PD 208 in the IDLE section in the connector 203 is indefinite.
  • the electro-optical conversion efficiency of the LD 207 and the photo-electric conversion efficiency of the PD 208 can vary due to temperature changes or the like, and the loss of the optical fiber 211 can vary due to bending or the like.
  • the IDLE section in which the value of the data signal input to the connector 202 continues to take the intermediate level cannot be correctly specified on the connector 203 side by threshold processing or the like. Therefore, when the data signal input to the connector 202 is an OOB signal or the like, it is difficult to reproduce in the connector 203 a voltage signal having the same waveform as the data signal input to the connector 202.
  • the value of the optical signal output from the connector 202 in the IDLE section may be set to an off level, for example.
  • the delay from the start of the IDLE interval until the value of the optical signal becomes off-level, and the light after the IDLE interval ends. It is necessary to suppress the delay until the signal value becomes high level or low level to 5 ns or less.
  • the current signal ⁇ Ib output from the compensator is a differential current signal for canceling the dullness of the rising / falling edge of the current signal ⁇ Ia output from the current driver, and the value of the sum signal ⁇ Ia + ⁇ Ib is specified. It is not for making it zero over the interval.
  • the current signal ⁇ I1 output from the error amplifier is a current signal representing the difference between the monitor signal Im and the light emission command signal Isig, and is not for setting the value of the sum signal ⁇ I1 + ⁇ I2 to 0 over a specific section. Absent. Therefore, the optical signal output from the connector 202 in the IDLE section does not meet the above-described purpose of setting the value of the optical signal to an off level, for example.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to turn off the value of an optical signal in a non-signal section (IDLE section in SAS, EI section in PCIe, Disable section in PON, etc.).
  • An optical transmitter is to realize an optical transmitter that has a shorter delay from the start of a no-signal interval until the value of an optical signal becomes an off level than before.
  • an optical transmitter includes a modulation driver that sucks a modulation current according to a data signal, an auxiliary driver that sucks or discharges an auxiliary current in a non-signal period, the bias current, and the modulation
  • a light emitting element in which a driving current obtained by subtracting the auxiliary current from the difference or sum of the current flows in or out, and the magnitude of the auxiliary current is such that the magnitude of the driving current in a non-signal period is that of the light emitting element. It is set so that it may become below a threshold current.
  • an optical transmission method includes a suction step for sucking a modulation current according to a data signal, a suction / discharge step for sucking or discharging an auxiliary current in a no-signal section, Including an inflow / outflow process for flowing in or out of the light emitting element a driving current obtained by subtracting the auxiliary current from the difference or sum of the bias current and the modulation current. It is characterized in that the magnitude of the drive current is set to be equal to or less than the threshold current of the light emitting element.
  • the auxiliary driver can realize the control so that the magnitude of the drive current in the no-signal section is equal to or less than the threshold current of the light emitting element. For this reason, compared with a conventional optical transmitter that realizes this control by stopping the power supply to the modulation driver and the bias current source, until the value of the optical signal becomes off-level after the no-signal interval starts. The delay can be shortened.
  • An active optical cable including a cable containing an optical fiber and a pair of connectors provided at both ends of the cable, wherein one or both of the pair of connectors includes the transmitter.
  • Optical cables are also included in the scope of the present invention.
  • an ONU Optical Network Unit
  • PON Passive Optical Network
  • an optical transmitter or an optical transmission method for setting an optical signal value to an off level in a no-signal section, and a delay from the start of the no-signal section to an optical signal value becoming an off level.
  • FIG. 2 is a block diagram which shows the structure of the optical transmitter which concerns on the 1st Embodiment of this invention. It is a wave form diagram of the voltage signal in each part of the optical transmitter of FIG.
  • FIG. 2 is a waveform diagram of a current signal in each part of the optical transmitter in FIG. 1.
  • FIG. 2 is a circuit diagram illustrating a configuration example of an IDLE detection circuit included in the optical transmitter of FIG. 1.
  • FIG. 5 is a waveform diagram of a voltage signal in each part of the IDLE detection circuit of FIG. 4.
  • FIG. 2 is a circuit diagram illustrating a first configuration example of a modulation driver and an auxiliary driver included in the optical transmitter of FIG. 1.
  • FIG. 4 is a circuit diagram illustrating a second configuration example of a modulation driver and an auxiliary driver included in the optical transmitter of FIG. 1.
  • FIG. 6 is a circuit diagram illustrating a third configuration example of a modulation driver and an auxiliary driver included in the optical transmitter of FIG. 1.
  • FIG. 2 is a circuit diagram illustrating a first configuration example of a bias current source included in the optical transmitter of FIG. 1.
  • FIG. 4 is a circuit diagram illustrating a second configuration example of a bias current source included in the optical transmitter of FIG. 1.
  • FIG. 2 is a circuit diagram illustrating a first configuration of a compensation current source included in the optical transmitter of FIG. 1.
  • FIG. 4 is a circuit diagram showing a second configuration of a compensation current source included in the optical transmitter of FIG. 1.
  • FIG. 14 is a circuit diagram illustrating a configuration example of a bias current source included in the optical transmitter of FIG. 13. It is a circuit diagram which shows the 1st structure of the compensation current source with which the optical transmitter of FIG. 13 is provided. It is a circuit diagram which shows the 2nd structure of the compensation current source with which the optical transmitter of FIG. 13 is provided.
  • FIG. 5 is a circuit diagram showing a first modification of the IDLE detection circuit shown in FIG. 4.
  • FIG. 5 is a circuit diagram showing a first modification of the IDLE detection circuit shown in FIG. 4.
  • FIG. 6 is a circuit diagram showing a second modification of the IDLE detection circuit shown in FIG. 4.
  • FIG. 27 is a waveform diagram of a voltage signal in each part of the IDLE detection circuit of FIG. 26.
  • FIG. 6 is a circuit diagram showing a third modification of the IDLE detection circuit shown in FIG. 4.
  • FIG. 27A is a circuit diagram of an IDLE detection circuit shown in FIG. 4 and a comparator that can be used in place of the low-pass filter provided in the IDLE detection circuit shown in FIG. (B) to (d) are waveform diagrams of voltage signals in respective parts of the comparator.
  • the optical transmitter according to the present embodiment is assumed to be used as a connector of an active optical cable that performs serial communication according to SAS (Serial Attached SCSI). Therefore, an OOB (Out (Of Band) signal is input as a data signal to the optical transmitter according to the present embodiment in the link-up sequence.
  • the OOB signal is a ternary voltage signal and includes a DATA section and an IDLE section.
  • the value of the OOB signal alternately takes a high level and a low level in the DATA period, and continues to take an intermediate level (a value smaller than the high level and larger than the low level) in the IDLE period.
  • the light emitting element included in the optical transmitter according to this embodiment is a VCSEL (VerticalELCavity Emitting Laser).
  • the optical transmitter according to the present embodiment converts the data signal into an optical signal by controlling the magnitude of the drive current flowing into the VCSEL via the anode terminal.
  • the present embodiment is not limited to the VCSEL, and can be applied to all light emitting elements capable of controlling the light emission amount by changing the magnitude of the inflowing drive current.
  • FIG. 1 is a block diagram showing the configuration of the optical transmitter 1.
  • the optical transmitter 1 includes an IDLE detection circuit 11, a squelch circuit 12, a modulation driver 13, an auxiliary driver 14, a bias current source 15, a compensation current source 16, and a VCSEL 17. ing.
  • the IDLE detection circuit 11, the squelch circuit 12, the modulation driver 13, the auxiliary driver 14, the bias current source 15, and the compensation current source 16 are integrated into a single integrated circuit (“TX-IC” in FIG. 1).
  • TX-IC integrated circuit
  • the present invention is not limited to this. That is, the optical transmitter 1 may be realized by a discrete circuit in which the IDLE detection circuit 11, the squelch circuit 12, the modulation driver 13, the auxiliary driver 14, the bias current source 15, and the compensation current source 16 are individually mounted.
  • the IDLE detection circuit 11 detects the IDLE section with reference to the data signal.
  • the IDLE section detected by the IDLE detection circuit 11 is a section (time zone) in which the value of the data signal is included in a predetermined range between the high level and the low level.
  • the IDLE detection circuit 11 generates an IDLE detection signal indicating an IDLE section.
  • the IDLE detection signal generated by the IDLE detection circuit 11 is a voltage signal whose value becomes high level in the IDLE section and whose value becomes low level outside the IDLE section (in the DATA section). For example, when the waveform of the data signal (time change of the input voltage v1) is as shown in FIG. 2A, the waveform of the IDLE detection signal (time change of the output voltage v2) is as shown in FIG. 2B. Become.
  • the IDLE detection signal generated by the IDLE detection circuit 11 is input to the squelch circuit 12 and the auxiliary driver 14. A configuration example of the IDLE detection circuit 11 will be described later with reference to another drawing.
  • the squelch circuit 12 refers to the IDLE detection signal and identifies the IDLE section. Further, the squelch circuit 12 corrects the value of the data signal to a low level in the IDLE section. That is, the squelch circuit 12 outputs the low level as the value of the corrected data signal within the IDLE interval, regardless of the value of the data signal before correction, and before the correction, outside the IDLE interval (in the DATA interval). The data signal value is output as the corrected data signal value. For example, when the waveform of the data signal (time change of the input voltage v1) is as shown in FIG. 2A and the waveform of the IDLE detection signal is as shown in FIG. 2B, the squelch circuit 12 corrects the waveform.
  • the waveform of the data signal (time change of the output voltage v3) is as shown in FIG.
  • the data signal corrected by the squelch circuit 12 is input to the modulation driver 13.
  • the data signal corrected by the squelch circuit 12 is hereinafter referred to as “corrected data signal”.
  • the modulation driver 13 sucks the modulation current i1 having a magnitude corresponding to the value of the corrected data signal. More specifically, (1) if the value of the corrected data signal is low level, the modulation current i1 having a predetermined magnitude (IM [A]) is sucked, and (2) the value of the corrected data signal Is at the high level, the absorption of the modulation current i1 is stopped. For example, when the waveform of the corrected data signal is as shown in FIG. 2C, the temporal change in the magnitude of the modulation current i1 is as shown in FIG. A configuration example of the modulation driver 13 will be described later with reference to another drawing.
  • the auxiliary driver 14 identifies the IDLE section with reference to the IDLE detection signal.
  • the auxiliary driver 14 sucks in an auxiliary current i2 having a predetermined size (IS [A]) in the IDLE section.
  • IB is the magnitude of the modulation current i1 drawn by the modulation driver 13 in the IDLE section
  • IB is the magnitude of the bias current i3 output from the bias current source 15, (3 ) ⁇ is a positive constant.
  • the waveform of the IDLE detection signal is as shown in FIG. 2B
  • the temporal change in the magnitude of the auxiliary current i2 is as shown in FIG. 3B.
  • a configuration example of the auxiliary driver 14 will be described later with reference to another drawing.
  • the bias current source 15 discharges a bias current i3 having a predetermined magnitude (IB [A]).
  • the time change of the magnitude of the bias current i3 is as shown in FIG.
  • the bias current source 15 can be configured by a DC current source having one end connected to the power supply (voltage VDD) and the other end connected to the output terminal OUT. Another configuration example of the bias current source 15 will be described later with reference to another drawing.
  • the compensation current source 16 has a shortage of the bias current i3 when the sum of the magnitude of the auxiliary current i2 and the magnitude of the modulation current i1 (IM [A] in the IDLE section) exceeds the magnitude of the bias current i3.
  • the compensation current i4 that compensates for is discharged.
  • the compensation current source 16 may be configured by a diode (diode clamp) having an anode terminal connected to a clamp power supply (voltage Vcramp) and a cathode terminal connected to an output terminal OUT. It can.
  • a diode diode clamp
  • Vcramp clamp power supply
  • cathode terminal connected to an output terminal OUT.
  • the modulation driver 13, the auxiliary driver 14, the bias current source 15, the compensation current source 16, and the VCSEL 17 subtract the modulation current i1 from the sum of the bias current i3 and the compensation current i4.
  • the drive current i5 (i3 + i4) ⁇ i1-i2 obtained by subtracting the auxiliary current i2 is connected so as to flow into the VCSEL 17. Therefore, when the temporal changes in the magnitudes of the modulation current i1, the auxiliary current i2, the bias current i3, and the compensation current i4 are as shown in (a), (b), (c), and (d) of FIG.
  • the time change of the magnitude of the inflowing drive current i5 is as shown in FIG.
  • the magnitude of the drive current i5 flowing into the VCSEL 17 in the IDLE section can be set to 0 [A]. That is, the VCSEL 17 can be turned off in the IDLE section.
  • the auxiliary driver 14 is used to control the magnitude of the drive current i5 flowing into the VCSEL 17 in the IDLE section to 0 [A].
  • the delay time from the start point / end point of the IDLE section to the extinction / lighting of the VCSEL 17 is compared with the case where the VCSEL 17 is extinguished / lit by stopping / resuming the power supply to the modulation driver 13 and the bias current source 15.
  • the delay time from the start point / end point of the IDLE section to the extinction / lighting of the VCSEL 17 is 5 nsec or less. This is 1/6 or less of the delay time (30 nsec or more) when the VCSEL 17 is turned off / on by stopping / resuming the power supply to the modulation driver 13 and the bias current source 15.
  • a configuration is adopted in which the magnitude of the drive current i5 flowing into the VCSEL 17 in the IDLE section is set to 0 [A].
  • the present invention is not limited to this.
  • a configuration may be adopted in which the magnitude of the drive current i5 flowing into the VCSEL 17 in the IDLE section is made equal to or less than the threshold current (oscillation start current) of the VCSEL 17. Even in this case, the VCSEL 17 can be turned off (including a mode in which the light emission state is set to be low) in the IDLE section.
  • the VCSEL 17 can be reliably turned off in the IDLE section. This is because the magnitude IS of the auxiliary current i2 absorbed by the auxiliary driver 14 in the IDLE section is set so as to satisfy IM + IS> IB. Moreover, according to the optical transmitter 1 of the present embodiment, even if the sum of the modulation current i1 magnitude IM and the auxiliary current magnitude IS exceeds the bias current i3 in the IDLE section, the output terminal OUT Thus, there is no concern that the voltage drop of 2 mm occurs and the operation of the modulation driver 13 and the auxiliary driver 14 is hindered.
  • a configuration is adopted in which the magnitude IS of the auxiliary current i2 that the auxiliary driver 14 sucks in the IDLE section is set so as to satisfy IM + IS> IB.
  • FIG. 4 is a circuit diagram showing a configuration example of the IDLE detection circuit 11.
  • FIG. 5 is a waveform diagram of a voltage signal in each part of the IDLE detection circuit 11 shown in FIG.
  • the IDLE detection circuit 11 has a function of detecting a section in which the value of the data signal is included in a predetermined range between the high level and the low level.
  • the IDLE detection circuit 11 shown in FIG. 4 implements such a function by the first comparator Comp1, the second comparator Comp2, the AND gate AND1, and the low-pass filter LPF1.
  • the data signal is input in the positive phase to the non-inverting input terminal of the first comparator Comp1, and the reference voltage V0 is input to the inverting input terminal of the first comparator Comp1.
  • the first comparator Comp1 compares the value of the positive phase data signal with the reference voltage V0, and generates a voltage signal indicating the comparison result.
  • the reference voltage V0 is set to the lower limit value of the above range.
  • the waveform of the positive phase data signal is as shown in FIG. 5A, and the waveform of the voltage signal generated by the first comparator Comp1 is as shown in FIG. 5B.
  • the voltage signal generated by the first comparator Comp1 is input to the AND gate AND1.
  • the data signal is input in reverse phase to the non-inverting input terminal of the second comparator Comp2, and the reference voltage V0 is input to the inverting input terminal of the second comparator Comp2.
  • the second comparator Comp2 compares the value of the data signal having the opposite phase with the reference voltage V0, and generates a voltage signal indicating the comparison result.
  • the waveform of the negative phase data signal is as shown in FIG. 5C
  • the waveform of the voltage signal generated by the second comparator Comp2 is as shown in FIG. 5D.
  • the voltage signal generated by the second comparator Comp2 is input to the AND gate AND1.
  • the AND gate AND1 refers to the voltage signal generated by the first comparator Comp1 and the voltage signal generated by the second comparator Comp2, and compares the comparison result of the first comparator Comp1 and the second comparator Comp2. A voltage signal indicating a logical product with the comparison result is generated.
  • the waveform of the voltage signal generated by the AND gate AND1 is as shown in FIG.
  • the voltage signal generated by the AND gate AND1 is input to the low pass filter LPF1.
  • the low-pass filter LPF1 smoothes the voltage signal generated by the AND gate AND1. That is, noise at the time of logic switching included in the voltage signal generated by the AND gate AND1 is removed.
  • the waveform of the voltage signal smoothed by the low-pass filter LPF1 is as shown in FIG. That is, the voltage signal smoothed by the low-pass filter LPF1 is a voltage signal whose value is high level within the IDLE section (outside the DATA section) and whose value is low level outside the IDLE section.
  • the voltage signal smoothed by the low-pass filter LPF1 is output to the outside (squelch circuit 12 and auxiliary driver 14) as an IDLE detection signal.
  • the squelch circuit 12 and the auxiliary driver 14 may be configured to operate with reference to an IDLE detection signal that is at a high level within the IDLE interval, or with reference to an IDLE detection signal that is at a high level outside the IDLE interval. It can also be configured to operate.
  • the squelch circuit 12 and the auxiliary driver 14 are configured to operate with reference to the latter IDLE detection signal, for example, the following configuration may be employed. That is, a configuration may be adopted in which the IDLE detection signal output from the IDLE detection circuit 11 is input to the squelch circuit 12 and the auxiliary driver 14 via an inverting amplifier.
  • the IDLE section of the data signal input to the optical transmitter 1 can be accurately identified, and an IDLE detection signal having edges at the start and end points of the identified IDLE section can be generated at high speed.
  • An IDLE detection circuit 11 capable of performing the above can be realized.
  • latter stage of AND gate AND1 is employ
  • the structure of the IDLE detection circuit 11 is not limited to this. That is, when the operating frequency of the AND gate AND1 is slow and spike noise at the time of logic switching is not included in the voltage signal generated by the AND gate AND1, the AND gate AND1 may be omitted (the first gate described later). (Refer to the modified example).
  • a configuration in which each of the positive-phase data signal and the negative-phase data signal is compared with a single reference voltage V0 is employed, but the configuration of the IDLE detection circuit 11 is not limited to this.
  • the IDLE detection circuit 11 can also be realized by a peak hold circuit like the signal detection circuit described in Patent Document 5, for example.
  • the reference voltage in the comparator described in Patent Document 5 may be set to a value larger than the intermediate level of the data signal and smaller than the high level of the data signal.
  • the response speed of the IDLE detection circuit 11 decreases, and it becomes difficult to achieve the response speed required by standards such as SAS 2.0 and PCIe 3.0.
  • FIG. 6 is a circuit diagram showing a first configuration example of the modulation driver 13 and the auxiliary driver 14.
  • the modulation driver 13 can be composed of a pair of transistors (npn transistors) Tr1 and Tr2 and a direct current source DC1.
  • the transistor Tr1 has a collector terminal connected to the output point OUT, a base terminal connected to the input point IN1_N, and an emitter terminal connected to the emitter terminal of the transistor Tr2.
  • the transistor Tr2 has a collector terminal connected to the power supply (power supply voltage VDD), a base terminal connected to the input point IN1_P, and an emitter terminal connected to the emitter terminal of the transistor Tr1.
  • An intermediate point between the emitter terminal of the transistor Tr1 and the emitter terminal of the transistor Tr2 is grounded via the direct current source DC1.
  • the current value of the direct current source DC1 can be set from the outside.
  • the data signal is input in the positive phase to the input point IN1_P of the modulation driver 13, and the data signal is input in the reverse phase to the input point IN1_N of the modulation driver 13. If the value of the data signal is low level, the modulation driver 13 sucks the modulation current i1 having a predetermined magnitude (IM [A]) from the output point OUT, and (2) the value of the data signal is high level. If there is, the absorption of the modulation current i1 from the output point OUT is stopped.
  • IM [A] a predetermined magnitude
  • the auxiliary driver 14 can be composed of a pair of transistors (npn transistors) Tr3 and Tr4 and a direct current source DC2. Since the configuration of the auxiliary driver 14 is the same as the configuration of the modulation driver 13, the description thereof is omitted here.
  • the IDLE detection signal is input in reverse phase to the input point IN2_P of the auxiliary driver 14, and the IDLE detection signal is input in positive phase to the input point IN2_N of the auxiliary driver 14. At this time, if the value of the IDLE detection signal is high, the auxiliary driver 14 sucks the auxiliary current i2 having a predetermined magnitude (IS [A]) from the output point OUT, and (2) IDLE. If the value of the detection signal is low level, the absorption of the modulation current i1 from the output point OUT is stopped.
  • npn transistors are used as the transistors Tr1 to Tr4 constituting the modulation driver 13 and the auxiliary driver 14, but the present invention is not limited to this. That is, NMOS transistors may be used as the transistors Tr1 to Tr4 constituting the modulation driver 13 and the auxiliary driver 14.
  • FIG. 7 is a circuit diagram showing a second configuration example of the modulation driver 13 and the auxiliary driver 14.
  • the modulation driver 13 shown in FIG. 7 has the modulation driver 13 shown in FIG. 6 as a main driver, and a pre-driver that amplifies the data signal is added to the preceding stage.
  • the main driver converts the data signal amplified by the pre-driver into a current signal.
  • the differential amplifier circuit is a circuit for differentially amplifying data signals, and includes a pair of resistors R1 and R2, a pair of transistors (npn transistors) Tr9 and Tr10, and a direct current source DC7.
  • the transistor Tr9 has a collector terminal connected to the power supply (voltage VDD) via the resistor R1, a base terminal connected to the input point IN1_N, and an emitter terminal connected to the emitter terminal of the transistor Tr10.
  • the transistor Tr10 has a collector terminal connected to the power supply (voltage VDD) via the resistor R2, a base terminal connected to the input point IN1_P, and an emitter terminal connected to the emitter terminal of the transistor Tr9.
  • An intermediate point between the emitter terminal of the transistor Tr9 and the emitter terminal of the transistor Tr10 is grounded via a direct current source DC7.
  • the emitter follower circuit is a circuit for making the output impedance of the pre-driver lower than the input impedance of the main driver, and includes a pair of transistors (npn transistors) Tr5 and Tr6 and a pair of direct current sources DC3 and DC4. It is configured.
  • the transistor Tr5 has a collector terminal connected to the power supply (voltage VDD), a base terminal connected to one output point of the differential amplifier circuit (collector terminal of the transistor Tr9), and an emitter terminal grounded via the DC current source DC3.
  • the emitter voltage of the transistor Tr5 is input to the base terminal of the transistor Tr2 constituting the main driver as a positive-phase data signal.
  • the transistor Tr6 has a collector terminal connected to the power supply (voltage VDD), a base terminal connected to the other output point of the differential amplifier circuit (collector terminal of the transistor Tr10), and an emitter terminal connected via the direct current source DC4. Is grounded.
  • the emitter voltage of the transistor Tr6 is input to the base terminal of the transistor Tr1 constituting the main driver as a data signal of opposite phase.
  • the auxiliary driver 14 shown in FIG. 7 has the auxiliary driver 14 shown in FIG. 6 as a main driver, and a pre-driver that amplifies the IDLE detection signal is added to the preceding driver.
  • the main driver converts the IDLE detection signal amplified by the pre-driver into a current signal. Since the configuration of the pre-driver added to the auxiliary driver 14 is the same as the configuration of the pre-driver added to the modulation driver 13, the description thereof is omitted here.
  • npn transistors are used as the transistors Tr1 to Tr12 constituting the modulation driver 13 and the auxiliary driver 14, but the present invention is not limited to this. That is, NMOS transistors may be used as Tr1 to Tr12 constituting the modulation driver 13 and the auxiliary driver 14.
  • FIG. 8 is a circuit diagram showing a third configuration example of the modulation driver 13 and the auxiliary driver 14.
  • the modulation driver 13 shown in FIG. 8 is obtained by adding a stabilization circuit X1 that stabilizes the output voltage of the pre-driver to the modulation driver 13 shown in FIG.
  • the stabilization circuit X1 includes a transistor (PMOS transistor) M1 and a voltage drop amount control circuit that controls the voltage drop amount in the transistor M1 according to the output voltage of the pre-driver.
  • the source terminal of the transistor M1 is connected to the power supply (voltage VDD), and the drain terminal of the transistor M1 is connected to the collector terminals of the transistors Tr9 and Tr10 that constitute the differential amplifier circuit of the predriver via resistors R1 and R2. ing.
  • the transistor M1 functions as a voltage drop device with a variable voltage drop amount.
  • the voltage drop amount control circuit includes a pair of resistors R1 and R2 having the same resistance value and an operational amplifier OP1.
  • the resistors R1 and R2 are connected in series between the emitter terminals of the transistors Tr5 and Tr6 constituting the emitter follower circuit of the pre-driver. Further, the voltage at the intermediate point between the resistors R1 and R2 matches the average value of the emitter voltages of the transistors Tr5 and Tr6 (hereinafter referred to as “average emitter voltage”).
  • the non-inverting input terminal of the operational amplifier OP1 is connected to the intermediate point between the resistors R1 and R2.
  • the average emitter voltage of the transistors Tr5 and Tr6 is input to the non-inverting input terminal of the operational amplifier OP1.
  • a predetermined reference voltage V1 is input to the inverting input terminal of the operational amplifier OP1.
  • the output terminal of the operational amplifier OP1 is connected to the gate terminal of the transistor M1.
  • the stabilization circuit X1 When the output voltage of the pre-driver, that is, the average emitter voltage of the transistors Tr5 and Tr6 exceeds the reference voltage V1, the stabilization circuit X1 operates as follows. That is, the output voltage of the operational amplifier OP1 increases, and as a result, the gate voltage of the transistor M1 increases. As a result, the source-drain resistance of the transistor M1 increases, and as a result, the amount of voltage drop in the transistor M1 increases. As a result, the voltage applied to the pre-driver is reduced, and as a result, the output voltage of the pre-driver is lowered. This operation continues until the average emitter voltage of the transistors Tr5 and Tr6 matches the reference voltage V1.
  • the stabilization circuit X1 operates as follows. That is, the output voltage of the operational amplifier OP1 decreases, and as a result, the gate voltage of the transistor M1 increases. As a result, the resistance between the source and drain of the transistor M1 is reduced, and as a result, the amount of voltage drop in the transistor M1 is reduced. As a result, the voltage applied to the pre-driver increases, and as a result, the output voltage of the pre-driver increases. This operation continues until the average emitter voltage of the transistors Tr5 and Tr6 matches the reference voltage V1.
  • the output voltage of the predriver varies according to the fluctuation of the power supply voltage of the predriver, in order to prevent the operating conditions of each element constituting the main driver from breaking, strict conditions are imposed on the fluctuation range of the power supply voltage of the predriver. It is necessary to impose. If the stabilization circuit X1 is added, the output voltage of the predriver does not fluctuate according to the fluctuation of the power supply voltage of the predriver, so that it is not necessary to impose strict conditions on the fluctuation range of the power supply voltage of the predriver.
  • the auxiliary driver 14 shown in FIG. 8 is obtained by adding a stabilization circuit X2 for stabilizing the output voltage of the pre-driver to the auxiliary driver 14 shown in FIG. Since the configuration of the stabilization circuit X2 added to the auxiliary driver 14 is the same as the configuration of the stabilization circuit X1 added to the modulation driver 13, the description thereof is omitted here.
  • PMOS transistors are used as the transistors M1 and M2 constituting the stabilization circuits X1 and X2, but the present invention is not limited to this.
  • pnp transistors may be used as the transistors constituting the stabilization circuits X1 and X2.
  • FIG. 9 is a circuit diagram showing a first configuration example of the bias current source 15.
  • the bias current source 15 can be composed of a pair of transistors (PMOS transistors) M3 and M4 and a DC current source DC9.
  • the source terminal of the transistor M3 is connected to the power supply (voltage VDD).
  • the source terminal of the transistor M4 is connected to the power supply (voltage VDD), and the drain terminal of the transistor M4 is connected to the gate terminal of the transistor M4 and to the gate terminal of the transistor M3. That is, the transistors M3 and M4 form a current mirror circuit having the drain terminal of the transistor M4 as an input point and the drain terminal of the transistor M3 as an output point.
  • the sizes of the transistors M3 and M4 are set so that the current i3 flowing out from the output point of the current mirror circuit is N times the current i3 'flowing out from the input point of the current mirror circuit. ing. Therefore, if the DC current source DC9 that flows the current i3 'of IB / N [A] is connected to the input point of the current mirror circuit, the current i3 of IB [A] can be taken out from the output point of the current mirror circuit. it can.
  • PMOS transistors are used as the transistors M3 and M4 constituting the bias current source 15, but the present invention is not limited to this. That is, pnp transistors may be used as the transistors M3 and M4 constituting the bias current source 15. However, the types of the transistors M3 and M4 are matched. That is, when a PMOS transistor is used as the transistor M3, a PMOS transistor is used as the transistor M4. When a pnp transistor is used as the transistor M3, a pnp transistor is used as the transistor M4.
  • FIG. 10 is a circuit diagram showing a second configuration example of the bias current source 15.
  • the bias current source 15 can be composed of an operational amplifier OP3, a transistor (PMOS transistor) M5, a pair of resistors R5 and R6, and a direct current source DC10.
  • the non-inverting input terminal of the operational amplifier OP3 is connected to the power supply (voltage VDD) via the resistor R6.
  • the inverting input terminal of the operational amplifier OP3 is connected to the power supply (voltage VDD) via R5 and to the source terminal of the transistor M5.
  • the output terminal of the operational amplifier OP3 is connected to the gate terminal of the transistor M5. That is, the operational amplifier OP3, the transistor M5, and the resistors R5 and R6 constitute a current mirror circuit having the non-inverting input terminal of the operational amplifier OP3 as an input point and the drain terminal of the transistor M5 as an output point.
  • a PMOS transistor is used as the transistor M5 constituting the bias current source 15.
  • the present invention is not limited to this. That is, a pnp transistor may be used as the transistor M5 constituting the bias current source 15.
  • the optical transmitter 1 may include (1) only the bias current source 15 configured as shown in FIG. 9, or (2) only the bias current source 15 configured as shown in FIG. (3) Both the bias current source 15 configured as shown in FIG. 9 and the bias current source 15 configured as shown in FIG. 10 are provided, and which bias current source 15 is used. May be configured to be switchable.
  • Use of the bias current source 15 configured as shown in FIG. 9 is suitable for transmission of intermittent signals such as OOB signals defined in SAS 2.0.
  • the bias current source 15 configured as shown in FIG. 9 has a tendency that the current ratio tends to fluctuate with respect to the fluctuation of the power supply (voltage VDD), but is resistant to abrupt fluctuation of the bias voltage of the VCSEL, and from the IDLE section to the DATA.
  • the use of the bias current source 15 configured as shown in FIG. 10 is suitable for transmission of a continuous signal defined in the InfiniBand standard or the like.
  • the bias current source 15 configured as shown in FIG. 10 has a tendency that the current ratio does not easily fluctuate with respect to fluctuations in the power supply (voltage VDD), but is weak against sudden fluctuations in the bias voltage of the VCSEL, and IDLE. This is because the response time for the transition from the section to the DATA section is long. Therefore, by adopting a configuration in which the bias current source to be used is switched to the one suitable for the type of data signal to be transmitted, the optical transmitter 1 suitable for both intermittent signal transmission and continuous signal transmission can be realized. .
  • FIG. 11 is a circuit diagram showing a first configuration example of the compensation current source 16.
  • the compensation current source 16 can be configured by a transistor (npn transistor) Tr13.
  • the collector terminal of the transistor Tr13 is connected to a power supply (voltage VDD), and the base terminal of the transistor Tr13 is connected to a clamp power supply (voltage Vcramp).
  • a Pnpn transistor is used as the transistor Tr13 constituting the compensation current source 16, but the present invention is not limited to this. That is, an NMOS transistor may be used as the transistor Tr13 constituting the compensation current source 16.
  • FIG. 12 is a circuit diagram showing a second configuration of the compensation current source 16.
  • a compensation current source 16 shown in FIG. 12 is obtained by adding an operational amplifier OP4 to the compensation current source 16 shown in FIG.
  • a non-inverting input terminal and an output terminal are directly connected so as to constitute a voltage follower circuit.
  • the inverting input terminal of the operational amplifier OP4 is connected to the clamp power supply (voltage Vcramp), and the output terminal of the operational amplifier OP4 is connected to the base terminal of the transistor Tr13.
  • FIG. 25 is a circuit diagram showing a configuration of an IDLE detection circuit 61a according to this modification.
  • the IDLE detection circuit 61a includes a first comparator Comp1, a second comparator Comp2, and an AND gate AND1 as in the IDLE detection circuit 11 shown in FIG.
  • the operating frequency of the AND gate AND1 is set sufficiently low (for example, 1/10 or less of the operating frequency of the comparators Comp1 and Comp2) so that the generated voltage signal does not include spike noise at the time of logic switching. ing.
  • the low-pass filter LPF1 for removing spike noise at the time of logic switching is omitted.
  • the IDLE detection circuit 11 shown in FIG. 4 and the IDLE detection circuit 61a shown in FIG. 25 compare each of the value of the positive phase data signal and the value of the negative phase data signal with a single reference voltage V0.
  • a section included in a range where the signal value is not less than the lower limit value V0 and not more than the upper limit value 2 ⁇ Vcom ⁇ V0 is detected as an IDLE section (Vcom represents a common voltage of the data signal).
  • Vcom represents a common voltage of the data signal.
  • this method has the common advantage that a single reference voltage source can be used at the cost of not being able to set the lower and upper limits of the range independently.
  • the IDLE detection circuit 61a shown in FIG. 25 has the further advantage that the circuit configuration can be simplified compared to the IDLE detection circuit 11a shown in FIG. 4 because the low-pass filter LPF1 is omitted.
  • FIG. 26 is a circuit diagram showing a configuration of an IDLE detection circuit 61b according to this modification.
  • FIG. 27 is a waveform diagram of a voltage signal in each part of the IDLE detection circuit 61b according to this modification.
  • the IDLE detection circuit 61b according to the present modification includes a first comparator Comp1, a second comparator Comp2, an AND gate AND1, and a low-pass filter LPF1, similarly to the IDLE detection circuit 11. .
  • the IDLE detection circuit 61b according to this modification is different from the IDLE detection circuit 11 in the following two points.
  • the first difference is that the data signal is input in the same phase (in the positive phase in this modification) to each of the non-inverting input terminal of the first comparator Comp1 and the inverting input terminal of the second comparator Comp2. is there. That is, a positive-phase data signal having a waveform illustrated in FIG. 27A is input to each of the two comparators Comp1 and Comp2.
  • the second difference is that different reference voltages V0a and V0b are input to the inverting input terminal of the first comparator Comp1 and the non-inverting input terminal of the second comparator Comp2.
  • the data signal is input in the positive phase to the non-inverting input terminal of the first comparator Comp1, and the reference voltage V0a is input to the inverting input terminal of the first comparator Comp1.
  • the first comparator Comp1 compares the value of the positive-phase data signal with the reference voltage V0a and generates a voltage signal indicating the comparison result.
  • the reference voltage V0a is set to a lower limit value of a predetermined range between the high level and the low level of the data signal.
  • the waveform of the positive phase data signal is as shown in FIG. 27B, and the waveform of the voltage signal generated by the first comparator Comp1 is as shown in FIG. 27C.
  • the voltage signal generated by the first comparator Comp1 is input to the AND gate AND1.
  • the data signal is input in the positive phase to the inverting input terminal of the second comparator Comp2, and the reference voltage V0b is input to the non-inverting input terminal of the second comparator Comp2.
  • the second comparator Comp2 compares the value of the positive-phase data signal with the reference voltage V0b and generates a voltage signal indicating the comparison result.
  • the reference voltage V0b is set to the upper limit value of the above range.
  • the waveform of the positive phase data signal is as shown in (d) of FIG. 27, and the waveform of the voltage signal generated by the second comparator Comp2 is as shown in (e) of FIG.
  • the voltage signal generated by the second comparator Comp2 is input to the AND gate AND1.
  • the AND gate AND1 refers to the voltage signal generated by the first comparator Comp1 and the voltage signal generated by the second comparator Comp2, and compares the comparison result of the first comparator Comp1 and the second comparator Comp2. A voltage signal indicating a logical product with the comparison result is generated.
  • the waveform of the voltage signal generated by the AND gate AND1 is as shown in (f) of FIG.
  • the voltage signal generated by the AND gate AND1 is input to the low pass filter LPF1.
  • the low-pass filter LPF1 smoothes the voltage signal generated by the AND gate AND1. That is, noise at the time of logic switching included in the voltage signal generated by the AND gate AND1 is removed.
  • the waveform of the voltage signal smoothed by the low-pass filter LPF1 is as shown in (g) of FIG. That is, the voltage signal smoothed by the low-pass filter LPF1 is a voltage signal whose value is high level within the IDLE section (outside the DATA section) and whose value is low level outside the IDLE section.
  • the voltage signal smoothed by the low-pass filter LPF1 is output to the outside (squelch circuit 12 and auxiliary driver 14) as an IDLE detection signal.
  • a positive phase data signal is input to each of the non-inverting input terminal of the first comparator Comp1 and the inverting input terminal of the second comparator Comp2, but a reverse phase data signal is input. Also good. Even in this case, it is possible to obtain a voltage signal whose value is at a high level within the IDLE interval and whose value is at a low level outside the IDLE interval.
  • the squelch circuit 12 and the auxiliary driver 14 may be configured to operate with reference to an IDLE detection signal that is at a high level within the IDLE interval, or with reference to an IDLE detection signal that is at a high level outside the IDLE interval. It can also be configured to operate.
  • the squelch circuit 12 and the auxiliary driver 14 are configured to operate with reference to the latter IDLE detection signal, for example, the following configuration may be employed. That is, a configuration may be adopted in which the IDLE detection signal output from the IDLE detection circuit 61b is input to the squelch circuit 12 and the auxiliary driver 14 via an inverting amplifier.
  • FIG. 28 is a circuit diagram showing a configuration of an IDLE detection circuit 61c according to this modification.
  • the IDLE detection circuit 61c includes a first comparator Comp1, a second comparator Comp2, and an AND gate AND1 like the IDLE detection circuit 61b shown in FIG.
  • the operating frequency of the AND gate AND1 is set sufficiently low (for example, 1/10 or less of the operating frequency of the comparators Comp1 and Comp2) so that the generated voltage signal does not include spike noise at the time of logic switching. ing.
  • the low-pass filter LPF1 for removing spike noise at the time of logic switching is omitted.
  • the IDLE detection circuit 61b shown in FIG. 26 and the IDLE detection circuit 61c shown in FIG. 28 compare the positive phase data signal with each of the two reference voltages V0a and V0b, so that the value of the data signal is equal to or higher than the lower limit value V0a.
  • a section included in a range that is equal to or lower than the upper limit value V0b is detected as an IDLE section.
  • the IDLE interval can be reliably detected regardless of the difference between the intermediate level of the data signal and the common voltage of the data signal.
  • This method has the advantage that the lower limit value and the upper limit value of the range can be set independently as a price for not being able to use only one reference voltage source.
  • the IDLE detection circuit 61c shown in FIG. 28 has the further advantage that the circuit configuration can be simplified compared to the IDLE detection circuit 61b shown in FIG. 26 because the low-pass filter LPF1 is omitted.
  • FIG. 29A is a circuit diagram of a comparator Comp3 that can be replaced with the low-pass filter LPF1
  • FIGS. 29B to 29D are waveform diagrams of voltage signals in respective parts of the comparator Comp3.
  • the comparator Comp3 smoothes the voltage signal generated by the AND gate AND1 similarly to the low-pass filter LPF1. That is, it has a function of removing noise at the time of logic switching included in the voltage signal generated by the AND gate AND1.
  • a voltage signal generated by the AND gate AND1 and having a waveform as shown in FIG. 29B is input to the non-inverting input terminal of the comparator Comp3.
  • This voltage signal includes noise at the time of logic switching.
  • the reference voltage V3 is input to the inverting input terminal of the third comparator Comp3.
  • the comparator Comp3 compares the voltage signal generated by the AND gate AND1 with the reference voltage V3, and generates a voltage signal indicating the comparison result.
  • the reference voltage V3 is set to be lower than the output voltage of the AND gate AND1 at the high level and higher than the noise peak voltage at the time of logic switching.
  • the voltage signal generated by the comparator Comp3 is as shown in FIG. That is, the output signal of the comparator Comp3 is a voltage signal whose value becomes high level within the IDLE interval (outside the DATA interval) and becomes low level outside the IDLE interval, like the output signal of the low pass filter LPF1.
  • the optical transmitter 1 can be suitably used as a connector for an active optical cable that performs serial communication according to PCIe.
  • the optical transmitter according to the present embodiment is assumed to be used as an ONU (Optical Network Unit) constituting a PON (Passive Optical Network). For this reason, a data signal and a BEN (Burst ENable) signal are input to the optical transmitter according to the present embodiment.
  • the data signal is a binary voltage signal and includes an Enable section and a Disable section. The value of the data signal takes a high level or a low level depending on the data to be transmitted in the Enable section, and alternately takes a high level and a low level in the Disable section regardless of the data to be transmitted (data to be transmitted). Is superimposed on the Enable section of the data signal).
  • the BEN signal is a binary voltage signal indicating the Enable section.
  • the value of the BEN signal continues to take a high level during the Enable section and continues to take a low level during the Disable section.
  • the light emitting element included in the optical transmitter according to the present embodiment is a DFB-LD (DistributedDisFeedback Laser Diode).
  • the optical transmitter according to the present embodiment converts the data signal into an optical signal by controlling the magnitude of the drive current flowing out from the DFB-LD via the cathode terminal.
  • the present embodiment is not limited to DFB-LD, and can be applied to all light-emitting elements capable of controlling the light emission amount by changing the magnitude of the driving current that flows out.
  • FIG. 13 is a block diagram showing a configuration of the optical transmitter 2.
  • the optical transmitter 2 includes a squelch circuit 22, a modulation driver 23, an auxiliary driver 24, a bias current source 25, a compensation current source 26, and a DFB-LD 27, as shown in FIG.
  • the squelch circuit 22, the modulation driver 23, the auxiliary driver 24, the bias current source 25, and the compensation current source 26 are mounted on a single integrated circuit (“TX-IC” in FIG. 13).
  • TX-IC integrated circuit
  • the present invention is not limited to this. That is, the optical transmitter 2 may be realized by a discrete circuit in which the squelch circuit 22, the modulation driver 23, the auxiliary driver 24, the bias current source 25, and the compensation current source 26 are individually mounted.
  • the squelch circuit 22 specifies the Disable section with reference to the BEN signal. Further, the squelch circuit 22 corrects the value of the data signal to a low level in the disable section. That is, the squelch circuit 22 outputs the low level as the value of the corrected data signal within the Disable interval, regardless of the value of the data signal before correction, and before the correction, outside the Disable interval (within the Enable interval). The data signal value is output as the corrected data signal value.
  • the waveform of the data signal time change of the input voltage v1
  • the waveform of the BEN signal time change of the input voltage v2
  • the waveform of the data signal corrected by the circuit 22 (time change of the output voltage v3) is as shown in FIG.
  • the data signal corrected by the squelch circuit 22 is input to the modulation driver 23.
  • the data signal corrected by the squelch circuit 22 is hereinafter referred to as “corrected data signal”.
  • the modulation driver 23 sucks the modulation current i1 having a magnitude corresponding to the value of the corrected data signal. More specifically, (1) if the value of the corrected data signal is at a high level, the modulation current i1 having a predetermined magnitude (IM [A]) is sucked, and (2) the value of the corrected data signal is If is low level, the absorption of the modulation current i1 is stopped. For example, when the waveform of the corrected data signal is as shown in FIG. 14C, the temporal change in the magnitude of the modulation current i1 is as shown in FIG. 15A.
  • the configuration of the modulation driver 23 is the same as that of the modulation driver 13 provided in the optical transmitter 1 according to the first embodiment.
  • the auxiliary driver 24 refers to the BEN signal and identifies the Disable section.
  • the auxiliary driver 24 discharges an auxiliary current i2 having a predetermined magnitude (IS [A]) in the Disable section.
  • Is set For example, when the waveform of the BEN signal is as shown in FIG. 14B, the temporal change in the magnitude of the auxiliary current i2 is as shown in FIG. 15B.
  • a configuration example of the auxiliary driver 24 will be described later with reference to another drawing.
  • the bias current source 25 sucks a bias current i3 having a predetermined magnitude (IB [A]).
  • the time change of the magnitude of the bias current i3 is as shown in FIG.
  • the bias current source 25 can be constituted by a DC current source having one end connected to the output terminal OUT and the other end grounded. Another configuration example of the bias current source 25 will be described later with reference to another drawing.
  • the compensation current source 26 When the difference obtained by subtracting the magnitude of the modulation current i1 (0 [A] in the disable period) from the magnitude of the auxiliary current i2 exceeds the magnitude of the bias current i3, the compensation current source 26 is short of the bias current i3. Is compensated for.
  • the temporal change in the magnitudes of the modulation current i1, the auxiliary current i2, and the bias current i3 are as shown in FIGS. 15A, 15B, and 15C, the temporal change in the magnitude of the compensation current i4 is It becomes like (d) of FIG.
  • the compensation current source 26 can be configured by a diode (diode clamp) whose anode terminal is connected to the output terminal OUT and whose cathode terminal is grounded, as shown in FIG. 13, for example.
  • the compensation current source 26 shown in FIG. 13 sucks the compensation current i4 from the output terminal OUT when the anode-cathode voltage of the diode exceeds the threshold voltage Vth, that is, when the voltage at the output terminal OUT exceeds the threshold voltage Vth.
  • Another configuration example of the compensation current source 26 will be described later with reference to another drawing.
  • the modulation driver 23, the auxiliary driver 24, the bias current source 25, the compensation current source 26, and the DFB-LD 27 modulate to the sum (i3 + i4) of the bias current i3 and the compensation current i4.
  • the drive current i5 (i3 + i4) + i1-i2 obtained by adding the current i1 and further subtracting the auxiliary current i2 is connected so as to flow out of the DFB-LD27. Therefore, if the time changes in the magnitudes of the modulation current i1, the auxiliary current i2, the bias current i3, and the compensation current i4 are as shown in FIGS. 15A, 15B, 15C, and 15D, DFB ⁇ The time change of the magnitude of the drive current i5 flowing out from the LD 27 is as shown in FIG.
  • the magnitude of the drive current i5 flowing out from the DFB-LD 27 in the Disable section can be set to 0 [A]. That is, the DFB-LD 27 can be turned off in the Disable section.
  • the auxiliary driver 24 is used to control the drive current i5 flowing out from the DFB-LD 27 to 0 [A] in the disable section.
  • the delay time from the start point / end point of the Disable section to the turn-off / light-on of the DFB-LD 27 can be shortened as compared with the case where the DFB-LD 27 is turned off / light-up by the cutoff / release of the bias current.
  • a configuration is adopted in which the magnitude of the drive current i5 flowing out from the DFB-LD 27 in the Disable section is set to 0 [A].
  • the present invention is not limited to this. . That is, a configuration may be adopted in which the magnitude of the drive current i5 flowing out from the DFB-LD 27 in the disable section is equal to or less than the threshold current (oscillation start current) of the DFB-LD 27. Even in this case, it is possible to turn off the DFB-LD 27 (including a mode in which the light emission state is set) in the disable section.
  • the DFB-LD 27 can be surely turned off in the Disable section. This is because the magnitude IS of the auxiliary current i2 discharged by the auxiliary driver 24 in the disable section is set to satisfy IS> IB. Moreover, according to the optical transmitter 2 according to the present embodiment, even if the magnitude IS of the auxiliary current i2 exceeds the magnitude of the bias current i3 in the disable period, a voltage drop occurs at the output terminal OUT, and the modulation driver 23 and There is no concern of hindering the operation of the auxiliary driver 24. This is because the shortage of the bias current i3 is compensated by the compensation current i4 discharged from the compensation current source 26 when the magnitude IS of the auxiliary current i2 exceeds the magnitude IB of the bias current i3.
  • a configuration is adopted in which the magnitude IS of the auxiliary current i2 that the auxiliary driver 24 draws in the Disable section is set to satisfy IS> IB.
  • the present invention is limited to this. It is not a thing.
  • the magnitude of the drive current i5 flowing out from the DFB-LD 27 in the Disable section can be set to 0 [A]. In this case, the shortage of the bias current i3 in the disable section does not occur, so that the compensation current source 26 can be omitted.
  • FIG. 16 is a circuit diagram illustrating a configuration example of the auxiliary driver 24.
  • the auxiliary driver 24 can be composed of a pair of transistors (pnp transistors) Tr21 and Tr22 and a direct current source DC21.
  • the transistor Tr21 has a collector terminal grounded, a base terminal connected to the input point IN_N, and an emitter terminal connected to the emitter terminal of the transistor Tr22.
  • the transistor Tr22 has a collector terminal connected to the output point OUT, a base terminal connected to the input point IN_P, and an emitter terminal connected to the emitter terminal of the transistor Tr21.
  • An intermediate point between the emitter terminal of the transistor Tr21 and the emitter terminal of the transistor Tr22 is connected to a power supply (voltage VDD) via a direct current source DC21.
  • the magnitude of the current flowing through the direct current source DC21 can be set from the outside.
  • the BEN signal is input in the positive phase to the input point IN_P of the auxiliary driver 24, and the BEN signal is input in the reverse phase to the input point IN_N of the modulation driver 13. If the value of the BEN signal is low level, the auxiliary driver 24 sucks the auxiliary current i2 having a predetermined magnitude (IS [A]) from the output point OUT, and if the value of the BEN signal is high level, The suction of the auxiliary current i2 from the output point OUT is suspended.
  • a predetermined magnitude IS [A]
  • pnp transistors are used as the transistors Tr21 and Tr22 constituting the auxiliary driver 24, but the present invention is not limited to this. That is, PMOS transistors may be used as the transistors Tr21 and Tr22 constituting the auxiliary driver 24.
  • FIG. 17 is a circuit diagram showing a first configuration example of the bias current source 15.
  • the bias current source 25 can be composed of a pair of transistors (npn transistors) Tr23 and Tr24 and a DC current source DC22.
  • the emitter terminal of the transistor Tr23 is grounded.
  • the base terminal of the transistor Tr23 is connected to the collector terminal of the transistor Tr23 and to the base terminal of the transistor Tr24.
  • the emitter terminal of the transistor Tr24 is grounded. That is, the transistors Tr34 and Tr24 constitute a current mirror circuit having the collector terminal of the transistor Tr23 as an input point and the collector terminal of the transistor Tr24 as an output point.
  • the sizes of the transistors Tr23 and Tr24 are set so that the magnitude of the current i3 flowing into the output point of the current mirror circuit is N times the magnitude of the current i3 ′ flowing into the input point of the current mirror circuit. ing. Therefore, if the DC current source DC22 that supplies the current i3 ′ of IB / N [A] is connected to the input point of the current mirror circuit, the current i3 of IB [A] can be extracted from the output point of the current mirror circuit. it can.
  • npn transistors are used as the transistors Tr23 and Tr24 constituting the bias current source 25, but the present invention is not limited to this. That is, NMOS transistors may be used as the transistors Tr23 and Tr24 constituting the bias current source 25.
  • FIG. 18 is a circuit diagram showing a first configuration example of the compensation current source 26.
  • the compensation current source 26 includes a voltage source VS21 that generates a predetermined voltage V0, a diode having an anode terminal connected to the output terminal OUT, and a cathode terminal grounded via the voltage source VS21. D21.
  • the compensation current source 26 shown in FIG. 18 sucks the compensation current i4 from the output terminal OUT when the anode-cathode voltage of the diode D21 exceeds the threshold voltage Vth, that is, when the voltage at the output terminal OUT exceeds V0 + Vth.
  • FIG. 19 is a circuit diagram showing a second configuration example of the compensation current source 26.
  • the compensation current source 26 includes a voltage source VS22 that generates a predetermined voltage V0, a collector terminal connected to the output terminal OUT, an emitter terminal grounded via the voltage source VS22, and a base A transistor (npn transistor) Tr25 whose terminal is short-circuited to its collector terminal can be used.
  • the compensation current source 26 shown in FIG. 19 sucks the compensation current i4 from the output terminal OUT when the base-emitter voltage of the transistor Tr25 exceeds the threshold voltage Vth, that is, when the voltage at the output terminal OUT exceeds V0 + Vth.
  • an npn transistor is used as the transistor Tr25 constituting the compensation current source 26, but the present invention is not limited to this. That is, an NMOS transistor may be used as the transistor Tr25 constituting the compensation current source 26.
  • FIG. 20 is a circuit diagram showing a third configuration example of the compensation current source 26.
  • the compensation current source 26 includes (1) a voltage source VS23 that generates a predetermined voltage V0, and (2) an inverting input terminal that is grounded via the voltage source VS23, An operational amplifier OP21 short-circuited to its own output terminal; and (3) a transistor (PMONS transistor) M21 having a drain terminal connected to the output terminal OUT, a source terminal grounded, and a base terminal connected to the output terminal of the operational amplifier OP21.
  • the operational amplifier OP21 constitutes a voltage follower circuit, the gate voltage of the transistor M21 matches the voltage V0 generated by the voltage source VS23. 20 compensates for the compensation current i4 from the output terminal OUT when the gate-source voltage of the transistor M21 exceeds the threshold voltage Vth, that is, when the voltage at the output terminal OUT exceeds the voltage V0 + Vth.
  • a PMOS transistor is used as the transistor M21 constituting the compensation current source 26, but the present invention is not limited to this. That is, a pnp transistor may be used as the transistor M21 constituting the compensation current source 26.
  • the optical transmitter 1 according to the first embodiment replaces the IDLE section detection circuit 11 with an input terminal IN2, thereby performing PON similarly to the optical transmitter 2 according to the second embodiment. It can be used as a constituent ONU.
  • the BEN signal is input to the squelch circuit 12 and the auxiliary driver 14 via the input terminal IN2.
  • a VCSEL is used as a light source, but the present invention is not limited to this. That is, any light source can be used as the light source in the optical transmitter 1 according to the first embodiment as long as the light emission amount can be changed by changing the inflowing drive current. it can. The same applies to the modification shown in FIG.
  • the optical transmitter 2 according to the second embodiment is similar to the optical transmitter 1 according to the first embodiment by replacing the input terminal IN2 with an IDLE section detection circuit 21 as shown in FIG. It can be used as a connector for an active optical cable.
  • the function and configuration of the IDLE section detection circuit 21 are the same as the function and configuration of the IDLE section detection circuit 11 provided in the optical transmitter 1 according to the first embodiment.
  • the data signal is input to the IDLE section detection circuit 21, and the IDLE detection signal generated by the IDLE section detection circuit 21 is input to the squelch circuit 22 and the auxiliary driver 24.
  • the DFB-LD is used as the light source, but the present invention is not limited to this. That is, any light source can be used as the light source in the optical transmitter 2 according to the second embodiment as long as the light emission amount can be changed by changing the driving current that flows out. it can.
  • FP-LD Fabry Perot Laser Diode
  • FP-LD Fabry Perot Laser Diode
  • the optical transmitter includes the modulation driver that sucks the modulation current according to the data signal, the auxiliary driver that sucks or discharges the auxiliary current in the no-signal section, the bias current, and the modulation current.
  • a light emitting element in which a driving current obtained by subtracting the auxiliary current from the difference or sum of the current flows in or out, and the magnitude of the auxiliary current is the threshold current of the light emitting element in the non-signal period It is set so that it may become the following.
  • the optical transmission method includes a suction step for sucking a modulation current according to a data signal, a suction / discharge step for sucking or discharging an auxiliary current in a no-signal section, and the bias current and the modulation current.
  • a suction step for sucking a modulation current according to a data signal
  • a suction / discharge step for sucking or discharging an auxiliary current in a no-signal section
  • the bias current and the modulation current included in the optical transmission method.
  • an inflow / outflow process in which a driving current obtained by subtracting the auxiliary current from the difference or sum is input to or output from the light emitting element.
  • the magnitude of the auxiliary current is determined by the magnitude of the driving current in the non-signal section It is set so that it may become below the threshold current of an element.
  • the auxiliary driver can realize the control so that the magnitude of the drive current in the no-signal section is equal to or less than the threshold current of the light emitting element. For this reason, compared with a conventional optical transmitter that realizes this control by stopping the power supply to the modulation driver and the bias current source, until the value of the optical signal becomes off-level after the no-signal interval starts. The delay can be shortened.
  • the auxiliary driver sucks the auxiliary current in the no-signal interval, and the light emitting element subtracts the auxiliary current from the difference between the bias current and the modulation current.
  • the magnitude of the auxiliary current is set such that the sum of the magnitude of the modulation current in the no-signal interval is equal to or greater than the magnitude of the bias current. It is preferable.
  • an optical transmitter that uses a light emitting element that can control the amount of light emission by changing the magnitude of an inflowing drive current as a light source, after the no-signal interval starts, The delay until the value reaches the off level can be shortened.
  • the magnitude of the auxiliary current is set so that the sum of the magnitude of the modulation current in the no-signal interval is larger than the magnitude of the bias current.
  • the transmitter further includes a compensation current source for discharging a compensation current that compensates for the shortage of the bias current when the sum of the magnitude of the modulation current and the magnitude of the auxiliary current exceeds the magnitude of the bias current. Is preferable.
  • the magnitude of the auxiliary current since the magnitude of the auxiliary current is set as described above, the magnitude of the drive current flowing into the light emitting element in the non-signal period is surely equal to or less than the threshold current of the light emitting element, for example, 0 [A] can be set.
  • the shortage of the bias current is compensated by the compensation current, even if the magnitude of the auxiliary current is set as described above, the operation of the modulation driver and the auxiliary driver is hindered in the non-signal period. There is no concern to come.
  • the data signal includes a DATA section in which a value takes a high level or a low level and an IDLE section in which the value continues to take an intermediate level, and the no-signal section is the IDLE section. Is preferable.
  • the delay from the start of the IDLE interval to the value of the optical signal can be shortened.
  • the auxiliary driver draws the auxiliary current according to a pre-driver that amplifies the IDLE detection signal indicating the IDLE section and the value of the IDLE detection signal amplified by the pre-driver. And a main driver for switching whether or not.
  • the amplitude of the IDLE detection signal input to the main driver (potential difference between high level and low level) is set to a predetermined level. It may need to be sized. According to the above configuration, the amplitude of the IDLE detection signal input to the main driver can be set to a predetermined value by the pre-driver. Therefore, the amplitude of the current signal output from the main driver can be set to a predetermined level without distorting the current signal.
  • the auxiliary driver includes a voltage drop inserted between a power source and the pre-driver, and a voltage of the voltage drop according to the magnitude of the output voltage of the pre-driver. It is preferable to further include a control circuit that controls the descending amount.
  • the auxiliary driver discharges the auxiliary current in the no-signal interval, and the light emitting element subtracts the auxiliary current from the sum of the bias current and the modulation current. It is preferable that the driving current flows out, and the auxiliary current is set to be larger than the bias current.
  • the optical signal is transmitted after the no-signal interval starts.
  • the delay until the value reaches the off level can be shortened.
  • the magnitude of the auxiliary current is set larger than the magnitude of the bias current, and the optical transmitter is configured such that the magnitude of the auxiliary current is the magnitude of the bias current. It is preferable to further include a compensation current source for discharging a compensation current that compensates for the shortage of the bias current.
  • the magnitude of the auxiliary current since the magnitude of the auxiliary current is set as described above, the magnitude of the drive current flowing out from the light emitting element in the non-signal period is surely equal to or less than the threshold current of the light emitting element, for example, 0 [ A].
  • the compensation current since the shortage of the bias current is compensated by the compensation current, even if the magnitude of the auxiliary current is set as described above, the operation of the modulation driver and the auxiliary driver is hindered in the non-signal period. There is no concern to come.
  • a BEN signal indicating an enable section and a disable section is input to the optical transmitter, and the no-signal section is the disable section.
  • the auxiliary driver switches whether to draw the auxiliary current according to the value of the BEN signal.
  • the delay from the start of the Disable period until the value of the optical signal becomes the off level can be shortened.
  • An active optical cable including a cable containing an optical fiber and a pair of connectors provided at both ends of the cable, wherein one or both of the pair of connectors includes the transmitter.
  • Optical cables are also included in the scope of the present invention.
  • an ONU Optical Network Unit
  • PON Passive Optical Network
  • the present invention can be suitably used for an optical transmitter that transmits a data signal including an OOB pattern or the like.
  • the present invention contributes to the realization of an optical transmitter conforming to a communication standard premised on the use of a metal cable such as SAS 2.0 or PCIe 3.0.
  • it can be suitably used as an ONU constituting a PON.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Communication System (AREA)
  • Semiconductor Lasers (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un émetteur optique (1) pourvu d'un pilote de modulation (13) qui tire un courant modulé (i1) correspondant à un signal de données, un pilote auxiliaire (14) qui tire un courant auxiliaire (i2) pendant des segments sans signal, et un laser VCSEL (17) qui applique un courant d'attaque (i5) d'entrée calculé par la soustraction du courant auxiliaire (i2) de la différence entre un courant de polarisation (i3) et le courant de modulation (i1).
PCT/JP2015/078959 2014-10-15 2015-10-13 Émetteur optique, câble optique actif, unité de réseau optique et procédé de transmission optique WO2016060134A1 (fr)

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