WO2016060011A1 - メモリセルおよび不揮発性半導体記憶装置 - Google Patents
メモリセルおよび不揮発性半導体記憶装置 Download PDFInfo
- Publication number
- WO2016060011A1 WO2016060011A1 PCT/JP2015/078333 JP2015078333W WO2016060011A1 WO 2016060011 A1 WO2016060011 A1 WO 2016060011A1 JP 2015078333 W JP2015078333 W JP 2015078333W WO 2016060011 A1 WO2016060011 A1 WO 2016060011A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- selection gate
- gate structure
- insulating film
- gate electrode
- Prior art date
Links
- 238000003860 storage Methods 0.000 title claims description 129
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 230000000694 effects Effects 0.000 claims abstract description 15
- 230000002093 peripheral effect Effects 0.000 claims abstract description 15
- 230000005669 field effect Effects 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims description 48
- 239000012535 impurity Substances 0.000 claims description 26
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 239000011159 matrix material Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 238000009825 accumulation Methods 0.000 abstract description 11
- 230000009467 reduction Effects 0.000 abstract description 4
- 230000005641 tunneling Effects 0.000 abstract 1
- 101100081899 Arabidopsis thaliana OST48 gene Proteins 0.000 description 15
- 230000000052 comparative effect Effects 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
Definitions
- the present invention relates to a memory cell and a nonvolatile semiconductor memory device.
- Patent Document 1 discloses a memory cell in which a memory gate structure is disposed between two select gate structures (see FIG. 16 in Patent Document 1).
- this memory cell includes a drain region to which a bit line is connected and a source region to which a source line is connected.
- One select gate structure is formed on the memory well from the drain region toward the source region.
- a memory gate structure and another selection gate structure are arranged and formed in order.
- a charge storage layer is provided in the memory gate structure, and data is written by injecting charges into the charge storage layer, or charges in the charge storage layer are extracted. Thus, data can be erased.
- a low bit voltage from the bit line is applied while the voltage is blocked by another selection gate structure connected to the source line. This is applied to the channel layer of the memory gate structure through the select gate structure.
- a high memory gate voltage is applied to the memory gate electrode in the memory gate structure, and charges can be injected into the charge storage layer by a quantum tunnel effect caused by a voltage difference between the bit voltage and the memory gate voltage.
- a memory gate line to which a high memory gate voltage is applied is shared by a plurality of memory cells. Therefore, when a high memory gate voltage is applied to the memory gate line in order to inject charge into the charge storage layer of one memory cell, the charge is stored in the charge storage layer in other memory cells sharing the memory gate line. Even when the implantation is not performed, a high memory gate voltage is applied to the memory gate electrode.
- the voltage application to the channel layer is blocked by another selection gate structure connected to the source line, and one selection gate structure A high bit voltage from the bit line is applied to the channel layer of the memory gate structure.
- a high bit voltage is applied to the channel layer, so that the voltage difference between the memory gate electrode and the channel layer is small. As a result, no charge can be injected into the charge storage layer without the quantum tunnel effect.
- the present invention has been made in consideration of the above points, and an object thereof is to propose a memory cell and a non-volatile semiconductor memory device that can realize a higher speed operation than before and can reduce the area of a peripheral circuit. To do.
- a memory cell of the present invention includes a drain region formed on the surface of a memory well and connected to a bit line, a source region formed on the surface of the memory well and connected to a source line, and the drain A memory gate structure formed between a source region and a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode stacked in this order on the memory well; and the drain region And a first select gate electrode is formed on the memory well between the memory gate structures via a first select gate insulating film, and one side wall spacer is provided on one side wall of the memory gate structure.
- a first select gate structure adjacent via the second select on the memory well between the source region and the memory gate structure A second select gate structure having a configuration in which a second select gate electrode is formed through a gate insulating film and adjacent to the other side wall of the memory gate structure through another side wall spacer; Even if a charge storage gate voltage necessary for injecting charges into the charge storage layer by the quantum tunnel effect is applied to the memory gate electrode, and a channel layer is formed on the memory well surface facing the memory gate electrode, The first selection gate structure cuts off the electrical connection between the drain region and the channel layer, and the second selection gate structure cuts off the electrical connection between the source region and the channel layer.
- a depletion layer is formed so as to surround the channel layer whose channel potential has increased based on the charge storage gate voltage, and the memory gate electrode and A channel from the channel layer to the first select gate insulating film and the second select gate insulating film by the depletion layer while reducing a voltage difference between the channel layers and preventing charge injection into the charge storage layer. It is characterized by preventing the potential from reaching.
- the memory cell of the present invention includes a drain region formed on the surface of the memory well and connected to the bit line, a source region formed on the surface of the memory well and connected to the source line, the drain region and the source A memory gate structure formed between the regions, in which a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode are sequentially stacked on the memory well; and the drain region and the memory gate A first selection gate electrode is formed on the memory well between the structures via a first selection gate insulating film, and is adjacent to one side wall of the memory gate structure via one side wall spacer.
- the first select gate structure and a second select gate insulating film on the memory well between the source region and the memory gate structure.
- a second select gate structure adjacent to the other side wall of the memory gate structure via another side wall spacer, the memory gate structure having a configuration in which a second select gate electrode is formed.
- the charge storage layer is formed only in a region where the memory gate electrode and the memory well face each other, and the one side wall spacer between the memory gate structure and the first selection gate structure, The charge storage layer is not formed on the other side wall spacer between the memory gate structure and the second selection gate structure, and the side wall of the memory gate electrode is interposed through the side wall spacer.
- the first selection gate electrode and the second selection gate electrode arranged opposite to each other along the line are formed in a sidewall shape with respect to the memory gate electrode.
- a charge storage gate voltage necessary for injecting charges into the charge storage layer by the quantum tunnel effect is applied to the memory gate electrode, and a channel layer is formed on the surface of the memory well facing the memory gate electrode.
- the first selection gate structure cuts off the electrical connection between the drain region and the channel layer
- the second selection gate structure cuts off the electrical connection between the source region and the channel layer.
- a depletion layer can be formed to surround the channel layer where the channel potential has risen based on the storage gate voltage. As a result, the voltage difference between the memory gate electrode and the channel layer is reduced to prevent charge injection into the charge storage layer.
- the channel potential reaches from the channel layer to the first selection gate insulating film and the second selection gate insulating film by the depletion layer. I can stop.
- the nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device in which memory cells to which bit lines and source lines are connected are arranged in a matrix, and the memory cells are any one of claims.
- the memory cell is characterized by the following.
- the bit line in the first selection gate structure and the second selection gate structure is not restricted by the charge storage gate voltage necessary for injecting the charge into the charge storage layer by the quantum tunnel effect. Since the voltage value of the bit line and the source line can be lowered to the voltage value necessary to cut off the electrical connection of the channel layer and the electrical connection of the source line and the channel layer. In accordance with the voltage reduction at the source line, each film thickness of the first selection gate insulating film of the first selection gate structure and the second selection gate insulating film of the second selection gate structure can be reduced. High speed operation can be realized.
- the film thickness of the gate insulating film of the field effect transistor can be reduced even in the peripheral circuit for controlling the memory cell.
- the circuit area can be reduced.
- FIG. 1 is a circuit diagram showing a circuit configuration of a nonvolatile semiconductor memory device including a memory cell of the present invention.
- 2 is a cross-sectional view showing a side cross-sectional configuration of a memory cell according to the present invention. It is the schematic where it uses for description of the gate insulating film capacity
- 6 is a table showing an example of voltage values at each portion during a data write operation, a data read operation, and a data erase operation.
- FIG. 5A is a schematic diagram showing a state immediately after the charge is injected into the charge storage layer in the memory cell of Comparative Example 1 in which the charge storage layer is also formed in the side wall spacer between the memory gate electrode and the first selection gate electrode.
- FIG. 5B is a schematic view showing a state in which charges in the charge storage layer are diffused with time after the charge is injected into the charge storage layer of FIG. 5A. It is the schematic which shows a mode when an electric charge is inject
- FIG. 7A shows Comparative Example 2 in which impurity diffusion regions are formed on the memory well surface between the memory gate structure and the first select gate structure and on the memory well surface between the memory gate structure and the second select gate structure, respectively.
- FIG. 7B is a schematic diagram showing the width of the depletion layer in the memory cell of the present invention
- FIG. 7C is a schematic diagram showing the width of the depletion layer when the impurity concentration of the memory well is changed.
- reference numeral 1 denotes a nonvolatile semiconductor memory device, which has a configuration in which memory cells 2a, 2b, 2c, 2d according to the present invention are arranged in a matrix.
- the non-volatile semiconductor memory device 1 includes one bit line BL1 (1b) in memory cells 2a, 2c (2b, 2d) arranged in one direction (in this case, the column direction) among these memory cells 2a, 2b, 2c, 2d.
- BL2 is shared, and a predetermined bit voltage can be uniformly applied to each bit line BL1, BL2 by the bit voltage application circuit 10.
- the nonvolatile semiconductor memory device 1 includes one first selection gate line DGL1 (DGL2) in memory cells 2a and 2b (2c and 2d) arranged in another direction (in this case, the row direction) orthogonal to one direction. ), And the first selection gate voltage application circuit 11 can uniformly apply a predetermined first selection gate voltage to each of the first selection gate lines DGL1 and DGL2.
- one memory gate line MGL, one second selection gate line SGL, and one source line SL are connected to all the memory cells 2a. , 2b, 2c, and 2d, a predetermined memory gate voltage is applied to the memory gate line MGL by the memory gate voltage application circuit 13, and a predetermined value is applied to the second selection gate line SGL by the second selection gate voltage application circuit 14.
- the second selection gate voltage is applied, and the source voltage application circuit 15 can apply a predetermined source voltage to the source line SL.
- one memory gate line MGL, one second selection gate line SGL, and one source line SL are shared by all the memory cells 2a, 2b, 2c, 2d.
- the present invention is not limited to this.
- a memory gate line and a second selection gate line are provided for each memory cell 2a, 2b (2c, 2d) arranged in the other direction (row direction).
- the source line may be shared.
- all the memory cells 2a, 2b, 2c, 2d are formed in one memory well MPW made of, for example, P type, and a predetermined voltage is applied to the memory well MPW by the substrate voltage application circuit 17.
- the substrate voltage can be applied.
- these memory cells 2a, 2b, 2c, and 2d all have the same configuration, the following description will be focused on the memory cell 2a in the first row and the first column.
- the memory cell 2a has a bit line BL1 connected to a drain region (not shown) formed on the surface of the memory well MPW and a source region (not shown) formed on the surface of the memory well MPW.
- the source line SL is connected, and the memory gate structure 4, the first selection gate structure 5, and the second selection gate structure 6 are formed on the drain region and the memory well MPW between the source regions.
- the memory cell 2a includes a first select gate structure 5 via a side wall spacer (not shown) on one side wall of the memory gate structure 4 formed on the memory well MPW between the drain region and the source region.
- the second select gate structure 6 is disposed on the other side wall of the memory gate structure 4 via the side wall spacer, and the first select gate structure 6 is arranged on the memory well MPW from the bit line BL1 toward the source line SL.
- the selection gate structure 5, the memory gate structure 4, and the second selection gate structure 6 are arranged in this order.
- the first selection gate electrode DG is formed on the memory well MPW between the sidewall spacer and the drain region via the first selection gate insulating film.
- a first selection gate line DGL1 is connected to the electrode DG.
- the first selection gate structure 5 includes a bit voltage applied from the bit line BL1 to the drain region of the surface of the memory well MPW at one end, and a first selection applied from the first selection gate line DGL1 to the first selection gate electrode DG. Due to the voltage difference with the gate voltage, a channel layer can be formed on the surface of the memory well MPW facing the first selection gate electrode DG.
- the first select gate structure 5 is formed by forming a channel layer on the surface of the memory well MPW facing the first select gate electrode DG, so that the bit line BL1 and the memory gate structure 4 are arranged.
- the channel layer on the surface of the well MPW is electrically connected, and the bit voltage from the bit line BL1 can be applied to the channel layer of the memory gate structure 4.
- the first select gate structure 5 has a channel layer formed by the bit line BL1 and the memory gate structure 4 by not forming a channel layer on the surface of the memory well MPW facing the first select gate electrode DG. The electrical connection with the layer can be cut off, and the application of the bit voltage from the bit line BL1 to the channel layer of the memory gate structure 4 can be prevented.
- the second selection gate electrode SG is formed on the memory well MPW between the sidewall spacer and the source region via the second selection gate insulating film, and the second selection gate electrode SG 2 Select gate line SGL is connected.
- the second selection gate structure 6 includes a source voltage applied from the source line SL to a source region on the surface of the memory well MPW at one end, and a second selection applied from the second selection gate line SGL to the second selection gate electrode SG. Due to the voltage difference with the gate voltage, a channel layer can be formed on the surface of the memory well MPW facing the second selection gate electrode SG.
- the second select gate structure 6 is configured such that the channel layer is formed on the surface of the memory well MPW facing the second select gate electrode SG, so that the source line SL and the memory in which the memory gate structure 4 is arranged The channel layer on the surface of the well MPW can be electrically connected.
- the second select gate structure 6 has a channel layer not formed on the surface of the memory well MPW facing the second select gate electrode SG, so that the source line SL and the channel layer of the memory gate structure 4 The electrical connection can be cut off, and the application of the source voltage from the source line SL to the channel layer of the memory gate structure 4 can be blocked.
- the memory gate structure 4 on the memory well MPW between the first select gate structure 5 and the second select gate structure 6 includes a lower gate insulating film, a charge storage layer EC, an upper gate insulating film on the memory well MPW,
- the memory gate electrode MG is stacked in this order, and the memory gate line MGL is connected to the memory gate electrode MG.
- the memory gate structure 4 having such a configuration generates a quantum tunnel effect due to a voltage difference between the memory gate electrode MG and the memory well MPW, and injects charges into the charge storage layer EC, or within the charge storage layer EC. It is designed to pull out the charge from.
- FIG. 2 is a sectional view showing a side sectional configuration of the memory cell 2a (2b).
- a P-type memory well MPW is formed on an insulating substrate 20 such as SiO 2 via an N-type deep well layer DNW.
- a memory gate structure 4 that forms a transistor structure
- a first selection gate structure 5 that forms an N-type MOS (Metal-Oxide-Semiconductor) transistor structure
- a second selection that also forms an N-type MOS transistor structure
- a gate structure 6 is formed in the memory well MPW.
- a drain region 31 at one end of the first select gate structure 5 and a source region 34 at one end of the second select gate structure 6 are formed on the surface of the memory well MPW with a predetermined distance.
- the bit line BL1 is connected to the drain region 31, and the source line SL is connected to the source region.
- the drain region 31 and the source region 34 are selected to have an impurity concentration of 1.0E21 / cm 3 or more, while the memory well MPW has a surface region (where the channel layer CH is formed) for example, the impurity concentration of the region) from the surface to 50 [nm] is 1.0E19 / cm 3 or less, preferably is selected to be 3.0E18 / cm 3 or less.
- the memory gate structure 4 is formed on the memory well MPW between the drain region 31 and the source region 34 via a lower gate insulating film 24a made of an insulating material such as SiO 2 , for example, silicon nitride (Si 3 N 4 ), It has a charge storage layer EC made of silicon oxynitride (SiON), alumina (Al 2 O 3 ), etc., and further on the charge storage layer EC via an upper gate insulating film 24b also made of an insulating member. It has a memory gate electrode MG.
- the memory gate structure 4 has a configuration in which the charge storage layer EC is insulated from the memory well MPW and the memory gate electrode MG by the lower gate insulating film 24a and the upper gate insulating film 24b.
- a side wall spacer 28a made of an insulating member is formed along one side wall, and the first selection gate structure 5 is adjacent to the memory gate structure 4 via the side wall spacer 28a.
- the sidewall spacer 28a formed between the memory gate structure 4 and the first selection gate structure 5 is formed with a predetermined film thickness, and the memory gate structure 4 and the first selection gate structure
- the body 5 can be insulated.
- the first selection gate structure 5 is an insulating member on the memory well MPW between the side wall spacer 28a and the drain region 31, and has a thickness of 9 [nm] or less, preferably 3 [nm] or less.
- a first selection gate insulating film 30 is formed, and a first selection gate electrode DG to which a first selection gate line DGL1 is connected is formed on the first selection gate insulating film 30.
- the sidewall spacer 28a between the memory gate structure 4 and the first selection gate structure 5 is preferably selected to have a width of 5 [nm] or more and 40 [nm] or less.
- a side wall spacer 28b made of an insulating member is formed on the other side wall of the memory gate structure 4, and the second select gate structure 6 is adjacent to the side wall spacer 28b.
- the side wall spacer 28b formed between the memory gate structure 4 and the second selection gate structure 6 is also formed with the same film thickness as the one side wall spacer 28a.
- the second select gate structure 6 can be insulated.
- the second selection gate structure 6 is an insulating member on the memory well MPW between the side wall spacer 28b and the source region 34, and has a thickness of 9 [nm] or less, preferably 3 [nm] or less.
- a second selection gate insulating film 33 is formed, and a second selection gate electrode SG connected to the second selection gate line SGL is formed on the second selection gate insulating film 33.
- the side walls when a predetermined voltage is applied to the memory gate electrode MG or the second selection gate electrode SG On the other hand, when the space between the memory gate structure 4 and the second selection gate structure 6 exceeds 40 [nm], there is a risk that a breakdown voltage failure may occur in the spacer 28b, between the memory gate electrode MG and the second selection gate electrode SG.
- the resistance in the memory well MPW is increased, and a read current is hardly generated between the memory gate structure 4 and the second selection gate structure 6 at the time of data reading described later. Therefore, in the case of this embodiment, it is desirable that the side wall spacer 28a between the memory gate structure 4 and the second selection gate structure 6 is also selected to have a width of 5 [nm] or more and 40 [nm] or less.
- the first selection gate electrode DG and the second selection gate electrode SG formed along the side wall of the memory gate electrode MG via the side wall spacers 28a and 28b are respectively connected to the memory gate electrode MG.
- the top is formed in a side wall shape that descends toward the memory well MPW.
- the memory cells 2a, 2b, 2c, and 2d having such a configuration can be formed by a general semiconductor manufacturing process using a photolithography technique, a film forming technique such as oxidation or CVD, an etching technique, and an ion implantation method. The description is omitted here.
- the first selection gate electrode DG and the second selection gate electrode SG having the sidewall shape described above are formed by first forming the memory gate electrode MG covered with the sidewall spacers 28a and 28b on the memory well MPW, and then By forming a conductive layer on the memory well MPW so as to cover the side wall spacers 28a and 28b around the gate electrode MG, and then etching back the conductive layer, the side wall spacers 28a and 28b on the side wall of the memory gate electrode MG are formed. It can be formed in a sidewall shape along.
- the memory gate electrode MG is formed before the first selection gate electrode DG and the second selection gate electrode SG.
- the first selection gate electrode DG and the second selection gate electrode SG are formed using a conductive layer different from the memory gate electrode MG by a process subsequent to the semiconductor manufacturing process for forming the memory gate electrode MG. Yes.
- a memory cell (also referred to as a write selection memory cell) 2a for injecting charges into the charge storage layer EC is supplied from the memory gate line MGL to the memory gate electrode MG of the memory gate structure 4.
- the channel layer CH can be formed along the surface of the memory well MPW opposed to the memory gate electrode MG by applying the charge storage gate voltage of V].
- a gate-off voltage of 0 [V] is applied to the second selection gate structure 6 from the second selection gate line SGL to the second selection gate electrode SG, and 0 [V] from the source line SL to the source region 34.
- Source off voltage can be applied.
- the second select gate structure 6 includes the source region 34 to which the source line SL is connected, the memory gate MPW, without the channel layer being formed on the surface of the memory well MPW facing the second select gate electrode SG.
- the electric connection with the four channel layers CH can be cut off, and the voltage application from the source line SL to the channel layer CH of the memory gate structure 4 can be blocked.
- the first selection gate structure 5 a first selection gate voltage of 1.5 [V] is applied from the first selection gate line DGL1 to the first selection gate electrode DG, and 0 [ V] charge storage bit voltage can be applied.
- the first select gate structure 5 becomes conductive in the memory well MPW facing the first select gate electrode DG, the drain region 31 to which the bit line BL1 is connected, the channel layer CH of the memory gate structure 4 and Can be electrically connected, and the channel layer CH of the memory gate structure 4 can be set to 0 [V] which is a charge storage bit voltage.
- the same substrate voltage of 0 [V] as the charge storage bit voltage can be applied to the memory well MPW.
- the memory gate electrode MG is 12 [V] and the channel layer CH is 0 [V]
- a large voltage of 12 [V] is generated between the memory gate electrode MG and the channel layer CH.
- a difference (12 [V]) is generated, and charges can be injected into the charge storage layer EC by the quantum tunnel effect generated thereby, and data can be written.
- the memory gate structure 4 of the other memory cell 2b is also Since a 12 [V] charge storage gate voltage is applied from the memory gate line MGL to the memory gate electrode MG, the charge storage gate voltage is transmitted to the memory well MPW, and the surface of the memory well MPW facing the memory gate electrode MG A channel layer CH may be formed along
- a gate-off voltage of 0 [V] is applied from the second select gate line SGL to the second select gate electrode SG, and 0 [V] is applied from the source line SL to the source region 34.
- a source off voltage of V] can be applied.
- the second select gate structure 6 of the memory cell 2b becomes non-conductive at the memory well MPW facing the second select gate electrode SG, and the source region 34 to which the source line SL is connected and the memory gate structure 4 The electrical connection with the channel layer CH can be cut off.
- a first selection gate voltage of 1.5 [V] is applied to the first selection gate structure 5 of the memory cell 2b from the first selection gate line DGL1 to the first selection gate electrode.
- An off voltage of 1.5 [V] can be applied to the drain region 31 from the line BL2.
- the memory well MPW is in a non-conducting state under the first selection gate structure 5 and the second selection gate structure 6 on both sides.
- the channel layer CH formed on the surface of the memory well MPW by MG is in a state where the electrical connection between the drain region 31 and the source region 34 is cut off, and the depletion layer D can be formed around the channel layer CH.
- a capacitance (hereinafter referred to as a gate insulating film capacitance) C2 obtained by the three-layer configuration of the upper gate insulating film 24b, the charge storage layer EC, and the lower gate insulating film 24a is formed in the memory well MPW.
- a capacity of depletion layer D (hereinafter referred to as depletion layer capacity) C1 surrounding channel layer CH as shown in FIG. 3, gate insulating film capacity C2 and depletion layer capacity C1 are connected in series.
- the channel potential Vch of the channel layer CH can be obtained from the following equation.
- the substrate voltage CV of the memory well MPW is 0 [V]
- the memory gate voltage MV of the memory gate electrode MG is 12 [V].
- the potential Vch is 9 [V].
- the channel potential Vch of the channel layer CH surrounded by the depletion layer D in the memory well MPW is 9 Therefore, the voltage difference between the memory gate electrode MG and the channel layer CH is as small as 3 [V].
- charge injection into the charge storage layer EC can be performed without the quantum tunnel effect. Can be blocked.
- an impurity diffusion region having a high impurity concentration is not formed in the memory well MPW region between the memory gate structure 4 and the first selection gate structure 5.
- the depletion layer D can be reliably formed around the channel layer CH formed around the surface of the memory well MPW, and the channel potential Vch can reach the first selection gate insulating film 30 from the channel layer CH by the depletion layer D. Can be blocked.
- the first select gate structure 5 even if the first select gate insulating film 30 is thinly formed in accordance with the low voltage applied to the drain region 31 from the bit line BL2, the channel Since the channel potential Vch of the layer CH is blocked by the depletion layer D, the dielectric breakdown of the first select gate insulating film 30 due to the channel potential Vch can be prevented.
- the memory well MPW since the impurity diffusion region having a high impurity concentration is not formed in the region of the memory well MPW between the memory gate structure 4 and the second selection gate structure 6, the memory well MPW
- the depletion layer D can be reliably formed around the channel layer CH formed around the surface, and the depletion layer D can prevent the channel potential Vch from reaching the second selection gate insulating film 33 from the channel layer CH.
- the second selection gate structure 6 even if the film thickness of the second selection gate insulating film 33 is reduced in accordance with the low source voltage applied from the source line SL to the source region 34, the channel layer Since the channel potential Vch of CH is blocked by the depletion layer D, the dielectric breakdown of the second select gate insulating film 33 due to the channel potential Vch can be prevented.
- the channel potential at the start of the operation varies depending on the charge accumulation state in the memory cells 2a and 2b. There is a risk of doing. Therefore, before the write operation, the potential of the bit lines BL1, BL2 or the source line SL is set to, for example, 0 [V], the first selection gate electrode DG or the second selection gate electrode SG is set to, for example, 1.5 [V], and the memory gate More preferably, the electrode MG is set to 1.5 [V], for example, and an operation of aligning the channel potentials of the memory cells 2a, 2b, 2c, and 2d with the potentials of the bit lines BL1 and BL2 or the source line SL is added. In that case, after the channel potentials are aligned, the first selection gate electrode DG or the second selection gate electrode SG is returned to the gate-off voltage of 0 [V], and then the write operation is started.
- FIG. 4 shows a data write operation for injecting charge into, for example, the charge storage layer EC of the memory cell 2a in the nonvolatile semiconductor memory device 1 of the present invention.
- Prog a data read operation
- Read on whether or not charges are stored in the charge storage layer EC of the memory cell 2a
- Erase is a table summarizing voltage values of respective parts during a data erasing operation (“Erase”).
- the column “Read” in FIG. 4 indicates the voltage value during the data read operation.
- the second select gate line SGL A second selection gate voltage of 1.5 [V] is applied to the source line SL, and a source voltage of 0 [V] is applied to the source line SL, whereby the second selection gate structure 6 of the memory cell 2a is provided.
- the memory well MPW becomes conductive, and the source line SL and the channel layer CH of the memory gate structure 4 can be electrically connected.
- a first selection gate voltage of 1.5 [V] is applied to the first selection gate line DGL1 connected to the first selection gate structure 5 of the memory cell 2a from which data is read, and the first selection gate A read voltage of 1.5 [V] can be applied to the bit line BL1 connected to the drain region 31 adjacent to the structure 5.
- 0 [V] can be applied from the memory gate line MGL to the memory gate electrode MG in the memory gate structure 4 of the memory cell 2a from which data is read.
- the memory well below the memory gate structure 4 The MPW becomes non-conductive, and the memory gate structure 4 can cut off the electrical connection between the first select gate structure 5 and the second select gate structure 6.
- the read voltage of 1.5 [V] on the bit line BL1 connected to the drain region adjacent to the first select gate structure 5 can be maintained as it is.
- the memory well MPW below the memory gate structure 4 Is in a conductive state, and the first selection gate structure 5 and the second selection gate structure 6 are electrically connected via the memory gate structure 4, and as a result, 0 [V] is supplied via the memory cell 2a.
- the source line SL is electrically connected to the 1.5 [V] bit line BL1.
- the read voltage of the bit line BL1 is applied to the source line SL of 0 [V], so that the read voltage of 1.5 [V] applied to the bit line BL1 is increased. descend.
- data indicating whether or not charges are accumulated in the charge accumulation layer EC of the memory cell 2a is read by detecting whether or not the read voltage of the bit line BL1 has changed. Can do.
- the first selection gate As shown in “non-selected row” in FIG.
- the charge accumulation state in the charge accumulation layer EC affects the read voltage of the bit line BL1. Can be prevented.
- the column “Erase” in FIG. 4 shows a voltage value at the time of data erasing operation for extracting charges in the charge storage layer EC of the memory cells 2 a and 2 c in the nonvolatile semiconductor memory device 1.
- a memory gate voltage of -12 [V] is applied to the memory gate structure 4 of each memory cell 2a, 2c from the memory gate line MGL to the memory gate electrode MG.
- Data in the charge storage layer EC can be extracted toward the memory well MPW to erase data.
- the column “Prog” in FIG. 4 indicates the voltage value (“selected column” and “selected row”) when the charge is injected into the charge storage layer EC of the memory cell 2a, and the charge storage layer EC of the memory cell 2a. Indicates the voltage value (“non-selected column” or “non-selected row”) when no charge is injected, and “(3) Operation principle for injecting charge into the charge storage layer in the write selected memory cell” described above and “(4) In the write non-selected memory cell in which a high voltage charge storage gate voltage is applied to the memory gate electrode, there is an overlapping explanation with respect to the operation principle that charges are not injected into the charge storage layer”. Description is omitted.
- FIG. 5A in which the same reference numerals are assigned to the corresponding parts to FIG. 2 shows the memory cell 100 which is Comparative Example 1, and the memory gate electrode
- the memory cell 2a is different from the memory cell 2a of the present invention shown in FIG. 2 in that the charge storage layer EC1 is also formed in the sidewall spacer 102 between the MG and the first selection gate electrode DG.
- FIG. 5A shows only the charge storage layer EC1 between the memory gate electrode MG and the first selection gate electrode DG, but the memory gate electrode MG and the second selection gate electrode SG (not shown in FIG. 5A).
- charge storage layers are formed in the side wall spacers therebetween.
- the charge storage layer EC1 shown in the comparative example extends from the end of the charge storage layer EC provided in the region ER1 below the memory gate electrode MG to the region between the memory gate electrode MG and the first selection gate electrode DG. After extending, it is refracted at a right angle and extends along the side wall of the memory gate electrode MG in the side wall spacer 102 between the memory gate electrode MG and the first selection gate electrode DG.
- the charges in the charge storage layer EC are changed over time to the memory gate electrode MG and It gradually diffuses into the charge storage layer EC1 between the first selection gate electrodes DG and directly above the region ER2 of the memory well MPW between the memory gate electrode MG and the first selection gate electrode DG as well as the charge storage layer EC. There is a possibility that the charge is accumulated in the charge accumulation layer EC1.
- the charge is stored up to the charge storage layer EC1 immediately above the region ER2 of the memory well MPW between the memory gate electrode MG and the first selection gate electrode DG.
- the resistance in the region ER2 of the memory well MPW between the memory gate electrode MG and the first selection gate electrode DG is increased, so that the memory current is reduced in the read operation, and the read performance is difficult to improve. There was a problem that it was difficult to operate.
- the charge storage layer EC is provided only in the region ER1 where the memory gate electrode MG faces the memory well MPW. Also, a charge storage layer is not provided in the side wall spacer 28a between the first select gate electrode DG and in the side wall spacer 28b between the memory gate electrode MG and the second select gate electrode SG (not shown in FIG. 6). It is configured.
- the memory cell 2a when charge is injected into the charge storage layer EC, the memory cell 2a causes the side wall spacers 28a and 28b to transfer the charge in the charge storage layer EC to the first selection gate electrode DG and the second selection gate electrode SG. Without reaching the vicinity, it is possible to stay in the region ER1 below the memory gate electrode MG and to prevent charge accumulation immediately above the region ER2 of the memory well MPW between the memory gate electrode MG and the first selection gate electrode DG. . Thus, in the memory cell 2a, the resistance value in the region ER2 of the memory well MPW between the memory gate electrode MG and the first selection gate electrode DG can be maintained in a low resistance state, and the read performance can be improved and the memory cell 2a can be operated at high speed.
- the lower gate insulating film 24a, the charge storage layer EC, the upper gate insulating film 24b, and the memory gate are formed on the memory well MPW between the drain region 31 and the source region 34.
- the memory gate structure 4 is stacked in the order of the electrodes MG, the first selection gate structure 5 is formed on one side wall of the memory gate structure 4 via the side wall spacer 28a, and the memory gate structure 4
- the second select gate structure 6 is formed on the other side wall via the side wall spacer 28b.
- the first selection gate structure 5 includes a first selection gate on the memory well MPW between the drain region 31 to which the bit line BL1 is connected and one sidewall spacer 28a provided on the sidewall of the memory gate structure 4.
- the first selection gate electrode DG is formed through the insulating film 30.
- the second select gate structure 6 has a second region on the memory well MPW between the source region 34 to which the source line SL is connected and the other side wall spacer 28b provided on the side wall of the memory gate structure 4.
- the second selection gate electrode SG is formed via the selection gate insulating film 33.
- the charge storage gate voltage necessary for the charge injection into the charge storage layer EC is applied to the memory gate electrode MG, and the memory gate electrode MG is opposed. Even if the channel layer CH is formed on the surface of the memory well MPW, the electrical connection between the drain region 31 and the channel layer CH is cut off by the first selection gate structure 5 and the source by the second selection gate structure 6 The electrical connection between the region 34 and the channel layer CH is also cut off.
- a depletion layer D is formed around the channel layer CH, and the channel potential Vch of the channel layer CH rises based on the charge storage gate voltage, so that the memory cell electrode MG and the channel layer CH are between.
- the depletion layer D can block the voltage application from the channel layer CH to the first selection gate insulating film 30 and the second selection gate insulating film 33 while reducing the voltage difference and preventing charge injection into the charge storage layer EC. .
- the first selection gate structure 5 and the second selection gate are not constrained by the high voltage charge storage gate voltage necessary for injecting charges into the charge storage layer EC by the quantum tunnel effect.
- the bit line BL1 and the source line SL are brought to a voltage value necessary to cut off the electrical connection between the bit line BL1 and the channel layer CH and the electrical connection between the source line SL and the channel layer CH. The voltage value of can be lowered.
- the thickness of the first selection gate insulating film 30 of the first selection gate structure 5 and the second selection gate structure 6 are adjusted in accordance with the voltage reduction in the bit line BL1 and the source line SL.
- the thickness of the second select gate insulating film 33 can be reduced, and high speed operation can be realized accordingly.
- the voltage applied to the bit line BL1 and the source line SL can be reduced, so that the gate insulating film thickness of the field effect transistor can be reduced even in the peripheral circuit that controls the memory cell 2a. Accordingly, the area of the peripheral circuit can be reduced.
- the nonvolatile semiconductor memory device 1 in which the memory cells 2a, 2b, 2c, and 2d are arranged in a matrix includes a bit voltage application circuit 10, a first selection gate voltage application circuit 11, and a memory gate.
- a voltage application circuit 13, a second selection gate voltage application circuit 14, a source voltage application circuit 15, and a substrate voltage application circuit 17 are provided.
- the bit lines BL1, BL2, the first select gate lines DGL1, DGL2, the source line SL, the second in all operations such as when the charge is extracted from each charge storage layer EC of the memory cells 2a, 2b, 2c, 2d
- the voltage value applied to the selection gate line SGL can be kept at 1.5 [V] or less.
- the nonvolatile semiconductor memory device 1 of the present invention includes the bit voltage application circuit 10, the first selection gate voltage application circuit 11, the second selection gate voltage application circuit 14, the memory gate voltage application circuit 13, and the source voltage application circuit 15
- each peripheral circuit of the substrate voltage application circuit 17 for example, CPU (Central Processing Unit) or ASIC (Application-Specific Integrated Circuit), logic circuit, input / output circuit with the maximum operating voltage set to 1.5 [V]
- Various other peripheral circuits and the like can be mixedly mounted on one semiconductor substrate together with the memory cells 2a, 2b, 2c, 2d, the bit voltage application circuit 10, and the like.
- the film thicknesses of the first selection gate insulating film 30 and the second selection gate insulating film 33 formed in the memory cells 2a, 2b, 2c, 2d The film thickness of the gate insulating film of the field-effect transistor constituting the circuit is selected to be the thinnest or less, and the film thickness of the first selection gate insulating film 30 and the second selection gate insulating film 33 is the bit A film of the gate insulating film of the field effect transistor constituting the bit voltage application circuit 10 connected to the lines BL1 and BL2 and the gate insulating film of the field effect transistor constituting the source voltage application circuit 15 connected to the source line SL It is desirable that the film thickness be the same as the thickness.
- the first select gate insulating film 30 and the second select gate insulating film 33 are thinned on the semiconductor substrate on which the peripheral circuit is embedded, so that the high speed operation is achieved. Further, the area of the peripheral circuit arranged around the memory cells 2a, 2b, 2c, 2d can be reduced.
- the memory cell 2a of the present invention shown in FIG. 2 will be described with reference to a memory cell 201 as shown in FIG.
- the memory cell 201 shown in FIG. 7A is a comparative example 2 in which an impurity diffusion region 207a is formed on the surface of the memory well MPW between the memory gate structure 204 and the first selection gate structure 205, and the memory gate structure This is different from the memory cell 2a shown in FIG. 2 described above in that an impurity diffusion region 207b is also formed on the surface of the memory well MPW between the fourth and second selection gate structures 206.
- impurity diffusion regions 207a and 207b having a higher impurity concentration than the memory well MPW in which the channel layer CH is formed are formed on the surface of the memory well MPW on both sides of the memory gate structure 204. Therefore, the channel potential of the channel layer CH is applied to the first selection gate insulating film 30 and the second selection gate insulating film 33 through the impurity diffusion regions 207a and 207b.
- the channel potential Vch of the channel layer CH is relaxed by the depletion layer having the width DW1 formed around the channel layer CH, and the channel layer CH is transferred to the first selection gate insulating film 30 and the first selection gate insulating film 33. Application of the channel potential Vch can be cut off.
- the application of the channel potential Vch from the channel layer CH to the first selection gate insulating film 30 and the second selection gate insulating film 33 can be reliably blocked, so that the bit line BL1 and the source line SL Even if the film thickness of the first selection gate insulating film 30 and the second selection gate insulating film 33 is reduced in accordance with the low voltage applied from the first selection gate insulating film 30 and the second selection gate insulating film 33 Insulation breakdown can be prevented.
- the width DW1 of the depletion layer is formed larger than the thickness of the first selection gate insulating film 30 and the second selection gate insulating film 33, so that the memory cell 201 of the comparative example 2 shown in FIG.
- the electric field applied to the first selection gate insulating film 30 and the second selection gate insulating film 33 can be suppressed to about half or less.
- the first selection gate insulation The film 30 and the second select gate insulating film 33 can be formed to a thickness of 9 [nm] or less.
- a channel layer The impurity concentration of the surface region where CH is formed may be 3E18 / cm 3 or less.
- FIG. 7C in which the same reference numerals are assigned to the parts corresponding to FIG. 7B, shows the present invention formed by the memory well MPW1 in which the impurity concentration of the surface region where the channel layer CH is formed is 3E18 / cm 3 or less.
- the memory cell 41 is shown.
- a high-voltage charge storage gate voltage is applied to the memory gate electrode MG, and the channel layer CH is formed on the surface of the memory well MPW1 facing the memory gate electrode MG.
- the memory gate structure MP4 is formed on the surface of the opposed memory well MPW1 by bringing the memory well MPW1 opposed to the first selection gate structure 5 and the second selection gate structure 6 into a non-conductive state.
- a depletion layer (not shown) can be formed around the channel layer CH, and charge injection into the charge storage layer EC can be prevented.
- the width DW2 of the depletion layer formed around the channel layer CH is extended, and the width DW2 of the depletion layer is extended.
- the electric field applied to the first selection gate insulating film 30 and the second selection gate insulating film 33 can be relaxed, and thus the first selection gate insulating film 30 and the second selection gate insulating film 33 can be made thinner.
- the first selection gate insulating film 30 and the second selection gate insulating film 33 Since the electric field applied to 33 can be reduced to about 1/4 compared to the memory cell 2a (FIG. 2) using the memory well MPW having an impurity concentration of 1.0E19 / cm 3 , the first selection gate The thickness of the insulating film 30 and the second select gate insulating film 33 can be formed to 3 [nm] or less.
- the memory well MPW1 between the first selection gate electrode DG and the second selection gate electrode SG only needs to have an impurity concentration of 3E18 / cm 3 or less in a region from the surface to 50 [nm].
- the electric field applied from the channel layer CH to the first selection gate insulating film 30 and the second selection gate insulating film 33 can be relaxed, and the film thickness of the first selection gate insulating film 30 and the second selection gate insulating film 33 can be reduced. It can be formed below 3 [nm].
- the P-type memory well MPW is used to form the memory gate structure 4 that forms the N-type transistor structure and the first selection gate structure that forms the N-type MOS transistor structure. 5 and the case where the first selection gate structure 6 that also forms the N-type MOS transistor structure is provided.
- the present invention is not limited to this, and the N-type memory well is used to form the P-type.
- the memory gate structure, the first selection gate structure, and the second selection gate structure The voltages applied to the bit line and the source line also change accordingly.
- the voltage applied to the bit line and the source line is not restricted by the charge storage gate voltage applied to the memory gate electrode. In the region of the second selection gate structure, the voltage can be lowered to a voltage value necessary to make the memory well nonconductive.
- the first selection gate insulating film of the first selection gate structure and the second selection gate insulating film of the second selection gate structure The thickness can be reduced, and accordingly, high-speed operation can be realized, and the area of the peripheral circuit can be reduced.
- the nonvolatile semiconductor memory device 1 of the present invention is not limited to the voltage value shown in FIG. 4 described above, and the memory gate structure 4 injects charges into the charge storage layer EC by the quantum tunnel effect.
- the memory well MPW is made non-conductive in the regions of the first selection gate structure 5 and the second selection gate structure 6, and the depletion layer is formed around the channel layer CH in the memory well MPW provided with the memory gate structure 4.
- Other various voltage values may be used as long as D is formed and charge injection into the charge storage layer EC can be prevented.
- various other voltages can be used as long as information on whether or not charges are accumulated in the charge accumulation layer EC of the memory cells 2a, 2b, 2c, and 2d can be read.
- a value may be used.
- Second selection gate insulation Film 34 Source region CH Channel layer D Depletion layer BL1, BL2 Bit line SL Source line MGL Memory gate line DGL1, DGL2 First selection gate line SGL Second selection gate line MPW, MPW1 Memory well MG Memory gate electrode DG First selection gate Electrode SG Second selection gate electrode EC Charge storage layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
Description
1.不揮発性半導体記憶装置の全体構成
2.メモリセルの詳細構成
3.書き込み選択メモリセルにおいて電荷蓄積層に電荷を注入させる動作原理について
4.高電圧の電荷蓄積ゲート電圧がメモリゲート電極に印加された書き込み非選択メモリセルにおいて、電荷蓄積層に電荷が注入されない動作原理について
5.不揮発性半導体記憶装置における各種動作時における電圧について
6.本発明のメモリセルにおける電荷蓄積層の構成について
7.作用および効果
8.他の実施の形態
図1において、1は不揮発性半導体記憶装置を示し、本発明によるメモリセル2a,2b,2c,2dが行列状に配置された構成を有する。不揮発性半導体記憶装置1は、これらメモリセル2a,2b,2c,2dのうち、一方向(この場合、列方向)に並ぶメモリセル2a,2c(2b,2d)で1本のビット線BL1(BL2)を共有しており、ビット電圧印加回路10によって各ビット線BL1,BL2毎に所定のビット電圧が一律に印加され得る。また、不揮発性半導体記憶装置1は、一方向と直交する他方向(この場合、行方向)に配置されたメモリセル2a,2b(2c,2d)で1本の第1選択ゲート線DGL1(DGL2)を共有しており、第1選択ゲート電圧印加回路11によって各第1選択ゲート線DGL1,DGL2毎に所定の第1選択ゲート電圧が一律に印加され得る。
ここで、図2はメモリセル2a(2b)の側断面構成を示す断面図である。実際上、図2に示すように、例えばメモリセル2aは、SiO2等の絶縁基板20上にN型のディープウェル層DNWを介してP型のメモリウェルMPWが形成されており、N型のトランジスタ構造を形成するメモリゲート構造体4と、N型のMOS(Metal-Oxide-Semiconductor)トランジスタ構造を形成する第1選択ゲート構造体5と、同じくN型のMOSトランジスタ構造を形成する第2選択ゲート構造体6とが当該メモリウェルMPWに形成されている。
次に、例えばメモリセル2aの電荷蓄積層ECに電荷を注入し、当該メモリセル2aにデータを書き込む場合について以下説明する。この場合、図2に示すように、電荷蓄積層ECに電荷を注入させるメモリセル(書き込み選択メモリセルとも呼ぶ)2aは、メモリゲート線MGLからメモリゲート構造体4のメモリゲート電極MGに12[V]の電荷蓄積ゲート電圧が印加され、当該メモリゲート電極MGと対向するメモリウェルMPWの表面に沿ってチャネル層CHが形成され得る。この際、第2選択ゲート構造体6には、第2選択ゲート線SGLから第2選択ゲート電極SGに0[V]のゲートオフ電圧が印加され、ソース線SLからソース領域34に0[V]のソースオフ電圧が印加され得る。これにより第2選択ゲート構造体6は、第2選択ゲート電極SGに対向したメモリウェルMPW表面にチャネル層が形成されることなく、ソース線SLが接続されたソース領域34と、メモリゲート構造体4のチャネル層CHとの電気的な接続を遮断し、ソース線SLからメモリゲート構造体4のチャネル層CHへの電圧印加を阻止し得る。
ここで、図1に示す不揮発性半導体記憶装置1では、メモリゲート線MGLを全てのメモリセル2a,2b,2c,2cで共有していることから、例えば1行1列目にあるメモリセル2aの電荷蓄積層ECにのみ電荷を注入するため、メモリゲート線MGLに高電圧の電荷蓄積ゲート電圧を印加すると、電荷蓄積層ECに電荷を注入しない他のメモリセル(書き込み非選択メモリセルとも呼ぶ)2b,2c,2dにもメモリゲート線MGLを介して各メモリゲート電極MGに高電圧の電荷蓄積ゲート電圧が印加され得る。
ここで、図4は、本発明の不揮発性半導体記憶装置1において、例えばメモリセル2aの電荷蓄積層ECに電荷を注入するデータ書き込み動作時(「Prog」)、メモリセル2aの電荷蓄積層ECに電荷が蓄積されているか否かのデータ読み出し動作時(「Read」)、およびメモリセル2a,2cの電荷蓄積層EC内の電荷を引き抜くデータ消去動作時(「Erase」)における各部位の電圧値について纏めた表である。
ここで、図2との対応部分に同一符号を付して示す図5Aは、比較例1であるメモリセル100を示し、メモリゲート電極MGおよび第1選択ゲート電極DG間にある側壁スペーサ102内にも電荷蓄積層EC1が形成されている点で、図2に示した本発明のメモリセル2aとは相違している。なお、図5Aは、メモリゲート電極MGおよび第1選択ゲート電極DG間の電荷蓄積層EC1だけを図示しているが、メモリゲート電極MGおよび第2選択ゲート電極SG(図5Aでは図示せず)間の側壁スペーサ内にも同様に電荷蓄積層が形成されている。
以上の構成において、メモリセル2aでは、ドレイン領域31およびソース領域34間のメモリウェルMPW上に、下部ゲート絶縁膜24a、電荷蓄積層EC、上部ゲート絶縁膜24bおよびメモリゲート電極MGの順で積層形成されたメモリゲート構造体4を備え、メモリゲート構造体4の一の側壁に側壁スペーサ28aを介して第1選択ゲート構造体5を形成し、当該メモリゲート構造体4の他の側壁に側壁スペーサ28bを介して第2選択ゲート構造体6を形成するようにした。
なお、本発明は、本実施形態に限定されるものではなく、本発明の要旨の範囲内で種々の変形実施が可能であり、例えば、メモリウェルにおいて、チャネル層CHが形成される表面領域の不純物濃度を3E18/cm3以下としてもよい。ここで、図7Bとの対応部分に同一符号を付して示す図7Cは、チャネル層CHが形成される表面領域の不純物濃度が3E18/cm3以下でなるメモリウェルMPW1により形成された本発明のメモリセル41を示す。
2a,2b,2c,2d メモリセル
4 メモリゲート構造体
5 第1選択ゲート構造体
6 第2選択ゲート構造体
30 第1選択ゲート絶縁膜
31 ドレイン領域
33 第2選択ゲート絶縁膜
34 ソース領域
CH チャネル層
D 空乏層
BL1,BL2 ビット線
SL ソース線
MGL メモリゲート線
DGL1,DGL2 第1選択ゲート線
SGL 第2選択ゲート線
MPW,MPW1 メモリウェル
MG メモリゲート電極
DG 第1選択ゲート電極
SG 第2選択ゲート電極
EC 電荷蓄積層
Claims (11)
- メモリウェル表面に形成され、ビット線が接続されたドレイン領域と、
前記メモリウェル表面に形成され、ソース線が接続されたソース領域と、
前記ドレイン領域および前記ソース領域間に形成され、前記メモリウェル上に下部メモリゲート絶縁膜、電荷蓄積層、上部メモリゲート絶縁膜およびメモリゲート電極の順で積層形成されたメモリゲート構造体と、
前記ドレイン領域および前記メモリゲート構造体間の前記メモリウェル上に第1選択ゲート絶縁膜を介して第1選択ゲート電極が形成された構成を有し、前記メモリゲート構造体の一の側壁に一の側壁スペーサを介して隣接した第1選択ゲート構造体と、
前記ソース領域および前記メモリゲート構造体間の前記メモリウェル上に第2選択ゲート絶縁膜を介して第2選択ゲート電極が形成された構成を有し、前記メモリゲート構造体の他の側壁に他の側壁スペーサを介して隣接した第2選択ゲート構造体とを備えており、
量子トンネル効果によって前記電荷蓄積層に電荷を注入するのに必要な電荷蓄積ゲート電圧が前記メモリゲート電極に印加され、前記メモリゲート電極が対向した前記メモリウェル表面にチャネル層が形成されても、前記第1選択ゲート構造体により前記ドレイン領域および前記チャネル層の電気的な接続を遮断し、かつ、前記第2選択ゲート構造体により前記ソース領域および前記チャネル層の電気的な接続も遮断することで、前記電荷蓄積ゲート電圧に基づいてチャネル電位が上昇した前記チャネル層を囲うように空乏層を形成し、前記メモリゲート電極および前記チャネル層間の電圧差を小さくして前記電荷蓄積層内への電荷注入を阻止しつつ、前記空乏層によって前記チャネル層から前記第1選択ゲート絶縁膜および前記第2選択ゲート絶縁膜へのチャネル電位の到達を阻止する
ことを特徴とするメモリセル。 - 前記第1選択ゲート電極と前記第2選択ゲート電極との間の前記メモリウェルは、前記ドレイン領域および前記ソース領域の不純物濃度よりも低く、かつ前記空乏層が形成された際に、該空乏層によって前記チャネル層から前記第1選択ゲート絶縁膜および前記第2選択ゲート絶縁膜への前記チャネル電位の到達を阻止する不純物濃度に選定されている
ことを特徴とする請求項1記載のメモリセル。 - 前記電荷蓄積層に電荷を注入する際には、
前記第2選択ゲート構造体により、前記ソース線から前記チャネル層への電圧印加を遮断する一方で、前記第1選択ゲート構造体により前記ビット線から前記チャネル層へビット電圧を印加し、前記電荷蓄積ゲート電圧と前記ビット電圧との電圧差により前記電荷蓄積層に電荷を注入する
ことを特徴とする請求項1または2記載のメモリセル。 - 前記電荷蓄積層は、前記メモリゲート電極と前記メモリウェルとが対向した領域にのみ形成されており、前記メモリゲート構造体および前記第1選択ゲート構造体間の前記一の側壁スペーサと、前記メモリゲート構造体および前記第2選択ゲート構造体間の前記他の側壁スペーサとには、前記電荷蓄積層が非形成である
ことを特徴とする請求項1~3のうちいずれか1項記載のメモリセル。 - 量子トンネル効果によって前記電荷蓄積層に電荷を注入する前に、前記チャネル電位を、前記ビット線または前記ソース線の電位によって揃える
ことを特徴とする請求項1~4のうちいずれか1項記載のメモリセル。 - 前記第1選択ゲート電極および前記第2選択ゲート電極が前記メモリゲート電極に対してサイドウォール状に形成されている
ことを特徴とする請求項1~5のうちいずれか1項記載のメモリセル。 - メモリウェル表面に形成され、ビット線が接続されたドレイン領域と、
前記メモリウェル表面に形成され、ソース線が接続されたソース領域と、
前記ドレイン領域および前記ソース領域間に形成され、前記メモリウェル上に下部メモリゲート絶縁膜、電荷蓄積層、上部メモリゲート絶縁膜およびメモリゲート電極の順で積層形成されたメモリゲート構造体と、
前記ドレイン領域および前記メモリゲート構造体間の前記メモリウェル上に第1選択ゲート絶縁膜を介して第1選択ゲート電極が形成された構成を有し、前記メモリゲート構造体の一の側壁に一の側壁スペーサを介して隣接した第1選択ゲート構造体と、
前記ソース領域および前記メモリゲート構造体間の前記メモリウェル上に第2選択ゲート絶縁膜を介して第2選択ゲート電極が形成された構成を有し、前記メモリゲート構造体の他の側壁に他の側壁スペーサを介して隣接した第2選択ゲート構造体とを備えており、
前記メモリゲート構造体は、前記メモリゲート電極と前記メモリウェルとが対向した領域にのみ前記電荷蓄積層が形成されており、前記メモリゲート構造体および前記第1選択ゲート構造体間の前記一の側壁スペーサと、前記メモリゲート構造体および前記第2選択ゲート構造体間の前記他の側壁スペーサとには、前記電荷蓄積層が非形成である構成を有し、
前記側壁スペーサを介して前記メモリゲート電極の側壁に沿って対向配置された前記第1選択ゲート電極および前記第2選択ゲート電極が前記メモリゲート電極に対してサイドウォール状に形成されている
ことを特徴とするメモリセル。 - 前記第1選択ゲート電極と前記第2選択ゲート電極との間のメモリウェルは、表面から50[nm]までの領域の不純物濃度が1E19/cm3以下であり、前記第1選択ゲート絶縁膜および前記第2選択ゲート絶縁膜の膜厚が9[nm]以下である
ことを特徴とする請求項1~7のうちいずれか1項記載のメモリセル。 - 前記第1選択ゲート電極と前記第2選択ゲート電極との間のメモリウェルは、表面から50[nm]までの領域の不純物濃度が3E18/cm3以下であり、前記第1選択ゲート絶縁膜および前記第2選択ゲート絶縁膜の膜厚が3[nm]以下である
ことを特徴とする請求項1~7のうちいずれか1項記載のメモリセル。 - ビット線およびソース線が接続されたメモリセルが行列状に配置された不揮発性半導体記憶装置であって、
前記メモリセルが請求項1~9のうちいずれか1項記載のメモリセルである
ことを特徴とする不揮発性半導体記憶装置。 - 前記メモリセルの周辺には周辺回路が設けられており、
前記メモリセルに形成されている前記第1選択ゲート絶縁膜および前記第2選択ゲート絶縁膜の膜厚が、前記周辺回路を構成する電界効果トランジスタのゲート絶縁膜の膜厚のうち、最も薄い膜厚以下に選定されており、かつ、前記第1選択ゲート絶縁膜および前記第2選択ゲート絶縁膜の膜厚が、前記ビット線に接続されたビット電圧印加回路を構成する電界効果トランジスタのゲート絶縁膜と、前記ソース線に接続されたソース電圧印加回路を構成する電界効果トランジスタのゲート絶縁膜との膜厚と同じ膜厚に形成されている
ことを特徴とする請求項10記載の不揮発性半導体記憶装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020177012609A KR102346468B1 (ko) | 2014-10-15 | 2015-10-06 | 메모리 셀 및 불휘발성 반도체 기억 장치 |
CN201580054928.0A CN106796887B (zh) | 2014-10-15 | 2015-10-06 | 存储器单元及非易失性半导体存储装置 |
SG11201703060UA SG11201703060UA (en) | 2014-10-15 | 2015-10-06 | Memory cell and non-volatile semiconductor storage device |
US15/515,199 US10038101B2 (en) | 2014-10-15 | 2015-10-06 | Memory cell and non-volatile semiconductor storage device |
EP15851362.2A EP3232465B1 (en) | 2014-10-15 | 2015-10-06 | Memory cell and non-volatile semiconductor storage device |
IL251710A IL251710B (en) | 2014-10-15 | 2017-04-12 | Memory cell and non-volatile semiconductor storage device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014-211095 | 2014-10-15 | ||
JP2014211095A JP5934324B2 (ja) | 2014-10-15 | 2014-10-15 | メモリセルおよび不揮発性半導体記憶装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016060011A1 true WO2016060011A1 (ja) | 2016-04-21 |
Family
ID=55746558
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2015/078333 WO2016060011A1 (ja) | 2014-10-15 | 2015-10-06 | メモリセルおよび不揮発性半導体記憶装置 |
Country Status (9)
Country | Link |
---|---|
US (1) | US10038101B2 (ja) |
EP (1) | EP3232465B1 (ja) |
JP (1) | JP5934324B2 (ja) |
KR (1) | KR102346468B1 (ja) |
CN (1) | CN106796887B (ja) |
IL (1) | IL251710B (ja) |
SG (1) | SG11201703060UA (ja) |
TW (1) | TWI612523B (ja) |
WO (1) | WO2016060011A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106887432A (zh) * | 2017-03-10 | 2017-06-23 | 上海华力微电子有限公司 | 一种提高sonos器件读取电流的方法 |
JP2017195010A (ja) * | 2016-04-20 | 2017-10-26 | 株式会社フローディア | 不揮発性半導体記憶装置のデータ書き込み方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI733626B (zh) * | 2020-07-07 | 2021-07-11 | 旺宏電子股份有限公司 | 記憶體裝置之操作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002164449A (ja) * | 2000-11-29 | 2002-06-07 | Hitachi Ltd | 半導体装置、icカード及び半導体装置の製造方法 |
JP2005142354A (ja) * | 2003-11-06 | 2005-06-02 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置及びその駆動方法及びその製造方法 |
JP2010028314A (ja) * | 2008-07-16 | 2010-02-04 | Seiko Epson Corp | 画像処理装置及び方法並びにプログラム |
US20140175533A1 (en) * | 2012-12-26 | 2014-06-26 | SK Hynix Inc. | Nonvolatile memory device and method for fabricating the same |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4923318B2 (ja) * | 1999-12-17 | 2012-04-25 | ソニー株式会社 | 不揮発性半導体記憶装置およびその動作方法 |
US20040129986A1 (en) | 2002-11-28 | 2004-07-08 | Renesas Technology Corp. | Nonvolatile semiconductor memory device and manufacturing method thereof |
KR100598107B1 (ko) * | 2004-09-21 | 2006-07-07 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 형성 방법 |
US7829938B2 (en) * | 2005-07-14 | 2010-11-09 | Micron Technology, Inc. | High density NAND non-volatile memory device |
JP2007234861A (ja) * | 2006-03-01 | 2007-09-13 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2008021666A (ja) * | 2006-07-10 | 2008-01-31 | Renesas Technology Corp | 不揮発性半導体記憶装置およびその製造方法 |
US7476588B2 (en) * | 2007-01-12 | 2009-01-13 | Micron Technology, Inc. | Methods of forming NAND cell units with string gates of various widths |
JP2009054707A (ja) | 2007-08-24 | 2009-03-12 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
JP2010278314A (ja) * | 2009-05-29 | 2010-12-09 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP5429305B2 (ja) * | 2009-11-26 | 2014-02-26 | 富士通セミコンダクター株式会社 | 不揮発性半導体記憶装置及びその消去方法 |
JP2011129816A (ja) * | 2009-12-21 | 2011-06-30 | Renesas Electronics Corp | 半導体装置 |
JP5524632B2 (ja) | 2010-01-18 | 2014-06-18 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP5538024B2 (ja) * | 2010-03-29 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 不揮発性半導体記憶装置 |
WO2013075067A1 (en) * | 2011-11-18 | 2013-05-23 | Aplus Flash Technology, Inc. | Low voltage page buffer for use in nonvolatile memory design |
JP2014103204A (ja) * | 2012-11-19 | 2014-06-05 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
KR20150130485A (ko) * | 2013-03-15 | 2015-11-23 | 마이크로칩 테크놀로지 인코포레이티드 | 저전력 판독 경로 및 고전압 소거/기록 경로를 구비한 eeprom 메모리 셀 |
US8945997B2 (en) * | 2013-06-27 | 2015-02-03 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits having improved split-gate nonvolatile memory devices and methods for fabrication of same |
-
2014
- 2014-10-15 JP JP2014211095A patent/JP5934324B2/ja active Active
-
2015
- 2015-10-06 KR KR1020177012609A patent/KR102346468B1/ko active IP Right Grant
- 2015-10-06 EP EP15851362.2A patent/EP3232465B1/en active Active
- 2015-10-06 US US15/515,199 patent/US10038101B2/en active Active
- 2015-10-06 CN CN201580054928.0A patent/CN106796887B/zh active Active
- 2015-10-06 WO PCT/JP2015/078333 patent/WO2016060011A1/ja active Application Filing
- 2015-10-06 SG SG11201703060UA patent/SG11201703060UA/en unknown
- 2015-10-15 TW TW104133904A patent/TWI612523B/zh active
-
2017
- 2017-04-12 IL IL251710A patent/IL251710B/en active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002164449A (ja) * | 2000-11-29 | 2002-06-07 | Hitachi Ltd | 半導体装置、icカード及び半導体装置の製造方法 |
JP2005142354A (ja) * | 2003-11-06 | 2005-06-02 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置及びその駆動方法及びその製造方法 |
JP2010028314A (ja) * | 2008-07-16 | 2010-02-04 | Seiko Epson Corp | 画像処理装置及び方法並びにプログラム |
US20140175533A1 (en) * | 2012-12-26 | 2014-06-26 | SK Hynix Inc. | Nonvolatile memory device and method for fabricating the same |
Non-Patent Citations (1)
Title |
---|
See also references of EP3232465A4 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017195010A (ja) * | 2016-04-20 | 2017-10-26 | 株式会社フローディア | 不揮発性半導体記憶装置のデータ書き込み方法 |
CN106887432A (zh) * | 2017-03-10 | 2017-06-23 | 上海华力微电子有限公司 | 一种提高sonos器件读取电流的方法 |
CN106887432B (zh) * | 2017-03-10 | 2019-08-30 | 上海华力微电子有限公司 | 一种提高sonos器件读取电流的方法 |
Also Published As
Publication number | Publication date |
---|---|
EP3232465A4 (en) | 2018-05-16 |
IL251710B (en) | 2020-07-30 |
JP5934324B2 (ja) | 2016-06-15 |
EP3232465A1 (en) | 2017-10-18 |
SG11201703060UA (en) | 2017-05-30 |
KR102346468B1 (ko) | 2021-12-31 |
CN106796887A (zh) | 2017-05-31 |
CN106796887B (zh) | 2020-09-08 |
EP3232465B1 (en) | 2024-05-08 |
KR20170069256A (ko) | 2017-06-20 |
US10038101B2 (en) | 2018-07-31 |
TW201621908A (zh) | 2016-06-16 |
JP2016082038A (ja) | 2016-05-16 |
US20170222036A1 (en) | 2017-08-03 |
IL251710A0 (en) | 2017-06-29 |
TWI612523B (zh) | 2018-01-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10593687B2 (en) | Semiconductor device and manufacturing method thereof | |
JP5538828B2 (ja) | 半導体装置およびその製造方法 | |
KR20150056049A (ko) | 반도체 장치 및 그 제조 방법 | |
US9214350B2 (en) | Semiconductor device having a capacitive element | |
JP2018056422A (ja) | 半導体装置 | |
WO2016060011A1 (ja) | メモリセルおよび不揮発性半導体記憶装置 | |
JP6613183B2 (ja) | 半導体装置の製造方法 | |
KR100904568B1 (ko) | 불휘발성 반도체 기억 소자 및 불휘발성 반도체 기억 장치 | |
JP2019117913A (ja) | 半導体装置およびその製造方法 | |
JP2010108976A (ja) | 半導体装置およびその製造方法 | |
US20050276117A1 (en) | Ballistic direct injection flash memory cell on strained silicon structures | |
JP6266688B2 (ja) | 不揮発性半導体記憶装置 | |
JP5934416B1 (ja) | メモリセルおよび不揮発性半導体記憶装置 | |
JP5961681B2 (ja) | メモリセル、不揮発性半導体記憶装置およびメモリセルの書き込み方法 | |
KR102667675B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP6783447B2 (ja) | 不揮発性半導体記憶装置のデータ書き込み方法 | |
JP2015015384A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15851362 Country of ref document: EP Kind code of ref document: A1 |
|
DPE1 | Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 15515199 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 251710 Country of ref document: IL |
|
WWE | Wipo information: entry into national phase |
Ref document number: 11201703060U Country of ref document: SG |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 20177012609 Country of ref document: KR Kind code of ref document: A |
|
REEP | Request for entry into the european phase |
Ref document number: 2015851362 Country of ref document: EP |