WO2016038757A1 - Dispositif électroluminescent à semi-conducteurs - Google Patents

Dispositif électroluminescent à semi-conducteurs Download PDF

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Publication number
WO2016038757A1
WO2016038757A1 PCT/JP2015/001130 JP2015001130W WO2016038757A1 WO 2016038757 A1 WO2016038757 A1 WO 2016038757A1 JP 2015001130 W JP2015001130 W JP 2015001130W WO 2016038757 A1 WO2016038757 A1 WO 2016038757A1
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WIPO (PCT)
Prior art keywords
layer
light emitting
semiconductor
insulating member
external connection
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PCT/JP2015/001130
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English (en)
Inventor
Mitsuyoshi Endo
Miyuki SHIMOJUKU
Yukihiro Nomura
Shuji Itonaga
Akihiro Kojima
Hideto Furuyama
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Kabushiki Kaisha Toshiba
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Publication of WO2016038757A1 publication Critical patent/WO2016038757A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • Embodiments described herein relate generally to a semiconductor light emitting device.
  • a semiconductor light emitting device with a chip size package structure in which a fluorescent material layer is provided on one surface side of a semiconductor layer including a light emitting layer and a interconnection layer, an external terminal, and a resin layer are provided on the other surface (mounting surface) side has been proposed.
  • the chip size package may have a problem with a heat radiation property due to a reduction in the area of the external terminal and high thermal resistance of solder.
  • An embodiment of the invention provides a semiconductor light emitting device with an excellent heat radiation property.
  • a semiconductor light emitting device includes a semiconductor layer, an n-side electrode, a p-side electrode, an insulating member, an n-side metal layer, and a p-side metal layer.
  • the semiconductor layer includes a first layer including an n-type semiconductor, a second layer including a p-type semiconductor, and a light emitting layer provided between the first layer and the second layer.
  • the n-side electrode is provided within a region overlapping the semiconductor layer, and in contact with the first layer.
  • the p-side electrode is provided within a region overlapping the semiconductor layer, and in contact with the second layer.
  • the insulating member is provided in an out-of-chip region located further outside than a side surface of the semiconductor layer.
  • the insulating member includes a surface of a portion contiguous to the side surface of the semiconductor layer.
  • the surface of the portion of the insulating member has reflectivity with respect to radiated light of the light emitting layer.
  • the n-side metal layer is in contact with the n-side electrode, and integrally extends to the out-of-chip region from a contact portion between the n-side electrode and the n-side metal layer.
  • the p-side metal layer is in contact with the p-side electrode, and integrally extends to the out-of-chip region from a contact portion between the p-side electrode and the p-side metal layer.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment
  • FIG. 2 is a schematic plan view of a semiconductor light emitting device according to the embodiment
  • FIG. 3 is a schematic cross-sectional view of a semiconductor layer according to the embodiment
  • FIGS. 4A and 4B are schematic views showing a method for manufacturing the semiconductor light emitting device of the embodiment
  • FIGS. 5A and 5B are schematic views showing a method for manufacturing the semiconductor light emitting device of the embodiment
  • FIGS. 6A and 6B are schematic views showing a method for manufacturing the semiconductor light emitting device of the embodiment
  • FIGS. 7A and 7B are schematic views showing a method for manufacturing the semiconductor light emitting device of the embodiment
  • FIGS. 1 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment
  • FIG. 2 is a schematic plan view of a semiconductor light emitting device according to the embodiment
  • FIG. 3 is a schematic cross-sectional view of a semiconductor layer according to the
  • FIGS. 13A and 13B are schematic plan views showing a method for manufacturing the semiconductor light emitting device of the embodiment;
  • FIG. 14 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment;
  • FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the semiconductor light emitting device of the embodiment;
  • FIG. 10 is a schematic cross-sectional view showing a method for manufacturing the semiconductor light emitting device of the embodiment;
  • FIG. 11 is a schematic cross-sectional view showing a method for manufacturing the semiconductor light emitting device of the embodiment;
  • FIG. 12 is a schematic cross-sectional view showing a method for manufacturing the semiconductor light emitting device of the embodiment;
  • FIGS. 13A and 13B are schematic plan views showing a method for manufacturing the semiconductor light emitting device of the embodiment;
  • FIG. 14 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment;
  • FIG. 14 is a schematic cross-sectional view of the semiconductor light emitting device according to the
  • FIG. 15 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 16 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 17 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 18 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 19 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIGS. 20A and 20B are schematic enlarged cross-sectional views of a part of the semiconductor light emitting device according to the embodiment
  • FIG. 21 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 21 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 22 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 23 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 24 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIGS. 25A and 25B are temperature profiles of the semiconductor light emitting device according to the embodiment
  • FIG. 26 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 27 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 28 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIG. 29 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment
  • FIGS. 30A and 30B are schematic cross-sectional views of the semiconductor light emitting device according to the embodiment.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment.
  • FIG. 2 is a schematic plan view of a mounting surface side of the semiconductor light emitting device according to the embodiment and corresponds to a bottom view in FIG. 1.
  • the semiconductor light emitting device includes a chip size device (hereinafter, simply referred to as a chip) 3 formed through wafer leveling, an insulating member 27 which is provided in the vicinity of the chip 3, and metal layers 71 and 72 which are provided on a mounting surface side.
  • a chip size device hereinafter, simply referred to as a chip
  • insulating member 27 which is provided in the vicinity of the chip 3
  • metal layers 71 and 72 which are provided on a mounting surface side.
  • the chip 3 includes electrodes 7 and 8, first interconnection layers (on-chip interconnection layers) 16 and 17, optical layers 30 and 33, and a semiconductor layer 15 which is provided between the first interconnection layers 16 and 17 and the optical layers 30 and 33.
  • FIG. 3 is a schematic enlarged cross-sectional view of the semiconductor layer 15.
  • the semiconductor layer 15 contains, for example, gallium nitride.
  • the semiconductor layer 15 includes a first layer 11 including an n-type semiconductor, a second layer 12 including a p-type semiconductor, and a light emitting layer 13 which is provided between the first layer 11 and the second layer 12.
  • the first layer 11 includes, for example, a foundation buffer layer and an n-type GaN layer.
  • the second layer 12 includes, for example, a p-type GaN layer.
  • the light emitting layer 13 contains a material that emits blue light, purple light, blue-purple light, ultraviolet light, and the like.
  • An emission peak wavelength of the light emitting layer 13 is, for example, 430 nm to 470 nm.
  • the semiconductor layer 15 is epitaxially grown on a substrate 10.
  • the substrate 10 is, for example, a silicon substrate, a sapphire substrate, a silicon carbide substrate, or the like.
  • the first layer 11, the light emitting layer 13, and the second layer 12 are epitaxially grown on the substrate 10 in this order. Thereafter, the second layer 12 and the light emitting layer 13 are selectively removed using a reactive ion etching (RIE) method using a mask not shown in the drawing.
  • RIE reactive ion etching
  • the semiconductor layer 15 includes a region (light emitting region) 15d having laminated films of the second layer 12 and the light emitting layer 13 and a region 15e having a second surface 11a of the first layer 11 which is not covered with the light emitting layer 13 and the second layer 12.
  • FIG. 4B corresponds to a bottom view of the semiconductor layer 15 shown in FIG. 3 and FIG. 4A.
  • the region 15e is formed in the form of an island surrounded by the light emitting region 15d.
  • the region 15e is formed on the outer circumference side of the light emitting region 15d so as to continuously surround the light emitting region 15d.
  • the area of the light emitting region 15d is wider than the area of the region 15e.
  • a first surface 15a which is not covered with the light emitting layer 13 and the second layer 12 is formed on the side of the first layer 11 which is opposite to the second surface 11a.
  • the semiconductor layer 15 has a side surface 15c which is formed so as to be continuous with the first surface 15a.
  • an n-side electrode 8 is provided on the second surface 11a of the first layer 11, and a p-side electrode 7 is provided on the surface of the second layer 12.
  • the p-side electrode 7 and the n-side electrode 8 are formed within a range of a region (chip region) which overlaps the semiconductor layer 15.
  • the area of the p-side electrode 7 is wider than the area of the n-side electrode 8 when seen in a plan view of FIG. 5B.
  • a contact area between the p-side electrode 7 and the second layer 12 is wider than a contact area between the n-side electrode 7 and the first layer 11.
  • an insulating film 14 is provided on the surface of the semiconductor layer 15 other than on the first surface 15a.
  • the insulating film 14 is an inorganic film and is, for example, a silicon oxide film.
  • the insulating film 14 is provided with a first opening 14a that exposes the p-side electrode 7 and a second opening 14b that exposes the n-side electrode 8.
  • a first opening 14a that exposes the p-side electrode 7
  • a second opening 14b that exposes the n-side electrode 8.
  • two n-side second openings 14b are formed so as to be separated from each other.
  • the surface of the p-side electrode 7 between the two second openings 14b is covered with the insulating film 14.
  • the side surface 15c of the first layer 11, the side surface of the second layer 12, and the side surface of the light emitting layer 13 are covered with the insulating film 14.
  • a first p-side interconnection layer 16 and a first n-side interconnection layer 17 are provided on the side of the semiconductor layer 15 which is opposite to the first surface 15a.
  • the first p-side interconnection layer 16 is formed within a range of a region (chip region) which overlaps the semiconductor layer 15.
  • the first p-side interconnection layer 16 is also provided within the first opening 14a and comes into contact with the p-side electrode 7.
  • the first p-side interconnection layer 16 is connected to the p-side electrode 7 through a contact portion 16a which is integrally formed within the first opening 14a. The first p-side interconnection layer 16 does not come into contact with the first layer 11.
  • the first n-side interconnection layer 17 is formed within a range of a region (chip region) which overlaps the semiconductor layer 15.
  • the first n-side interconnection layer 17 is also provided within the second opening 14b and comes into contact with the n-side electrode 8.
  • the first n-side interconnection layer 17 is connected to the n-side electrode 8 through the contact portion 17a which is integrally formed within the second opening 14b.
  • the first n-side interconnection layer 17 is formed in the form of a line pattern extending in a direction in which two island-shaped n-side electrodes 8 are connected to each other.
  • the insulating film 14 is provided between the p-side electrode 7 and a portion of the first n-side interconnection layer 17 between two n-side electrodes 8 and is provided between the second layer 12 and the portion of the first n-side interconnection layer 17 between two n-side electrodes 8.
  • the first n-side interconnection layer 17 does not come into contact with the p-side electrode 7 and the second layer 12.
  • the light emitting region 15d including the light emitting layer 13 occupies most of a planar region of the semiconductor layer 15.
  • the area of the p-side electrode 7 connected to the light emitting region 15d is wider than the area of the n-side electrode 8. Therefore, a wide light emitting surface is obtained, and thus it is possible to make an optical output high.
  • the p-side electrode 7 is provided between the second layer 12 and the first p-side interconnection layer 16. As shown in FIG. 20A, the p-side electrode 7 is laminated films of a plurality of layers (for example, three layers). The p-side electrode 7 includes a first film 7a, a second film 7b, and a third film 7c which are provided in this order from the second layer 12 side.
  • the first film 7a is a silver (Ag) film having a high reflectance with respect to light emitted from the light emitting layer 13 and the fluorescent material layer 30.
  • the second film 7b is a titanium (Ti) film
  • the third film 7c is a platinum (Pt) film.
  • the n-side electrode 8 is provided between the first layer 11 and the contact portion 17a of the first n-side interconnection layer 17. As shown in FIG. 20B, the n-side electrode 8 is laminated films of a plurality of layers (for example, three layers). The n-side electrode 8 includes a first film 8a, a second film 8b, and a third film 8c which are provided in this order from the first layer 11 side.
  • the first film 8a is an aluminum (Al) film having a high reflectance with respect to light emitted from the light emitting layer 13 and the fluorescent material layer 30.
  • the second film 8b is a titanium (Ti) film
  • the third film 8c is a platinum (Pt) film.
  • an insulating film 18 is provided on the surfaces of the first p-side interconnection layer 16 and the first n-side interconnection layer 17.
  • the insulating film 18 is also provided between the first p-side interconnection layer 16 and the first n-side interconnection layer 17.
  • the insulating film 18 is, for example, an inorganic film, and is a silicon oxide film or the like.
  • the insulating film 18 is provided with a first opening 18a that exposes a portion (p-side pad 16b) of the first p-side interconnection layer 16 and a second opening 18b that exposes a portion (n-side pad 17b) of the first n-side interconnection layer 17.
  • the area of the p-side pad 16b is larger than the area of the n-side pad 17b.
  • the area of the n-side pad 17b is wider than the contact area between the first n-side interconnection layer 17 and the n-side electrode 8.
  • the substrate 10 on the first surface 15a is removed as will be described later.
  • An optical layer giving desired optical characteristics to light emitted from the semiconductor light emitting device is provided on the first surface 15a from which the substrate 10 is removed.
  • the fluorescent material layer 30 is provided on the first surface 15a of the semiconductor layer 15, and a transmissive layer (first transmissive layer) 33 is provided on the fluorescent material layer 30.
  • the fluorescent material layer 30 includes a plurality of granular fluorescent materials 31.
  • the fluorescent materials 31 is excited by radiated light of the light emitting layer 13 and radiates light having a wavelength different from that of the radiated light.
  • the plurality of fluorescent materials 31 are dispersed in a binder 32.
  • the binder 32 transmits the radiated light of the light emitting layer 13 and the radiated light of the fluorescent materials 31.
  • the term "transmit" used herein is not limited to a transmittance being 100% and also includes a case where a portion of light is absorbed.
  • a transparent resin such as, for example, a silicone resin can be used as the binder 32.
  • the transmissive layer 33 does not contain fluorescent material particles. In addition, the transmissive layer 33 protects the fluorescent material layer 30 when grinding the surface of the insulating member 27 to be described later.
  • the transmissive layer 33 functions as a light scattering layer. That is, the transmissive layer 33 includes a plurality of granular scattering materials (for example, a silicon oxide and a titanium compound) which scatter the radiated light of the light emitting layer 13 and a binder (for example, a transparent resin) which transmits the radiated light of the light emitting layer 13.
  • a plurality of granular scattering materials for example, a silicon oxide and a titanium compound
  • a binder for example, a transparent resin
  • the insulating member 27 is provided in an out-of-chip region located further outside than the side surface of the semiconductor layer 15.
  • the insulating member 27 is thicker than the semiconductor layer 15 and supports the semiconductor layer 15.
  • the insulating member 27 covers the side surface of the semiconductor layer 15 through the insulating film 14.
  • the insulating member 27 is also provided outside the side surfaces of the optical layers (the fluorescent material layer 30 and the transmissive layer 33) and covers the side surfaces of the optical layers.
  • the insulating member 27 is provided in the vicinity of the chip 3 including the semiconductor layer 15, the electrodes 7 and 8, the first interconnection layers (on-chip interconnection layers) 16 and 17, and the optical layers, and supports the chip 3.
  • An upper face 27a of the insulating member 27 and the upper face of the transmissive layer 33 form a flat surface.
  • An insulating film 26 is provided on the back face of the insulating member 27.
  • a second p-side interconnection layer 21 is provided on the first p-side pad 16b of the first p-side interconnection layer 16.
  • the second p-side interconnection layer 21 comes into contact with the first p-side pad 16b of the first p-side interconnection layer 16 and extends to the out-of-chip region.
  • a portion of the second p-side interconnection layer 21 which extends to the out-of-chip region is supported by the insulating member 27 through the insulating film 26.
  • a portion of the second p-side interconnection layer 21 also extends to a region overlapping the first n-side interconnection layer 17 through the insulating film 18.
  • a second n-side interconnection layer 22 is provided on the first n-side pad 17b of the first n-side interconnection layer 17.
  • the second n-side interconnection layer 22 comes into contact with the first n-side pad 17b of the first n-side interconnection layer 17 and extends to the out-of-chip region.
  • a portion of the second n-side interconnection layer 22 which extends to the out-of-chip region is supported by the insulating member 27 through the insulating film 26.
  • FIG. 13B shows an example of planar layouts of the second p-side interconnection layer 21 and the second n-side interconnection layer 22.
  • the second p-side interconnection layer 21 and the second n-side interconnection layer 22 are disposed asymmetrically with respect to a center line c that divides the planar region of the semiconductor layer 15 into two equal parts, and the lower face (surface on the mounting surface side) of the second p-side interconnection layer 21 is wider than the lower face of the second n-side interconnection layer 22.
  • an insulating film 19 is provided on the surfaces of the second p-side interconnection layer 21 and the second n-side interconnection layer 22.
  • the insulating film 19 is, for example, an inorganic film, and is a silicon oxide film or the like.
  • the insulating film 19 is provided with a first opening 19a that exposes a second p-side pad 21a of the second p-side interconnection layer 21 and a second opening 19b that exposes a second n-side pad 22a of the second n-side interconnection layer 22.
  • a p-side external connection electrode 23 is provided on the second p-side pad 21a of the second p-side interconnection layer 21.
  • the p-side external connection electrode 23 comes into contact with the second p-side pad 21a of the second p-side interconnection layer 21 and is provided on the second p-side interconnection layer 21.
  • a portion of the p-side external connection electrode 23 is also provided in a region overlapping the first n-side interconnection layer 17 through the insulating films 18 and 19 and is provided in a region overlapping the second n-side interconnection layer 22 through the insulating film 19.
  • the p-side external connection electrode 23 extends to the chip region overlapping the semiconductor layer 15 and the out-of-chip region.
  • the p-side external connection electrode 23 is thicker than the first p-side interconnection layer 16 and is thicker than the second p-side interconnection layer 21.
  • An n-side external connection electrode 24 is provided on the second n-side pad 22a of the second n-side interconnection layer 22.
  • the n-side external connection electrode 24 is disposed in the out-of-chip region and comes into contact with the second n-side pad 22a of the second n-side interconnection layer 22.
  • the n-side external connection electrode 24 is thicker than the first n-side interconnection layer 17 and is thicker than the second n-side interconnection layer 22.
  • a resin layer (insulating layer) 25 is provided between the p-side external connection electrode 23 and the n-side external connection electrode 24.
  • the resin layer 25 comes into contact with the side surface of the p-side external connection electrode 23 and the side surface of the n-side external connection electrode 24 and is filled between the p-side external connection electrode 23 and the n-side external connection electrode 24.
  • the resin layer 25 is provided in the vicinity of the p-side external connection electrode 23 and in the vicinity of the n-side external connection electrode 24 and covers the side surface of the p-side external connection electrode 23 and the side surface of the n-side external connection electrode 24.
  • the resin layer 25 increases the mechanical strength of the p-side external connection electrode 23 and the n-side external connection electrode 24.
  • the resin layer 25 functions as a solder resist that prevents the wet spreading of solder during mounting.
  • the lower face of the p-side external connection electrode 23 serves as a p-side mounting surface (p-side external terminal) 23a which is exposed from the resin layer 25 and can be connected to an external circuit such as a mounting substrate.
  • the lower face of the n-side external connection electrode 24 serves as an n-side mounting surface (n-side external terminal) 24a which is exposed from the resin layer 25 and can be connected to an external circuit such as a mounting substrate.
  • the p-side mounting surface 23a and the n-side mounting surface 24a are bonded to a land pattern of the mounting substrate through, for example, solder or a conductive bonding material.
  • the p-side mounting surface 23a and the n-side mounting surface 24a protrude further than the surface of the resin layer 25. Thereby, the solder shape of a connection portion during mounting is stabilized, and thus it is possible to improve the reliability of mounting.
  • FIG. 2 shows an example of planar layouts of the p-side mounting surface 23a and the n-side mounting surface 24a.
  • the p-side mounting surface 23a and the n-side mounting surface 24a are disposed asymmetrically with respect to the center line c that divides the planar region of the semiconductor layer 15 into two equal parts, and the p-side mounting surface 23a is wider than the n-side mounting surface 24a.
  • An interval between the p-side mounting surface 23a and the n-side mounting surface 24a is set to be an interval in which solder does not bridge a space between the p-side mounting surface 23a and the n-side mounting surface 24a during mounting.
  • An n-side electrode contact surface (the second surface 11a of the first layer 11) in the semiconductor layer 15 is rearranged in a wider region including the out-of-chip region by the first n-side interconnection layer 17 and the second n-side interconnection layer 22.
  • a p-side metal layer 71 and an n-side metal layer 72 are provided on the mounting surface side.
  • the p-side metal layer 71 includes the first p-side interconnection layer 16, the second p-side interconnection layer 21, and the p-side external connection electrode 23.
  • the n-side metal layer 72 includes the first n-side interconnection layer 17, the second n-side interconnection layer 22, and the n-side external connection electrode 24.
  • the semiconductor layer 15 is formed on the substrate by an epitaxial growth method.
  • the substrate is removed, and the semiconductor layer 15 does not include the substrate on the first surface 15a side. It is possible to achieve a reduction in the height of the semiconductor light emitting device by removing the substrate. In addition, it is possible to form fine irregularities in the first surface 15a of the semiconductor layer 15 and to achieve an improvement in light extraction efficiency by removing the substrate.
  • the semiconductor layer 15 is supported on a support constituted by a composite body of the metal layers 71 and 72 and the resin layer 25.
  • the semiconductor layer 15 is supported from the side surface thereof by the insulating member 27 which is, for example, a resin layer thicker than the semiconductor layer 15.
  • copper, gold, nickel, or silver can be used as materials of the metal layers 71 and 72.
  • Using copper among these can result in improvements in thermal conductivity, migration resistance, and adhesiveness to an insulating material.
  • the p-side external connection electrode 23, the n-side external connection electrode 24, and the resin layer 25 are formed to have appropriate thicknesses (heights), and thus the p-side external connection electrode 23, the n-side external connection electrode 24, and the resin layer 25 can absorb and relax the stress. In particularly, it is possible to improve the stress relaxation effect by using the resin layer 25, which is more flexible than the semiconductor layer 15, as a portion of the support on the mounting surface side.
  • the metal layers 71 and 72 contain, for example, copper with high thermal conductivity as their main components, and a good thermal conductor extends to the region overlapping the light emitting layer 13 over a wide area. Heat generated from the light emitting layer 13 is radiated to the mounting substrate using a short path formed below the chip through the metal layers 71 and 72.
  • the p-side mounting surface 23a of the p-side metal layer 71 which is connected to the light emitting region 15d of the semiconductor layer 15 overlaps most of the planar region of the semiconductor layer 15 when seen in a plan view shown in FIG. 2, and thus it is possible to radiate heat to the mounting substrate through the p-side metal layer 71 with high efficiency.
  • the p-side mounting surface 23a also extends to the out-of-chip region. Therefore, it is possible to increase the planar size of the solder bonded to the p-side mounting surface 23a and to improve a heat radiation property with respect to the mounting substrate through the solder.
  • the second n-side interconnection layer 22 extends to the out-of-chip region. For this reason, it is possible to dispose the n-side mounting surface 24a in the out-of-chip region without being restricted by the p-side mounting surface 23a which is laid out so as to occupy most of the region overlapping the chip.
  • the n-side mounting surface 24a is disposed in the out-of-chip region, and thus it is possible to further widen the area than in a case where the n-side mounting surface 24a is laid out only in the range of the chip region.
  • n-side it is possible to increase the planar size of the solder bonded to the n-side mounting surface 24a and to improve a heat radiation property with respect to the mounting substrate through the solder.
  • Light radiated to the first surface 15a side from the light emitting layer 13 is incident on the fluorescent material layer 30, and a portion of the light excites the fluorescent materials 31, and thus, for example, white light is obtained as mixed light of the light of the light emitting layer 13 and the light of the fluorescent materials 31.
  • Light radiated to the mounting surface side from the light emitting layer 13 is reflected by the p-side electrode 7 and the n-side electrode 8 and is directed to the side of the fluorescent material layer 30 located at the upper side.
  • the transmissive layer (first transmissive layer) 33 is provided on the fluorescent material layer 30, and a transmissive layer (second transmissive layer) 34 is provided on the transmissive layer 33 and the insulating member 27 in the out-of-chip region.
  • the transmissive layer 34 contains a plurality of granular scattering materials (for example, a silicon oxide) which scatter the radiated light of the light emitting layer 13 and a binder (for example, a transparent resin) which transmits the radiated light of the light emitting layer 13.
  • a binder for example, a transparent resin
  • the transmissive layer 34 functions as a light scattering layer.
  • the planar size of the transmissive layer 34 which is the light scattering layer is larger than the planar size of the fluorescent material layer 30 and the planar size of the transmissive layer 33. That is, the planar size of the transmissive layer 34 is larger than the planar size of the chip 3. Therefore, it is possible to widen the range of light emitted to the outside from the semiconductor light emitting device and to obtain light distribution characteristics with a wide angle.
  • the surface of a portion of the insulating member 27 which is contiguous to at least the side surface of the semiconductor layer 15 has reflectivity with respect to the radiated light of the light emitting layer 13.
  • a portion of the insulating member 27 which is contiguous to the side surface of the fluorescent material layer 30 and a portion of the insulating member which is contiguous to the side surface of the transmissive layer 33 have reflectivity with respect to the radiated light of the light emitting layer 13 and the radiated light of the fluorescent materials 31.
  • the vicinity of a boundary between the insulating member 27 and the transmissive layer 34 has reflectivity with respect to the radiated light of the light emitting layer 13 and the radiated light of the fluorescent materials 31.
  • the insulating member 27 is a resin layer having a reflectance which is not less than 50% with respect to the radiated light of the light emitting layer 13 and the radiated light of the fluorescent materials 31.
  • the fluorescent material layer 30 is formed on the first surface 15a of the semiconductor layer 15 through a wafer leveling process, and the planar size of the fluorescent material layer 30 is substantially the same as the planar size of the semiconductor layer 15 or is slightly larger than the planar size of the semiconductor layer 15.
  • the fluorescent material layer 30 is not formed so as to be wrapped around the side surface of the semiconductor layer 15 and the mounting surface side. That is, the fluorescent material layer 30 is not wastefully formed on the side surface side of the chip and the mounting surface side from which light is not extracted to the outside, and thus it is possible to achieve a reduction in cost.
  • an LED chip is mounted on a mounting substrate through a bump or the like, and then a fluorescent material layer is formed so as to cover the entire chip.
  • a resin is underfilled between bumps.
  • the resin layer 25 different from the fluorescent material layer 30 is provided in the vicinity of the p-side external connection electrode 23 and in the vicinity of the n-side external connection electrode 24 in a state before the mounting shown in FIG. 1, and thus it is possible to give characteristics suitable for stress relaxation to the mounting surface side.
  • the resin layer 25 is already provided on the mounting surface side, underfilling after the mounting becomes unnecessary.
  • the resin layer 25 has a structure in which a resin serving as a base is filled with a filler such as silica particles with high density, and is adjusted so as to have an appropriate hardness as a support.
  • the chip size device 3 is realized at a low cost by collectively forming the semiconductor layer 15, the electrodes 7 and 8, the on-chip interconnection layers 16 and 17, and the optical layer through wafer leveling, and the external terminals (mounting surfaces) 23a and 34a extend to the out-of-chip region, and thus it is possible to increase a heat radiation property. Therefore, it is possible to provide the semiconductor light emitting device with high reliability at a low price.
  • FIG. 4B, FIG. 5B, FIG. 6B, FIG. 7B, FIG. 8B, FIG. 13A, and FIG. 13B correspond to the bottom views of FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9, and FIG. 10, respectively.
  • the semiconductor layer 15 is epitaxially grown on the substrate 10, for example, by a metal organic chemical vapor deposition (MOCVD) method.
  • the substrate 10 is, for example, a silicon substrate.
  • the substrate 10 may be a sapphire substrate or a silicon carbide substrate.
  • the semiconductor layer 15 is, for example, a nitride semiconductor layer containing gallium nitride (GaN).
  • laminated films of the second layer 12 and the light emitting layer 13 is selectively etched by a reactive ion etching (RIE) method, and the second surface 11a of the first layer 11 is exposed as shown in FIGS. 4A and 4B.
  • RIE reactive ion etching
  • the first layer 11 is selectively removed and is divided into the plurality of semiconductor layers 15 in the substrate 10.
  • Grooves for separating the plurality of semiconductor layers 15 are formed, for example, in a grid pattern.
  • the p-side electrode 7 is formed on the surface of the second layer 12, and the n-side electrode 8 is formed on the second surface 11a of the first layer 11.
  • the insulating film 14 is formed so as to cover the semiconductor layer 15 and the electrodes 7 and 8, and then the first opening 14a and the second opening 14b are formed in the insulating film 14.
  • the first p-side interconnection layer 16 and the first n-side interconnection layer 17 are formed.
  • the first p-side interconnection layer 16 is formed within the first opening 14a and comes into contact with the p-side electrode 7.
  • the first n-side interconnection layer 17 is formed within the second opening 14b and comes into contact with the n-side electrode 8. In addition, the first n-side interconnection layer 17 comes into contact with the n-side electrodes 8, for example, at two locations.
  • the first n-side interconnection layer 17 is linearly formed so as to extend in a direction connecting the n-side electrodes 8 positioned at the two locations.
  • the insulating film 14 is interposed between the p-side electrode 7 and the portion of the first n-side interconnection layer 17 which is linearly formed, and the first n-side interconnection layer 17 does not come into contact with the p-side electrode 7.
  • the p-side electrode 7, the n-side electrode 8, the first p-side interconnection layer 16, and the first n-side interconnection layer 17 are formed within a range of a region overlapping the semiconductor layer 15.
  • the insulating film 18 is formed on the surface of the first p-side interconnection layer 16 and the surface of the first n-side interconnection layer 17, and the first opening 18a and the second opening 18b are formed in the insulating film 18.
  • the first p-side pad 16b of the first p-side interconnection layer 16 is exposed by the first opening 18a
  • the first n-side pad 17b of the first n-side interconnection layer 17 is exposed by the second opening 18b.
  • the substrate 10 is removed.
  • the substrate 10 is removed in a state where a stacked body including the semiconductor layer 15 and the interconnection layers 16 and 17 is supported by a temporary support which is not shown in the drawing.
  • the substrate 10 which is a silicon substrate is removed by dry etching such as RIE.
  • the silicon substrate 10 may be removed by wet etching.
  • the substrate can be removed by a laser lift-off method.
  • the semiconductor layer 15 which is epitaxially grown on the substrate 10 may have a large internal stress.
  • the p-side metal layer 71, the n-side metal layer 72, and the resin layer 25 are materials that are flexible as compared with the semiconductor layer 15 formed of, for example, a GaN-based material. Accordingly, even when the internal stress during the epitaxial growth is released at a time during the peeling of the substrate 10, the p-side metal layer 71, the n-side metal layer 72, and the resin layer 25 absorb the stress. Therefore, it is possible to avoid damaging the semiconductor layer 15 in the process of removing the substrate 10.
  • the first surface 15a of the semiconductor layer 15 which is exposed by the removal of the substrate 10 is roughened as necessary.
  • the fluorescent material layer 30 mentioned above is formed on the first surface 15a, and the transmissive layer 33 is formed on the fluorescent material layer 30. These processes are performed in a wafer state.
  • the wafer is diced into a plurality of chips 3.
  • the chip 3 is supported by a temporary support not shown in the drawing.
  • the insulating member (supporting member) 27 is formed in the vicinity (out-of-chip region) of the chip 3 and on the chip 3 (on the transmissive layer 33).
  • the insulating film 26 is formed on the lower face of the insulating member 27 in FIG. 9. Thereby, a step between the chip 3 and the insulating member 27 is removed, and thus it is possible to improve the reliability of a interconnection layer to be formed subsequently.
  • resin materials can be used as the insulating film 26, but an imide-based resin, a phenol-based resin, a silicone-based resin, an epoxy-based resin, and the like which are particularly excellent in heat resistance are suitable.
  • the second p-side interconnection layer 21 is formed on the first p-side pad 16b of the first p-side interconnection layer 16 and on the insulating film 26 in the out-of-chip region.
  • the second n-side interconnection layer 22 is formed on the first n-side pad 17b of the first n-side interconnection layer 17 and on the insulating film 26 in the out-of-chip region.
  • the second n-side interconnection layer 22 is aligned with the chip 3. Since the first n-side pad 17b is rearranged over an area wider than the n-side electrode 8, it is possible to connect the second n-side interconnection layer 22 to the first n-side pad 17b by reliably superimposing the second n-side interconnection layer on the first n-side pad even when the position of the second n-side interconnection layer 22 formed is slightly shifted with respect to the chip 3.
  • the insulating film 19 is formed on the surface of the second p-side interconnection layer 21 and the surface of the second n-side interconnection layer 22, and the first opening 19a and the second opening 19b are formed in the insulating film 19.
  • the second p-side pad 21a of the second p-side interconnection layer 21 is exposed by the first opening 19a.
  • the second n-side pad 22a of the second n-side interconnection layer 22 is exposed by the second opening 19b.
  • the p-side external connection electrode 23 is formed on the second p-side pad 21a.
  • the n-side external connection electrode 24 is formed on the second n-side pad 22a.
  • the resin layer 25 is formed between the p-side external connection electrode 23 and the n-side external connection electrode 24, in the vicinity of the p-side external connection electrode 23, and in the vicinity of the n-side external connection electrode 24.
  • the upper face of the insulating member 27 on the transmissive layer 33 and the upper face of the insulating member 27 in the out-of-chip region are ground.
  • the insulating member 27 on the transmissive layer 33 is removed, and the upper face of the transmissive layer 33 and the upper face of the insulating member 27 in the out-of-chip region are flattened as shown in FIG. 12.
  • the grinding is not performed to the height at which the upper face of the fluorescent material layer 30 is exposed, and the transmissive layer 33 remaining on the fluorescent material layer 30 protects the fluorescent material layer 30.
  • the transmissive layer (scattering layer) 34 having a planar size larger than that of the chip 3 is formed on the flattened upper face of the transmissive layer 33 and the flattened upper face of the insulating member 27.
  • semiconductor light emitting devices of other embodiments will be described with reference to FIGS. 14 to 17.
  • the same components as those of the semiconductor light emitting device shown in FIG. 1 will be denoted by the same reference numerals and signs, and a detailed description thereof will be omitted here.
  • an inorganic film 41 is provided between an insulating member 27 and the side surface of a fluorescent material layer 30 and between the insulating member 27 and the side surface of a transmissive layer 33.
  • an inorganic film 42 is provided between an upper face 27a of the insulating member 27 and a transmissive layer 34.
  • the inorganic film 41 and the inorganic film 42 are, for example, silicon oxide films.
  • the inorganic film 41 increases adhesiveness between the fluorescent material layer 30 and the insulating member (for example, a white resin) 27 and increases adhesiveness between the transmissive layer 33 and the insulating member 27.
  • the inorganic film 42 increases adhesiveness between the insulating member 27 and the transmissive layer 34.
  • the roughening of the side surfaces of optical layers is effective in increasing the adhesiveness to the insulating member 27.
  • a transmissive layer 33 is provided on a first surface 15a of a semiconductor layer 15, and a fluorescent material layer 30 is provided on the transmissive layer 33.
  • adhesiveness between the semiconductor layer 15 and the fluorescent material layer 30 may be increased by forming an inorganic film such as, for example, a silicon oxide film as a transmissive layer between the semiconductor layer 15 and the fluorescent material layer 30.
  • the refractive index of the transmissive layer 33 it is possible to improve the extraction efficiency of light from the semiconductor layer 15 by setting the refractive index of the transmissive layer 33 to a refractive index midway between the refractive index of the semiconductor layer 15 and the refractive index of the fluorescent material layer 30.
  • the semiconductor layer 15 and the fluorescent material layer 30 are separated from each other by the transmissive layer 33, and thus it is possible to reduce a rate at which heat radiated from the fluorescent material layer 30 is transferred to the semiconductor layer 15.
  • a transmissive layer 33 is provided on a first surface 15a of a semiconductor layer 15, and a fluorescent material layer 30 is provided on the transmissive layer 33 and on an insulating member 27 in an out-of-chip region.
  • the transmissive layer 33 is provided in a region surrounded by the insulating member 27, and the fluorescent material layer 30 has a planar size larger than that of the transmissive layer 33.
  • the transmissive layer 33 since light emitted from the semiconductor layer 15 spreads within the fluorescent material layer 30 via the transmissive layer 33, it is possible to widen a light emission range as compared with FIG. 15 mentioned above. Thereby, it is possible to obtain effects such as an improvement in photoelectric conversion efficiency and the dispersion of and reduction in heat generation due to photoconversion in the fluorescent material layer 30.
  • a first transmissive layer 33 is provided on a first surface 15a of a semiconductor layer 15, and a second transmissive layer 34 is provided on the first transmissive layer 33 and on an insulating member 27 in an out-of-chip region.
  • a fluorescent material layer 30 is provided on a second transmissive layer 34.
  • the first transmissive layer 33 is provided in a region surrounded by the insulating member 27, and the second transmissive layer 34 and the fluorescent material layer 30 have planar sizes larger than that of the first transmissive layer 33.
  • An effect of spreading light emitted from the semiconductor layer 15 further than in the example of FIG. 16 is obtained by providing the second transmissive layer 34, and thus it is possible to obtain further effects of improving photoelectric conversion efficiency by the expansion of a light emission range and dispersing and reducing heat generation of the fluorescent material layer 30.
  • an inorganic film 41 may be provided between the insulating member 27 and the side surface of the fluorescent material layer 30 and between the insulating member 27 and the side surface of the transmissive layer 33 as shown in FIG. 21.
  • an inorganic film 41 may be provided between the insulating member 27 and the side surface of the transmissive layer 33, and an inorganic film 42 may be provided between the fluorescent material layer 30 and the upper face of the insulating member 27.
  • an inorganic film 41 may be provided between the insulating member 27 and the side surface of the transmissive layer 33, and an inorganic film 42 may be provided between the transmissive layer 34 and the upper face of the insulating member 27.
  • FIG. 18 is a schematic cross-sectional view of a semiconductor light emitting device of another embodiment.
  • the same components as those in the embodiment shown in FIG. 1 will be denoted by the same reference numerals and signs, and a detailed description thereof will be omitted here.
  • the semiconductor light emitting device shown in FIG. 18 includes a chip 3, an insulating member 27 which is provided in the vicinity of the chip 3, and metal layers 61 and 62 which are provided on the mounting surface side.
  • optical layers such as a fluorescent material layer, a transmissive layer, and a scattering layer.
  • a semiconductor layer 15 has the same configuration as that in the above-described embodiment.
  • a p-side electrode 7 is provided on the surface of a second layer 12 of the semiconductor layer 15, and an n-side electrode 8 is provided on a second surface 11a of a first layer 11.
  • the p-side electrode 7 and the n-side electrode 8 are provided within a range of a region (chip region) which overlaps the semiconductor layer 15.
  • An insulating film 26 is formed on the opposite side to a first surface 15a of the semiconductor layer 15.
  • the insulating film 26 is provided with an opening that exposes the p-side electrode 7 and an opening that exposes the n-side electrode 8.
  • a p-side metal layer 61 and an n-side metal layer 62 are provided on the opposite side to the first surface 15a of the semiconductor layer 15.
  • the p-side metal layer 61 comes into contact with the p-side electrode 7 through the opening formed in the insulating film 26 in the region (chip region) overlapping the semiconductor layer 15 and integrally extends to an out-of-chip region from a contact portion coming into contact with the p-side electrode 7.
  • the p-side metal layer 61 is electrically connected to the second layer 12 through the p-side electrode 7 and does not come into contact with the first layer 11.
  • the n-side metal layer 62 comes into contact with the n-side electrode 8 through the opening formed in the insulating film 26 in the region (chip region) overlapping the semiconductor layer 15 and integrally extends to the out-of-chip region from a contact portion coming into contact with the n-side electrode 8.
  • the n-side metal layer 62 is electrically connected to the first layer 11 through the n-side electrode 8.
  • the insulating film 62 is provided between the n-side metal layer 62 and the p-side electrode 7 and between the n-side metal layer 62 and the second layer 12, and the n-side metal layer 62 does not come into contact with the p-side electrode 7 and the second layer 12.
  • the area of a contact surface between the p-side electrode 7 and the p-side metal layer 61 is wider than the area of a contact surface between the n-side electrode 8 and the n-side metal layer 62.
  • the area of the p-side metal layer 61 is wider than the area of the n-side metal layer 62.
  • the insulating member 27 is provided in an out-of-chip region located further outside than the side surface of the semiconductor layer 15.
  • the insulating member 27 is thicker than the semiconductor layer 15.
  • a portion of the p-side metal layer 61 which extends to the out-of-chip region is supported by the insulating member 27 through the insulating film 26.
  • a portion of the n-side metal layer 62 which extends to the out-of-chip region is supported by the insulating member 27 through the insulating film 26.
  • a p-side external connection electrode 23 is provided on the p-side metal layer 61.
  • the p-side external connection electrode 23 comes into contact with the p-side metal layer 61 and is electrically connected to the p-side metal layer 61.
  • the p-side external connection electrode 23 is thicker than the p-side metal layer 61.
  • the insulating film 45 is provided on the surface of the n-side metal layer 62.
  • the insulating film 45 is, for example, an inorganic film and is a silicon oxide film or the like.
  • the insulating film 45 is provided with an opening that exposes an n-side pad 62b of the n-side metal layer 62.
  • An n-side external connection electrode 24 is provided on the n-side pad 62b.
  • the n-side external connection electrode 24 is disposed in the out-of-chip region and comes into contact with the n-side pad 62b of the n-side metal layer 62 to be electrically connected to the n-side metal layer 62.
  • the n-side external connection electrode 24 is thicker than the n-side metal layer 62.
  • a resin layer 25 is provided between the p-side external connection electrode 23 and the n-side external connection electrode 24.
  • the resin layer 25 comes into contact with the side surface of the p-side external connection electrode 23 and the side surface of the n-side external connection electrode 24 and is filled between the p-side external connection electrode 23 and the n-side external connection electrode 24.
  • the resin layer 25 is provided in the vicinity of the p-side external connection electrode 23 and in the vicinity of the n-side external connection electrode 24 and covers the side surface of the p-side external connection electrode 23 and the side surface of the n-side external connection electrode 24.
  • the lower face of the p-side external connection electrode 23 is exposed from the resin layer 25 and serves as a p-side mounting surface (p-side external terminal) 23a which can be connected to an external circuit such as a mounting substrate.
  • the lower face of the n-side external connection electrode 24 is exposed from the resin layer 25 and serves as an n-side mounting surface (n-side external terminal) 24a which can be connected to an external circuit such as a mounting substrate.
  • the p-side mounting surface 23a and the n-side mounting surface 24a are bonded to a land pattern of the mounting substrate through, for example, solder or a conductive bonding material.
  • the p-side mounting surface 23a and the n-side mounting surface 24a are disposed asymmetrically with respect to a center line that divides the planar region of the semiconductor layer 15 into two equal parts.
  • the p-side mounting surface 23a is wider than the n-side mounting surface 24a.
  • a contact area between the n-side external connection electrode 24 and the n-side pad 62b of the n-side metal layer 62 is larger than a contact area between the n-side electrode 8 and the n-side metal layer 62.
  • An n-side electrode contact surface (the second surface 11a of the first layer 11) in the semiconductor layer 15 is rearranged in a wider region by the n-side metal layer 62.
  • the semiconductor layer 15 is supported on a support constituted by a composite body of the metal layers 61 and 62, the external connection electrodes 23 and 24, and the resin layer 25.
  • the semiconductor layer 15 is supported from the side surface thereof by the insulating member 27 which is, for example, a resin layer thicker than the semiconductor layer 15.
  • copper, gold, nickel, or silver can be used as materials of the metal layers 61 and 62 and the external connection electrodes 23 and 24.
  • Using copper among these can result in improvements in thermal conductivity, migration resistance, and adhesiveness to an insulating material.
  • the p-side external connection electrode 23, the n-side external connection electrode 24, and the resin layer 25 are formed to have appropriate thicknesses (heights), and thus the p-side external connection electrode 23, the n-side external connection electrode 24, and the resin layer 25 can absorb and relax stress applied thereto during mounting. In particular, it is possible to improve the stress relaxation effect by using the resin layer 25, which is more flexible than the semiconductor layer 15, as a portion of the support on the mounting surface side.
  • the metal layers 61 and 62 and the external connection electrodes 23 and 24 contain, for example, copper with high thermal conductivity as their main components, and a good thermal conductor extends to the region overlapping the light emitting layer 13 over a wide area. Heat generated from the light emitting layer 13 is radiated to the mounting substrate using a short path formed below the chip through the metal layers 61 and 62 and the external connection electrodes 23 and 24.
  • the p-side mounting surface 23a connected to a light emitting region of the semiconductor layer 15 overlaps most of the planar region of the semiconductor layer 15, it is possible to radiate heat to the mounting substrate through the p-side metal layer 61 and the p-side external connection electrode 23 with high efficiency.
  • the p-side mounting surface 23a also extends to the out-of-chip region. Therefore, it is possible to increase the planar size of the solder bonded to the p-side mounting surface 23a and to improve a heat radiation property with respect to the mounting substrate through the solder.
  • the n-side metal layer 62 extends to the out-of-chip region. For this reason, it is possible to dispose the n-side mounting surface 24a in the out-of-chip region without being restricted by the p-side mounting surface 23a which is laid out so as to occupy most of the region overlapping the chip.
  • the n-side mounting surface 24a is disposed in the out-of-chip region, and thus it is possible to further widen the area than in a case where the n-side mounting surface 24a is laid out only in the range of the chip region.
  • n-side it is possible to increase the planar size of the solder bonded to the n-side mounting surface 24a and to improve a heat radiation property with respect to the mounting substrate through the solder.
  • the p-side metal layer 61 is integrally extracted right to the side from a portion (on-chip portion) which comes into contact with the p-side electrode 7 and extends to the out-of-chip region.
  • the n-side metal layer 62 is extracted right to the side from a portion (on-chip portion) which comes into contact with the n-side electrode 8 and extends to the out-of-chip region. Therefore, it is possible to effectively release heat of the semiconductor layer 15 to the mounting substrate through a wide mounting surface.
  • the fluorescent material layer 30 is formed through a wafer leveling process and is not formed so as to be wrapped around the side surface of the semiconductor layer 15 and the mounting surface side. For this reason, the fluorescent material layer 30 is not wastefully formed on the side surface side of the chip and the mounting surface side from which light is not extracted, and thus it is possible to achieve a reduction in cost.
  • the resin layer 25 different from the fluorescent material layer 30 is provided in the vicinity of the p-side external connection electrode 23 and in the vicinity of the n-side external connection electrode 24 in a state before the mounting shown in FIG. 18, and thus it is possible to give characteristics suitable for stress relaxation to the mounting surface side.
  • the resin layer 25 is already provided on the mounting surface side, underfilling after the mounting becomes unnecessary.
  • the resin layer 25 has a structure in which a resin serving as a base is filled with a filler such as silica particles with high density, and is adjusted so as to have an appropriate hardness as a support.
  • the chip size device 3 is realized at a low cost by collectively forming the semiconductor layer 15 and the optical layer through wafer leveling, and the metal layers 61 and 62 and the external terminals (mounting surfaces) 23a and 34a extend to the out-of-chip region, and thus it is possible to increase a heat radiation property. Therefore, it is possible to provide the semiconductor light emitting device with high reliability at a low cost.
  • an inorganic film 46 is provided between the insulating member 27 and the side surface of the semiconductor layer 15 and between the insulating member 27 and the side surface of the fluorescent material layer 30 in the device of FIG. 18.
  • the inorganic film 46 which is, for example, a silicon oxide film increases adhesiveness between the semiconductor layer 15 and the insulating member 27 and adhesiveness between the fluorescent material layer 30 and the insulating member 27.
  • a fluorescent material layer is provided on a semiconductor layer including a light emitting layer and a transmissive layer is provided on the fluorescent material layer
  • heat accompanying light emission of the light emitting layer and the fluorescent material layer is transferred to the transmissive layer.
  • the transmissive layer may deteriorate due to heat, and emission characteristics of a semiconductor light emitting device may deteriorate.
  • the deterioration due to heat of the transmissive layer may be a problem in the semiconductor light emitting device having high optical power.
  • a heat insulating layer 51 is provided between the fluorescent material layer 30 and the transmissive layer 33.
  • the heat insulating layer 51 has transmittance with respect to light emitted from the light emitting layer 13 and light emitted from the fluorescent materials 31.
  • the heat insulating layer 51 is formed of a silicon oxide film (SiO 2 film) having a small heat transfer coefficient and high light transmittance using a sputtering method.
  • FIG. 25A is a temperature profile example of layers in a structure in which the heat insulating layer 51 is not provided.
  • FIG. 25B is a temperature profile example of layers in a structure in which the heat insulating layer 51 is provided between the fluorescent material layer 30 and the transmissive layer 33.
  • heat from the semiconductor layer 15 and the fluorescent material layer 30 is not likely to be transferred to the transmissive layer 33 due to providing the heat insulating layer 51.
  • the temperature rise of the transmissive layer 33 is suppressed, and it is possible to prevent the thermal deterioration of the transmissive layer 33.
  • the structure in which the heat insulating layer 51 is provided is particularly suitable for a high-power semiconductor light emitting device.
  • a method of forming the heat insulating layer 51 is not limited to a sputtering method.
  • a deposition method, a plating method, a coating method, a sol-gel method, and the like can be used.
  • the material of the heat insulating layer 51 is not limited to SiO 2 , and it is possible to use various types of oxynitride having high light transmittance and a low heat transfer coefficient (for example, a heat transfer coefficient which is not more than 30 W/(m 2 K)), a heat-resistant resin, and the like.
  • a heat transfer coefficient which is not more than 30 W/(m 2 K) for example, SrTiO 3 , MgO, ZrO 2 , and yttria stabilized zirconia (YSZ) can be used as the material of the heat insulating layer 51.
  • the heat insulating layer 51 may have a porous structure.
  • a heat insulating layer 51 may be provided between the fluorescent material layer 30 and the transmissive layer 33 as shown in FIG. 26.
  • a distance over which light (excitation light) of the light emitting layer 13 travels in the fluorescent material layer 30 in an oblique direction is longer than a distance over which the excitation light travels in the fluorescent material layer 30 in a thickness direction.
  • the excitation light traveling in the fluorescent material layer 30 in an oblique direction excites more fluorescent materials 31.
  • a light beam is a light beam having a larger emission angle among light beams emitted from the fluorescent material layer 30, the light beam has a luminescent color (for example, yellowish) of the fluorescent materials 31.
  • a light extracting surface (top face in FIG. 1) of the semiconductor light emitting device is viewed from an oblique direction, there is a tendency for, for example, dark yellowish light to be seen as compared with a case where the light extracting surface is viewed from right above. That is, color breakup may occur in which the color of light seen varies depending on the angle at which the semiconductor light emitting device is viewed.
  • the fluorescent material layer 30 is provided in the region surrounded by the insulating member 27, and the upper end of the side surface of the insulating member 27 which is contiguous to the fluorescent material layer 30 protrudes further than the upper face of the fluorescent material layer 30.
  • a step is formed between the upper face 27a of the insulating member 27 and the upper face of the fluorescent material layer 30.
  • the vicinity of the fluorescent material layer 30 is surrounded by the insulating member 27. Further, a region of which the vicinity is surrounded by the insulating member 27 is also formed above the fluorescent material layer 30.
  • portions of the insulating member 27 which are contiguous to the side surface of the fluorescent material layer 30 and the side surface of the transmissive layer 33 have reflectivity with respect to the radiated light of the light emitting layer 13 and the radiated light of the fluorescent materials 31.
  • a portion of light emitted from the fluorescent material layer 30 in an oblique direction is directed toward the side surface of the insulating member 27 and is reflected from the side surface of the insulating member 27.
  • the side surface of the insulating member 27 which surrounds the vicinity of the side surfaces of the optical layers (the fluorescent material layer 30 and the transmissive layer 33) is not limited to being perpendicular to a light emitting surface (the first surface 15a of the semiconductor layer 15 or the upper face of the fluorescent material layer 30), and may be oblique as shown in FIG. 27.
  • the width of the region surrounded by the side surface of the insulating member 27 continuously becomes larger from a lower portion to an upper portion on the semiconductor layer 15 side.
  • the upper face and the side surface of the insulating member 27 form an obtuse angle.
  • the width of the region surrounded by the side surface of the insulating member 27 may become larger in a stepwise manner from the lower portion to the upper portion on the semiconductor layer 15 side.
  • the side surface of the insulating member 27 which surrounds the vicinity of the optical layer is inclined, and thus it is possible to achieve a large light distribution angle as compared with a vertical side surface.
  • a space 53 surrounded by the side surface of the insulating member 27 may be provided on the fluorescent material layer 30 without providing a transmissive layer on the fluorescent material layer 30. Also in this structure, oblique light emitted from the fluorescent material layer 30 can be reflected from the side surface of the insulating member 27.
  • a reflection layer 52 different from the insulating member 27 may be provided on the top surface of the insulating member 27.
  • the reflection layer 52 is, for example, an aluminum (Al) layer or a scattering layer containing a light scattering material.
  • Al aluminum
  • the oblique light emitted from the fluorescent material layer 30 can also be reflected from the reflection layer 52.
  • a structure in which the fluorescent material layer 30 is provided within only a region surrounded by the insulating member 27 can result in reductions in the amount of fluorescent material layer 30 used and cost.
  • a structure in which a transmissive layer is not interposed between the semiconductor layer 15 and the fluorescent material layer 30 has a tendency to radiate heat of the fluorescent material layer 30 to the mounting substrate through the semiconductor layer 15 and a metal located below the semiconductor layer. Therefore, it is possible to suppress the temperature rise of the fluorescent material layer 30.
  • the structures shown in FIGS. 18 and 19 include only one optical layer (fluorescent material layer 30) being stacked on the semiconductor layer 15 and are low in cost.
  • the refractive index of the transmissive layer is set to a refractive index midway between the refractive index of the transmissive layer 32 of the fluorescent material layer 30 and the refractive index of air, and thus it is possible to improve light extraction efficiency.
  • the refractive index of the transmissive layer is set to a refractive index midway between the refractive index of the semiconductor layer (for example, GaN) 15 and the refractive index of the transmissive layer 32 of the fluorescent material layer 30, and thus it is possible to improve light extraction efficiency from the semiconductor layer 15. In addition, it is possible to reduce light returning from the fluorescent material layer 30 to the semiconductor layer 15.
  • the area of excitation emission can be enlarged. Therefore, it is possible to improve photoelectric conversion efficiency and to disperse heat of the fluorescent material layer 30.
  • the transmissive layer 34 is provided on the upper face 27a of the insulating member 27 in the vicinity of the chip 3 and the fluorescent material layer 30 is provided on the transmissive layer 34, light spreads laterally within the transmissive layer 34 extending over the entire surface of a package.
  • reflected light from the fluorescent material layer 30 is reflected from the insulating member 27 again and spreads laterally within the transmissive layer 34. Therefore, photoelectric conversion efficiency is further increased.
  • the giving of a scattering property to the transmissive layer 34 results in a further increase in photoelectric conversion efficiency.
  • a sapphire substrate used for the epitaxial growth of the semiconductor layer 15 may be left as a transmissive layer on the first surface 15a.
  • the transmissive layer is not limited to a resin material, and a crystal or glass may be used.
  • the transmissive layer is not limited to a light scattering function, and may have a function as a condensing lens or a diffusion lens.

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Selon un mode de réalisation de l'invention, un dispositif électroluminescent à semi-conducteurs comprend une couche de semi-conducteur, une électrode côté n, une électrode côté p, un élément isolant, une couche métallique côté n et une couche métallique côté p. La couche de semi-conducteur comprend une première couche, une seconde couche et une couche électroluminescente. L'électrode côté n est en contact avec la première couche. L'électrode côté p est en contact avec la seconde couche. L'élément isolant est disposé dans une région hors puce située davantage vers l'extérieur qu'une surface latérale de la couche de semi-conducteur. L'élément isolant comprend une surface d'une partie contigüe à la surface latérale de la couche de semi-conducteur. La surface de la partie de l'élément isolant possède une réflectivité par rapport à une lumière rayonnée de la couche électroluminescente. La couche métallique côté n est en contact avec l'électrode côté n, et s'étend d'un seul tenant vers la région hors puce à partir d'une partie de contact entre l'électrode côté n et la couche métallique côté n. La couche métallique côté p est en contact avec l'électrode côté p, et s'étend d'un seul tenant vers la région hors puce à partir d'une partie de contact entre l'électrode côté p et la couche métallique côté p.
PCT/JP2015/001130 2014-09-12 2015-03-03 Dispositif électroluminescent à semi-conducteurs WO2016038757A1 (fr)

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