WO2016037347A1 - 显示面板测试装置及方法 - Google Patents

显示面板测试装置及方法 Download PDF

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Publication number
WO2016037347A1
WO2016037347A1 PCT/CN2014/086373 CN2014086373W WO2016037347A1 WO 2016037347 A1 WO2016037347 A1 WO 2016037347A1 CN 2014086373 W CN2014086373 W CN 2014086373W WO 2016037347 A1 WO2016037347 A1 WO 2016037347A1
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WO
WIPO (PCT)
Prior art keywords
signal
display panel
tested
control
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/086373
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English (en)
French (fr)
Inventor
王振岭
黄泰钧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/404,640 priority Critical patent/US9626888B2/en
Publication of WO2016037347A1 publication Critical patent/WO2016037347A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes

Definitions

  • the present invention relates to the field of display panel testing, and in particular, to a display panel testing apparatus and method.
  • the test signal is provided to the display panel, and the display panel displays a screen corresponding to the test signal after receiving the test signal.
  • the driving switch circuit for example, the driving transistor
  • Vth switching voltage threshold
  • a display panel testing device includes: an interface circuit for connecting to a display panel to be tested; a test circuit connected to the interface circuit, the test circuit being used for the display panel to be tested Generating a test signal when in a test state, and providing the test signal to the display panel to be tested through the interface circuit, and for generating an adjustment signal when the display panel to be tested is in a predetermined state, and passing through the interface
  • the circuit provides the adjustment signal to the display panel to be tested; wherein the adjustment signal is used to clean at least part of the afterimage signal retained by the display panel to be tested when the display panel to be tested is in the predetermined state;
  • the test circuit includes: a test signal generation circuit for generating the test signal; an adjustment signal generation circuit for generating the adjustment signal; and a selection circuit for receiving the test signal and the adjustment signal, and for Outputting the test signal when the display panel to be tested is in the test state, and for The adjustment signal is output when the display panel to be tested is in the predetermined state; the predetermined state is a shutdown state of
  • the selection circuit includes: a first switch, the first switch includes: a first input end for receiving the test signal; and a first output end for the first switch The test signal is output when the first current channel between the input end and the first output end is turned on; the first control end is configured to receive the first control signal, and control the first according to the first control signal a second switch, the second switch includes: a second input for receiving the adjustment signal; and a second output for the second input and the second The adjusting signal is output when the second current channel between the output ends is turned on; the second control terminal is configured to receive the second control signal, and control the opening or closing of the second current channel according to the second control signal; And a control circuit, configured to be connected to the first control end and the second control end, wherein the control circuit is configured to generate the first control signal and the second control signal.
  • the first control terminal when the display panel to be tested is in the test state, the first control terminal is configured to control the first current channel to be turned on according to the first control signal, and the second The control end is configured to control the second current channel to be closed according to the second control signal; when the display panel to be tested is in the predetermined state, the first control end is configured to be controlled according to the first control signal The first current channel is closed, and the second control terminal is configured to control the second current channel to be turned on according to the second control signal.
  • a display panel testing device includes: an interface circuit for connecting to a display panel to be tested; and a test circuit connected to the interface circuit, the test circuit being used for the Generating a test signal when the test display panel is in a test state, and providing the test signal to the display panel to be tested through the interface circuit, and generating an adjustment signal when the display panel to be tested is in a predetermined state, and passing The interface circuit provides the adjustment signal to the display panel to be tested; wherein the adjustment signal is used to clean at least part of the remaining of the display panel to be tested when the display panel to be tested is in the predetermined state Shadow signal.
  • the predetermined state is a power-on state of the display panel to be tested; the power-on state corresponds to a state in which the display panel to be tested is turned on for a moment or a state in a first predetermined time after power-on. .
  • the test circuit and the interface circuit are configured to control the adjustment signal to reach the display panel to be tested prior to the power-on signal.
  • the predetermined state is a shutdown state of the display panel to be tested; the shutdown state corresponds to a moment when the to-be-tested display panel is turned off or a second predetermined time after shutdown. status.
  • the test circuit includes: a test signal generation circuit for generating the test signal; an adjustment signal generation circuit for generating the adjustment signal; and a selection circuit for receiving The test signal and the adjustment signal are used to output the test signal when the display panel to be tested is in the test state, and to output the same when the display panel to be tested is in the predetermined state Adjust the signal.
  • the selection circuit includes: a first switch, the first switch includes: a first input terminal for receiving the test signal; and a first output terminal for Outputting the test signal when the first current channel between the first input terminal and the first output terminal is turned on; and a first control terminal, configured to receive the first control signal, and according to the first control signal Controlling the opening or closing of the first current channel; a second switch comprising: a second input terminal for receiving the adjustment signal; and a second output terminal for The adjustment signal is output when the second current channel between the second input terminal and the second output terminal is turned on; and a second control terminal is configured to receive the second control signal and control the device according to the second control signal Opening or closing a second current channel; and a control circuit coupled to the first control terminal and the second control terminal, the control circuit configured to generate the first control signal and the second control signal.
  • the first control terminal when the display panel to be tested is in the test state, the first control terminal is configured to control the first current channel to be turned on according to the first control signal, and the second The control end is configured to control the second current channel to be closed according to the second control signal; when the display panel to be tested is in the predetermined state, the first control end is configured to be controlled according to the first control signal The first current channel is closed, and the second control terminal is configured to control the second current channel to be turned on according to the second control signal.
  • the adjustment signal includes: at least one turn-on signal, the turn-on signal is used to turn on the thin film transistor switch of the display panel to be tested; and at least one clean-up signal is used for When the thin film transistor switch is in an on state, it is written into the pixel electrode of the display panel to be tested to clean at least part of the afterimage signal retained by the display panel to be tested.
  • the turn-on signal is a high level signal, and the clear signal is a low level signal;
  • the test circuit is further configured to pass the turn-on signal to a scan line of the display panel to be tested And input to a gate of the thin film transistor switch, and a data line for passing the cleaning signal through the display panel to be tested and the thin film transistor switch to the pixel electrode.
  • the cleaning signal is used to cause at least a portion of the charge of the pixel electrode in the display panel to be tested to disappear or be cancelled, so that the electric field of the pixel electrode in the display panel to be tested is restored To the initial state.
  • the display panel to be tested is an active matrix organic light emitting diode panel
  • the test circuit is further configured to: when the active matrix organic light emitting diode panel is in the predetermined state
  • the source matrix organic light emitting diode panel transmits a suppression signal for providing a driving switch circuit to the active matrix organic light emitting diode panel to suppress a switching voltage threshold shift of the driving switch circuit.
  • the active matrix organic light emitting diode panel includes a driving switch circuit for receiving a power-on signal and a shutdown signal
  • the driving switch circuit includes a triode
  • the triode includes a a third control end, a first end, and a second end, the first end is configured to receive the power-on signal, the second end is configured to receive a power-off signal, and the third control end is respectively separated from the first end Connecting two plates of a capacitor, the second end further connected to a diode;
  • the suppression signal is for providing one end of the diode connected to the second end of the transistor, the suppression signal
  • a positive voltage signal is used to cause the voltage at the second end to be higher than the voltage at the third control terminal to suppress the switching voltage threshold shift.
  • a display panel testing method comprising the steps of: generating, by the test circuit, a test signal when the display panel to be tested is in the test state, and providing the display panel to be tested through the interface circuit And the test circuit generates an adjustment signal when the display panel to be tested is in the predetermined state, and provides the adjustment signal to the display panel to be tested through the interface circuit to clear the to-be-tested At least a portion of the afterimage signal retained by the display panel is tested.
  • the method further includes the following steps: when the display panel to be tested is in the test state, the test signal generation circuit generates the test signal, and the selection circuit receives the test Signaling and outputting the test signal; and when the display panel to be tested is in the predetermined state, the adjustment signal generating circuit generates the adjustment signal, the selection circuit receives the adjustment signal, and outputs the Adjust the signal.
  • the method further includes the following steps: the control circuit generates the first control signal and the second control signal; when the display panel to be tested is in the test state, the first switch The first control terminal receives the first control signal, and controls the first current channel to be turned on according to the first control signal, so that the first output end of the first switch outputs the test signal, and the second switch The second control terminal receives the second control signal, and controls the second current channel to be turned off according to the second control signal; and when the to-be-tested display panel is in the predetermined state, the first control terminal receives the Determining a first control signal, and controlling the first current channel to be turned off according to the first control signal, the second control terminal receiving the second control signal, and controlling the second according to the second control signal The current channel is turned on to cause the second output terminal to output the adjustment signal; wherein the first current channel is an electrical connection between the first input terminal and the first output terminal Channel, the second current path is a current path between said second input terminal and the second output terminal.
  • the adjustment signal includes: at least one turn-on signal, the turn-on signal is used to turn on the thin film transistor switch of the display panel to be tested; and at least one clean-up signal is used for When the thin film transistor switch is in an on state, it is written into the pixel electrode of the display panel to be tested to clean at least part of the afterimage signal retained by the display panel to be tested; the method further includes the following steps: The test circuit inputs the turn-on signal to a gate of the thin film transistor switch through a scan line of the display panel to be tested, and passes the clean signal through the data line of the display panel to be tested and the thin film transistor A switch is input to the pixel electrode.
  • the display panel to be tested is an active matrix organic light emitting diode panel
  • the method further includes the following steps: when the active matrix organic light emitting diode panel is in the predetermined state, The test circuit sends a suppression signal to the active matrix organic light emitting diode panel to suppress a switching voltage threshold shift of the driving switch circuit of the active matrix organic light emitting diode panel.
  • the present invention can make the display panel to be tested not appear after the booting.
  • FIG. 1 is a schematic view of a display panel test device of the present invention for testing a display panel to be tested
  • FIG. 2 is a block diagram of the display panel testing device of FIG. 1;
  • Figure 3 is a block diagram of the test circuit of Figure 2;
  • Figure 4 is a block diagram of the selection circuit of Figure 3;
  • FIG. 5 is a schematic diagram of signals received by the display panel to be tested in different states in FIG. 1;
  • FIG. 6 is a flow chart of a method for testing a display panel of the present invention.
  • Figure 7 is a flow chart showing the working steps of the test circuit of Figure 6;
  • FIG. 8 is a flow chart showing the steps of the test circuit of FIG. 7 outputting a test signal when the display panel to be tested is in a test state;
  • FIG. 9 is a flow chart showing the steps of the test circuit of FIG. 7 outputting an adjustment signal when the display panel to be tested is in a predetermined state.
  • FIG. 1 is a schematic diagram of a display panel testing device 102 of the present invention for testing a display panel 101 to be tested
  • FIG. 2 is a block diagram of the display panel testing device 102 of FIG. 1
  • the display panel to be tested of the present invention may be, for example, an LCD (Liquid Crystal) Display, LCD panel), AMOLED (Active Matrix Organic Light Emitting) Diode, active matrix OLED panel) and other display panels.
  • LCD Liquid Crystal
  • AMOLED Active Matrix Organic Light Emitting
  • OLED panel active matrix OLED panel
  • the display panel testing device 102 of the present invention includes an interface circuit 201 and a test circuit 202.
  • the display panel testing device 102 of the present invention is connected to the display panel 101 to be tested through the interface circuit 201.
  • the display panel testing device 102 of the present invention may further include a machine table for carrying the display panel 101 to be tested, so that the operator can detect the display panel 101 to be tested.
  • the interface circuit 201 is disposed on the carrier platform.
  • the interface circuit 201 is used to connect to the display panel 101 to be tested.
  • the interface circuit 201 includes at least one interface, and at least one of the interfaces interfaces with a signal interface (for example, a test pad (Pad)) in the display panel 101 to be tested.
  • a signal interface for example, a test pad (Pad)
  • the test circuit 202 is connected to the interface circuit 201, and the test circuit 202 is configured to generate a test signal when the display panel 101 to be tested is in a test state (for example, a state of displaying a test screen) 502, and
  • the interface circuit 201 provides the test signal to the display panel 101 to be tested, and is configured to generate an adjustment signal when the display panel 101 to be tested is in a predetermined state (501, 503), and pass through the interface circuit 201
  • the test display panel 101 is described as providing the adjustment signal.
  • the predetermined state (501, 503) is the power on state 501 and/or the power off state 503 of the display panel 101 to be tested.
  • the power-on state 501 corresponds to a state in which the display panel 101 to be tested is turned on for a moment or a state in the first predetermined time after power-on
  • the power-off state 503 corresponds to a state in which the display panel 101 to be tested is turned off for a moment or The state of the second predetermined time after shutdown.
  • the first predetermined time and the second predetermined time may both be in the range of 0.01 seconds to 5 seconds, for example, the first predetermined time, the second predetermined time is 0.02 seconds, 0.035 seconds, 0.050 seconds, 0.08 seconds, 0.09 seconds, 1.12 seconds, 1.20 seconds, 1.25 seconds, 1.38 seconds, 1.45 seconds, 1.56 seconds, 1.69 seconds, 1.72 seconds, 1.85 seconds, 1.99 seconds, 2.03 seconds, 2.13 seconds, 2.30 seconds, 2.41 seconds, 2.55 seconds , 2.64 seconds, 2.73 seconds, 2.89 seconds, 2.96 seconds, 3.10 seconds, 3.30 seconds, 3.35 seconds, 3.51 seconds, 3.60 seconds, 3.73 seconds, 3.87 seconds, 3.95 seconds, 4.03 seconds, 4.20 seconds, 4.29 seconds, 4.36 seconds, 4.51 Any one of seconds, 4.62 seconds, 4.78 seconds, 4.89 seconds, 4.96 seconds, 5 seconds, etc.; the second predetermined time and the first predetermined time may or may not be equal.
  • the predetermined state is the shutdown state 503.
  • the test circuit 202 and the interface circuit 201 are configured to control the adjustment signal to reach the first signal before a power-on signal (eg, a lighting voltage signal (OVDD))
  • a power-on signal eg, a lighting voltage signal (OVDD)
  • the display panel 101 to be tested that is, the test circuit and the interface circuit 201 are used to clear the residual in the display panel 101 to be tested before the display panel 101 to be tested is turned on (lighted) by the adjustment signal. Shadow signal.
  • the adjustment signal is used to clean at least part of the afterimage signal retained by the display panel 101 to be tested when the display panel 101 to be tested is in the predetermined state.
  • the image signal is a signal corresponding to the test screen or other screen remaining after the shutdown of the display panel 101 to be tested, that is, the afterimage signal and the pixel electrode of the display panel 101 to be tested (or The charge remaining in the liquid crystal capacitor) corresponds to the charge associated with the test picture or other picture.
  • the test circuit 202 is configured to provide the adjustment signal to the display panel 101 to be tested through the interface circuit 201 when the display panel 101 to be tested is in the shutdown state 503, so that the test is to be tested.
  • the residual signal (afterimage signal) in the display panel 101 is cleaned so that the image to be tested 101 does not appear to have an afterimage at the next power-on.
  • FIG. 3 is a block diagram of the test circuit 202 of FIG.
  • the test circuit 202 includes a test signal generation circuit 302, an adjustment signal generation circuit 303, and a selection circuit 301.
  • the test signal generation circuit 302 is configured to generate the test signal.
  • the adjustment signal generating circuit 303 is configured to generate the adjustment signal.
  • the selection circuit 301 is configured to receive the test signal and the adjustment signal, and is configured to output the test signal when the display panel 101 to be tested is in the test state 502, and to be used in the display to be tested
  • the adjustment signal is output when the panel 101 is in the predetermined state.
  • the selection circuit 301 is configured to output the test signal to the display panel 101 to be tested through the interface circuit 201 when the display panel 101 to be tested is in the test state 502, and When the display panel 101 to be tested is in the predetermined state, the adjustment signal is output to the display panel 101 to be tested through the interface circuit 201.
  • FIG. 4 is a block diagram of the selection circuit 301 of FIG.
  • the selection circuit 301 includes a first switch 402, a second switch 403, and a control circuit 401.
  • Each of the first switch 402 and the second switch 403 may be a triode, wherein the first switch 402 includes a first input end 4023, a first output end 4021, and a first control end 4022.
  • the second switch 403 includes a second input end 4033, a second output end 4031, and a second control end 4032.
  • the first input terminal 4023 is configured to receive the test signal
  • the first output terminal 4021 is configured to output when the first current channel between the first input terminal 4023 and the first output terminal 4021 is turned on.
  • the test signal, the first control end 4022 is configured to receive the first control signal K1, and control the opening or closing of the first current channel according to the first control signal K1.
  • the second input end 4033 is configured to receive the adjustment signal
  • the second output end 4031 is configured to output when the second current channel between the second input end 4033 and the second output end 4031 is turned on.
  • the adjustment signal, the second control end 4032 is configured to receive the second control signal K2, and control the opening or closing of the second current channel according to the second control signal K2.
  • the control circuit 401 is connected to the first control terminal 4022 and the second control terminal 4032, and the control circuit 401 is configured to generate the first control signal K1 and the second control signal K2.
  • the first control terminal 4022 when the display panel 101 to be tested is in the test state 502, the first control terminal 4022 is configured to control the first current channel to be turned on according to the first control signal K1.
  • the second control end 4032 is configured to control the second current channel to be turned off according to the second control signal K2.
  • the first control terminal 4022 When the display panel 101 to be tested is in the predetermined state, the first control terminal 4022 is configured to control the first current channel to be closed according to the first control signal K1, and the second control terminal 4032 is configured to be used.
  • the second current channel is controlled to be turned on according to the second control signal K2.
  • the first control signal K1 is a low level signal corresponding to the first current channel off
  • the first control signal K1 is a high level signal corresponding to the first current channel opening.
  • the second control signal K2 is a low level signal corresponding to the second current channel off, and the second control signal K2 is a high level signal corresponding to the second current channel opening. vice versa.
  • the adjustment signal includes at least one on signal (G1, G2, G3, etc.) and at least one clear signal (D1, D2, D3, D4, D5, D6, etc.).
  • the turn-on signal is used to turn on the thin film transistor switch of the display panel 101 to be tested.
  • the cleaning signal is used to write to the pixel electrode of the display panel 101 to be tested when the thin film transistor switch is in an on state to clean at least part of the afterimage signal retained by the display panel 101 to be tested. That is, the cleaning signal is used to cause at least a portion of the charge of the pixel electrode in the display panel 101 to be tested to disappear or be cancelled, thereby causing the electric field of the pixel electrode in the display panel 101 to be tested to return to the initial state.
  • the turn-on signal is a high level signal
  • the clear signal is a low level signal. vice versa.
  • the turn-on signals G1, G2, G3 are high level signals when the display panel to be tested is in the predetermined state (the boot state 501 and the power-off state 503).
  • the cleaning signals D1, D2, D3, D4, D5, D6) are low level signals when the display panel to be tested is in the predetermined state (the boot state 501 and the shutdown state 503).
  • the test circuit 202 is further configured to input the turn-on signal to a gate of the thin film transistor switch through a scan line of the display panel 101 to be tested, and to pass the clean-up signal to the display panel to be tested A data line of 101 and the thin film transistor switch are input to the pixel electrode.
  • the display panel to be tested is an active matrix organic light emitting diode panel
  • the active matrix organic light emitting diode panel includes a driving switch circuit
  • the driving switch circuit is configured to receive a power on signal) (OVDD) and a shutdown signal (OVSS)
  • the drive switch circuit includes a triode, the triode includes a third control end, a first end, and a second end, the first end is configured to receive the power-on signal, The second end is configured to receive a shutdown signal, the third control end and the first end are respectively connected to two plates of a capacitor, and the second end is further connected to a diode
  • the test circuit further And transmitting, to the active matrix organic light emitting diode panel, a suppression signal, when the active matrix organic light emitting diode panel is in the predetermined state, the suppression signal is used to provide the active matrix organic light emitting diode panel
  • Vth switching voltage threshold
  • the suppression signal is for providing one end of the diode connected to the second end of the triode
  • the suppression signal is a positive voltage signal
  • the positive voltage signal is used to place the triode in a reverse bias (reverse cutoff/reverse bias) state, that is, causing a voltage of the second end to be higher than a voltage of the third control terminal, thereby suppressing the switching voltage threshold (Vth) offset, improving The service life of the active matrix organic light emitting diode panel.
  • FIG. 6 is a flowchart of a method for testing a display panel of the present invention.
  • the display panel testing method of the present invention (ie, the method in which the display panel testing device 102 tests the display panel 101 to be tested) includes the following steps:
  • Step 601 the test circuit 202 generates a test signal when the display panel 101 to be tested is in the test state 502.
  • Step 602 the test circuit 202 provides the test signal to the display panel 101 to be tested through the interface circuit 201.
  • Step 603 the test circuit 202 generates an adjustment signal when the display panel 101 to be tested is in the predetermined state.
  • step 603 the test circuit 202 provides the adjustment signal to the display panel 101 to be tested through the interface circuit 201 to clean at least part of the afterimage signal retained by the display panel 101 to be tested.
  • step 601 and the step 602 and the step 603 and the step 604 are in no particular order, that is, the step 601 and the step 602 may be performed before the step 603 and the step 604.
  • Step 603 and step 604 may also be performed before the step 601 and the step 602.
  • the step 603 and the step 604 may also be performed simultaneously with the step 601 and the step 602.
  • the predetermined state is the power on state 501 or the power off state 503 of the display panel 101 to be tested.
  • the power-on state 501 corresponds to a state in which the display panel 101 to be tested is turned on for a moment or a state in the first predetermined time after power-on
  • the power-off state 503 corresponds to a state in which the display panel 101 to be tested is turned off for a moment or The state of the second predetermined time after shutdown.
  • the first predetermined time and the second predetermined time may both be in the range of 0.01 seconds to 5 seconds, for example, the first predetermined time, the second predetermined time is 0.02 seconds, 0.035 seconds, 0.050 seconds, 0.08 seconds, 0.09 seconds, 1.12 seconds, 1.20 seconds, 1.25 seconds, 1.38 seconds, 1.45 seconds, 1.56 seconds, 1.69 seconds, 1.72 seconds, 1.85 seconds, 1.99 seconds, 2.03 seconds, 2.13 seconds, 2.30 seconds, 2.41 seconds, 2.55 seconds , 2.64 seconds, 2.73 seconds, 2.89 seconds, 2.96 seconds, 3.10 seconds, 3.30 seconds, 3.35 seconds, 3.51 seconds, 3.60 seconds, 3.73 seconds, 3.87 seconds, 3.95 seconds, 4.03 seconds, 4.20 seconds, 4.29 seconds, 4.36 seconds, 4.51 Any one of seconds, 4.62 seconds, 4.78 seconds, 4.89 seconds, 4.96 seconds, 5 seconds, etc.; the second predetermined time and the first predetermined time may or may not be equal.
  • the predetermined state is the shutdown state 503.
  • the test circuit 202 and the interface circuit 201 control the adjustment signal to reach the display panel 101 to be tested prior to the power-on signal, that is, the test circuit And the interface circuit 201 clears the afterimage signal in the display panel 101 to be tested before the display panel 101 to be tested is turned on (lighted) by the adjustment signal.
  • the adjustment signal is used to clean at least part of the afterimage signal retained by the display panel 101 to be tested when the display panel 101 to be tested is in the predetermined state.
  • the image signal is a signal corresponding to the test screen or other screen remaining after the shutdown of the display panel 101 to be tested, that is, the afterimage signal and the pixel electrode of the display panel 101 to be tested (or The charge remaining in the liquid crystal capacitor) corresponds to the charge associated with the test picture or other picture.
  • the test circuit 202 provides the adjustment signal to the display panel 101 to be tested through the interface circuit 201 when the display panel 101 to be tested is in the shutdown state 503, so that the display panel to be tested The residual signal (afterimage signal) in 101 is cleaned so that the display panel 101 to be tested does not exhibit image sticking at the next power-on.
  • Figure 7 is a flow chart of the operational steps of the test circuit 202 of Figure 6.
  • the method further includes the following steps:
  • Step 701 When the display panel 101 to be tested is in the test state 502, the test signal generation circuit 302 generates the test signal.
  • Step 702 the selection circuit 301 receives the test signal and outputs the test signal.
  • Step 703 when the display panel 101 to be tested is in the predetermined state, the adjustment signal generating circuit 303 generates the adjustment signal.
  • Step 704 the selection circuit 301 receives the adjustment signal, and outputs the adjustment signal.
  • step 701 and the step 702 and the step 703 and the step 704 are in no particular order, that is, the step 701 and the step 702 may be performed before the step 703 and the step 704.
  • Step 703 and step 704 may also be performed before the step 701 and the step 702.
  • the step 703 and the step 704 may also be performed simultaneously with the step 701 and the step 702.
  • the selection circuit 301 outputs the test signal to the display panel 101 to be tested through the interface circuit 201 when the display panel 101 to be tested is in the test state 502, and in the to-be-tested The adjustment signal is output to the display panel 101 to be tested through the interface circuit 201 when the display panel 101 is in the predetermined state.
  • FIG. 8 is a flow chart showing the steps of the test circuit 202 of FIG. 7 outputting a test signal when the display panel 101 to be tested is in the test state 502.
  • the method further includes the following steps:
  • step 801 the control circuit 401 generates the first control signal K1 and the second control signal K2.
  • Step 802 the first control end 4022 of the first switch 402 receives the first control signal K1.
  • Step 803 the first control terminal 4022 controls the first current channel to be turned on according to the first control signal K1, so that the first output terminal 4021 of the first switch 402 outputs the test signal.
  • Step 804 the second control end 4032 of the second switch 403 receives the second control signal K2.
  • Step 804 the second control terminal 4032 controls the second current channel to be turned off according to the second control signal K2.
  • step 802 and the step 803 and the step 804 and the step 805 are in no particular order, that is, the step 802 and the step 803 can be performed before the step 804 and the step 805.
  • Step 804 and step 805 may also be performed before the step 802 and the step 803.
  • the step 804 and the step 805 may also be performed simultaneously with the step 802 and the step 803.
  • the first control signal K1 is a low level signal corresponding to the first current channel off, and the first control signal K1 is a high level signal corresponding to the first current channel opening.
  • the second control signal K2 is a low level signal corresponding to the second current channel off, and the second control signal K2 is a high level signal corresponding to the second current channel opening. vice versa.
  • FIG. 9 is a flow chart showing the steps of the test circuit 202 of FIG. 7 outputting an adjustment signal when the display panel 101 to be tested is in a predetermined state.
  • the method further includes the following steps:
  • Step 901 the control circuit 401 generates the first control signal K1 and the second control signal K2.
  • Step 902 the first control terminal 4022 receives the first control signal K1.
  • Step 903 The first control terminal 4022 controls the first current channel to be turned off according to the first control signal K1.
  • Step 904 the second control end 4032 receives the second control signal K2.
  • Step 905 the second control terminal 4032 controls the second current channel to be turned on according to the second control signal K2, so that the second output terminal 4031 outputs the adjustment signal.
  • the step 902 and the step 903 and the step 904 and the step 905 are in no particular order, that is, the step 902 and the step 903 can be performed before the step 904 and the step 905.
  • the step 904 and the step 905 may also be performed before the step 902 and the step 903.
  • the step 904 and the step 905 may also be performed simultaneously with the step 902 and the step 903.
  • the first current channel is a current channel between the first input terminal 4023 and the first output terminal 4021
  • the second current channel is the second input terminal 4033 and the second output. Current path between terminals 4031.
  • the adjustment signal includes at least one on signal and at least one clear signal.
  • the turn-on signal is used to turn on the thin film transistor switch of the display panel 101 to be tested.
  • the cleaning signal is used to write to the pixel electrode of the display panel 101 to be tested when the thin film transistor switch is in an on state to clean at least part of the afterimage signal retained by the display panel 101 to be tested. That is, the cleaning signal is used to cause at least a portion of the charge of the pixel electrode in the display panel 101 to be tested to disappear or be cancelled, thereby causing the electric field of the pixel electrode in the display panel 101 to be tested to return to the initial state.
  • the turn-on signals (G1, G2, G3) are high level signals when the display panel to be tested is in the predetermined state (the boot state 501 and the shutdown state 503).
  • the cleaning signals (D1, D2, D3, D4, D5, D6) are low level signals when the display panel to be tested is in the predetermined state (the boot state 501 and the shutdown state 503).
  • the method also includes the following steps:
  • the test circuit 202 inputs the turn-on signal to the gate of the thin film transistor switch through the scan line of the display panel 101 to be tested, and passes the clean signal through the data line of the display panel 101 to be tested.
  • the thin film transistor switch is input to the pixel electrode.
  • the display panel to be tested is an active matrix organic light emitting diode panel
  • the active matrix organic light emitting diode panel includes a driving switch circuit
  • the driving switch circuit is configured to receive a power on signal) (OVDD) and a shutdown signal (OVSS)
  • the drive switch circuit includes a triode, the triode includes a third control end, a first end, and a second end, the first end is configured to receive the power-on signal, The second end is configured to receive a shutdown signal, the third control end and the first end are respectively connected to two plates of a capacitor, and the second end is further connected to a diode
  • the method further includes The following steps:
  • the test circuit sends a suppression signal to the active matrix organic light emitting diode panel when the active matrix organic light emitting diode panel is in the predetermined state, and the test circuit provides the suppression signal to the active A matrix OLED panel drives a switching circuit to suppress a switching voltage threshold (Vth) offset of the drive switching circuit.
  • Vth switching voltage threshold
  • the test circuit supplies the suppression signal to one end of the diode connected to the second end of the transistor, the suppression signal is a positive voltage signal, and the positive voltage signal is used to make
  • the triode is in a reverse bias (reverse cutoff/reverse bias) state, that is, the voltage of the second end is higher than the voltage of the third control terminal, thereby suppressing the switching voltage threshold (Vth) bias Moving to increase the service life of the active matrix organic light emitting diode panel.

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Abstract

一种显示面板测试装置及方法,显示面板测试装置包括:接口电路(201),用于与待测试显示面板(101)连接;测试电路(202),用于分别在待测试显示面板(101)处于测试状态(502)或预定状态时生成测试信号或调整信号,并通过接口电路(201)向待测试显示面板(101)提供测试信号或调整信号;其中,调整信号用于清理待测试显示面板(101)保留的至少部分残影信号。

Description

显示面板测试装置及方法 技术领域
本发明涉及显示面板测试领域,特别涉及一种显示面板测试装置及方法。
背景技术
传统的对显示面板的进行测试的技术方案一般为:
将测试信号提供给显示面板,显示面板在接收到测试信号后显示与该测试信号对应的画面。
然而,在对显示面板进行测试的过程中,往往需要对显示面板进行开机和关机操作。
在实践中,发明人发现现有技术至少存在以下问题:
显示面板开机时会显示上次关机时的残影。
此外,在对AMOLED(Active Matrix Organic Light Emitting Diode,有源矩阵有机发光二极管面板)进行测试的过程中,所述AMOLED的驱动开关电路(例如,驱动晶体管)会由于老化而使得开关电压阈值(Vth)发生偏移。
故,有必要提出一种新的技术方案,以解决上述技术问题。
技术问题
本发明的目的在于提供一种显示面板测试装置及方法,其能使得待测试显示面板在开机时不会出现残影。
技术解决方案
一种显示面板测试装置,所述显示面板测试装置包括:接口电路,用于与待测试显示面板连接;测试电路,与所述接口电路连接,所述测试电路用于在所述待测试显示面板处于测试状态时生成测试信号,并通过所述接口电路向所述待测试显示面板提供所述测试信号,以及用于在所述待测试显示面板处于预定状态时生成调整信号,并通过所述接口电路向所述待测试显示面板提供所述调整信号;其中,所述调整信号用于在所述待测试显示面板处于所述预定状态时清理所述待测试显示面板保留的至少部分残影信号;所述测试电路包括:测试信号生成电路,用于生成所述测试信号;调整信号生成电路,用于生成所述调整信号;选择电路,用于接收所述测试信号和所述调整信号,并用于在所述待测试显示面板处于所述测试状态时输出所述测试信号,以及用于在所述待测试显示面板处于所述预定状态时输出所述调整信号;所述预定状态为所述待测试显示面板的关机状态;所述关机状态对应所述待测试显示面板关机时一瞬间的状态或关机后的第二预定时间内的状态;所述第二预定时间处于0.01秒至5秒的范围内。
在上述显示面板测试装置中,所述选择电路包括:第一开关,所述第一开关包括:第一输入端,用于接收所述测试信号;第一输出端,用于在所述第一输入端和所述第一输出端之间的第一电流通道开启时输出所述测试信号;第一控制端,用于接收第一控制信号,并根据所述第一控制信号控制所述第一电流通道的开启或关闭;第二开关,所述第二开关包括:第二输入端,用于接收所述调整信号;第二输出端,用于在所述第二输入端和所述第二输出端之间的第二电流通道开启时输出所述调整信号;第二控制端,用于接收第二控制信号,并根据所述第二控制信号控制所述第二电流通道的开启或关闭;控制电路,与所述第一控制端和所述第二控制端连接,所述控制电路用于生成所述第一控制信号和所述第二控制信号。
在上述显示面板测试装置中,在所述待测试显示面板处于所述测试状态时,所述第一控制端用于根据所述第一控制信号控制所述第一电流通道开启,所述第二控制端用于根据所述第二控制信号控制所述第二电流通道关闭;在所述待测试显示面板处于所述预定状态时,所述第一控制端用于根据所述第一控制信号控制所述第一电流通道关闭,所述第二控制端用于根据所述第二控制信号控制所述第二电流通道开启。
一种显示面板测试装置,所述显示面板测试装置包括:一接口电路,用于与待测试显示面板连接;以及一测试电路,与所述接口电路连接,所述测试电路用于在所述待测试显示面板处于测试状态时生成测试信号,并通过所述接口电路向所述待测试显示面板提供所述测试信号,以及用于在所述待测试显示面板处于预定状态时生成调整信号,并通过所述接口电路向所述待测试显示面板提供所述调整信号;其中,所述调整信号用于在所述待测试显示面板处于所述预定状态时清理所述待测试显示面板保留的至少部分残影信号。
在上述显示面板测试装置中,所述预定状态为所述待测试显示面板的开机状态;所述开机状态对应所述待测试显示面板开机时一瞬间的状态或开机后第一预定时间内的状态。
在上述显示面板测试装置中,在所述预定状态为所述开机状态的情况下,所述测试电路和所述接口电路用于控制所述调整信号先于开机信号到达所述待测试显示面板。
在上述显示面板测试装置中,所述预定状态为所述待测试显示面板的关机状态;所述关机状态对应所述待测试显示面板关机时一瞬间的状态或关机后的第二预定时间内的状态。
在上述显示面板测试装置中,所述测试电路包括:一测试信号生成电路,用于生成所述测试信号;一调整信号生成电路,用于生成所述调整信号;以及一选择电路,用于接收所述测试信号和所述调整信号,并用于在所述待测试显示面板处于所述测试状态时输出所述测试信号,以及用于在所述待测试显示面板处于所述预定状态时输出所述调整信号。
在上述显示面板测试装置中,所述选择电路包括:一第一开关,所述第一开关包括:一第一输入端,用于接收所述测试信号;一第一输出端,用于在所述第一输入端和所述第一输出端之间的第一电流通道开启时输出所述测试信号;以及一第一控制端,用于接收第一控制信号,并根据所述第一控制信号控制所述第一电流通道的开启或关闭;一第二开关,所述第二开关包括:一第二输入端,用于接收所述调整信号;一第二输出端,用于在所述第二输入端和所述第二输出端之间的第二电流通道开启时输出所述调整信号;以及一第二控制端,用于接收第二控制信号,并根据所述第二控制信号控制所述第二电流通道的开启或关闭;以及一控制电路,与所述第一控制端和所述第二控制端连接,所述控制电路用于生成所述第一控制信号和所述第二控制信号。
在上述显示面板测试装置中,在所述待测试显示面板处于所述测试状态时,所述第一控制端用于根据所述第一控制信号控制所述第一电流通道开启,所述第二控制端用于根据所述第二控制信号控制所述第二电流通道关闭;在所述待测试显示面板处于所述预定状态时,所述第一控制端用于根据所述第一控制信号控制所述第一电流通道关闭,所述第二控制端用于根据所述第二控制信号控制所述第二电流通道开启。
在上述显示面板测试装置中,所述调整信号包括:至少一开启信号,所述开启信号用于开启所述待测试显示面板的薄膜晶体管开关;以及至少一清理信号,所述清理信号用于在所述薄膜晶体管开关处于开启状态时写入到所述待测试显示面板的像素电极中,以清理所述待测试显示面板保留的至少部分所述残影信号。
在上述显示面板测试装置中,所述开启信号为高电平信号,所述清理信号为低电平信号;所述测试电路还用于将所述开启信号通过所述待测试显示面板的扫描线输入至所述薄膜晶体管开关的栅极,以及用于将所述清理信号通过所述待测试显示面板的数据线和所述薄膜晶体管开关输入至所述像素电极。
在上述显示面板测试装置中,所述清理信号用于使得所述待测试显示面板中的像素电极的电荷的至少一部分消失或被抵消,以使得所述待测试显示面板中的像素电极的电场恢复至初始状态。
在上述显示面板测试装置中,所述待测试显示面板为有源矩阵有机发光二极管面板,所述测试电路还用于在所述有源矩阵有机发光二极管面板处于所述预定状态时向所述有源矩阵有机发光二极管面板发送一抑制信号,所述抑制信号用于提供给所述有源矩阵有机发光二极管面板的驱动开关电路,以抑制所述驱动开关电路的开关电压阈值偏移。
在上述显示面板测试装置中,所述有源矩阵有机发光二极管面板包括驱动开关电路,所述驱动开关电路用于接收开机信号和关机信号,所述驱动开关电路包括一个三极管,所述三极管包括一第三控制端、第一末端、第二末端,所述第一末端用于接收所述开机信号,所述第二末端用于接收关机信号,所述第三控制端与所述第一末端分别连接一个电容的两块极板,所述第二末端还与一个二极管连接;所述抑制信号用于提供给与所述三极管的所述第二末端连接的所述二极管的一端,所述抑制信号为正电压信号,所述正电压信号用于使得所述第二末端的电压比所述第三控制端的电压高,以抑制所述开关电压阈值偏移。
一种显示面板测试方法,所述方法包括以下步骤:所述测试电路在所述待测试显示面板处于所述测试状态时生成测试信号,并通过所述接口电路向所述待测试显示面板提供所述测试信号;以及所述测试电路在所述待测试显示面板处于所述预定状态时生成调整信号,并通过所述接口电路向所述待测试显示面板提供所述调整信号,以清理所述待测试显示面板保留的至少部分所述残影信号。
在上述显示面板测试方法中,所述方法还包括以下步骤:在所述待测试显示面板处于所述测试状态时,所述测试信号生成电路生成所述测试信号,所述选择电路接收所述测试信号,并输出所述测试信号;以及在所述待测试显示面板处于所述预定状态时,所述调整信号生成电路生成所述调整信号,所述选择电路接收所述调整信号,并输出所述调整信号。
在上述显示面板测试方法中,所述方法还包括以下步骤:控制电路生成所述第一控制信号和所述第二控制信号;在所述待测试显示面板处于所述测试状态时,第一开关的第一控制端接收所述第一控制信号,并根据所述第一控制信号控制第一电流通道开启,以使所述第一开关的第一输出端输出所述测试信号,第二开关的第二控制端接收所述第二控制信号,并根据所述第二控制信号控制第二电流通道关闭;以及在所述待测试显示面板处于所述预定状态时,所述第一控制端接收所述第一控制信号,并根据所述第一控制信号控制所述第一电流通道关闭,所述第二控制端接收所述第二控制信号,并根据所述第二控制信号控制所述第二电流通道开启,以使所述第二输出端输出所述调整信号;其中,所述第一电流通道为所述第一输入端和所述第一输出端之间的电流通道,所述第二电流通道为所述第二输入端和所述第二输出端之间的电流通道。
在上述显示面板测试方法中,所述调整信号包括:至少一开启信号,所述开启信号用于开启所述待测试显示面板的薄膜晶体管开关;以及至少一清理信号,所述清理信号用于在所述薄膜晶体管开关处于开启状态时写入到所述待测试显示面板的像素电极中,以清理所述待测试显示面板保留的至少部分所述残影信号;所述方法还包括以下步骤:所述测试电路将所述开启信号通过所述待测试显示面板的扫描线输入至所述薄膜晶体管开关的栅极,以及将所述清理信号通过所述待测试显示面板的数据线和所述薄膜晶体管开关输入至所述像素电极。
在上述显示面板测试方法中,所述待测试显示面板为有源矩阵有机发光二极管面板,所述方法还包括以下步骤:在所述有源矩阵有机发光二极管面板处于所述预定状态时,所述测试电路向所述有源矩阵有机发光二极管面板发送一抑制信号,以抑制所述有源矩阵有机发光二极管面板的驱动开关电路的开关电压阈值偏移。
有益效果
相对现有技术,本发明可以使得待测试显示面板在开机时不会出现残影。
附图说明
图1为本发明的显示面板测试装置测试待测试显示面板的示意图;
图2为图1中的显示面板测试装置的框图;
图3为图2中的测试电路的框图;
图4为图3中的选择电路的框图;
图5为图1中的待测试显示面板在不同状态下所接收到的信号的示意图;
图6为本发明的显示面板测试方法的流程图;
图7为图6中的测试电路的工作步骤的流程图;
图8为图7中测试电路在待测试显示面板处于测试状态时输出测试信号的步骤的流程图;
图9为图7中测试电路在待测试显示面板处于预定状态时输出调整信号的步骤的流程图。
本发明的最佳实施方式
以下各实施例的说明是参考附加的图式,用以例示本发明可用以实施的特定实施例。
参考图1、图2和图5,图1为本发明的显示面板测试装置102测试待测试显示面板101的示意图,图2为图1中的显示面板测试装置102的框图,图5为图1中的待测试显示面板在不同状态下所接收到的信号的示意图。
本发明的待测试显示面板可以是诸如LCD(Liquid Crystal Display,液晶显示面板)、AMOLED(Active Matrix Organic Light Emitting Diode,有源矩阵有机发光二极管面板)等显示面板。
本发明的显示面板测试装置102包括接口电路201和测试电路202。本发明的显示面板测试装置102通过所述接口电路201与所述待测试显示面板101连接。本发明的显示面板测试装置102还可以包括机台,所述机台用于承载所述待测试显示面板101,以便于操作员对所述待测试显示面板101进行检测。
所述接口电路201设置于所述承载机台上。所述接口电路201用于与待测试显示面板101连接。具体地,所述接口电路201包括至少一个接口,至少一个所述接口与所述待测试显示面板101中的信号接口(例如,测试垫(Pad))对接。所述测试电路202与所述接口电路201连接,所述测试电路202用于在所述待测试显示面板101处于测试状态(例如,显示测试画面的状态)502时生成测试信号,并通过所述接口电路201向所述待测试显示面板101提供所述测试信号,以及用于在所述待测试显示面板101处于预定状态(501,503)时生成调整信号,并通过所述接口电路201向所述待测试显示面板101提供所述调整信号。
其中,所述预定状态(501,503)为所述待测试显示面板101的开机状态501和/或关机状态503。所述开机状态501对应所述待测试显示面板101开机时一瞬间的状态或开机后第一预定时间内的状态,所述关机状态503对应所述待测试显示面板101关机时一瞬间的状态或关机后的第二预定时间内的状态。所述第一预定时间和所述第二预定时间均可处于0.01秒至5秒的范围内,例如,所述第一预定时间、所述第二预定时间为0.02秒,0.035秒,0.050秒,0.08秒,0.09秒,1.12秒,1.20秒,1.25秒,1.38秒,1.45秒,1.56秒,1.69秒,1.72秒,1.85秒,1.99秒,2.03秒,2.13秒,2.30秒,2.41秒,2.55秒,2.64秒,2.73秒,2.89秒,2.96秒,3.10秒,3.30秒,3.35秒,3.51秒,3.60秒,3.73秒,3.87秒,3.95秒,4.03秒,4.20秒,4.29秒,4.36秒,4.51秒,4.62秒,4.78秒,4.89秒,4.96秒,5秒等中的任意一者;所述第二预定时间和所述第一预定时间可以相等,也可以不相等。
优选地,所述预定状态为所述关机状态503。
在所述预定状态为所述开机状态501的情况下,所述测试电路202和所述接口电路201用于控制所述调整信号先于开机信号(例如,发光电压信号(OVDD))到达所述待测试显示面板101,即,所述测试线路和所述接口电路201用于通过所述调整信号在所述待测试显示面板101开机(点亮)之前清理所述待测试显示面板101中的残影信号。
其中,所述调整信号用于在所述待测试显示面板101处于所述预定状态时清理所述待测试显示面板101保留的至少部分残影信号。所述残影信号是所述待测试显示面板101在关机后残留的所述测试画面或其它画面所对应的信号,即,所述残影信号与所述待测试显示面板101的像素电极(或液晶电容)中残留的与所述测试画面或其它画面相关的电荷对应。
例如,所述测试电路202用于在所述待测试显示面板101处于所述关机状态503时通过所述接口电路201向所述待测试显示面板101提供所述调整信号,以使得所述待测试显示面板101中的残留信号(残影信号)被清理,从而使得所述待测试显示面板101在下一次开机时不出现残影。
参考图3,图3为图2中的测试电路202的框图。在本实施例中,所述测试电路202包括测试信号生成电路302、调整信号生成电路303和选择电路301。
所述测试信号生成电路302用于生成所述测试信号。所述调整信号生成电路303用于生成所述调整信号。
所述选择电路301用于接收所述测试信号和所述调整信号,并用于在所述待测试显示面板101处于所述测试状态502时输出所述测试信号,以及用于在所述待测试显示面板101处于所述预定状态时输出所述调整信号。具体地,所述选择电路301用于在所述待测试显示面板101处于所述测试状态502时将所述测试信号通过所述接口电路201输出至所述待测试显示面板101,以及用于在所述待测试显示面板101处于所述预定状态时将所述调整信号通过所述接口电路201输出至所述待测试显示面板101。
参考图4,图4为图3中的选择电路301的框图。在本实施例中,所述选择电路301包括第一开关402、第二开关403和控制电路401。所述第一开关402和所述第二开关403均可以是三极管,其中,所述第一开关402包括第一输入端4023、第一输出端4021和第一控制端4022。所述第二开关403包括第二输入端4033、第二输出端4031和第二控制端4032。
所述第一输入端4023用于接收所述测试信号,所述第一输出端4021用于在所述第一输入端4023和所述第一输出端4021之间的第一电流通道开启时输出所述测试信号,所述第一控制端4022用于接收第一控制信号K1,并根据所述第一控制信号K1控制所述第一电流通道的开启或关闭。
所述第二输入端4033用于接收所述调整信号,所述第二输出端4031用于在所述第二输入端4033和所述第二输出端4031之间的第二电流通道开启时输出所述调整信号,所述第二控制端4032用于接收第二控制信号K2,并根据所述第二控制信号K2控制所述第二电流通道的开启或关闭。
所述控制电路401与所述第一控制端4022和所述第二控制端4032连接,所述控制电路401用于生成所述第一控制信号K1和所述第二控制信号K2。
在本实施例中,在所述待测试显示面板101处于所述测试状态502时,所述第一控制端4022用于根据所述第一控制信号K1控制所述第一电流通道开启,所述第二控制端4032用于根据所述第二控制信号K2控制所述第二电流通道关闭。在所述待测试显示面板101处于所述预定状态时,所述第一控制端4022用于根据所述第一控制信号K1控制所述第一电流通道关闭,所述第二控制端4032用于根据所述第二控制信号K2控制所述第二电流通道开启。例如,所述第一控制信号K1为低电平信号与所述第一电流通道关闭对应,所述第一控制信号K1为高电平信号与所述第一电流通道开启对应。所述第二控制信号K2为低电平信号与所述第二电流通道关闭对应,所述第二控制信号K2为高电平信号与所述第二电流通道开启对应。反之亦然。
在本实施例中,所述调整信号包括至少一开启信号(G1、G2、G3,等等)和至少一清理信号(D1、D2、D3、D4、D5、D6,等等)。所述开启信号用于开启所述待测试显示面板101的薄膜晶体管开关。所述清理信号用于在所述薄膜晶体管开关处于开启状态时写入到所述待测试显示面板101的像素电极中,以清理所述待测试显示面板101保留的至少部分所述残影信号,即,所述清理信号用于使得所述待测试显示面板101中的像素电极的电荷的至少一部分消失或被抵消,从而使得所述待测试显示面板101中的像素电极的电场恢复至初始状态。
在本实施例中,所述开启信号为高电平信号,所述清理信号为低电平信号。反之亦然。例如,如图5所示,开启信号(G1、G2、G3)在所述待测试显示面板处于所述预定状态(所述开机状态501和所述关机状态503)时均为高电平信号,所述清理信号(D1、D2、D3、D4、D5、D6)在所述待测试显示面板处于所述预定状态(所述开机状态501和所述关机状态503)时均为低电平信号。
所述测试电路202还用于将所述开启信号通过所述待测试显示面板101的扫描线输入至所述薄膜晶体管开关的栅极,以及用于将所述清理信号通过所述待测试显示面板101的数据线和所述薄膜晶体管开关输入至所述像素电极。
通过上述技术方案,可以使得在所述待测试显示面板101关机(测试完)后,残留于像素电极中的与所述测试画面或其它画面相关的电荷被清理,即,使得所述像素电极的电场恢复至初始状态,因此,可以使得待测试显示面板在开机时不会出现残影。
作为一种改进,在所述待测试显示面板为有源矩阵有机发光二极管面板的情况下(其中,所述有源矩阵有机发光二极管面板包括驱动开关电路,所述驱动开关电路用于接收开机信号(OVDD)和关机信号(OVSS),所述驱动开关电路包括一个三极管,所述三极管包括一第三控制端、第一末端、第二末端,所述第一末端用于接收所述开机信号,所述第二末端用于接收关机信号,所述第三控制端与所述第一末端分别连接一个电容的两块极板,所述第二末端还与一个二极管连接),所述测试电路还用于在所述有源矩阵有机发光二极管面板处于所述预定状态时向所述有源矩阵有机发光二极管面板发送一抑制信号,所述抑制信号用于提供给所述有源矩阵有机发光二极管面板的驱动开关电路,以抑制所述驱动开关电路的开关电压阈值(Vth)偏移。术语“偏移”是指偏离正常(预定)值。
具体地,所述抑制信号用于提供给与所述三极管的所述第二末端连接的所述二极管的一端,所述抑制信号为正电压信号,所述正电压信号用于使得所述三极管处于反向偏制(反向截止/反向偏压)状态,即,使得所述第二末端的电压比所述第三控制端的电压高,从而抑制所述开关电压阈值(Vth)偏移,提高所述有源矩阵有机发光二极管面板的使用寿命。
参考图6,图6为本发明的显示面板测试方法的流程图。本发明的显示面板测试方法(即,显示面板测试装置102测试待测试显示面板101的方法)包括以下步骤:
步骤601,所述测试电路202在所述待测试显示面板101处于所述测试状态502时生成测试信号。
步骤602,所述测试电路202通过所述接口电路201向所述待测试显示面板101提供所述测试信号。
步骤603,所述测试电路202在所述待测试显示面板101处于所述预定状态时生成调整信号。
步骤603,所述测试电路202通过所述接口电路201向所述待测试显示面板101提供所述调整信号,以清理所述待测试显示面板101保留的至少部分所述残影信号。
所述步骤601和所述步骤602以及所述步骤603和所述步骤604不分先后次序,即,所述步骤601和所述步骤602可以先于所述步骤603和所述步骤604执行,所述步骤603和所述步骤604也可以先于所述步骤601和所述步骤602执行,所述步骤603和所述步骤604也可以与所述步骤601和所述步骤602同时执行。
其中,所述预定状态为所述待测试显示面板101的开机状态501或关机状态503。所述开机状态501对应所述待测试显示面板101开机时一瞬间的状态或开机后第一预定时间内的状态,所述关机状态503对应所述待测试显示面板101关机时一瞬间的状态或关机后的第二预定时间内的状态。所述第一预定时间和所述第二预定时间均可处于0.01秒至5秒的范围内,例如,所述第一预定时间、所述第二预定时间为0.02秒,0.035秒,0.050秒,0.08秒,0.09秒,1.12秒,1.20秒,1.25秒,1.38秒,1.45秒,1.56秒,1.69秒,1.72秒,1.85秒,1.99秒,2.03秒,2.13秒,2.30秒,2.41秒,2.55秒,2.64秒,2.73秒,2.89秒,2.96秒,3.10秒,3.30秒,3.35秒,3.51秒,3.60秒,3.73秒,3.87秒,3.95秒,4.03秒,4.20秒,4.29秒,4.36秒,4.51秒,4.62秒,4.78秒,4.89秒,4.96秒,5秒等中的任意一者;所述第二预定时间和所述第一预定时间可以相等,也可以不相等。
优选地,所述预定状态为所述关机状态503。
在所述预定状态为所述开机状态501的情况下,所述测试电路202和所述接口电路201控制所述调整信号先于开机信号到达所述待测试显示面板101,即,所述测试线路和所述接口电路201通过所述调整信号在所述待测试显示面板101开机(点亮)之前清理所述待测试显示面板101中的残影信号。
所述调整信号用于在所述待测试显示面板101处于所述预定状态时清理所述待测试显示面板101保留的至少部分残影信号。所述残影信号是所述待测试显示面板101在关机后残留的所述测试画面或其它画面所对应的信号,即,所述残影信号与所述待测试显示面板101的像素电极(或液晶电容)中残留的与所述测试画面或其它画面相关的电荷对应。
例如,所述测试电路202在所述待测试显示面板101处于所述关机状态503时通过所述接口电路201向所述待测试显示面板101提供所述调整信号,以使得所述待测试显示面板101中的残留信号(残影信号)被清理,从而使得所述待测试显示面板101在下一次开机时不出现残影。
参考图7,图7为图6中的测试电路202的工作步骤的流程图。在本实施例中,所述方法还包括以下步骤:
步骤701,在所述待测试显示面板101处于所述测试状态502时,所述测试信号生成电路302生成所述测试信号。
步骤702,所述选择电路301接收所述测试信号,并输出所述测试信号。
步骤703,在所述待测试显示面板101处于所述预定状态时,所述调整信号生成电路303生成所述调整信号。
步骤704,所述选择电路301接收所述调整信号,并输出所述调整信号。
所述步骤701和所述步骤702以及所述步骤703和所述步骤704不分先后次序,即,所述步骤701和所述步骤702可以先于所述步骤703和所述步骤704执行,所述步骤703和所述步骤704也可以先于所述步骤701和所述步骤702执行,所述步骤703和所述步骤704也可以与所述步骤701和所述步骤702同时执行。
具体地,所述选择电路301在所述待测试显示面板101处于所述测试状态502时将所述测试信号通过所述接口电路201输出至所述待测试显示面板101,以及在所述待测试显示面板101处于所述预定状态时将所述调整信号通过所述接口电路201输出至所述待测试显示面板101。
参考图8,图8为图7中测试电路202在待测试显示面板101处于测试状态502时输出测试信号的步骤的流程图。在本实施例中,在所述待测试显示面板101处于所述测试状态502时,所述方法还包括以下步骤:
步骤801,控制电路401生成所述第一控制信号K1和所述第二控制信号K2。
步骤802,第一开关402的第一控制端4022接收所述第一控制信号K1。
步骤803,所述第一控制端4022根据所述第一控制信号K1控制第一电流通道开启,以使所述第一开关402的第一输出端4021输出所述测试信号。
步骤804,第二开关403的第二控制端4032接收所述第二控制信号K2。
步骤804,所述第二控制端4032根据所述第二控制信号K2控制第二电流通道关闭。
所述步骤802和所述步骤803以及所述步骤804和所述步骤805不分先后次序,即,所述步骤802和所述步骤803可以先于所述步骤804和所述步骤805执行,所述步骤804和所述步骤805也可以先于所述步骤802和所述步骤803执行,所述步骤804和所述步骤805也可以与所述步骤802和所述步骤803同时执行。
例如,所述第一控制信号K1为低电平信号与所述第一电流通道关闭对应,所述第一控制信号K1为高电平信号与所述第一电流通道开启对应。所述第二控制信号K2为低电平信号与所述第二电流通道关闭对应,所述第二控制信号K2为高电平信号与所述第二电流通道开启对应。反之亦然。
参考图9,图9为图7中测试电路202在待测试显示面板101处于预定状态时输出调整信号的步骤的流程图。在所述待测试显示面板101处于所述预定状态时,所述方法还包括以下步骤:
步骤901,所述控制电路401生成所述第一控制信号K1和所述第二控制信号K2。
步骤902,所述第一控制端4022接收所述第一控制信号K1。
步骤903,所述第一控制端4022根据所述第一控制信号K1控制所述第一电流通道关闭。
步骤904,所述第二控制端4032接收所述第二控制信号K2。
步骤905,所述第二控制端4032根据所述第二控制信号K2控制所述第二电流通道开启,以使所述第二输出端4031输出所述调整信号。
所述步骤902和所述步骤903以及所述步骤904和所述步骤905不分先后次序,即,所述步骤902和所述步骤903可以先于所述步骤904和所述步骤905执行,所述步骤904和所述步骤905也可以先于所述步骤902和所述步骤903执行,所述步骤904和所述步骤905也可以与所述步骤902和所述步骤903同时执行。
其中,所述第一电流通道为所述第一输入端4023和所述第一输出端4021之间的电流通道,所述第二电流通道为所述第二输入端4033和所述第二输出端4031之间的电流通道。
在本实施例中,所述调整信号包括至少一开启信号和至少一清理信号。所述开启信号用于开启所述待测试显示面板101的薄膜晶体管开关。所述清理信号用于在所述薄膜晶体管开关处于开启状态时写入到所述待测试显示面板101的像素电极中,以清理所述待测试显示面板101保留的至少部分所述残影信号,即,所述清理信号用于使得所述待测试显示面板101中的像素电极的电荷的至少一部分消失或被抵消,从而使得所述待测试显示面板101中的像素电极的电场恢复至初始状态。
如图5所示,开启信号(G1、G2、G3)在所述待测试显示面板处于所述预定状态(所述开机状态501和所述关机状态503)时均为高电平信号,所述清理信号(D1、D2、D3、D4、D5、D6)在所述待测试显示面板处于所述预定状态(所述开机状态501和所述关机状态503)时均为低电平信号。
所述方法还包括以下步骤:
所述测试电路202将所述开启信号通过所述待测试显示面板101的扫描线输入至所述薄膜晶体管开关的栅极,以及将所述清理信号通过所述待测试显示面板101的数据线和所述薄膜晶体管开关输入至所述像素电极。
通过上述技术方案,可以使得在所述待测试显示面板101关机(测试完)后,残留于像素电极中的与所述测试画面或其它画面相关的电荷被清理,即,使得所述像素电极的电场恢复至初始状态,因此,可以使得待测试显示面板在开机时不会出现残影。
作为一种改进,在所述待测试显示面板为有源矩阵有机发光二极管面板的情况下(其中,所述有源矩阵有机发光二极管面板包括驱动开关电路,所述驱动开关电路用于接收开机信号(OVDD)和关机信号(OVSS),所述驱动开关电路包括一个三极管,所述三极管包括一第三控制端、第一末端、第二末端,所述第一末端用于接收所述开机信号,所述第二末端用于接收关机信号,所述第三控制端与所述第一末端分别连接一个电容的两块极板,所述第二末端还与一个二极管连接),所述方法还包括以下步骤:
所述测试电路在所述有源矩阵有机发光二极管面板处于所述预定状态时向所述有源矩阵有机发光二极管面板发送一抑制信号,所述测试电路将所述抑制信号提供给所述有源矩阵有机发光二极管面板的驱动开关电路,以抑制所述驱动开关电路的开关电压阈值(Vth)偏移。
具体地,所述测试电路将所述抑制信号提供给与所述三极管的所述第二末端连接的所述二极管的一端,所述抑制信号为正电压信号,所述正电压信号用于使得所述三极管处于反向偏制(反向截止/反向偏压)状态,即,使得所述第二末端的电压比所述第三控制端的电压高,从而抑制所述开关电压阈值(Vth)偏移,提高所述有源矩阵有机发光二极管面板的使用寿命。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板测试装置,其中
    所述显示面板测试装置包括:
    接口电路,用于与待测试显示面板连接;
    测试电路,与所述接口电路连接,所述测试电路用于在所述待测试显示面板处于测试状态时生成测试信号,并通过所述接口电路向所述待测试显示面板提供所述测试信号,以及用于在所述待测试显示面板处于预定状态时生成调整信号,并通过所述接口电路向所述待测试显示面板提供所述调整信号;
    其中,所述调整信号用于在所述待测试显示面板处于所述预定状态时清理所述待测试显示面板保留的至少部分残影信号;
    所述测试电路包括:
    测试信号生成电路,用于生成所述测试信号;
    调整信号生成电路,用于生成所述调整信号;
    选择电路,用于接收所述测试信号和所述调整信号,并用于在所述待测试显示面板处于所述测试状态时输出所述测试信号,以及用于在所述待测试显示面板处于所述预定状态时输出所述调整信号;
    所述预定状态为所述待测试显示面板的关机状态;
    所述关机状态对应所述待测试显示面板关机时一瞬间的状态或关机后的第二预定时间内的状态;
    所述第二预定时间处于0.01秒至5秒的范围内。
  2. 根据权利要求1所述的显示面板测试装置,其中
    所述选择电路包括:
    第一开关,所述第一开关包括:
    第一输入端,用于接收所述测试信号;
    第一输出端,用于在所述第一输入端和所述第一输出端之间的第一电流通道开启时输出所述测试信号;
    第一控制端,用于接收第一控制信号,并根据所述第一控制信号控制所述第一电流通道的开启或关闭;
    第二开关,所述第二开关包括:
    第二输入端,用于接收所述调整信号;
    第二输出端,用于在所述第二输入端和所述第二输出端之间的第二电流通道开启时输出所述调整信号;
    第二控制端,用于接收第二控制信号,并根据所述第二控制信号控制所述第二电流通道的开启或关闭;
    控制电路,与所述第一控制端和所述第二控制端连接,所述控制电路用于生成所述第一控制信号和所述第二控制信号。
  3. 根据权利要求2所述的显示面板测试装置,其中
    在所述待测试显示面板处于所述测试状态时,所述第一控制端用于根据所述第一控制信号控制所述第一电流通道开启,所述第二控制端用于根据所述第二控制信号控制所述第二电流通道关闭;
    在所述待测试显示面板处于所述预定状态时,所述第一控制端用于根据所述第一控制信号控制所述第一电流通道关闭,所述第二控制端用于根据所述第二控制信号控制所述第二电流通道开启。
  4. 一种显示面板测试装置,其中
    所述显示面板测试装置包括:
    一接口电路,用于与待测试显示面板连接;以及
    一测试电路,与所述接口电路连接,所述测试电路用于在所述待测试显示面板处于测试状态时生成测试信号,并通过所述接口电路向所述待测试显示面板提供所述测试信号,以及用于在所述待测试显示面板处于预定状态时生成调整信号,并通过所述接口电路向所述待测试显示面板提供所述调整信号;
    其中,所述调整信号用于在所述待测试显示面板处于所述预定状态时清理所述待测试显示面板保留的至少部分残影信号。
  5. 根据权利要求4所述的显示面板测试装置,其中
    所述预定状态为所述待测试显示面板的开机状态;
    所述开机状态对应所述待测试显示面板开机时一瞬间的状态或开机后第一预定时间内的状态。
  6. 根据权利要求5所述的显示面板测试装置,其中
    在所述预定状态为所述开机状态的情况下,所述测试电路和所述接口电路用于控制所述调整信号先于开机信号到达所述待测试显示面板。
  7. 根据权利要求4所述的显示面板测试装置,其中
    所述预定状态为所述待测试显示面板的关机状态;
    所述关机状态对应所述待测试显示面板关机时一瞬间的状态或关机后的第二预定时间内的状态。
  8. 8、根据权利要求4所述的显示面板测试装置,其中
    所述测试电路包括:
    一测试信号生成电路,用于生成所述测试信号;
    一调整信号生成电路,用于生成所述调整信号;以及
    一选择电路,用于接收所述测试信号和所述调整信号,并用于在所述待测试显示面板处于所述测试状态时输出所述测试信号,以及用于在所述待测试显示面板处于所述预定状态时输出所述调整信号。
  9. 根据权利要求8所述的显示面板测试装置,其中
    所述选择电路包括:
    一第一开关,所述第一开关包括:
    一第一输入端,用于接收所述测试信号;
    一第一输出端,用于在所述第一输入端和所述第一输出端之间的第一电流通道开启时输出所述测试信号;以及
    一第一控制端,用于接收第一控制信号,并根据所述第一控制信号控制所述第一电流通道的开启或关闭;
    一第二开关,所述第二开关包括:
    一第二输入端,用于接收所述调整信号;
    一第二输出端,用于在所述第二输入端和所述第二输出端之间的第二电流通道开启时输出所述调整信号;以及
    一第二控制端,用于接收第二控制信号,并根据所述第二控制信号控制所述第二电流通道的开启或关闭;以及
    一控制电路,与所述第一控制端和所述第二控制端连接,所述控制电路用于生成所述第一控制信号和所述第二控制信号。
  10. 根据权利要求9所述的显示面板测试装置,其中
    在所述待测试显示面板处于所述测试状态时,所述第一控制端用于根据所述第一控制信号控制所述第一电流通道开启,所述第二控制端用于根据所述第二控制信号控制所述第二电流通道关闭;
    在所述待测试显示面板处于所述预定状态时,所述第一控制端用于根据所述第一控制信号控制所述第一电流通道关闭,所述第二控制端用于根据所述第二控制信号控制所述第二电流通道开启。
  11. 根据权利要求4所述的显示面板测试装置,其中
    所述调整信号包括:
    至少一开启信号,所述开启信号用于开启所述待测试显示面板的薄膜晶体管开关;以及
    至少一清理信号,所述清理信号用于在所述薄膜晶体管开关处于开启状态时写入到所述待测试显示面板的像素电极中,以清理所述待测试显示面板保留的至少部分所述残影信号。
  12. 根据权利要求11所述的显示面板测试装置,其中
    所述开启信号为高电平信号,所述清理信号为低电平信号;
    所述测试电路还用于将所述开启信号通过所述待测试显示面板的扫描线输入至所述薄膜晶体管开关的栅极,以及用于将所述清理信号通过所述待测试显示面板的数据线和所述薄膜晶体管开关输入至所述像素电极。
  13. 根据权利要求12所述的显示面板测试装置,其中
    所述清理信号用于使得所述待测试显示面板中的像素电极的电荷的至少一部分消失或被抵消,以使得所述待测试显示面板中的像素电极的电场恢复至初始状态。
  14. 根据权利要求4所述的显示面板测试装置,其中
    所述待测试显示面板为有源矩阵有机发光二极管面板,所述测试电路还用于在所述有源矩阵有机发光二极管面板处于所述预定状态时向所述有源矩阵有机发光二极管面板发送一抑制信号,所述抑制信号用于提供给所述有源矩阵有机发光二极管面板的驱动开关电路,以抑制所述驱动开关电路的开关电压阈值偏移。
  15. 根据权利要求14所述的显示面板测试装置,其中
    所述有源矩阵有机发光二极管面板包括驱动开关电路,所述驱动开关电路用于接收开机信号和关机信号,所述驱动开关电路包括一个三极管,所述三极管包括一第三控制端、第一末端、第二末端,所述第一末端用于接收所述开机信号,所述第二末端用于接收关机信号,所述第三控制端与所述第一末端分别连接一个电容的两块极板,所述第二末端还与一个二极管连接;
    所述抑制信号用于提供给与所述三极管的所述第二末端连接的所述二极管的一端,所述抑制信号为正电压信号,所述正电压信号用于使得所述第二末端的电压比所述第三控制端的电压高,以抑制所述开关电压阈值偏移。
  16. 一种显示面板测试方法,其中
    所述方法包括以下步骤:
    所述测试电路在所述待测试显示面板处于所述测试状态时生成测试信号,并通过所述接口电路向所述待测试显示面板提供所述测试信号;以及
    所述测试电路在所述待测试显示面板处于所述预定状态时生成调整信号,并通过所述接口电路向所述待测试显示面板提供所述调整信号,以清理所述待测试显示面板保留的至少部分所述残影信号。
  17. 根据权利要求16所述的显示面板测试方法,其中
    所述方法还包括以下步骤:
    在所述待测试显示面板处于所述测试状态时,所述测试信号生成电路生成所述测试信号,所述选择电路接收所述测试信号,并输出所述测试信号;以及
    在所述待测试显示面板处于所述预定状态时,所述调整信号生成电路生成所述调整信号,所述选择电路接收所述调整信号,并输出所述调整信号。
  18. 根据权利要求17所述的显示面板测试方法,其中
    所述方法还包括以下步骤:
    控制电路生成所述第一控制信号和所述第二控制信号;
    在所述待测试显示面板处于所述测试状态时,第一开关的第一控制端接收所述第一控制信号,并根据所述第一控制信号控制第一电流通道开启,以使所述第一开关的第一输出端输出所述测试信号,第二开关的第二控制端接收所述第二控制信号,并根据所述第二控制信号控制第二电流通道关闭;以及
    在所述待测试显示面板处于所述预定状态时,所述第一控制端接收所述第一控制信号,并根据所述第一控制信号控制所述第一电流通道关闭,所述第二控制端接收所述第二控制信号,并根据所述第二控制信号控制所述第二电流通道开启,以使所述第二输出端输出所述调整信号;
    其中,所述第一电流通道为所述第一输入端和所述第一输出端之间的电流通道,所述第二电流通道为所述第二输入端和所述第二输出端之间的电流通道。
  19. 根据权利要求16所述的显示面板测试方法,其中
    所述调整信号包括:
    至少一开启信号,所述开启信号用于开启所述待测试显示面板的薄膜晶体管开关;以及
    至少一清理信号,所述清理信号用于在所述薄膜晶体管开关处于开启状态时写入到所述待测试显示面板的像素电极中,以清理所述待测试显示面板保留的至少部分所述残影信号;
    所述方法还包括以下步骤:
    所述测试电路将所述开启信号通过所述待测试显示面板的扫描线输入至所述薄膜晶体管开关的栅极,以及将所述清理信号通过所述待测试显示面板的数据线和所述薄膜晶体管开关输入至所述像素电极。
  20. 根据权利要求16所述的显示面板测试方法,其中
    所述待测试显示面板为有源矩阵有机发光二极管面板,所述方法还包括以下步骤:
    在所述有源矩阵有机发光二极管面板处于所述预定状态时,所述测试电路向所述有源矩阵有机发光二极管面板发送一抑制信号,以抑制所述有源矩阵有机发光二极管面板的驱动开关电路的开关电压阈值偏移。
PCT/CN2014/086373 2014-09-10 2014-09-12 显示面板测试装置及方法 Ceased WO2016037347A1 (zh)

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