WO2016011638A1 - 相变存储器的数据存储方法及控制装置 - Google Patents

相变存储器的数据存储方法及控制装置 Download PDF

Info

Publication number
WO2016011638A1
WO2016011638A1 PCT/CN2014/082918 CN2014082918W WO2016011638A1 WO 2016011638 A1 WO2016011638 A1 WO 2016011638A1 CN 2014082918 W CN2014082918 W CN 2014082918W WO 2016011638 A1 WO2016011638 A1 WO 2016011638A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
pulse signal
stored
memory cell
phase change
Prior art date
Application number
PCT/CN2014/082918
Other languages
English (en)
French (fr)
Inventor
李震
何强
缪向水
徐荣刚
赵俊峰
韦竹林
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201480037842.2A priority Critical patent/CN105723461A/zh
Priority to PCT/CN2014/082918 priority patent/WO2016011638A1/zh
Priority to JP2017504023A priority patent/JP6388422B2/ja
Priority to KR1020177004140A priority patent/KR20170031746A/ko
Publication of WO2016011638A1 publication Critical patent/WO2016011638A1/zh
Priority to US15/412,795 priority patent/US10083749B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse

Definitions

  • Embodiments of the present invention relate to data storage technologies, and in particular, to a data storage method and a control device for a phase change memory. Background technique
  • Phase Change Memory is the fastest growing new non-volatile memory. It uses the different resistance values of phase change materials in crystalline and amorphous states to store corresponding data. It is applied to rewritable compact discs (CDs) and digital versatile discs (Digital Versatile Discs). In order to meet the requirements of massive information storage, research on high-density storage of phase-change memory is particularly important. Conventional methods for achieving high density phase change memory include: reducing the phase change cell area and reducing the peripheral circuit area. The former requires an improvement in the structure of the device and is limited by the size of the lithography, which requires optimization of the integrated circuit design.
  • a multi-value storage method for implementing a phase change memory generally includes: an erase process (SET) and a write process (RESET).
  • the erasing process is to apply a pulse of low amplitude and long pulse width to the memory cell of the phase change memory to make the memory cell into a stable low resistance crystalline state.
  • the writing process is to apply a pulse of high amplitude and narrow pulse width to the memory cell, so that the memory cell becomes a high resistance amorphous state, because the resistance value of the memory cell of the phase change memory is according to the width of the applied programming pulse.
  • the amplitude changes, so by applying a single pulse having different pulse widths of different amplitudes to the memory cells, an amorphous state having different resistance values can be realized, and the amorphous states of the different resistance values correspond to different storage states, thereby Implement multi-value storage of phase change memory.
  • Embodiments of the present invention provide a data storage method and a control device for a phase change memory to solve the problem of implementing hot crosstalk generated by multi-value storage of a phase change memory in the prior art.
  • an embodiment of the present invention provides a data storage method for a phase change memory, including: acquiring data to be stored, where the data to be stored is multi-bit data;
  • the write pulse signal is a signal including at least two consecutive pulses; the interval between the at least two consecutive pulses is the same, and the at least The interval between two consecutive pulses is a value determined according to the data to be stored;
  • the method further includes:
  • Determining whether the data to be stored is the largest data or the minimum data of the multi-bit data; the generating the rub pulse signal and the write pulse signal according to the data to be stored includes: when the data to be stored is not the When the maximum data or the minimum data of the multi-bit data is generated, the rub pulse signal and the write pulse signal are generated according to the data to be stored.
  • the method further includes:
  • the data to be stored is the largest data or the minimum data of the multi-bit data
  • generating a rub pulse signal according to the data to be stored and applying the rub pulse signal to a storage unit of the phase change memory
  • the memory cell becomes crystalline to characterize the data to be stored by the crystalline state of the memory cell.
  • the pulse widths of the at least two consecutive pulses are the same.
  • the pulse width of the at least two consecutive pulses ranges from 30 ns to 50 ns.
  • the interval between the at least two consecutive pulses ranges from 10 ns to 50 ns.
  • the wipe pulse signal and the write pulse signal are voltage signals; or The wipe pulse signal and the write pulse signal are current signals.
  • the write pulse signal is a voltage signal including at least two consecutive pulses, and amplitudes of the at least two consecutive pulses The range is lv-1.5v.
  • the embodiment of the present invention further provides a phase change memory control device, including: an obtaining module, configured to acquire data to be stored, where the data to be stored is multi-bit data; and a generating module, configured to Storing data, generating a rub pulse signal and a write pulse signal; wherein the write pulse signal is a signal including at least two consecutive pulses; an interval between the at least two consecutive pulses is the same, and the at least two consecutive pulses The interval between them is a value determined according to the data to be stored;
  • control module configured to apply the erase pulse signal to a memory cell of the phase change memory to change the memory cell to a crystalline state, and apply the write pulse signal to the memory cell to cause the memory cell to become An amorphous state of the first resistance value, the magnitude of the first resistance value and the interval between the at least two consecutive pulses satisfy a specific functional relationship to be characterized by amorphous state of the first resistance value of the memory cell The data to be stored.
  • control device further includes:
  • a determining module configured to determine whether the data to be stored is the largest data or the smallest data in the multi-bit data
  • the generating module is further configured to: when the data to be stored is not the maximum data or the minimum data of the multi-bit data, generate the rub pulse signal and the write pulse signal according to the data to be stored.
  • the generating module is further configured to: when the to-be-stored data is the largest data or the largest of the multi-bit data When the data is small, the rubbing pulse signal is generated according to the data to be stored;
  • the control module is further configured to apply the wipe pulse signal to a memory cell of the phase change memory to change the memory cell to a crystalline state to characterize the data to be stored by a crystalline state of the memory cell.
  • an embodiment of the present invention further provides a phase change memory control device, including: a processor and a communication bus; the processor is connected to the communication bus, and the communication bus and the phase change memory are stored. Units are connected;
  • the processor is configured to execute a data storage method of the phase change memory according to any one of the above, and control data storage of the storage unit by using the communication bus.
  • the embodiment of the present invention further provides a computer readable medium, comprising: computer executable instructions for being retrieved and executed by a processor of a computer; the computer executed instructions comprising the phase change memory of any of the above The computer storage method corresponding to the data storage method.
  • the data storage method and the control device of the phase change memory provided by the embodiment of the present invention generate a write pulse signal including at least two consecutive pulses according to the data to be stored, and apply the write pulse signal to the storage unit of the phase change memory, so that the The storage unit becomes an amorphous state corresponding to the resistance value of the data to be stored to represent the data to be stored, and realizes multi-value storage of a single storage unit. Since the write pulse signal includes at least two consecutive pulses, the single application pulse can be reduced. The temperature of the memory cell is increased to alleviate the problem of thermal crosstalk caused by excessive heat.
  • FIG. 1 is a flowchart of a data storage method of a phase change memory according to Embodiment 1 of the present invention
  • FIG. 2 is a flowchart of a data storage method of a phase change memory according to Embodiment 2 of the present invention
  • FIG. 4 is a schematic structural diagram of a memory cell of a phase change memory
  • FIG. 5 is a flowchart of a data storage method of a phase change memory according to Embodiment 4 of the present invention
  • FIG. 6 is a schematic structural diagram of a phase change memory control apparatus according to Embodiment 5 of the present invention.
  • 7 is a schematic diagram of connection between a control device of a phase change memory and a phase change memory according to Embodiment 6 of the present invention;
  • FIG. 8 is a schematic structural diagram of a computer readable medium according to Embodiment 7 of the present invention.
  • the technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention.
  • the embodiments are a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
  • the embodiment provides a storage method of a phase change memory, which generates a write pulse signal according to a plurality of bits of data to be stored, wherein the write pulse signal is a signal including at least two consecutive pulses, and the interval between the at least two consecutive pulses is the same And the interval between the at least two consecutive pulses needs to be determined according to the multi-bit data to be stored, so that the memory cell can be made amorphous by the first resistance value by applying the write pulse signal to the memory unit a state, a magnitude of the first resistance value is related to an interval between the at least two consecutive pulses, so that the memory cells can obtain amorphous states of different resistance values by using write pulse signals having different intervals of at least two consecutive pulses Record different multi-bit data to achieve multi-value storage of a single storage unit.
  • FIG. 1 is a data storage method of a phase change memory according to Embodiment 1 of the present invention. As shown in FIG. 1 , the method specifically includes the following steps:
  • Step 101 Acquire data to be stored, where the data to be stored is multi-bit data.
  • the multi-bit data can be multi-bit binary data.
  • the data to be stored may be data that receives external input, data that is pre-configured in the storage unit of the phase change memory, or data that is generated according to pre-configured data generation rules. If the data is to be stored n-bit data, the data may be stored as a 2 ⁇ ⁇ data in any one data.
  • Step 102 Generate, according to the data to be stored, a wipe pulse signal and a write pulse signal, where the write pulse signal is a signal including at least two consecutive pulses; between the at least two consecutive pulses The intervals are the same, and the interval between the at least two consecutive pulses is a value determined according to the data to be stored.
  • the memory cells of the phase change memory may be utilized with different resistance values to characterize different data to be stored. Since the resistance value of the memory cell is closely related to the degree of amorphization of the phase change material layer of the memory cell, and the degree of amorphization depends on the temperature of the phase change material layer, an electrical pulse having different parameters can be applied to heat the phase change material. To different temperatures, therefore, according to different data to be stored, a write pulse signal composed of at least two consecutive pulses having different intervals can be generated, so that the memory cells are in an amorphous state with different resistance values to store different to be stored. Data, enabling multi-value storage.
  • the temperature increase of the single application pulse to the memory cell can be reduced, thereby solving the multi-value realized by the single pulse with high amplitude and narrow pulse width in the prior art. Store the resulting hot crosstalk problem.
  • the interval between the at least two consecutive pulses may be the same, and the interval between the at least two consecutive pulses may be determined according to the data to be stored.
  • the predetermined interval may be divided into 2 ⁇ ⁇ range bisected, and in accordance with the size of the data to be stored in two location data, determining the least interval between two successive pulses. That is to say, the interval between at least two consecutive pulses in the write pulse signal corresponding to the adjacent data to be stored is an interval corresponding to the adjacent equal division.
  • the interval between the at least two consecutive pulses corresponding to the adjacent data to be stored is further determined according to the number of the at least two consecutive pulses, the pulse width of the single pulse, and the pulse width.
  • the value is fine-tuned. Specifically, if the number of the at least two consecutive pulses is larger, the corresponding amplitude is smaller, and correspondingly, if the number of the at least two consecutive pulses is smaller, the corresponding pulse interval is smaller. In order to reduce the loss of heat, make full use of the heat generated by the pulse; if the pulse width of the single pulse is narrow, the corresponding pulse interval is small; if the pulse amplitude is small, the corresponding pulse interval is small.
  • the interval between the at least two consecutive pulses may also be a value obtained by the preset data and the pulse interval correspondence table according to the data to be stored. If the data to be stored as bit data [eta], the pulse interval and the preset data corresponding relationship table includes at least 2 ⁇ ⁇ pulse intervals corresponding to each data.
  • the predetermined pulse interval data in the correspondence table 2 ⁇ ⁇ specific numerical data respectively corresponding pulse intervals, before step 102 may be in the ho, based on the number of data bits can be stored, respectively to be stored for the All the data of the data are subjected to a test experiment, thereby obtaining a pulse interval required to store the resistance value of the amorphous state corresponding to the data, and storing the data to be stored and the corresponding pulse thereof to obtain the correspondence relationship of the data pulse interval table.
  • Step 103 Applying the erase pulse signal to the memory cell of the phase change memory to change the memory cell to a crystalline state.
  • the memory cell Since in the initial state, the memory cell is mostly amorphous. To ensure the stability and accuracy of the amorphous resistance value characterizing the data to be stored, a wipe pulse signal is applied to the memory cell such that the memory cell is in a stable crystalline state. Usually, the resistance value of the memory cell in the crystalline state is smaller than the resistance value when the memory cell is in the amorphous state.
  • the wipe pulse signal may comprise at least one pulse of a low amplitude long pulse width pulse.
  • the amplitude of the one pulse may be less than a preset amplitude, and the preset amplitude may be a pulse corresponding to heating the phase change material layer of the memory cell to a melting point temperature. Amplitude.
  • the pulse width of the erase pulse is greater than the time required to heat the phase change material of the memory cell to the crystallization temperature based on pulses less than the predetermined amplitude.
  • the amplitude of the pulse included in the rub pulse signal may be between 0.5v and 1.5v, and the pulse width of the pulse included in the rub pulse signal may be between 100ns and 300ns.
  • the wipe pulse signal since the heat required to heat the phase change material layer of the memory cell to the melting point temperature is fixed, if the wipe pulse signal includes at least two consecutive pulses, the amplitude of the pulse included in the erase pulse signal is smaller than the erase pulse signal includes one The amplitude corresponding to the pulse.
  • the amplitude of the pulse included in the rub pulse signal and the specific number of pulses may be determined according to the material of the phase change material layer of the memory cell or the internal structure of the memory cell. For example, if the wipe pulse signal includes a pulsed signal, the wipe pulse signal may include a signal having an amplitude of 0.8 volts and a pulse width of 300 ns.
  • Step 104 Apply a write pulse signal to the memory cell to change the memory cell to an amorphous state of a first resistance value, where a size of the first resistance value and an interval between the at least two consecutive pulses satisfy a specific functional relationship And characterizing the data to be stored by an amorphous state of the first resistance value of the memory cell.
  • the phase change material layer of the memory cell is heated by Joule heat generated by the write pulse signal Heating the phase change material layer to a temperature above the melting point and rapidly cooling to below the crystallization temperature, so that the phase change material layer becomes an amorphous state of the first resistance value, and the first resistance value is at least two The interval between consecutive pulses satisfies a specific functional relationship. At this time, the magnitude of the first resistance value is larger than the resistance value when the memory cell is in a crystalline state.
  • R represents the resistance value of the amorphous state of the memory cell
  • ⁇ represents the amorphization ratio of the phase change material layer. with. Minute It is the resistance value of the phase change unit when it is completely crystalline and completely amorphous.
  • the phase change material layer for a particular material is fixed. with. , can be obtained in advance according to the experiment.
  • the amorphization rate c a is actually the volume V of the amorphized region of the phase change material layer.
  • the ratio of the total volume V OTr of the phase change material layer can be expressed as the following formula (2):
  • the volume V of the amorphized region of the phase change material layer According to the critical temperature T a of the crystallization and amorphization of the phase change material layer, and the melting point temperature T m of the phase change material layer, by the following formula (3)
  • phase change material layer of the memory cell is known and determined, then the melting point temperature r m of the phase change material layer is known.
  • the Joule heat generated according to the heat applied to the phase change material layer is obtained by the following formula (4):
  • ⁇ is the power dissipated, that is, the power consumption, and the Joule heat generated by the applied write pulse signal can be obtained according to parameters such as the interval between at least two consecutive pulses in the write pulse signal.
  • the resistance value of the amorphous state of the memory cell i.e., the magnitude of the first resistance value, satisfies the above-described functional relationship with the interval between at least two consecutive pulses in the applied write pulse signal.
  • the interval between at least two consecutive pulses in the write pulse signal is determined according to the data to be stored, for different data to be stored, corresponding to at least two consecutive pulses in the write pulse signal
  • the intervals are different.
  • the heat generated by applying the write pulse signals having different pulse intervals to the memory cell is different, the temperature of the phase change material layer of the memory cell is inevitably different, and the resistance values of the amorphous states obtained at different temperatures are also different.
  • the memory cells of the amorphous state having different resistance values can be used to characterize different data to be stored, respectively.
  • the resistance values of the amorphous states corresponding to the memory cells obtained by applying the write pulse signals having different pulse intervals to the memory cells are different, wherein the difference between the resistance values corresponding to the adjacent pulse intervals is larger than the preset Threshold.
  • the amplitude of the at least two consecutive pulses is greater than the amplitude of the wipe pulse signal, the at least two consecutive The pulse width of the pulse is less than the pulse width of the erase pulse signal.
  • the amplitude of the at least two consecutive pulses may be greater than a preset amplitude, and the preset amplitude may be a pulse amplitude corresponding to heating the phase change material layer of the memory cell to a melting point temperature.
  • the amplitude of the write pulse signal composed of at least two consecutive pulses is necessarily smaller than the amplitude of the write pulse signal composed of a single pulse.
  • the write pulse signal is thus applied to the memory cell to reduce the temperature increase of the memory cell by a single application of the pulse, thereby reducing or avoiding thermal crosstalk problems due to excessive heat.
  • the spacing between adjacent pulses is the same, for example, may be 50 ns. Since the at least two consecutive pulses are further spaced from each other, the write pulse signal is applied to the memory cell, and the memory cell can fully utilize the heat generated by applying the preceding pulse, and thus, the sum of the amplitudes of the at least two consecutive pulses , also smaller than the amplitude of the write pulse signal composed of the single pulse. That is, applying the write pulse signal to the memory cell also reduces the total energy required to apply the write pulse signal, thereby reducing power consumption.
  • the corresponding data to be stored is characterized by an amorphous having a certain resistance value by applying a combination of the erase pulse signal and the write pulse signal. That is to say, in this embodiment, no data may be stored for the crystalline state of the memory cell.
  • the data corresponding to the record may be stored according to the resistance value or the current value of the storage unit.
  • the larger the resistance value of the memory cell or the smaller the current value the smaller or larger the stored data can be.
  • the resistance value or current value of the memory cell corresponds to the size of the data stored in the memory, and can be configured in advance.
  • the memory cell is changed to an amorphous state corresponding to the resistance value of the data to be stored by a write pulse signal determined according to the data to be stored of the plurality of bits, and the data to be stored is characterized. Achieving multi-value storage of a single memory cell, since the write pulse signal includes at least two consecutive pulses, reducing the temperature increase of the memory cell by a single applied pulse reduces or avoids the problem of thermal crosstalk caused by excessive heat.
  • the use of the at least two consecutive pulses reduces the amplitude of the write pulse signal, reduces the difficulty of controlling the amplitude of the write pulse signal by the pulse generation circuit, and has fewer adjustment parameters and better control.
  • the storage unit has different resistance values of the amorphous state, and improves stability of storing a plurality of data by using the storage unit; and the interval between the at least two consecutive pulses in the write pulse signal of different data to be stored is different, so that the pulse
  • the structure of the generating circuit is simple; and the use of a write pulse including at least two consecutive pulses can reduce the control power consumption and save energy by making full use of the heat generated by the applied pulse.
  • This embodiment also provides a data storage method of a phase change memory.
  • a portion of the data may be stored in a crystalline state of the phase change memory, and the remaining data may be stored in an amorphous state of the different resistance values of the phase change memory.
  • a part of the data that can be stored in the crystalline state can be the largest data or the smallest data in the multi-digit data.
  • FIG. 2 is a flowchart of a data storage method of a phase change memory according to Embodiment 2 of the present invention. As shown in FIG. 2, in the foregoing solution, in step 102, before generating the wipe pulse signal and the write pulse signal according to the data to be stored, the solution further includes:
  • Step 201 Determine whether the data to be stored is the largest data or the minimum data in the multi-bit data.
  • the step 201 actually determines whether the data to be stored is 00 or 11.
  • the step 102 generates a wipe pulse signal and a write pulse signal according to the data to be stored, and specifically includes:
  • Step 202 When the to-be-stored data is not the maximum data or the minimum data of the multi-bit data, generate the wipe pulse signal and the write pulse signal according to the to-be-stored data.
  • the corresponding data to be stored is characterized by the amorphous body having a certain resistance value by combining the application of the rub pulse signal and the write pulse signal.
  • the method further includes:
  • Step 203 When the data to be stored is the largest data or the smallest data in the multi-bit data, And generating the erase pulse signal according to the data to be stored, and applying the erase pulse signal to the memory unit to change the memory cell to a crystalline state to represent the data to be stored by a crystalline state of the memory cell.
  • the maximum data or the minimum data can be characterized by a crystalline state only by using a scheme of applying a write pulse signal. That is to say, in this embodiment, the maximum or minimum data of the multi-bit data can be stored for the crystalline state of the memory cell.
  • the maximum data is characterized by a crystalline state
  • a scheme for generating a corresponding write pulse signal according to the minimum data and then applying a write pulse signal is performed, and the amorphous state corresponding to the resistance value is used for characterization; If the minimum data is characterized by a crystalline state, a solution for generating a corresponding write pulse signal according to the maximum data is required, and then a write pulse signal is applied, and characterized by an amorphous state corresponding to the resistance value.
  • determining whether the crystalline state of the memory cell represents maximum data or minimum data may be determined according to a predetermined data storage rule. If the data storage rule is to sequentially store the multi-bit data from small to large according to the order of the resistance values of the storage unit, the minimum data is represented by the crystal state; if the data storage rule is powered according to the storage unit The internal current values are stored in ascending order, and sequentially store multiple bits of data from small to large.
  • the pulse widths of the at least two consecutive pulses are the same. Further, the pulse of the at least two consecutive pulses may range from 30 ns to 50 ns.
  • the interval between the at least two consecutive pulses is in the range of
  • the different pulse intervals are preferably 10 ns, 15 ns, 25 ns, 30 ns, 40 ns, 45 ns, and 50 ns.
  • the data to be stored is 2-bit data, that is, any of 00, 01, 10, 11, 4 data
  • the interval between at least two consecutive pulses in the write pulse signal determined according to the 4 data is preferred, Can be 50ns, 40ns, 25ns and 10ns.
  • the write pulse signal of the four different pulses is applied to the memory cell, four different amorphous states respectively can be obtained, and the four amorphous states respectively have different resistance values, wherein the pulse interval is smaller
  • the pulse interval of the write pulse signal can be determined to be 10 ns according to the data to be stored, and then applying the write pulse signal to the memory unit can make the memory cell become a resistance value of 1 ⁇ ⁇ . If the stored data is 01, according to the data to be stored, it can be determined that the pulse interval of the write pulse signal is 25 ns, then applying the write pulse signal to the memory unit can make the memory cell have a resistance value of 100 k An amorphous state of ⁇ ; if the stored data is 10, determining that the pulse interval of the write pulse signal is 40 ns according to the data to be stored, applying the write pulse signal to the memory cell may cause the memory cell to become a resistance value 10k Q amorphous state; if the data to be stored is 11, according to the data to be stored, it can be determined that the pulse interval of the write pulse signal is 50 ns, and applying the write pulse signal to the memory unit can make the memory cell become a resistance value It is an amorphous state
  • the wipe pulse signal and the write pulse signal are voltage signals; or the wipe pulse signal and the write pulse signal are current signals.
  • the write pulse signal is a voltage signal comprising at least two consecutive pulses, and the amplitude of the at least two consecutive pulses is preferably in the range of lv - 1.5v.
  • the amplitudes of the at least two consecutive pulses are the same.
  • the amplitudes of the at least two consecutive pulses are the same and may each be 1.27v.
  • FIG. 3 is a flowchart of a data storage method of a phase change memory according to Embodiment 2 of the present invention. As shown in FIG. 3, the method specifically includes the following steps: Step 301: Obtain a first to-be-stored data, where the first to-be-stored data is multi-bit data.
  • Obtaining the to-be-stored data may be obtained according to a pre-configured data generation rule.
  • the storage unit can store 2-bit data
  • the data generation rule can be a generation rule from small to large
  • the first to-be-stored data can be 00.
  • Step 302 Generate a rub pulse signal and a first write pulse signal according to the first data to be stored, where the first write pulse signal is a signal including two consecutive pulses, and the interval between the two consecutive pulses is according to the first waiting The first interval determined by the stored data.
  • the wipe pulse signal may be An electrical pulse having an amplitude of 0.8 V and a pulse width of 300 ns.
  • the first write pulse signal is a signal comprising two consecutive pulses having an amplitude of 1.27 v and a pulse width of 30 ns.
  • the first interval can be 50 ns.
  • Step 303 applying the erase pulse signal to an upper electrode of the memory cell, changing a phase change material layer of the memory cell to a crystalline state, and applying the first write pulse signal to an upper electrode of the memory cell to enable the storing
  • the phase change material layer of the cell changes to a first amorphous state, and the first data to be stored is stored by the first amorphous state.
  • the memory cell includes: an upper electrode 41, a lower electrode 44, a phase change material layer 42, and an insulating layer 43.
  • the upper electrode 41 and the lower electrode 44 are each composed of a conductive material such as a metal aluminum electrode.
  • the phase change material layer 42 is a GST material.
  • the upper electrode 41 can receive an applied erase pulse or write pulse by being connected to a signal source of the controller.
  • the lower electrode 42 can be grounded through a selection transistor.
  • the phase change material layer 42 can be heated by the rubbing pulse signal to generate Joule heat, and the phase change material is obtained.
  • the temperature of the layer 42 is heated to a temperature above the crystallization temperature of the phase change material layer 42 and below the melting point temperature.
  • the crystallization temperature may be, for example, 400 k, and the melting temperature is 600 k.
  • Applying the write pulse signal having the first interval to the phase change material layer of the memory cell allows the memory cell to become amorphous with 1000 ⁇ . That is, the first resistance value may be 1000 ⁇ .
  • Step 304 Obtain a second to-be-stored data.
  • the second data to be stored may be 01.
  • Step 305 Generate the erase pulse signal and the second write pulse signal according to the second data to be stored, where the second write pulse signal is a signal including two consecutive pulses, and an interval between the two consecutive pulses is according to the The second interval determined by the second data to be stored.
  • This second interval can be 40 ns.
  • the pulse width and amplitude of the second write pulse signal may be the same as the first write pulse signal.
  • the rub pulse signal can be the same as the rub pulse signal described above.
  • Step 306 applying the erase pulse signal to an upper electrode of the memory cell, changing a phase change material layer of the memory cell to a crystalline state, and applying the second write pulse signal to an upper electrode of the memory cell, so that The phase change material of the memory cell changes to a second amorphous state, and the second data to be stored is stored by the second amorphous state.
  • the phase change material layer of the memory cell can be changed to the second amorphous state, such as an amorphous state having a resistance value of 100 k ⁇ .
  • Step 307 Acquire a third to-be-stored data.
  • the third to-be-stored data may be 10.
  • Step 308 Generate the erase pulse signal and the third write pulse signal according to the third data to be stored, where the third write pulse signal is a signal including two consecutive pulses, and an interval between the two consecutive pulses is according to the The third interval determined by the third data to be stored.
  • This third interval can be 25 ns.
  • the pulse width and amplitude of the third write pulse signal may be the same as the first write pulse signal.
  • the rub pulse signal may be the same as the rub pulse signal described above, and is an electric pulse having an amplitude of 0.8 v and a pulse width of 300 ns.
  • Step 309 applying the erase pulse signal to an upper electrode of the memory cell, changing a phase change material layer of the memory cell to a crystalline state, and applying the third write pulse signal to an upper electrode of the memory cell, so that The phase change material of the memory cell changes to a third amorphous state, and the third data to be stored is stored by the third amorphous state.
  • the phase change material layer of the memory cell can be changed to the third amorphous state, such as an amorphous state having a resistance value of 10 kQ.
  • Step 310 Acquire a fourth to-be-stored data.
  • the fourth to-be-stored data may be 11.
  • Step 311 Generate the erase pulse signal and the fourth write pulse signal according to the fourth to-be-stored data, where the fourth write pulse signal is a signal including two consecutive pulses, and an interval between the two consecutive pulses is according to the The fourth interval determined by the fourth data to be stored.
  • the fourth interval can be 10 ns.
  • the pulse width and amplitude of the fourth write pulse signal may be the same as the first write pulse signal.
  • the rub pulse signal can be the same as the rub pulse signal described above.
  • Step 312 applying the erase pulse signal to the upper electrode of the memory cell, changing a phase change material layer of the memory cell to a crystalline state, and applying the fourth write pulse signal to an upper electrode of the memory cell, so that the The phase change material of the memory cell changes to a fourth amorphous state, and the fourth standby state is stored by the fourth amorphous state Storing data.
  • the phase change material layer of the memory cell can be changed to the fourth amorphous state, such as an amorphous state having a resistance value of 10 ⁇ .
  • the memory cell can have an amorphous state and a crystalline state of four different resistance values.
  • the amorphous state of the memory cell is a first amorphous state, a second amorphous state, a third amorphous state, and a fourth amorphous state in descending order of resistance values.
  • the first amorphous state, the second amorphous state, the third amorphous state, and the fourth amorphous state of the memory cell may store 00, 01, 10, 11, respectively, to store four 2-bit data.
  • the write pulse composed of two identical pulses in this embodiment is only a preferred embodiment of the scheme of the present embodiment, the present invention is not limited in order, and the scheme can also be realized by the same pulse composition of more than two.
  • the storage unit is changed to an amorphous state corresponding to the resistance value of the data to be stored by a write pulse signal applied to the storage unit to determine an interval between the at least two consecutive pulses according to the data to be stored, and the storage corresponds to The data to be stored, the multi-bit data storage of a single storage unit is realized, and the multi-bit data of the single storage unit is realized by the write pulse signal including at least two consecutive pulses to increase the storage density of the storage unit. Since the adjustment parameters are less, the resistance values of different amorphous states of the memory unit can be better controlled, and the stability of storing a plurality of data by using the storage unit is improved.
  • FIG. 5 is a flowchart of a data storage method of a phase change memory according to Embodiment 4 of the present invention. As shown in FIG. 5, the method specifically includes the following steps: Step 501: Acquire data to be stored, where the data to be stored is multi-bit data.
  • Step 502 Determine whether the data to be stored is the smallest data in the multi-bit data.
  • Obtaining the first to-be-stored data may be obtained according to a pre-configured data generation rule, or may be acquired by acquiring an external input device. Determining whether the data to be stored is the smallest data in the multi-bit data is actually determining whether each bit of the data to be stored is 0. If both are 0, the data to be stored is the minimum data in the multi-bit data. .
  • Step 503 If the data to be stored is the smallest data of the multi-bit data, generate the rub pulse signal according to the data to be stored, and apply the rub pulse signal to an upper electrode of the storage unit to make the phase of the storage unit The material layer becomes crystalline, and the data to be stored is stored by the crystal state.
  • Step 504 If the data to be stored is not the smallest data in the multi-bit data, according to the waiting The stored data generates the erase pulse signal and the write pulse signal, the write pulse signal being a signal comprising two consecutive pulses, the interval between the two consecutive pulses being an interval determined according to the data to be stored.
  • Step 505 Apply the erase pulse signal to the upper electrode of the memory cell, change the phase change material layer of the memory cell to a crystalline state, and apply the write pulse signal to the upper electrode of the memory cell to make the memory cell
  • the phase change material layer becomes amorphous, and the data to be stored is stored by the amorphous state.
  • the crystalline state can be used to store the smallest data in the multi-bit data.
  • the crystalline state can also be used to store the largest data in the multi-bit data, and the corresponding method steps are the same as the above embodiment. Similar, it will not be repeated here.
  • the embodiment of the present invention is specifically described by the method of storing the minimum data of the multi-bit data in a crystalline state.
  • the beneficial effects are similar to those of the foregoing embodiment, and details are not described herein again.
  • the write pulse signal composed of two identical pulses in this embodiment is only a preferred solution of the solution of the embodiment, the present invention is not limited in order, and the solution can also be implemented by more than two identical pulse components. .
  • FIG. 6 is a schematic structural diagram of a phase change memory control apparatus according to Embodiment 5 of the present invention. As shown in FIG. 6, the phase change memory control device 600 includes:
  • the obtaining module 601 is configured to obtain data to be stored, where the data to be stored is multi-bit data.
  • a generating module 602 configured to generate a wipe pulse signal and a write pulse signal according to the data to be stored; wherein the write pulse signal is a signal including at least two consecutive pulses, the interval between the at least two consecutive pulses is the same, and The interval between the at least two consecutive pulses is a value determined according to the data to be stored.
  • the control module 603 is configured to apply the wipe pulse signal to the memory cell of the phase change memory to change the memory cell to a crystalline state, and apply the write pulse signal to the memory cell to change the memory cell to a first resistance value.
  • the magnitude of the first resistance value and the interval between the at least two consecutive pulses satisfy a specific functional relationship to characterize the data to be stored by an amorphous state of the first resistance value of the memory cell.
  • phase change memory control device 600 as described above further includes:
  • the determining module is configured to determine whether the data to be stored is the largest data or the smallest data in the multi-bit data.
  • the generating module 602 is further configured to: when the data to be stored is not the largest data in the multi-bit data or At the time of the minimum data, the erase pulse signal and the write pulse signal are generated according to the data to be stored.
  • the generating module 602 is further configured to: when the data to be stored is the maximum data or the minimum data in the multi-bit data, generate a rub pulse signal according to the data to be stored.
  • the control module 603 is further configured to apply the wipe pulse signal to the memory cell to change the memory cell to a crystalline state to characterize the data to be stored by the crystalline state of the memory cell.
  • the embodiment of the present invention provides a phase change memory control device, which can implement the data storage method of the phase change memory according to any of the above embodiments, and the beneficial effects thereof are similar to those of the foregoing embodiment, and are not described herein again.
  • FIG. 7 is a schematic diagram showing the connection between a control device and a phase change memory of a phase change memory according to Embodiment 6 of the present invention.
  • the control device 700 of the phase change memory includes a processor 701 and a control bus 702.
  • the processor 702 is connected to the memory unit 704 of the phase change memory 703 via the control bus 702.
  • the processor 701 is configured to execute the data storage method of the phase change memory according to any of the above embodiments, and control the storage unit 704 to perform data storage by using the control bus 702.
  • the phase change memory control device 700 further includes a memory for storing a program, and the processor 701 executes the method of data storage by calling a program in the memory.
  • the memory 701 may include a high speed random access memory (RAM), and may also include a non-volatile memory such as at least one disk memory.
  • the embodiment of the present invention provides a phase change memory control device, which can implement the data storage method of the phase change memory according to any of the above embodiments, and the beneficial effects thereof are similar to those of the foregoing embodiment, and are not described herein again.
  • FIG. 8 is a schematic structural diagram of a computer readable medium according to Embodiment 7 of the present invention.
  • the computer readable medium 800 includes: a computer executing instructions 801.
  • the computer execution instructions 801 are available to the computer's processor for retrieval and execution.
  • the computer-executable instructions include computer instructions corresponding to the data storage method of the phase change memory of any of the above.
  • the computer-executable instructions included in the computer-readable medium provided by the embodiment may include computer instructions corresponding to the data storage method of the phase change memory according to any of the above embodiments, for the processor of the computer to retrieve and execute.
  • the beneficial effects are similar to the above embodiments, and are no longer embarrassed here. Said.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种相变存储器的数据存储方法及控制装置。该方法包括：获取待存储数据，该待存储数据为多位数据（S101）；根据该待存储数据，产生擦脉冲信号和写脉冲信号，该写脉冲信号为包括至少两个连续脉冲的信号，该至少两个连续脉冲的间隔相同，且该至少两个连续脉冲的间隔为根据该待存储数据而确定的值（S102）；将该擦脉冲信号施加至该相变存储器的存储单元使该存储单元变为晶态（S103）；将该写脉冲信号施加至该存储单元使该存储单元变为第一电阻值的非晶态，以通过该存储单元的第一电阻值的非晶态表征所述待存储数据（S104）。可解决多值存储时的热串扰问题。

Description

相变存储器的数据存储方法及控制装置
技术领域
本发明实施例涉及数据存储技术， 尤其涉及一种相变存储器的数据存储 方法及控制装置。 背景技术
相变存储器（Phase Change Memory, 简称 PCM)是目前发展最快的一种 新型非挥发性存储器， 它利用相变材料在晶态和非晶态时表征的不同电阻值 来存储对应的数据， 广泛应用于可重写的光盘 （Compact Disc, 简称 CD) 和 数字多功能光盘 （Digital Versatile Disc, 简称 DVD) 上。 为适应海量信息存 储的要求， 对相变存储器的高密度存储研究显得尤为重要。 实现高密度相变 存储器的传统方法包括： 减小相变单元面积和减小外围电路面积。 前者需要 对器件结构进行改进以及受到光刻尺寸的限制，后者需对集成电路设计优化。
为了克服上述问题， 多值存储技术应用而生。 多值存储技术， 有别于传 统的二值存储方法，能够充分利用相变材料在晶态和非晶态之间电阻的差异， 在一个存储单元上实现至少 2位 （bk) 的数据存储。 现有技术中， 实现相变 存储器的多值存储方法一般包括： 擦除过程 （SET) 及写入过程 （RESET) 。 擦除过程， 是对该相变存储器的存储单元施加一个低幅值长脉宽的脉冲， 使 该存储单元变为稳定的低阻晶态。 写入过程， 是对该存储单元施加一个高幅 值窄脉宽的脉冲， 使该存储单元变为高阻的非晶态， 由于相变存储器的存储 单元的电阻值根据施加的编程脉冲的宽度和幅值而改变， 因此通过给存储单 元施加具有不同幅值不同脉宽的单脉冲，可以实现具有不同电阻值的非晶态， 该不同电阻值的非晶态， 对应不同的存储状态， 从而实现相变存储器的多值 存储。
现有技术中采用高幅值窄脉宽的单脉冲实现多值存储， 然而， 高幅值窄 脉宽的单脉冲施加到相变存储器的存储单元， 会使得存储单元的温度过快， 产生热串扰问题。 发明内容
本发明实施例提供一种相变存储器的数据存储方法及控制装置， 以解决 现有技术实现对相变存储器的多值存储时产生的热串扰的问题。
第一方面， 本发明实施例提供一种相变存储器的数据存储方法， 包括： 获取待存储数据， 所述待存储数据为多位数据；
根据所述待存储数据， 产生擦脉冲信号和写脉冲信号； 其中， 所述写脉 冲信号为包括至少两个连续脉冲的信号； 所述至少两个连续脉冲之间的间隔 相同， 且所述至少两个连续脉冲之间的间隔为根据所述待存储数据而确定的 值；
将所述擦脉冲信号施加至所述相变存储器的存储单元使所述存储单元变 为晶态；
将所述写脉冲信号施加至所述存储单元使所述存储单元变为第一电阻值 的非晶态， 所述第一电阻值的大小与所述至少两个连续脉冲之间的间隔满足 特定函数关系， 以通过所述存储单元的第一电阻值的非晶态表征所述待存储 数据。
根据第一方面， 在第一方面的第一种可能实现的方式中， 所述方法还包 括：
确定所述待存储数据是否为所述多位数据中的最大数据或最小数据； 所述根据所述待存储数据， 产生擦脉冲信号和写脉冲信号包括： 当所述待存储数据不为所述多位数据中的最大数据或最小数据时， 根据 所述待存储数据， 产生所述擦脉冲信号和所述写脉冲信号。
根据第一方面的第一种可能实现的方式， 在第二种可能实现的方式中， 所述方法还包括：
当所述待存储数据为所述多位数据中的最大数据或最小数据时， 根据所 述待存储数据产生擦脉冲信号， 将所述擦脉冲信号施加至所述相变存储器的 存储单元使所述存储单元变为晶态， 以通过所述存储单元的晶态表征所述待 存储数据。
根据第一方面至第一方面的第二种可能实现的方式中任一一种， 在第三 种可能实现的方式中， 所述至少两个连续脉冲的脉宽相同。
根据第一方面的第三种可能实现的方式， 在第四种可能实现的方式中， 所述至少两个连续脉冲的脉宽范围为 30ns-50ns。
根据第一方面至第一方面的第四种可能实现的方式中任一一种， 在第五 种可能实现的方式中， 所述至少两个连续脉冲之间的间隔的范围为 10ns-50ns。
根据第一方面至第一方面的第五种可能实现的方式中任一一种， 在第六 种可能实现的方式中， 所述擦脉冲信号和所述写脉冲信号为电压信号； 或者， 所述擦脉冲信号和所述写脉冲信号为电流信号。
根据第一方面的第六种可能实现的方式， 在第七种可能实现的方式中， 所述写脉冲信号为包括至少两个连续脉冲的电压信号， 且所述至少两个连续 脉冲的幅值范围为 lv-1.5v。
第二方面， 本发明实施例还提供一种相变存储器的控制装置， 包括： 获取模块， 用于获取待存储数据， 所述待存储数据为多位数据； 生成模块， 用于根据所述待存储数据， 产生擦脉冲信号和写脉冲信号； 其中， 所述写脉冲信号为包括至少两个连续脉冲的信号； 所述至少两个连续 脉冲之间的间隔相同， 且所述至少两个连续脉冲之间的间隔为根据所述待存 储数据而确定的值；
控制模块， 用于将所述擦脉冲信号施加至所述相变存储器的存储单元使 所述存储单元变为晶态， 将所述写脉冲信号施加至所述存储单元使所述存储 单元变为第一电阻值的非晶态， 所述第一电阻值的大小与所述至少两个连续 脉冲之间的间隔满足特定函数关系， 以通过所述存储单元的第一电阻值的非 晶态表征所述待存储数据。
根据第二方面， 在第二方面的第一种可能实现的方式中， 所述控制装置 还包括：
判断模块， 用于确定所述待存储数据是否为所述多位数据中的最大数据 或最小数据；
所述生成模块， 还用于当所述待存储数据不为所述多位数据中的最大数 据或最小数据时， 根据所述待存储数据， 产生所述擦脉冲信号和所述写脉冲 信号。
根据第二方面的第一种可能实现的方式， 在第二种可能实现的方式中， 所述生成模块， 还用于当所述待存储数据为所述多位数据中的最大数据或最 小数据时， 根据所述待存储数据产生所述擦脉冲信号；
所述控制模块， 还用于将所述擦脉冲信号施加至所述相变存储器的存储 单元使所述存储单元变为晶态， 以通过所述存储单元的晶态表征所述待存储 数据。
第三方面， 本发明实施例还提供一种相变存储器的控制装置， 包括： 处 理器、 通信总线； 所述处理器与所述通信总线连接， 所述通信总线与所述相 变存储器的存储单元相连接；
所述处理器， 用于执行上述任一所述的相变存储器的数据存储方法， 并 通过所述通信总线对所述存储单元的数据存储进行控制。
第四方面， 本发明实施例还提供一种计算机可读介质， 包括计算机执行 指令， 以供计算机的处理器进行调取并执行； 所述计算机执行指令包括上述 任一项所述的相变存储器的数据存储方法对应的计算机指令。
本发明实施例提供的相变存储器的数据存储方法及控制装置， 根据待存 储数据生成包括至少两个连续脉冲的写脉冲信号， 并将该写脉冲信号施加至 相变存储器的存储单元， 使该存储单元变为与该待存储数据对应电阻值的非 晶态来表征该待存储数据， 实现单个存储单元的多值存储， 由于该写脉冲信 号包括至少两个连续脉冲，能够降低单次施加脉冲对该存储单元的温度增加， 减轻由于热量过大所引起的热串扰问题。 附图说明 为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作一简单地介绍， 显而易见地， 下 面描述中的附图是本发明的一些实施例， 对于本领域普通技术人员来讲， 在 不付出创造性劳动性的前提下， 还可以根据这些附图获得其他的附图。 图 1为本发明实施例一所提供的相变存储器的数据存储方法的流程图； 图 2为本发明实施例二所提供的相变存储器的数据存储方法的流程图； 图 3为本发明实施例二所提供的相变存储器的数据存储方法的流程图； 图 4为相变存储器的存储单元的结构示意图；
图 5为本发明实施例四所提供的相变存储器的数据存储方法的流程图； 图 6为本发明实施例五所提供的相变存储器的控制装置的结构示意图。 图 7为本发明实施例六所提供的相变存储器的控制装置与相变存储器的 连接示意图；
图 8为本发明实施例七所提供的计算机可读介质的结构示意图。 具体实施方式 为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例是本发明一部分实施例， 而不是全部的实施例。 基于 本发明中的实施例， 本领域普通技术人员在没有作出创造性劳动前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本实施例提供一种相变存储器的存储方法， 根据多位的待存储数据产生 写脉冲信号， 该写脉冲信号为包括至少两个连续脉冲的信号， 该至少两个连 续脉冲之间的间隔相同， 且该至少两个连续脉冲之间的间隔需要根据该多位 的待存储数据来确定， 从而通过将该写脉冲信号施加至存储单元， 可使得该 存储单元变为第一电阻值的非晶态， 第一电阻值的大小与该至少两个连续脉 冲之间的间隔有关， 因而通过具有不同间隔至少两个连续脉冲的写脉冲信号 可使得该存储单元获得不同电阻值的非晶态以分别记录不同的多位数据， 实 现单个存储单元的多值存储。 上述过程中， 由于写脉冲信号为包括至少两个 连续脉冲的信号， 能够有效减小写脉冲信号的幅值， 降低单次施加脉冲对该 存储单元的温度增加， 从而解决现有技术中采用高幅值窄脉宽的单脉冲实现 的多值存储产生的热串扰问题。 图 1为本发明实施例一所提供的相变存储器 的数据存储方法。 如图 1所示， 该方法具体包括如下歩骤：
歩骤 101、 获取待存储数据， 该待存储数据为多位数据。
该多位数据可以为多位二进制数据。 该待存储数据可以为接收外部输入 的数据， 也可以为预先配置在该相变存储器的存储单元内部的数据， 还可以 为根据预先配置的数据产生规则所生产的数据。若该待存储数据为 n位数据， 则该待存储数据可以为 2Λη个数据中任一一个数据。
歩骤 102、 根据该待存储数据， 产生擦脉冲信号和写脉冲信号； 其中， 该写脉冲信号为包括至少两个连续脉冲的信号； 该至少两个连续脉冲之间的 间隔相同， 且该至少两个连续脉冲之间的间隔为根据该待存储数据而确定的 值。
在本发明实施例中， 可以利用变相存储器的存储单元处于不同电阻值来 表征不同的待存储数据。 由于存储单元的电阻值与该存储单元的相变材料层 的非晶化程度密切相关， 而非晶化程度取决于相变材料层的温度， 施加具有 不同参数的电脉冲可以把相变材料加热到不同的温度， 因此， 可以根据不同 的待存储数据，产生具有不同间隔的至少两个连续脉冲所构成的写脉冲信号， 使得存储单元处于不同电阻值的非晶态， 以存储不同的待存储数据， 实现多 值存储。 而当写脉冲信号为包括至少两个连续脉冲的信号时， 能够降低单次 施加脉冲对该存储单元的温度增加， 从而解决现有技术中采用高幅值窄脉宽 的单脉冲实现的多值存储产生的热串扰问题。
具体地， 该至少两个连续脉冲间的间隔可以相同， 且该至少两个连续脉 冲间的间隔可以根据该待存储数据来确定。 例如， 可以将该预设的间隔范围 进行 2Λη等分的划分， 并按照该待存储数据在 2 个数据中的大小位置， 确 定该至少两个连续脉冲间的间隔。 也就是说， 相邻的该待存储数据对应的写 脉冲信号中至少两个连续脉冲间的间隔为相邻等分对应的间隔。 需要说明的 是， 实际应用情况中， 相邻的该待存储数据对应的该至少两个连续脉冲之间 的间隔还需根据该至少两个连续脉冲的个数、 单个脉冲的脉宽及脉冲幅值进 行微调。 具体来说， 若该至少两个连续脉冲的个数较多， 则对应的幅值较小， 对应的， 若该至少两个连续脉冲的个数较小， 则该对应的脉冲间隔则较小， 以减少热量的损失， 充分利用脉冲产生的热量； 若该单个脉冲的脉宽较窄， 则对应的脉冲间隔较小； 若脉冲幅值较小， 则对应的脉冲间隔较小。
又例如， 该至少两个连续脉冲之间的间隔还可以是根据该待存储数据通 过预设的数据与脉冲间隔对应关系表所获得的值。 若该待存储数据为 η位数 据， 则该预设的数据与脉冲间隔对应关系表至少包括 2Λη个数据各自对应的 脉冲间隔。 该预设的数据与脉冲间隔对应关系表中 2Λη个数据各自对应的脉 冲间隔的具体数值， 可以是在该歩骤 102之前， 可根据该待存储数据的位数， 分别对该待存储数据的所有数据进行测试实验， 从而获得存储该些数据对应 的非晶态的电阻值所需的脉冲间隔， 并将该些待存储数据及其对应的脉冲将 进行保存获得该数据脉冲间隔对应关系表。 歩骤 103、 将该擦脉冲信号施加至该相变存储器的存储单元使该存储单 元变为晶态。
由于在初始状态下， 该存储单元多为非晶态。 为保证表征该待存储数据 的非晶态电阻值的稳定性及准确性， 需对该存储单元施加擦脉冲信号， 使得 该存储单元位于稳定的晶态。 通常情况下， 该存储单元位于晶态时的电阻值 小于该存储单元位于非晶态时的电阻值。
具体地， 该擦脉冲信号可包括至少一个低幅值长脉宽的脉冲的信号。 若 该擦脉冲信号为包括一个脉冲的信号， 则该一个脉冲的幅值可以小于预设幅 值， 该预设幅值可以为将该存储单元的相变材料层加热至熔点温度所对应的 脉冲幅值。 该擦脉冲的脉宽大于根据小于该预设幅值的脉冲， 将该存储单元 的相变材料加热至晶化温度所需的时间。 该擦脉冲信号所包括的脉冲的幅值 可以为 0.5v-1.5v之间，该擦脉冲信号所包括的脉冲的脉宽可以为 100ns-300ns 之间。 由于将该存储单元的相变材料层加热至熔点温度所需要的热量固定， 若该擦脉冲信号包括至少两个连续脉冲， 则该擦脉冲信号所包括脉冲的幅值 小于该擦脉冲信号包括一个脉冲时所对应的幅值。 该擦脉冲信号所包括脉冲 的幅值及脉冲的具体个数， 可根据该存储单元的相变材料层的材料或该存储 单元的内部结构确定。 举例来说， 如该擦脉冲信号包括一个脉冲的信号， 该 擦脉冲信号可以包括幅值为 0.8v， 脉宽为 300ns的电脉冲的信号。
歩骤 104、 将写脉冲信号施加至该存储单元使该存储单元变为第一电阻 值的非晶态， 该第一电阻值的大小与该至少两个连续脉冲之间的间隔满足特 定函数关系， 以通过该存储单元的第一电阻值的非晶态表征该待存储数据。
对该存储单元施加该写脉冲信号， 使得该相变材料层变为第一电阻值的 非晶态， 具体地， 通过该写脉冲信号产生的焦耳热对该存储单元的相变材料 层进行加热， 将该相变材料层加热至熔点温度以上， 并迅速冷却至晶化温度 以下， 使得该相变材料层变为第一电阻值的非晶态， 该第一电阻值的大小与 该至少两个连续脉冲间的间隔满足特定函数关系。 此时， 该第一电阻值的大 小大于该存储单元为晶态时的电阻值。
具体地，该存储单元非晶态的电阻值 R与相变材料层的非晶化率 Ca密切 相关， 且满足如下公式 ( 1 ) ： R = (l - Ca )Rc。 + CaRa。 ( 1 ) 。 该公式 （1 ) 中 R 表示存储单元非晶态的电阻值， ^表示相变材料层的非晶化率， 。和 。分 别是相变单元完全晶态和完全非晶态时的电阻值。 对于特定材料的相变材料 层具有固定的 。和 。， 可预先根据实验获得。
该非晶化率 ca实际为该相变材料层的非晶化区域的体积 V。与该相变 材料层总体积 VOTr的比值， 可表示为如下公式 （2 ) ：
( 2 ) 。
该相变材料层的非晶化区域的体积 V。可根据该相变材料层的晶化与 非晶化的临界温度 Ta, 及该相变材料层的熔点温度 Tm,通过如下公式（3 ) 定
Tk)十 0(Tf
dt V∞ \ Ui / a ( 3 ) 。 对于某一相变存储器， 其存储单元的相变材料层的材料是已知且确 定， 那么， 该相变材料层的熔点温度 rm即为已知的。
对于， 相变材料层的晶化与非晶化的临界温度 rfl， 可根据施加至该相 变材料层的热量， 也就是施加的写脉冲产生的焦耳热采用如下公式 （4 ) 获得：
T = ~~ d-dt
α J C ( 4 ) 。 上述， ^为耗散功率， 即功率的耗损， 而^为施加的写脉冲信号产生 的焦耳热， 可根据该写脉冲信号中至少两个连续脉冲之间的间隔等参数获 得。 因而， 该存储单元非晶态的电阻值， 即该第一电阻值的大小， 与施加 的写脉冲信号中至少两个连续脉冲之间的间隔满足上述函数关系。
具体地， 由于该写脉冲信号中至少两个连续脉冲之间的间隔是根据该 待存储数据确定的， 因而对于不同的待存储数据其对应的该写脉冲信号中 至少两个连续脉冲之间的间隔不同。将该具有不同脉冲间隔的写脉冲信号施 加至该存储单元所产生的热量不同， 该存储单元的相变材料层所加热的温度 必然不同， 不同温度所获得的非晶态的电阻值也不同。 该具有不同电阻值的 非晶态的该存储单元可分别用于表征不同的该待存储数据。 施加该具有不同 脉冲间隔的写脉冲信号至该存储单元所获得的该存储单元对应的非晶态的电 阻值不同， 其中， 相邻脉冲间隔所对应的电阻值的差值较大， 超过预设阈值。
该至少两个连续脉冲的幅值大于该擦脉冲信号的幅值， 该至少两个连续 脉冲的脉宽小于该擦脉冲信号的脉宽。 在本实施例方案中， 该至少两个连续 脉冲的幅值可以大于预设幅值， 该预设幅值可以为将该存储单元的相变材料 层加热至熔点温度所对应的脉冲幅值。
由于将该存储单元的相变材料加热至熔点温度所需的热量一定， 采用至 少两个连续脉冲所组成的该写脉冲信号的幅值， 必然小于由单脉冲组成的写 脉冲信号的幅值。 因而对该存储单元施加该写脉冲信号， 降低单次施加脉冲 对该存储单元的温度增加， 从而减少或避免由于热量过大所引起的热串扰问 题。
该至少两个连续脉冲之间存在间隔， 且相邻脉冲之间的间隔相同， 例如 可以均为 50ns。 由于该至少两个连续脉冲彼此之间还存在间隔， 对该存储单 元施加该写脉冲信号， 该存储单元可充分利用施加前面脉冲所产生的热量， 因而， 该至少两个连续脉冲幅值之和， 也小于该单脉冲组成的写脉冲信号的 幅值。 也就是说， 对该存储单元施加该写脉冲信号， 还可减少施加写脉冲信 号所需的总能量， 从而降低功耗。
在该实施例方案中， 对于任一待存储数据均可通过施加擦脉冲信号与写 脉冲信号结合的方式，通过具有一定电阻值的非晶体表征对应的待存储数据。 也就是说， 该实施例方案中， 对存储单元的晶态可不存储任何数据。
本实施例方案中， 可以根据该存储单元的电阻值或电流值大小， 存储记 录对应的数据。 该方案中， 该存储单元电阻值越大或电流值越小， 所存储记 录的数据可以小， 也可以大。 具体地， 该存储单元的电阻值或电流值与其存 储记录的数据的大小对应关系， 可预先进行配置。
需要说明的是， 该至少两个连续脉冲之间的间隔越小， 将该至少两个连 续脉冲施加至该存储单元， 该存储单元所得到的非晶态的电阻值越大。
本实施例方案中， 通过施加至存储单元的根据多位的待存储数据所确定 的写脉冲信号将该存储单元变为与该待存储数据对应电阻值的非晶态， 表征 该待存储数据， 实现单个存储单元的多值存储， 由于该写脉冲信号包括至少 两个连续脉冲， 降低单次施加脉冲对该存储单元的温度增加， 减少或避免由 于热量过大所引起的热串扰问题。
同时， 采用该包括至少两个连续脉冲， 降低写脉冲信号的幅值， 减少脉 冲产生电路对该写脉冲信号的幅值控制难度， 其调整参数较少， 更好地控制 该存储单元不同非晶态的电阻值， 提高采用该存储单元存储多个数据的稳定 性； 由于不同待存储数据的写脉冲信号中仅该至少两个连续脉冲之间的间隔 不同， 使得该脉冲产生电路的结构简单； 而且采用包括至少两个连续脉冲的 写脉冲， 由于充分利用施加脉冲所产生的热量， 还可降低控制功耗， 节约能 源。
本实施例还提供一种相变存储器的数据存储方法。 在本实施例方案中， 可利用相变存储器的晶态存储一部分数据， 利用该相变存储器的不同电阻值 的非晶态存储其余数据。 其中， 可利用晶态存储的一部分数据可以为多位数 据中的最大数据或最小数据。 若该一部分数据为该多位数据的最大数据， 则 利用不同电阻值的非晶态存储的其余数据， 即为该多位数据中除该最大数据 之外的其他数据； 若该一部分数据为该多位数据的最小数据， 则利用不同电 阻值的非晶态存储的其余数据， 即为该多位数据中除该最小数据之外的其他 数据。图 2为本发明实施例二所提供的相变存储器的数据存储方法的流程图。 如图 2所示， 该方案在上述方案中歩骤 102根据该待存储数据， 产生擦脉冲 信号和写脉冲信号之前， 还包括：
歩骤 201、 确定该待存储数据是否为该多位数据中的最大数据或最小数 据。
若该待存储数据为 2位数据， 则该 2位数据中 00为最大数据， 11即为 最大数据。 该歩骤 201实际为确定该待存储数据是否为 00或者 11。
优选的， 上述歩骤 102根据该待存储数据， 产生擦脉冲信号和写脉冲信 号， 具体包括：
歩骤 202、 当该待存储数据不为该多位数据中的最大数据或最小数据时， 根据该待存储数据， 产生该擦脉冲信号和该写脉冲信号。
需要说明的是， 在该歩骤 202后还需执行上述歩骤 103和 104， 以通过 该具有第一电阻值的非晶态表征该待存储数据。
然而， 在本实施例方案中， 对于多位数据中的非最大数据或最小数据， 采用施加擦脉冲信号与写脉冲信号结合的方式， 通过具有一定电阻值的非晶 体表征对应的待存储数据。
上述方案的基础上， 进一歩地， 该方法还包括：
歩骤 203、 当该待存储数据为该多位数据中的最大数据或最小数据时， 根据该待存储数据产生该擦脉冲信号， 将该擦脉冲信号施加至该存储单元使 该存储单元变为晶态， 以通过该存储单元的晶态表征该待存储数据。
而对于， 该多位数据中的最大数据或最小数据， 则可仅采用施加写脉冲 信号的方案， 通过晶态表征该最大数据或最小数据。 也就是说， 该实施例方 案中， 对存储单元的晶态可存储该多位数据中最大数据或最小数据。
需要说明的是， 若通过晶态表征该最大数据， 则对于最小数据还是需要 根据其产生对应的写脉冲信号， 继而施加写脉冲信号的方案， 通过对应电阻 值的非晶态进行表征； 对应的， 若通过晶态表征该最小数据， 则对于最大数 据还是需要根据其产生对应的写脉冲信号， 继而施加写脉冲信号的方案， 通 过对应电阻值的非晶态进行表征。
具体确定该存储单元的晶态表征最大数据还是最小数据， 可以根据预定 的数据存储规则进行确定。 若该数据存储规则为根据该存储单元电阻值从小 到大的顺序， 依次存储从小到大的多位数据， 则通过该晶态表征该最小数据; 若该数据存储规则为根据该存储单元通电时内部电流值从小到大的顺序， 依 次存储从小到大的多位数据。
优选的， 上述任一实施例方案中的， 该至少两个连续脉冲的脉宽相同。 进一歩地， 该至少两个连续脉冲的脉冲范围可以为 30ns-50ns。
具体地， 根据该存储单元的相变材料层的结构和 /或该存储单元的结构， 可在该脉宽范围内选择对应的脉宽。
在上述方案的基础上， 该至少两个连续脉冲之间的间隔的范围为
10ns-50ns。
具体地， 为保证不同脉冲间隔的写脉冲信号对应的存储单元的非晶态电 阻值之间具有差异以便读出并区分该不同的电阻值， 从而保证不同的该存储 多位数据的稳定性。该不同脉冲间隔优选的，可以为 10ns、 15ns, 25ns, 30ns, 40ns, 45ns及 50ns。 假设该待存储数据为 2位数据， 即 00、 01、 10、 11， 4 个数据中任一， 根据该 4个数据所确定的写脉冲信号中至少两个连续脉冲之 间的间隔优选的， 可以为 50ns、 40ns, 25ns及 10ns。
若将该 4个不同脉冲将该的写脉冲信号施加至该存储单元， 则可分别获 得 4种不同的非晶态， 该 4种非晶态分别具有不同的电阻值， 其中， 脉冲间 隔越小的写脉冲信号对应的非晶态的电阻值越大， 电流值则越小。 也就是说， 施加脉冲间隔为 10ns的写脉冲信号至该存储单元，所获得的该存储单元的非 晶态的电阻值最大。 假设该存储单元按照电流值从小到大， 也就是电阻从大 到小的顺序， 分别存储从小到大的数据。 若该待存储数据为 00， 则根据该待 存储数据可确定该写脉冲信号的脉冲间隔为 10ns， 那么将该写脉冲信号施加 至该存储单元可使得该存储单元变为电阻值为 1Μ Ω的非晶态；若该存储数据 为 01， 根据该待存储数据可确定该写脉冲信号的脉冲间隔为 25ns， 那么将该 写脉冲信号施加至该存储单元可使得该存储单元变为电阻值为 100k Ω的非晶 态； 若该存储数据为 10， 根据该待存储数据可确定该写脉冲信号的脉冲间隔 为 40ns， 将该写脉冲信号施加至该存储单元可使得该存储单元变为电阻值为 10k Q的非晶态； 若待存储数据为 11， 根据该待存储数据可确定该写脉冲信 号的脉冲间隔为 50ns， 将该写脉冲信号施加至该存储单元可使得该存储单元 变为电阻值为 10 Ω的非晶态。
更近一歩地， 该擦脉冲信号和该写脉冲信号为电压信号； 或者， 该擦脉 冲信号和该写脉冲信号为电流信号。
若该该写脉冲信号为包括至少两个连续脉冲的电压信号， 且该至少两个 连续脉冲的幅值范围优选为 lv-1.5v。
具体地， 该至少两个连续脉冲的幅值相同。 采用幅值相同的至少两个连 续脉冲的写脉冲， 可简化脉冲产生的结构。该至少两个连续脉冲的幅值相同， 可以均为 1.27v。
本实施例还提供一种相变存储器的数据存储方法。 本实施例通过具体的 实例对上述各实施例方案进行实例说明。 图 3为本发明实施例二所提供的相 变存储器的数据存储方法的流程图。 如图 3所示， 该方法具体包括如下： 歩骤 301、 获取第一待存储数据， 该第一待存储数据为多位数据。
获取该待存储数据可以是根据预先配置的数据生成规则， 所获取的。 在 本实施例中， 该存储单元可存储 2位数据， 该数据生成规则可以为从小到大 的生成规则， 该第一待存储数据可以为 00。
歩骤 302、 根据该第一待存储数据产生擦脉冲信号及第一写脉冲信号， 该第一写脉冲信号为包括两个连续脉冲的信号， 该两个连续脉冲的间隔为根 据该第一待存储数据所确定的第一间隔。
若该第一写脉冲信号及该擦脉冲信号为电压信号， 该擦脉冲信号可以为 幅值为 0.8v、 脉宽为 300ns的电脉冲。 该第一写脉冲信号为包括两个幅值为 1.27v、 脉宽 30ns的连续脉冲的信号。 该第一间隔可以为 50ns。
歩骤 303、 将该擦脉冲信号施加至存储单元的上电极， 使该存储单元的 相变材料层变为晶态， 将该第一写脉冲信号施加至该存储单元的上电极， 使 该存储单元的相变材料层变为第一非晶态， 通过该第一非晶态存储该第一待 存储数据。
图 4为相变存储器的存储单元的结构示意图。 如图 4所示， 该存储单元 包括： 上电极 41、 下电极 44、 相变材料层 42和绝缘层 43。 该上电极 41和 该下电极 44均为导电材料组成， 如金属铝电极。 该相变材料层 42为 GST材 料。 其中， 该上电极 41可通过与控制器的信号源连接， 接收施加的擦脉冲或 写脉冲。 该下电极 42可通过选择晶体管接地。
当该存储单元的上电极 41与脉冲产生电路的输出端连接，接收到该擦脉 冲信号之后，可通过该擦脉冲信号对该相变材料层 42进行加热，产生焦耳热， 将该相变材料层 42的温度加热至该相变材料层 42的晶化温度以上， 熔点温 度以下。 在本实施例中， 该晶化温度例如可以为 400k， 该熔点温度为 600k。 该擦脉冲信号施加过后， 该存储单元的该相变材料层则变为电阻为 10Ω的晶 态。
将具有第一间隔的写脉冲信号施加至存储单元的上电极 41， 通过该写脉 冲信号产生的焦耳热对该相变材料层 42的进行加热， 将该相变材料层 42加 热至熔点温度以上， 并迅速冷却至晶化温度以下， 使得该相变材料层 42变为 具有第一电阻值的非晶态。
将具有该第一间隔的写脉冲信号施加至该存储单元的相变材料层， 可使 得该存储单元变为具有 1000ΚΩ的非晶态。 即该第一电阻值可以为 1000ΚΩ。
歩骤 304、 获取第二待存储数据。
该第二待存储数据可以为 01。
歩骤 305、 根据该第二待存储数据产生该擦脉冲信号及第二写脉冲信号， 该第二写脉冲信号为包括两个连续脉冲的信号， 该两个连续脉冲之间的间隔 为根据该第二待存储数据所确定的第二间隔。
该第二间隔可以为 40ns。 该第二写脉冲信号的脉宽及幅值可以与该第一 写脉冲信号相同。 该擦脉冲信号可以与上述擦脉冲信号相同。 歩骤 306、 将该擦脉冲信号施加至该存储单元的上电极， 使该存储单元 的相变材料层变为晶态，并将该第二写脉冲信号施加至该存储单元的上电极， 使该存储单元的相变材料变为第二非晶态， 通过该第二非晶态存储该第二待 存储数据。
将该第二写脉冲信号施加至该存储单元的上电极， 可将该存储单元的相 变材料层变为该第二非晶态， 如电阻值为 100kQ的非晶态。
歩骤 307、 获取第三待存储数据。
该第三待存储数据可以为 10。
歩骤 308、 根据该第三待存储数据产生该擦脉冲信号及第三写脉冲信号， 该第三写脉冲信号为包括两个连续脉冲的信号， 该两个连续脉冲之间的间隔 为根据该第三待存储数据所确定的第三间隔。
该第三间隔可以为 25ns。 该第三写脉冲信号的脉宽及幅值可以与该第一 写脉冲信号相同。 该擦脉冲信号可以与上述擦脉冲信号相同， 为幅值为 0.8v、 脉宽为 300ns的电脉冲。
歩骤 309、 将该擦脉冲信号施加至该存储单元的上电极， 使该存储单元 的相变材料层变为晶态， 将该第三写脉冲信号施加至该存储单元的上电极， 使该存储单元的相变材料变为第三非晶态， 通过该第三非晶态存储该第三待 存储数据。
将该间隔为 25ns的该第三写脉冲信号施加至该存储单元的上电极， 可将 该存储单元的相变材料层变为该第三非晶态， 如电阻值为 10kQ的非晶态。
歩骤 310、 获取第四待存储数据。
该第四待存储数据可以为 11。
歩骤 311、 根据该第四待存储数据产生该擦脉冲信号及第四写脉冲信号， 该第四写脉冲信号为包括两个连续脉冲的信号， 该两个连续脉冲之间的间隔 为根据该第四待存储数据所确定的第四间隔。
该第四间隔可以为 10ns。 该第四写脉冲信号的脉宽及幅值可以与该第一 写脉冲信号相同。 该擦脉冲信号可以与上述擦脉冲信号相同。
歩骤 312、 将该擦脉冲信号施加至该存储单元的上电极， 使该存储单元 的相变材料层变为晶态， 将该第四写脉冲信号施加至该存储单元的上电极， 使该存储单元的相变材料变为第四非晶态， 通过该第四非晶态存储该第四待 存储数据。
将该间隔为 10ns的写脉冲信号施加至该存储单元的上电极， 可将该存储 单元的相变材料层变为该第四非晶态， 如电阻值为 10Ω的非晶态。
在本实施例中， 该存储单元可具有四种不同电阻值的非晶态及晶态。 该 存储单元的非晶态， 按照以电阻值的不同， 从小到大依次为第一非晶态、 第 二非晶态、 第三非晶态及第四非晶态。 该存储单元的第一非晶态、 第二非晶 态、 第三非晶态及第四非晶态可分别存储 00、 01、 10、 11， 以此来存储 4个 2位数据。
虽然， 本实施例中以两个相同脉冲所组成的写脉冲仅为本实施例方案的 优选方案， 然本发明并不依次为限制， 该方案还可通过大于两个的相同脉冲 组成来实现。
本实施例具体， 通过施加至存储单元的根据待存储数据确定至少两个连 续脉冲之间的间隔的写脉冲信号将该存储单元变为与该待存储数据对应电阻 值的非晶态， 存储对应的该待存储数据， 实现单个存储单元的多位数据存储， 通过包括至少两个连续脉冲的写脉冲信号， 实现单存储单元的多位数据从而 提高该存储单元的存储密度。 由于其调整参数较少， 还可更好地控制该存储 单元不同非晶态的电阻值， 提高采用该存储单元存储多个数据的稳定性。
本实施例还提供一种相变存储器的数据存储方法。 本实施例通过具体的 实例对上述各实施例方案进行实例说明。 图 5为本发明实施例四所提供的相 变存储器的数据存储方法的流程图。 如图 5所示， 该方法具体包括如下： 歩骤 501、 获取待存储数据， 该待存储数据为多位数据。
歩骤 502、 确定该待存储数据是否为该多位数据中的最小数据。
获取该第一待存储数据可以是根据预先配置的数据生成规则，所获取的， 也可以为获取外部输入设备所输入的数据。 确定该待存储数据是否为该多位 数据中的最小数据实际为确定该待存储数据的每一位是否均为 0， 若均为 0， 则该待存储数据为该多位数据中的最小数据。
歩骤 503、 若该待存储数据为该多位数据中的最小数据， 则根据该待存 储数据产生该擦脉冲信号， 将该擦脉冲信号施加至存储单元的上电极， 使该 存储单元的相变材料层变为晶态， 通过该晶态存储该待存储数据。
歩骤 504、 若该待存储数据不是该多位数据中的最小数据， 则根据该待 存储数据产生该擦脉冲信号及写脉冲信号， 该写脉冲信号为包括两个连续脉 冲的信号， 该两个连续脉冲之间的间隔为根据该待存储数据所确定的间隔。
歩骤 505、 将该擦脉冲信号施加至存储单元的上电极， 使该存储单元的 相变材料层变为晶态， 将该写脉冲信号施加至该存储单元的上电极， 使该存 储单元的相变材料层变为非晶态， 通过该非晶态存储该待存储数据。
在该实施例中， 该晶态可用于存储该多位数据中的最小数据， 对应的， 该晶态还可用于存储该多位数据中的最大数据， 其对应的方法歩骤与上述实 施例类似， 在此不再赘述。
本实施例具体通过晶态存储该多位数据中的最小数据对上述实施例方案 进行具体说明， 其有益效果与上述实施例类似， 在此不再赘述。
虽然， 本实施例中以两个相同脉冲所组成的写脉冲信号仅为本实施例方 案的优选方案， 然本发明并不依次为限制， 该方案还可通过大于两个的相同 脉冲组成来实现。
本实施例还提供一种相变存储器的控制装置。 图 6为本发明实施例五所 提供的相变存储器的控制装置的结构示意图。 如图 6所示， 该相变存储器的 控制装置 600包括：
获取模块 601， 用于获取待存储数据， 该待存储数据为多位数据。
生成模块 602， 用于根据该待存储数据， 产生擦脉冲信号和写脉冲信号； 其中， 该写脉冲信号为包括至少两个连续脉冲的信号， 该至少两个连续脉冲 之间的间隔相同， 且该至少两个连续脉冲之间的间隔为根据该待存储数据而 确定的值。
控制模块 603， 用于将该擦脉冲信号施加至该相变存储器的存储单元使 该存储单元变为晶态， 将该写脉冲信号施加至该存储单元使该存储单元变为 第一电阻值的非晶态， 该第一电阻值的大小与该至少两个连续脉冲之间的间 隔满足特定函数关系， 以通过该存储单元的第一电阻值的非晶态表征该待存 储数据。
进一歩地， 如上所述的该相变存储器的控制装置 600还包括：
判断模块， 用于确定该待存储数据是否为该多位数据中的最大数据或最 小数据。
生成模块 602， 还用于当该待存储数据不为该多位数据中的最大数据或 最小数据时， 根据该待存储数据， 产生该擦脉冲信号和该写脉冲信号。
优选的， 上述生成模块 602， 还用于当该待存储数据为该多位数据中的 最大数据或最小数据时， 根据该待存储数据产生擦脉冲信号。
控制模块 603， 还用于将该擦脉冲信号施加至该存储单元使该存储单元 变为晶态， 以通过该存储单元的晶态表征该待存储数据。
本实施例方案提供一种相变存储器的控制装置， 可实施上述任一实施例 所述的相变存储器的数据存储方法， 其有益效果与上述实施例类似， 在此不 再赘述。
本实施例还提供一种相变存储器的控制装置。 图 7为本发明实施例六所 提供的相变存储器的控制装置与相变存储器的连接示意图。 如图 7所示， 该 相变存储器的控制装置 700包括：处理器 701、控制总线 702 ;该处理器 702 通过该控制总线 702与相变存储器 703的存储单元 704相连接。
处理器 701， 用于执行上述任一实施例所述的相变存储器的数据存储 方法， 并通过控制总线 702控制存储单元 704进行数据存储。
优选的， 该相变存储器的控制装置 700还包括存储器， 用以存储一段程 序， 该处理器 701通过调用该存储器中的程序以执行上述数据存储的方法歩 骤。 存储器 701可能包含高速随机存取存储器 （Random Access Memory, 简称 RAM) ， 也可能还包括非不稳定的存储器 （non-volatile memory) ， 例如至少一个磁盘存储器。
本实施例方案提供一种相变存储器的控制装置， 可实施上述任一实施例 所述的相变存储器的数据存储方法， 其有益效果与上述实施例类似， 在此不 再赘述。
本发明实施例还提供一种计算机可读介质。 图 8为本发明实施例七所提 供的计算机可读介质的结构示意图。 如图 8所示， 该计算机可读介质 800包 括： 计算机执行指令 801。 该计算机执行指令 801 可供计算机的处理器进行 调取并执行。 该计算机执行指令包括如上任一项所述的相变存储器的数据存 储方法对应的计算机指令。
该实施例方案提供的计算机可读介质所包括的计算机执行指令可包括上 述任一实施例所述的相变存储器的数据存储方法对应的计算机指令， 以供计 算机的处理器进行调取并执行， 其有益效果与上述实施例类似， 在此不再赘 述。
本领域普通技术人员可以理解： 实现上述方法实施例的全部或部分歩骤 可以通过程序指令相关的硬件来完成， 前述的程序可以存储于一计算机可读 取存储介质中， 该程序在执行时， 执行包括上述方法实施例的歩骤； 而前述 的存储介质包括： ROM、 RAM, 磁碟或者光盘等各种可以存储程序代码的介 质。
最后应说明的是： 以上各实施例仅用以说明本发明的技术方案， 而非对 其限制； 尽管参照前述各实施例对本发明进行了详细的说明， 本领域的普通 技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改， 或者对其中部分或者全部技术特征进行等同替换； 而这些修改或者替换， 并 不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims

权利 要 求 书
1、 一种相变存储器的数据存储方法， 其特征在于， 包括：
获取待存储数据， 所述待存储数据为多位数据；
根据所述待存储数据， 产生擦脉冲信号和写脉冲信号； 其中， 所述写脉 冲信号为包括至少两个连续脉冲的信号； 所述至少两个连续脉冲之间的间隔 相同， 且所述至少两个连续脉冲之间的间隔为根据所述待存储数据而确定的 值；
将所述擦脉冲信号施加至所述相变存储器的存储单元使所述存储单元变 为晶态；
将所述写脉冲信号施加至所述存储单元使所述存储单元变为第一电阻值 的非晶态， 所述第一电阻值的大小与所述至少两个连续脉冲之间的间隔满足 特定函数关系， 以通过所述存储单元的第一电阻值的非晶态表征所述待存储 数据。
2、 根据权利要求 1所述的方法， 其特征在于， 还包括：
确定所述待存储数据是否为所述多位数据中的最大数据或最小数据； 所述根据所述待存储数据， 产生擦脉冲信号和写脉冲信号包括： 当所述待存储数据不为所述多位数据中的最大数据或最小数据时， 根据 所述待存储数据， 产生所述擦脉冲信号和所述写脉冲信号。
3、 根据权利要求 2所述的方法， 其特征在于， 还包括：
当所述待存储数据为所述多位数据中的最大数据或最小数据时， 根据所 述待存储数据产生擦脉冲信号， 将所述擦脉冲信号施加至所述相变存储器的 存储单元使所述存储单元变为晶态， 以通过所述存储单元的晶态表征所述待 存储数据。
4、 根据权利要求 1-3中任一项所述的方法， 其特征在于， 所述至少两个 连续脉冲的脉宽相同。
5、 根据权利要求 4所述的方法， 其特征在于， 所述至少两个连续脉冲的 脉宽范围为 30ns-50ns。
6、 根据权利要求 1-5中任一项所述的方法， 其特征在于， 所述至少两个 连续脉冲之间的间隔的范围为 10ns-50ns。
7、 根据权利要求 1-6中所述的方法， 其特征在于， 所述擦脉冲信号和所 述写脉冲信号为电压信号； 或者， 所述擦脉冲信号和所述写脉冲信号为电流 信号。
8、 根据权利要求 7所述的方法， 其特征在于， 所述写脉冲信号为包括至 少两个连续脉冲的电压信号， 且所述至少两个连续脉冲的幅值范围为 lv-1.5v。
9、 一种相变存储器的控制装置， 其特征在于， 包括：
获取模块， 用于获取待存储数据， 所述待存储数据为多位数据； 生成模块， 用于根据所述待存储数据， 产生擦脉冲信号和写脉冲信号； 其中， 所述写脉冲信号为包括至少两个连续脉冲的信号； 所述至少两个连续 脉冲之间的间隔相同， 且所述至少两个连续脉冲之间的间隔为根据所述待存 储数据而确定的值；
控制模块， 用于将所述擦脉冲信号施加至所述相变存储器的存储单元使 所述存储单元变为晶态， 将所述写脉冲信号施加至所述存储单元使所述存储 单元变为第一电阻值的非晶态， 所述第一电阻值的大小与所述至少两个连续 脉冲之间的间隔满足特定函数关系， 以通过所述存储单元的第一电阻值的非 晶态表征所述待存储数据。
10、 根据权利要求 9所述的装置， 其特征在于， 还包括：
判断模块， 用于确定所述待存储数据是否为所述多位数据中的最大数据 或最小数据；
所述生成模块， 还用于当所述待存储数据不为所述多位数据中的最大数 据或最小数据时， 根据所述待存储数据， 产生所述擦脉冲信号和所述写脉冲 信号。
11、 根据权利要求 10所述的装置， 其特征在于，
所述生成模块， 还用于当所述待存储数据为所述多位数据中的最大数据 或最小数据时， 根据所述待存储数据产生所述擦脉冲信号；
所述控制模块， 还用于将所述擦脉冲信号施加至所述相变存储器的存储 单元使所述存储单元变为晶态， 以通过所述存储单元的晶态表征所述待存储 数据。
12、 一种相变存储器的控制装置， 其特征在于， 包括： 处理器、 通信总 线； 所述处理器与所述通信总线连接， 所述通信总线与所述相变存储器的存 储单元相连接；
所述处理器， 用于执行上述权利要求 1-8 中任一所述的相变存储器的数 据存储方法， 并通过所述通信总线对所述存储单元的进行数据存储。
13、 一种计算机可读介质， 其特征在于， 包括计算机执行指令， 以供计 算机的处理器进行调取并执行； 所述计算机执行指令包括权利要求 1-8 中任 一项所述的相变存储器的数据存储方法对应的计算机指令。
PCT/CN2014/082918 2014-07-24 2014-07-24 相变存储器的数据存储方法及控制装置 WO2016011638A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201480037842.2A CN105723461A (zh) 2014-07-24 2014-07-24 相变存储器的数据存储方法及控制装置
PCT/CN2014/082918 WO2016011638A1 (zh) 2014-07-24 2014-07-24 相变存储器的数据存储方法及控制装置
JP2017504023A JP6388422B2 (ja) 2014-07-24 2014-07-24 相変化メモリのデータ記憶方法及び制御装置
KR1020177004140A KR20170031746A (ko) 2014-07-24 2014-07-24 데이터 저장 방법 및 상변화 메모리
US15/412,795 US10083749B2 (en) 2014-07-24 2017-01-23 Data storage method and phase change memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2014/082918 WO2016011638A1 (zh) 2014-07-24 2014-07-24 相变存储器的数据存储方法及控制装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/412,795 Continuation US10083749B2 (en) 2014-07-24 2017-01-23 Data storage method and phase change memory

Publications (1)

Publication Number Publication Date
WO2016011638A1 true WO2016011638A1 (zh) 2016-01-28

Family

ID=55162437

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/082918 WO2016011638A1 (zh) 2014-07-24 2014-07-24 相变存储器的数据存储方法及控制装置

Country Status (5)

Country Link
US (1) US10083749B2 (zh)
JP (1) JP6388422B2 (zh)
KR (1) KR20170031746A (zh)
CN (1) CN105723461A (zh)
WO (1) WO2016011638A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11335403B2 (en) 2018-06-06 2022-05-17 Micron Technology, Inc. Techniques for programming multi-level self-selecting memory cell

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100067291A1 (en) * 2007-03-02 2010-03-18 Elpida Memory, Inc. Method for programming phase-change memory and method for reading date from the same
CN101699562A (zh) * 2009-11-23 2010-04-28 中国科学院上海微系统与信息技术研究所 一种相变存储器的擦写方法
CN101763891A (zh) * 2008-12-24 2010-06-30 复旦大学 一种相变存储器单元及其操作方法
CN101777380A (zh) * 2009-01-12 2010-07-14 旺宏电子股份有限公司 写入相变存储器元件的方法
CN103093815A (zh) * 2013-01-10 2013-05-08 华中科技大学 一种多值相变随机存储器的存储单元及操作方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228524A (en) * 1979-01-24 1980-10-14 Harris Corporation Multilevel sequence of erase pulses for amorphous memory devices
JP4285899B2 (ja) 2000-10-10 2009-06-24 三菱電機株式会社 溝を有する半導体装置
JP3722287B2 (ja) 2002-06-11 2005-11-30 アサ電子工業株式会社 リミットスイッチ
US6813177B2 (en) * 2002-12-13 2004-11-02 Ovoynx, Inc. Method and system to store information
KR100498493B1 (ko) 2003-04-04 2005-07-01 삼성전자주식회사 저전류 고속 상변화 메모리 및 그 구동 방식
US7327602B2 (en) 2004-10-07 2008-02-05 Ovonyx, Inc. Methods of accelerated life testing of programmable resistance memory elements
JP2006260703A (ja) 2005-03-18 2006-09-28 Sharp Corp 不揮発性半導体記憶装置
JP4313372B2 (ja) * 2005-05-11 2009-08-12 シャープ株式会社 不揮発性半導体記憶装置
JP2007080311A (ja) * 2005-09-12 2007-03-29 Sony Corp 記憶装置及び半導体装置
KR100738092B1 (ko) 2006-01-05 2007-07-12 삼성전자주식회사 상전이 메모리 소자의 멀티-비트 동작 방법
US7626858B2 (en) 2006-06-09 2009-12-01 Qimonda North America Corp. Integrated circuit having a precharging circuit
US7903447B2 (en) 2006-12-13 2011-03-08 Macronix International Co., Ltd. Method, apparatus and computer program product for read before programming process on programmable resistive memory cell
US20080266802A1 (en) 2007-04-30 2008-10-30 Rockwell Automation Technologies, Inc. Phase change cooled electrical connections for power electronic devices
KR101274190B1 (ko) 2007-07-30 2013-06-14 삼성전자주식회사 저항체를 이용한 비휘발성 메모리 장치
KR101390337B1 (ko) 2007-09-13 2014-04-29 삼성전자주식회사 멀티-레벨 상변환 메모리 장치, 그것의 프로그램 방법,그리고 그것을 포함한 메모리 시스템
KR101291222B1 (ko) * 2007-11-29 2013-07-31 삼성전자주식회사 상변화 메모리 소자의 동작 방법
KR20090095313A (ko) 2008-03-05 2009-09-09 삼성전자주식회사 저항성 메모리 소자의 프로그래밍 방법
KR101430171B1 (ko) 2008-07-18 2014-08-14 삼성전자주식회사 다중치 상변화 메모리 소자
CN101359504B (zh) 2008-08-05 2011-08-10 中国科学院上海微系统与信息技术研究所 高速写入相变存储器及其高速写入方法
US20100067290A1 (en) 2008-09-15 2010-03-18 Savransky Semyon D Method of programming of phase-change memory and associated devices and materials
US8036014B2 (en) 2008-11-06 2011-10-11 Macronix International Co., Ltd. Phase change memory program method without over-reset
JP2010123164A (ja) * 2008-11-18 2010-06-03 Elpida Memory Inc 半導体記憶装置及びその制御方法
WO2010076834A1 (en) 2008-12-31 2010-07-08 Ferdinando Bedeschi Reliable set operation for phase-change memory cell
WO2010125805A1 (ja) * 2009-04-27 2010-11-04 パナソニック株式会社 抵抗変化型不揮発性記憶素子の書き込み方法及び抵抗変化型不揮発性記憶装置
US8848421B2 (en) * 2010-03-30 2014-09-30 Panasonic Corporation Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device
CN102142517B (zh) 2010-12-17 2017-02-08 华中科技大学 一种低热导率的多层相变材料
WO2013080499A1 (ja) * 2011-12-02 2013-06-06 パナソニック株式会社 抵抗変化型不揮発性記憶素子の書き込み方法および抵抗変化型不揮発性記憶装置
US9378821B1 (en) * 2013-01-18 2016-06-28 Cypress Semiconductor Corporation Endurance of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells
CN103093816B (zh) 2013-01-29 2015-08-05 中国科学院苏州纳米技术与纳米仿生研究所 相变存储器驱动电路及置位和复位方法
CN103714852B (zh) * 2013-12-18 2017-03-01 华中科技大学 一种精确控制微纳尺寸相变材料非晶化率连续变化的方法
US9324428B1 (en) 2015-01-25 2016-04-26 Macronix International Co., Ltd. Memory device and operation method thereof
KR102251814B1 (ko) 2015-02-06 2021-05-13 삼성전자주식회사 메모리 장치, 그것의 동작 및 제어 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100067291A1 (en) * 2007-03-02 2010-03-18 Elpida Memory, Inc. Method for programming phase-change memory and method for reading date from the same
CN101763891A (zh) * 2008-12-24 2010-06-30 复旦大学 一种相变存储器单元及其操作方法
CN101777380A (zh) * 2009-01-12 2010-07-14 旺宏电子股份有限公司 写入相变存储器元件的方法
CN101699562A (zh) * 2009-11-23 2010-04-28 中国科学院上海微系统与信息技术研究所 一种相变存储器的擦写方法
CN103093815A (zh) * 2013-01-10 2013-05-08 华中科技大学 一种多值相变随机存储器的存储单元及操作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11335403B2 (en) 2018-06-06 2022-05-17 Micron Technology, Inc. Techniques for programming multi-level self-selecting memory cell

Also Published As

Publication number Publication date
CN105723461A (zh) 2016-06-29
US20170133090A1 (en) 2017-05-11
KR20170031746A (ko) 2017-03-21
JP6388422B2 (ja) 2018-09-12
US10083749B2 (en) 2018-09-25
JP2017527941A (ja) 2017-09-21

Similar Documents

Publication Publication Date Title
US7746688B2 (en) PRAM and method of firing memory cells
TWI430271B (zh) 藉由變異重置振幅之pcm多階式記憶胞編程
US7787316B2 (en) Semiconductor memory device and write control method thereof
CN103137191B (zh) 用于对相变存储器单元编程的方法和装置
TWI493547B (zh) 相變記憶體及開關（ｐｃｍｓ）記憶體裝置中之漂移管理
US10629261B2 (en) Enhancing nucleation in phase-change memory cells
US20120250403A1 (en) Method for Programming A Resistive Memory Cell, A Method And A Memory Apparatus For Programming One Or More Resistive Memory Cells In A Memory Array
JP2009054274A (ja) 可変抵抗メモリ装置及びその動作方法並びに可変抵抗メモリシステム
US10037803B2 (en) Apparatus and method for programming a multi-level phase change memory (PCM) cell based on an actual resistance value and a reference resistance value
KR101780539B1 (ko) 다치형 상변화 메모리의 쓰기 방법 및 시스템
CN211350111U (zh) 相变存储器设备
WO2016011637A1 (zh) 相变存储器的数据存储方法及控制装置
TWI648738B (zh) 非揮發性記憶體系統、可調非揮發性記憶體單元及用於將一或多個位元記錄在至少一個記憶體單元中之方法
WO2016011638A1 (zh) 相变存储器的数据存储方法及控制装置
US7710790B2 (en) Semiconductor memory device and write control method thereof
Asadinia et al. The emerging phase change memory
CN115083476A (zh) 一种相变存储器的操作方法、相变存储器及存储器系统
CN113851164A (zh) 相变存储器单元的操作方法及系统、计算机可读存储介质
JP2024523151A (ja) 重み更新における直線性向上のための相変化メモリに基づくシナプス・デバイスのパルシング
US20100165727A1 (en) Phase change material memory having no erase cycle

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14898304

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2017504023

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20177004140

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 14898304

Country of ref document: EP

Kind code of ref document: A1