WO2016000310A1 - 一种多路帧头检测的方法和装置 - Google Patents
一种多路帧头检测的方法和装置 Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2656—Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
- H04L27/2278—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using correlation techniques, e.g. for spread spectrum signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/042—Detectors therefor, e.g. correlators, state machines
Definitions
- the present invention relates to a synchronous receiving technology in the field of digital optical communications, and in particular, to a method and apparatus for detecting multiple headers.
- the frame synchronization technology occupies a very important position in optical communication, and the position of the frame synchronization module at the receiving end of the optical communication system is as shown in FIG. 1.
- the signal enters the frame synchronization module after fine equalization, frequency offset estimation and phase offset estimation.
- the frame synchronization mainly completes the frame header marking function, and provides frame header indication information for subsequent phase blur compensation and deletion of the frame header training sequence operation, and indicates the system. Synchronization status, reflecting the advantages and disadvantages of channel conditions.
- the frame synchronization technology uses the group synchronization code inserted in the signal to realize the search and labeling of the frame header.
- the insertion of the group synchronization code has two modes: centralized insertion and distributed insertion.
- the corresponding insertion signals are respectively called code groups and symbols. According to different needs, both methods are used in the optical communication system, and one type is used independently or a mixture of the two is used.
- some of the frame header detection is performed by using the code group period autocorrelation property, and some of the frame header detection is performed according to the periodicity of occurrence of the symbol.
- the detection process generally includes two stages of searching and capturing, corresponding to two states of out-of-synchronization and synchronization, and the position of the frame header is marked for subsequent use by the relevant module when the frame header is detected.
- the indicators for measuring the quality of the frame synchronization method include the frame synchronization setup time and the stability of the system after synchronization. A good frame synchronization method should enable the system to synchronize quickly. If the channel conditions are stable after synchronization, there is no burst channel. If the deterioration factor occurs, the system should work stably and cannot enter the out-of-step state frequently.
- the conventional optical communication frame synchronization scheme is shown in FIG. 2, and the multi-channel data transmission synchronization device is configured to synchronize multi-channel data in the multi-channel data source to the receiving end circuit through the data transmission physical path, the multi-channel
- the data source includes frame header data having a frame synchronization signal
- the apparatus includes a multi-channel data synchronization circuit for implementing multi-channel data transmission synchronization, the multi-channel data synchronization circuit including a reception frame header extraction circuit and multi-channel data a synchronization circuit, wherein the receiving frame header extraction circuit receives the data stream on the physical path of the data transmission, extracts the frame header data therefrom, and transmits the data to the multiplex data synchronization circuit; and the multiplex data synchronization circuit transmits the data according to the received frame header extraction circuit
- the header data is converted into a synchronized data stream by using a frame synchronization signal in the header data.
- embodiments of the present invention are expected to provide a method and apparatus for detecting multiple headers.
- the embodiment of the invention provides a method for detecting multiple headers, the method comprising:
- a frame header decision and a lane decision are performed according to the threshold decision result.
- the auto-correlation of each of the frame header sequences is higher than the first threshold, and the cross-correlation between any two frame header sequences is lower than the second threshold.
- the hard decision processing on the input data to obtain a receiving sequence includes:
- a hard decision is made according to the sample sign bit of the input data, the sample sign bit is 0, the hard decision result is 0, the sample sign bit is 1, and the hard decision result is 1; the hard decision result constitutes the receive sequence.
- the performing a sliding correlation operation between the received sequence and the locally pre-stored frame header sequence corresponding to each channel lane, respectively, to obtain an operation result including:
- N is an integer greater than 1.
- the comparing the operation result with the preset threshold to obtain a threshold decision result including:
- the result of the threshold decision is that the received sequence is inverted with the nth frame header sequence; when the operation result is less than or equal to the second threshold, the threshold decision result is obtained as the received sequence and the nth frame
- the head sequence is not inverted; 0 ⁇ n ⁇ N, n is an integer.
- the performing the frame header determination and the lane determination according to the threshold decision result including:
- the operation result is less than or equal to the second threshold, determining that the location of the received sequence is a frame header position, and acquiring a lane number corresponding to the nth frame header sequence participating in the corresponding operation; otherwise, determining the receiving sequence The location is not the frame header position.
- An embodiment of the present invention further provides a device for detecting multiple headers, where the device includes: a hard decision unit, a sliding correlation unit, a threshold decision unit, a frame header determination, and a channel lane determination unit, where
- the hard decision unit is configured to perform hard decision processing on the input data to obtain a receiving sequence
- the sliding correlation unit is configured to perform a sliding correlation operation on the received sequence and a locally pre-stored frame header sequence to obtain an operation result;
- the threshold decision unit is configured to compare the operation result with a preset threshold to obtain a threshold decision result
- the frame header determination and lane determination unit is configured to perform a frame header determination and a lane determination according to the threshold decision result.
- the auto-correlation of each of the frame header sequences is higher than the first threshold, and the cross-correlation between any two frame header sequences is lower than the second threshold.
- the hard decision unit is further configured to perform a hard decision according to the sample sign bit of the input data, the sample sign bit is 0, the hard decision result is 0, the sample sign bit is 1, and the hard decision result is 1.
- the hard decision result constitutes the received sequence.
- the sliding correlation unit is further configured to perform an exclusive-synchronization and summation operation on the N sequence header sequences corresponding to the N lanes, and the length of the XOR summation and the frame The lengths of the header sequences are the same, and the operation result is the result of the sliding exclusive OR sum; the receiving sequence is respectively XORed with the N frame header sequences and summed to obtain N operation results; N is An integer greater than one.
- the threshold decision unit is further configured to compare the operation result of the sliding correlation operation between the receiving sequence and the nth frame header sequence, respectively, with a preset first threshold and a second threshold, respectively, when the operation
- the result of the threshold decision is that the received sequence is inverted with the nth frame header sequence
- the threshold decision result is The receiving sequence and the nth frame header sequence are not inverted; 0 ⁇ n ⁇ N, n is an integer.
- the frame header determination and lane determination unit is further configured to: when the operation result is less than or equal to the second threshold, determine that the location of the received sequence is a frame header position, and obtain an nth frame participating in the corresponding operation.
- the lane number corresponding to the header sequence is further configured to: when the operation result is less than or equal to the second threshold, determine that the location of the received sequence is a frame header position, and obtain an nth frame participating in the corresponding operation. The lane number corresponding to the header sequence.
- the embodiment of the invention further provides a computer readable storage medium, the storage medium comprising a set of computer executable instructions for performing the method of detecting the multiple headers.
- a method and device for detecting multi-channel frame headers provided by embodiments of the present invention can enable optical communication
- the two nodes of the letter quickly establish chain communication, and have strong anti-interference ability (the probability of system out-of-synchronization is low under the condition that the channel environment is relatively stable), which satisfies the need of variable frequency range of the channel, and has simple frame synchronization and hardware. Easy to implement, stable synchronization and other advantages.
- FIG. 1 is a block diagram of a receiving end processing of an optical communication system in the prior art
- FIG. 2 is a schematic diagram of a synchronization device for multi-channel data transmission in the prior art
- FIG. 3 is a flowchart of a method for detecting multiple headers according to an embodiment of the present invention.
- FIG. 4 is a structural diagram of a device for detecting multiple headers according to an embodiment of the present invention.
- FIG. 5 is a schematic structural diagram of a structure of a transmitting end according to an embodiment of the present invention.
- FIG. 6 is a schematic diagram of a typical data frame format according to an embodiment of the present invention.
- FIG. 7 is a schematic diagram of a sequence of frame headers according to an embodiment of the present invention.
- FIG. 8 is a schematic diagram of a frame synchronization principle of a receiving end according to an embodiment of the present invention.
- FIG. 9a is a schematic diagram of autocorrelation of a frame header sequence corresponding to original data XI according to an embodiment of the present invention.
- FIG. 9b is a schematic diagram of autocorrelation of a frame header sequence corresponding to original data XQ according to an embodiment of the present invention.
- 9c is a schematic diagram of autocorrelation of a frame header sequence corresponding to original data YI according to an embodiment of the present invention.
- FIG. 9 is a schematic diagram showing the autocorrelation of a frame header sequence corresponding to the original data YQ according to an embodiment of the present invention.
- 9e is a schematic diagram of cross-correlation of a frame header sequence of original data XI and XQ according to an embodiment of the present invention.
- 9f is a schematic diagram of cross-correlation of a frame header sequence of original data XI and YI according to an embodiment of the present invention.
- 9g is a schematic diagram of cross-correlation of a frame header sequence of original data XI and YQ according to an embodiment of the present invention.
- 9h is a schematic diagram of cross-correlation of a frame header sequence of original data XQ and YI according to an embodiment of the present invention.
- 9i is a schematic diagram of cross-correlation of a frame header sequence of original data XQ and YQ according to an embodiment of the present invention.
- FIG. 9j is a schematic diagram of cross-correlation of a frame header sequence of original data YI and YQ according to an embodiment of the present invention.
- the method mainly includes:
- step 101 hard decision processing is performed on the input data to obtain a receiving sequence.
- the input data subjected to the frame synchronization processing is soft information after frequency offset phase shift correction and compensation, and it can be understood that the input data has no influence of frequency offset and phase offset.
- the input data of the frame synchronization is first subjected to hard decision processing, that is, the hard decision is performed according to the sample symbol bit of the input data, the sample sign bit is 0, the hard decision result is 0, the sample sign bit is 1, and the hard decision result is 1.
- the received sequence is composed of hard decision results.
- Step 102 Perform a sliding correlation operation on the received sequence and the locally pre-stored frame header sequence corresponding to each lane to obtain an operation result.
- the number of lanes in multi-channel data transmission is selected according to actual needs.
- the number of lanes can be 4, or 8, or 16, and so on.
- a frame header sequence corresponding to each path is respectively set, and the frame header sequence needs to satisfy the following conditions: the autocorrelation of each frame header sequence is higher than the first threshold, and any two frame header sequences are The cross-correlation between the two is lower than the second threshold.
- the values of the first threshold and the second threshold may be selected according to actual application requirements.
- the sequence of frame headers corresponding to each lane is different, and it is necessary to ensure that the autocorrelation of these frame header sequences is high and the cross-correlation is low.
- Autocorrelation is the correlation of two different time points in a stochastic process, and the opposite is cross-correlation, which is the correlation of different time points of two stochastic processes.
- Autocorrelation is a measure of the degree of signal correlation. That is to say, autocorrelation can be regarded as the product of multiplication of the signal with its own delayed signal. The autocorrelation also plays an important role in signal detection. The best acceptance criteria under the principle of minimum error.
- Cross-correlation is the covariance cov(X,Y) used in statistics to represent two random vectors X and Y. In the field of signal processing, cross-correlation is a measure used to represent the similarity between two signals.
- cross-correlation can be considered as The product of the multiplication of the signal with the delayed signal of the other signal is integrated.
- the high autocorrelation and low cross-correlation are necessary conditions for screening the frame header sequence.
- the receiving sequence is separately subjected to a sliding correlation operation with a locally pre-stored frame header sequence corresponding to each lane, and the operation result is obtained, including:
- the sequence of the N headers corresponding to the N lanes is respectively subjected to a SOR and summation operation, and the length of the XOR summation is the same as the length of the frame header sequence, and the operation result is a sliding XOR summation result.
- the receiving sequence is subjected to a sliding exclusive OR summation operation with the N frame header sequences to obtain N operation results; N is an integer greater than 1.
- the logical expression of the exclusive OR operation is: the same is 0, the difference is 1; that is, if the sequence is received If a certain bit is the same as a bit of the XOR sequence of the XOR, the XOR result is 0. If a bit of the received sequence is different from a bit of the XOR sequence, the XOR The result of the operation is 1. Then, the result of the Sliding XOR and summation can reflect the number of elements in the sequence of the received sequence and the sequence of XORs that are XORed.
- Step 103 Compare the operation result with a preset threshold to obtain a threshold decision result.
- the operation result of performing a sliding correlation operation between the receiving sequence and the nth frame header sequence is compared with a preset first threshold and a second threshold respectively, when the operation result is greater than or equal to the first threshold, Obtaining the threshold decision result, the receiving sequence is inverted with the nth frame header sequence; when the operation result is less than or equal to the second threshold, obtaining the threshold decision result as the receiving sequence and the first
- the n frame header sequences are not inverted; 0 ⁇ n ⁇ N, n is an integer.
- the values of the first threshold and the second threshold may be set according to actual application requirements.
- Step 104 Perform frame header determination and lane determination according to the threshold decision result.
- determining that the location where the receiving sequence is located is a frame header position, and acquiring a lane number corresponding to the nth frame header sequence participating in the corresponding operation; otherwise, determining the location The location where the received sequence is located is not the position of the frame header.
- the method for detecting multiple headers in the foregoing embodiment of the present invention can be applied to a data receiving device of an optical communication system.
- the embodiment of the present invention further provides a device for detecting multiple headers.
- the device includes: a hard decision unit 10, and a sliding correlation unit. 20.
- the hard decision unit 10 is configured to perform hard decision processing on the input data to obtain a receiving sequence.
- the sliding correlation unit 20 is configured to perform a sliding correlation operation between the received sequence and a locally pre-stored frame header sequence to obtain an operation result;
- the threshold decision unit 30 is configured to compare the operation result with a preset threshold to obtain Threshold decision result;
- the frame header decision and lane decision unit 40 is configured to perform a frame header decision and a lane decision based on the threshold decision result.
- a frame header sequence corresponding to each path is respectively set, and the frame header sequence needs to satisfy the following conditions: the autocorrelation of each frame header sequence is higher than the first threshold, and any two frame header sequences are The cross-correlation between the two is lower than the second threshold.
- the values of the first threshold and the second threshold may be selected according to actual application requirements. That is to say, the sequence of frame headers corresponding to each lane is different, and it is necessary to ensure that the autocorrelation of these frame header sequences is high and the cross-correlation is low.
- the number of lanes in multi-channel data transmission is selected according to actual needs.
- the number of lanes can be 4, or 8, or 16, and so on.
- the hard decision unit 10 is further configured to perform a hard decision according to the sample sign bit of the input data, the sample sign bit is 0, the hard decision result is 0, the sample sign bit is 1, and the hard decision result is 1;
- the hard decision result constitutes the received sequence.
- the sliding correlation unit 20 is further configured to perform an exclusive-synchronization and summation operation on the N sequence header sequences corresponding to the N lanes, and the length of the XOR sum sum is The length of the frame header sequence is the same, and the operation result is the result of the sliding exclusive OR sum; the receiving sequence is respectively subjected to sliding exclusive OR summation with the N frame header sequences to obtain N operation results; Is an integer greater than 1.
- the logical expression of the exclusive OR operation is: the same is 0, the difference is 1; that is, if a bit of the received sequence is the same as a bit of the sequence of the XOR of the exclusive OR, the result of the exclusive OR operation is 0, if If the bit of the received sequence is different from the bit of the sequence of the XOR that is XORed, the result of the exclusive OR operation is 1. Then, the result of the Sliding XOR and summation can reflect the number of elements in the sequence of the received sequence and the sequence of XORs that are XORed.
- the threshold decision unit 30 is further configured to compare the operation result of the sliding correlation operation between the receiving sequence and the nth frame header sequence, respectively, with a preset first threshold and a second threshold, when When the operation result is greater than or equal to the first threshold, the threshold decision result is obtained as The receiving sequence is inverted with the nth frame header sequence; when the operation result is less than or equal to the second threshold, the threshold decision result is obtained: the receiving sequence and the nth frame header sequence are not inverted ; 0 ⁇ n ⁇ N, n is an integer.
- the frame header determination and lane determination unit 40 is further configured to: when the operation result is less than or equal to the second threshold, determine that the location of the received sequence is a frame header position, and obtain the nth part participating in the corresponding operation. The lane number corresponding to the frame header sequence.
- the hard decision unit 10, the sliding correlation unit 20, the threshold decision unit 30, the frame header determination and channel lane determination unit 40 may be configured by a central processing unit (CPU) of the multiplex frame header detecting device.
- CPU central processing unit
- the multiplexer header detection device of the embodiment of the present invention may be located in a data receiving device of the optical communication system. Accordingly, the embodiment of the present invention further provides a receiving device including the multiplex header detecting device.
- the sequence of N code groups for correlation reception is very strong, the cross-correlation is very low, thereby avoiding the occurrence of missed detection and false alarm, and improving the speed and reliability of synchronization;
- the two nodes of the optical communication are quickly established to communicate with each other, and the anti-interference ability is strong (the probability of the system being out of synchronization after the channel environment is relatively stable) is low, and the channel frequency offset range is varied, and the frame synchronization is simple to implement.
- the hardware is easy to implement and the synchronization performance is stable.
- the method and apparatus for detecting multiple headers in the embodiment of the present invention are further described in detail below by taking the frame synchronization of the 4-way lane as an example.
- the frame synchronization of this embodiment includes two parts of the transmitting end and the receiving end.
- the composition of the transmitting end mainly includes: a data grouping module 50, an encoding module 60, and a frame header sequence inserting module 70.
- the input data of the transmitting end is sent to the four lanes through the data packet processing module, and is distributed to the four lanes as the original data of the optical transmission data.
- the original data on the four lanes are respectively recorded as XI, XQ, YI and YQ, wherein XI and XQ are in the X-polarization state during light transmission Transmission, YI and YQ are transmitted in the Y polarization state during optical transmission;
- the encoding module 60 performs data encoding on the four lanes on the data processed by the data packet to improve the anti-interference ability and error correction capability of the data;
- the frame header sequence inserting module 70 inserts a frame header sequence into the encoded data according to the data frame format, and completes the data frame framing process.
- the framing data can be sent out from the sender after pre-processing of data transmission.
- Figure 6 shows a typical data frame format, where a is the input frame header sequence and b is the encoded data frame content.
- the data parallelism on the four lanes is typically 64. Therefore, the typical value of a in Figure 6 is 64, and the number of 0s in the four headers is 32, which ensures that the insertion of the frame header does not affect.
- the balance of 0, 1 and the sequence of frame headers on each lane are different, the autocorrelation is very high and the cross-correlation is very low, as shown in Fig. 7.
- Autocorrelation is the correlation of two different time points in a stochastic process, and the opposite is cross-correlation, which is the correlation of different time points of two stochastic processes.
- Autocorrelation is a measure of the degree of signal correlation. That is to say, autocorrelation can be regarded as the product of multiplication of the signal with its own delayed signal. The autocorrelation also plays an important role in signal detection. The best acceptance criteria under the principle of minimum error.
- Cross-correlation is the covariance cov(X,Y) used in statistics to represent two random vectors X and Y. In the field of signal processing, cross-correlation is a measure used to represent the similarity between two signals.
- FIG. 9a shows the autocorrelation of the frame header sequence corresponding to the original data XI
- FIG. 9b shows the autocorrelation of the frame header sequence corresponding to the original data XQ
- FIG. 9c shows the autocorrelation of the frame header sequence corresponding to the original data YI.
- Figure 9d shows the raw data YQ pair
- the autocorrelation of the frame header sequence should be
- FIG. 9e shows the cross-correlation of the frame header sequences of the original data XI and XQ
- FIG. 9f shows the cross-correlation of the frame header sequences of the original data XI and YI
- FIG. 9g shows the original data XI.
- FIG. 9h shows the cross-correlation of the frame header sequences of the original data XQ and YI
- FIG. 9i shows the cross-correlation of the frame header sequences of the original data XQ and YQ
- FIG. 9j shows the original data.
- the frame synchronization principle of the receiving end is shown in Figure 8.
- the input data of the frame synchronization module is the soft information after the frequency offset phase offset correction and compensation. It can be understood that the data has no influence of frequency offset and phase offset; the frame synchronization input data is first After the hard decision processing, the hard-decised data constitutes a receiving sequence, and the local four-lane frame header sequence (same as the frame end sequence of the four-lane inserted by the transmitting end) is respectively subjected to a correlation operation, and the receiving sequence and the local are calculated.
- the input data is subjected to hard decision processing, that is, 0/1 is judged according to the sample symbol bit of the input data, and the hard decision result constitutes a receiving sequence;
- the receiving sequence is XORed with the pre-stored four frame header sequences (corresponding to four lanes respectively) and summed, and the XOR summation length is 64 bits;
- the OOF state if it is 6 times (according to actual needs, the number of times can be set to The value of the correlation operation reaches the set threshold (ie, A ⁇ 12) at the position of the integer multiple of the interval frame length, and enters the frame synchronization (IF, In Frame) state;
- the set threshold ie, A ⁇ 12
- the synchronization frame header cannot be found, indicating that the frame is out of synchronization OOF state, and the frame header is re-searched;
- the Lost Of Frame (LOF) alarm is reported.
- the synchronization frame header is found, the IF state is entered, and the LOF alarm state is cleared.
- the data of the current frame keeps the Lane number and status of the previous frame detection to the subsequent modules (such as the phase blur compensation module);
- the Lane is out of step alarm; where UI indicates unit interval, and the skew value exceeds [-128UI, +128UI] , indicating that the delay difference is too large, beyond the processing power of the system, reporting an alarm, indicating that the channel conditions are too bad.
- the embodiment of the present invention further provides a computer readable storage medium, the storage medium comprising a set of computer executable instructions for performing the method for detecting multiple headers provided by the above embodiments of the present invention.
- the implementation of the embodiment of the present invention enables the two nodes of the optical communication to quickly establish a chain communication, and the anti-interference ability is strong (the probability of the system being out of synchronization after the channel environment is relatively stable) is low.
- the requirement of variable channel frequency offset range has the advantages of simple frame synchronization, easy implementation of hardware, and stable synchronization performance.
- embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
- the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
- the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
- These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. Instructions are provided for implementation in the stream The steps of a function specified in one or more processes and/or block diagrams in one or more blocks.
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Abstract
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Claims (13)
- 一种多路帧头检测的方法,所述方法包括:对输入数据进行硬判决处理,得到接收序列;将所述接收序列与本地预存的与各通道lane对应的帧头序列分别进行滑动相关运算,得到运算结果;将所述运算结果与预设门限进行比较,得到门限判决结果;根据所述门限判决结果进行帧头判定和lane判定。
- 根据权利要求1所述多路帧头检测的方法,其中,所述本地预存的对应所有lane的帧头序列中,各帧头序列的自相关性高于第一阈值,且任意两个帧头序列之间的互相关性低于第二阈值。
- 根据权利要求1或2所述多路帧头检测的方法,其中,所述对输入数据进行硬判决处理,得到接收序列,包括:根据所述输入数据的样点符号位进行硬判决,样点符号位为0,硬判决结果为0,样点符号位为1,硬判决结果为1;硬判决结果组成所述接收序列。
- 根据权利要求3所述多路帧头检测的方法,其中,所述将接收序列与本地预存的与各通道lane对应的帧头序列分别进行滑动相关运算,得到运算结果,包括:将所述接收序列分别与N条lane对应的N个帧头序列进行滑动异或并求和运算,所述异或并求和的长度与所述帧头序列的长度相同,所述运算结果为所述滑动异或并求和的结果;所述接收序列分别与N个帧头序列进行滑动异或并求和运算,得到N个运算结果;N为大于1的整数。
- 根据权利要求4所述多路帧头检测的方法,其中,所述将运算结果与预设门限进行比较,得到门限判决结果,包括:将所述接收序列与第n个帧头序列进行滑动相关运算的运算结果, 与预设的第一门限和第二门限分别进行比较,当所述运算结果大于等于第一门限时,得到所述门限判决结果为所述接收序列与所述第n个帧头序列反相;当所述运算结果小于等于第二门限时,得到所述门限判决结果为所述接收序列与所述第n个帧头序列未反相;0<n<N,n为整数。
- 根据权利要求5所述多路帧头检测的方法,其中,所述根据门限判决结果进行帧头判定和lane判定,包括:当所述运算结果小于等于第二门限时,判定所述接收序列所在的位置是帧头位置,并获取参与相应运算的第n个帧头序列所对应的lane号;否则,判定所述接收序列所在的位置不是帧头位置。
- 一种多路帧头检测的装置,所述装置包括:硬判决单元、滑动相关单元、门限判决单元、帧头判定与通道lane判定单元,其中,所述硬判决单元,配置为对输入数据进行硬判决处理,得到接收序列;所述滑动相关单元,配置为将所述接收序列与本地预存的帧头序列进行滑动相关运算,得到运算结果;所述门限判决单元,配置为将所述运算结果与预设门限进行比较,得到门限判决结果;所述帧头判定与lane判定单元,配置为根据所述门限判决结果进行帧头判定和lane判定。
- 根据权利要求7所述多路帧头检测的装置,其中,所述本地预存的对应所有lane的帧头序列中,各帧头序列的自相关性高于第一阈值,且任意两个帧头序列之间的互相关性低于第二阈值。
- 根据权利要求7或8所述多路帧头检测的装置,其中,所述硬判决单元还配置为,根据所述输入数据的样点符号位进行硬判决,样点符号位为0,硬判决结果为0,样点符号位为1,硬判决结果为1;硬判决结果组成所述接收序列。
- 根据权利要求9所述多路帧头检测的装置,其中,所述滑动相关单元还配置为,将所述接收序列分别与N条lane对应的N个帧头序列进行滑动异或并求和运算,所述异或并求和的长度与所述帧头序列的长度相同,所述运算结果为所述滑动异或并求和的结果;所述接收序列分别与N个帧头序列进行滑动异或并求和运算,得到N个运算结果;N为大于1的整数。
- 根据权利要求10所述多路帧头检测的装置,其中,所述门限判决单元还配置为,将所述接收序列与第n个帧头序列进行滑动相关运算的运算结果,与预设的第一门限和第二门限分别进行比较,当所述运算结果大于等于第一门限时,得到所述门限判决结果为所述接收序列与所述第n个帧头序列反相;当所述运算结果小于等于第二门限时,得到所述门限判决结果为所述接收序列与所述第n个帧头序列未反相;0<n<N,n为整数。
- 根据权利要求11所述多路帧头检测的装置,其中,所述帧头判定与lane判定单元还配置为,在所述运算结果小于等于第二门限时,判定所述接收序列所在的位置是帧头位置,并获取参与相应运算的第n个帧头序列所对应的lane号。
- 一种计算机可读存储介质,所述存储介质包括一组计算机可执行指令,所述指令用于执行权利要求1-6任一项所述的多路帧头检测的方法。
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