WO2016000310A1 - 一种多路帧头检测的方法和装置 - Google Patents

一种多路帧头检测的方法和装置 Download PDF

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Publication number
WO2016000310A1
WO2016000310A1 PCT/CN2014/085928 CN2014085928W WO2016000310A1 WO 2016000310 A1 WO2016000310 A1 WO 2016000310A1 CN 2014085928 W CN2014085928 W CN 2014085928W WO 2016000310 A1 WO2016000310 A1 WO 2016000310A1
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Prior art keywords
sequence
frame header
threshold
result
decision
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PCT/CN2014/085928
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English (en)
French (fr)
Inventor
贾臭臭
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深圳市中兴微电子技术有限公司
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Priority to EP14896873.8A priority Critical patent/EP3163825B1/en
Priority to KR1020177002289A priority patent/KR101982246B1/ko
Priority to JP2016576041A priority patent/JP6423022B2/ja
Priority to RU2017102361A priority patent/RU2650496C1/ru
Publication of WO2016000310A1 publication Critical patent/WO2016000310A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2656—Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
    • H04L27/2278—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using correlation techniques, e.g. for spread spectrum signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Definitions

  • the present invention relates to a synchronous receiving technology in the field of digital optical communications, and in particular, to a method and apparatus for detecting multiple headers.
  • the frame synchronization technology occupies a very important position in optical communication, and the position of the frame synchronization module at the receiving end of the optical communication system is as shown in FIG. 1.
  • the signal enters the frame synchronization module after fine equalization, frequency offset estimation and phase offset estimation.
  • the frame synchronization mainly completes the frame header marking function, and provides frame header indication information for subsequent phase blur compensation and deletion of the frame header training sequence operation, and indicates the system. Synchronization status, reflecting the advantages and disadvantages of channel conditions.
  • the frame synchronization technology uses the group synchronization code inserted in the signal to realize the search and labeling of the frame header.
  • the insertion of the group synchronization code has two modes: centralized insertion and distributed insertion.
  • the corresponding insertion signals are respectively called code groups and symbols. According to different needs, both methods are used in the optical communication system, and one type is used independently or a mixture of the two is used.
  • some of the frame header detection is performed by using the code group period autocorrelation property, and some of the frame header detection is performed according to the periodicity of occurrence of the symbol.
  • the detection process generally includes two stages of searching and capturing, corresponding to two states of out-of-synchronization and synchronization, and the position of the frame header is marked for subsequent use by the relevant module when the frame header is detected.
  • the indicators for measuring the quality of the frame synchronization method include the frame synchronization setup time and the stability of the system after synchronization. A good frame synchronization method should enable the system to synchronize quickly. If the channel conditions are stable after synchronization, there is no burst channel. If the deterioration factor occurs, the system should work stably and cannot enter the out-of-step state frequently.
  • the conventional optical communication frame synchronization scheme is shown in FIG. 2, and the multi-channel data transmission synchronization device is configured to synchronize multi-channel data in the multi-channel data source to the receiving end circuit through the data transmission physical path, the multi-channel
  • the data source includes frame header data having a frame synchronization signal
  • the apparatus includes a multi-channel data synchronization circuit for implementing multi-channel data transmission synchronization, the multi-channel data synchronization circuit including a reception frame header extraction circuit and multi-channel data a synchronization circuit, wherein the receiving frame header extraction circuit receives the data stream on the physical path of the data transmission, extracts the frame header data therefrom, and transmits the data to the multiplex data synchronization circuit; and the multiplex data synchronization circuit transmits the data according to the received frame header extraction circuit
  • the header data is converted into a synchronized data stream by using a frame synchronization signal in the header data.
  • embodiments of the present invention are expected to provide a method and apparatus for detecting multiple headers.
  • the embodiment of the invention provides a method for detecting multiple headers, the method comprising:
  • a frame header decision and a lane decision are performed according to the threshold decision result.
  • the auto-correlation of each of the frame header sequences is higher than the first threshold, and the cross-correlation between any two frame header sequences is lower than the second threshold.
  • the hard decision processing on the input data to obtain a receiving sequence includes:
  • a hard decision is made according to the sample sign bit of the input data, the sample sign bit is 0, the hard decision result is 0, the sample sign bit is 1, and the hard decision result is 1; the hard decision result constitutes the receive sequence.
  • the performing a sliding correlation operation between the received sequence and the locally pre-stored frame header sequence corresponding to each channel lane, respectively, to obtain an operation result including:
  • N is an integer greater than 1.
  • the comparing the operation result with the preset threshold to obtain a threshold decision result including:
  • the result of the threshold decision is that the received sequence is inverted with the nth frame header sequence; when the operation result is less than or equal to the second threshold, the threshold decision result is obtained as the received sequence and the nth frame
  • the head sequence is not inverted; 0 ⁇ n ⁇ N, n is an integer.
  • the performing the frame header determination and the lane determination according to the threshold decision result including:
  • the operation result is less than or equal to the second threshold, determining that the location of the received sequence is a frame header position, and acquiring a lane number corresponding to the nth frame header sequence participating in the corresponding operation; otherwise, determining the receiving sequence The location is not the frame header position.
  • An embodiment of the present invention further provides a device for detecting multiple headers, where the device includes: a hard decision unit, a sliding correlation unit, a threshold decision unit, a frame header determination, and a channel lane determination unit, where
  • the hard decision unit is configured to perform hard decision processing on the input data to obtain a receiving sequence
  • the sliding correlation unit is configured to perform a sliding correlation operation on the received sequence and a locally pre-stored frame header sequence to obtain an operation result;
  • the threshold decision unit is configured to compare the operation result with a preset threshold to obtain a threshold decision result
  • the frame header determination and lane determination unit is configured to perform a frame header determination and a lane determination according to the threshold decision result.
  • the auto-correlation of each of the frame header sequences is higher than the first threshold, and the cross-correlation between any two frame header sequences is lower than the second threshold.
  • the hard decision unit is further configured to perform a hard decision according to the sample sign bit of the input data, the sample sign bit is 0, the hard decision result is 0, the sample sign bit is 1, and the hard decision result is 1.
  • the hard decision result constitutes the received sequence.
  • the sliding correlation unit is further configured to perform an exclusive-synchronization and summation operation on the N sequence header sequences corresponding to the N lanes, and the length of the XOR summation and the frame The lengths of the header sequences are the same, and the operation result is the result of the sliding exclusive OR sum; the receiving sequence is respectively XORed with the N frame header sequences and summed to obtain N operation results; N is An integer greater than one.
  • the threshold decision unit is further configured to compare the operation result of the sliding correlation operation between the receiving sequence and the nth frame header sequence, respectively, with a preset first threshold and a second threshold, respectively, when the operation
  • the result of the threshold decision is that the received sequence is inverted with the nth frame header sequence
  • the threshold decision result is The receiving sequence and the nth frame header sequence are not inverted; 0 ⁇ n ⁇ N, n is an integer.
  • the frame header determination and lane determination unit is further configured to: when the operation result is less than or equal to the second threshold, determine that the location of the received sequence is a frame header position, and obtain an nth frame participating in the corresponding operation.
  • the lane number corresponding to the header sequence is further configured to: when the operation result is less than or equal to the second threshold, determine that the location of the received sequence is a frame header position, and obtain an nth frame participating in the corresponding operation. The lane number corresponding to the header sequence.
  • the embodiment of the invention further provides a computer readable storage medium, the storage medium comprising a set of computer executable instructions for performing the method of detecting the multiple headers.
  • a method and device for detecting multi-channel frame headers provided by embodiments of the present invention can enable optical communication
  • the two nodes of the letter quickly establish chain communication, and have strong anti-interference ability (the probability of system out-of-synchronization is low under the condition that the channel environment is relatively stable), which satisfies the need of variable frequency range of the channel, and has simple frame synchronization and hardware. Easy to implement, stable synchronization and other advantages.
  • FIG. 1 is a block diagram of a receiving end processing of an optical communication system in the prior art
  • FIG. 2 is a schematic diagram of a synchronization device for multi-channel data transmission in the prior art
  • FIG. 3 is a flowchart of a method for detecting multiple headers according to an embodiment of the present invention.
  • FIG. 4 is a structural diagram of a device for detecting multiple headers according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a structure of a transmitting end according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a typical data frame format according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a sequence of frame headers according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a frame synchronization principle of a receiving end according to an embodiment of the present invention.
  • FIG. 9a is a schematic diagram of autocorrelation of a frame header sequence corresponding to original data XI according to an embodiment of the present invention.
  • FIG. 9b is a schematic diagram of autocorrelation of a frame header sequence corresponding to original data XQ according to an embodiment of the present invention.
  • 9c is a schematic diagram of autocorrelation of a frame header sequence corresponding to original data YI according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram showing the autocorrelation of a frame header sequence corresponding to the original data YQ according to an embodiment of the present invention.
  • 9e is a schematic diagram of cross-correlation of a frame header sequence of original data XI and XQ according to an embodiment of the present invention.
  • 9f is a schematic diagram of cross-correlation of a frame header sequence of original data XI and YI according to an embodiment of the present invention.
  • 9g is a schematic diagram of cross-correlation of a frame header sequence of original data XI and YQ according to an embodiment of the present invention.
  • 9h is a schematic diagram of cross-correlation of a frame header sequence of original data XQ and YI according to an embodiment of the present invention.
  • 9i is a schematic diagram of cross-correlation of a frame header sequence of original data XQ and YQ according to an embodiment of the present invention.
  • FIG. 9j is a schematic diagram of cross-correlation of a frame header sequence of original data YI and YQ according to an embodiment of the present invention.
  • the method mainly includes:
  • step 101 hard decision processing is performed on the input data to obtain a receiving sequence.
  • the input data subjected to the frame synchronization processing is soft information after frequency offset phase shift correction and compensation, and it can be understood that the input data has no influence of frequency offset and phase offset.
  • the input data of the frame synchronization is first subjected to hard decision processing, that is, the hard decision is performed according to the sample symbol bit of the input data, the sample sign bit is 0, the hard decision result is 0, the sample sign bit is 1, and the hard decision result is 1.
  • the received sequence is composed of hard decision results.
  • Step 102 Perform a sliding correlation operation on the received sequence and the locally pre-stored frame header sequence corresponding to each lane to obtain an operation result.
  • the number of lanes in multi-channel data transmission is selected according to actual needs.
  • the number of lanes can be 4, or 8, or 16, and so on.
  • a frame header sequence corresponding to each path is respectively set, and the frame header sequence needs to satisfy the following conditions: the autocorrelation of each frame header sequence is higher than the first threshold, and any two frame header sequences are The cross-correlation between the two is lower than the second threshold.
  • the values of the first threshold and the second threshold may be selected according to actual application requirements.
  • the sequence of frame headers corresponding to each lane is different, and it is necessary to ensure that the autocorrelation of these frame header sequences is high and the cross-correlation is low.
  • Autocorrelation is the correlation of two different time points in a stochastic process, and the opposite is cross-correlation, which is the correlation of different time points of two stochastic processes.
  • Autocorrelation is a measure of the degree of signal correlation. That is to say, autocorrelation can be regarded as the product of multiplication of the signal with its own delayed signal. The autocorrelation also plays an important role in signal detection. The best acceptance criteria under the principle of minimum error.
  • Cross-correlation is the covariance cov(X,Y) used in statistics to represent two random vectors X and Y. In the field of signal processing, cross-correlation is a measure used to represent the similarity between two signals.
  • cross-correlation can be considered as The product of the multiplication of the signal with the delayed signal of the other signal is integrated.
  • the high autocorrelation and low cross-correlation are necessary conditions for screening the frame header sequence.
  • the receiving sequence is separately subjected to a sliding correlation operation with a locally pre-stored frame header sequence corresponding to each lane, and the operation result is obtained, including:
  • the sequence of the N headers corresponding to the N lanes is respectively subjected to a SOR and summation operation, and the length of the XOR summation is the same as the length of the frame header sequence, and the operation result is a sliding XOR summation result.
  • the receiving sequence is subjected to a sliding exclusive OR summation operation with the N frame header sequences to obtain N operation results; N is an integer greater than 1.
  • the logical expression of the exclusive OR operation is: the same is 0, the difference is 1; that is, if the sequence is received If a certain bit is the same as a bit of the XOR sequence of the XOR, the XOR result is 0. If a bit of the received sequence is different from a bit of the XOR sequence, the XOR The result of the operation is 1. Then, the result of the Sliding XOR and summation can reflect the number of elements in the sequence of the received sequence and the sequence of XORs that are XORed.
  • Step 103 Compare the operation result with a preset threshold to obtain a threshold decision result.
  • the operation result of performing a sliding correlation operation between the receiving sequence and the nth frame header sequence is compared with a preset first threshold and a second threshold respectively, when the operation result is greater than or equal to the first threshold, Obtaining the threshold decision result, the receiving sequence is inverted with the nth frame header sequence; when the operation result is less than or equal to the second threshold, obtaining the threshold decision result as the receiving sequence and the first
  • the n frame header sequences are not inverted; 0 ⁇ n ⁇ N, n is an integer.
  • the values of the first threshold and the second threshold may be set according to actual application requirements.
  • Step 104 Perform frame header determination and lane determination according to the threshold decision result.
  • determining that the location where the receiving sequence is located is a frame header position, and acquiring a lane number corresponding to the nth frame header sequence participating in the corresponding operation; otherwise, determining the location The location where the received sequence is located is not the position of the frame header.
  • the method for detecting multiple headers in the foregoing embodiment of the present invention can be applied to a data receiving device of an optical communication system.
  • the embodiment of the present invention further provides a device for detecting multiple headers.
  • the device includes: a hard decision unit 10, and a sliding correlation unit. 20.
  • the hard decision unit 10 is configured to perform hard decision processing on the input data to obtain a receiving sequence.
  • the sliding correlation unit 20 is configured to perform a sliding correlation operation between the received sequence and a locally pre-stored frame header sequence to obtain an operation result;
  • the threshold decision unit 30 is configured to compare the operation result with a preset threshold to obtain Threshold decision result;
  • the frame header decision and lane decision unit 40 is configured to perform a frame header decision and a lane decision based on the threshold decision result.
  • a frame header sequence corresponding to each path is respectively set, and the frame header sequence needs to satisfy the following conditions: the autocorrelation of each frame header sequence is higher than the first threshold, and any two frame header sequences are The cross-correlation between the two is lower than the second threshold.
  • the values of the first threshold and the second threshold may be selected according to actual application requirements. That is to say, the sequence of frame headers corresponding to each lane is different, and it is necessary to ensure that the autocorrelation of these frame header sequences is high and the cross-correlation is low.
  • the number of lanes in multi-channel data transmission is selected according to actual needs.
  • the number of lanes can be 4, or 8, or 16, and so on.
  • the hard decision unit 10 is further configured to perform a hard decision according to the sample sign bit of the input data, the sample sign bit is 0, the hard decision result is 0, the sample sign bit is 1, and the hard decision result is 1;
  • the hard decision result constitutes the received sequence.
  • the sliding correlation unit 20 is further configured to perform an exclusive-synchronization and summation operation on the N sequence header sequences corresponding to the N lanes, and the length of the XOR sum sum is The length of the frame header sequence is the same, and the operation result is the result of the sliding exclusive OR sum; the receiving sequence is respectively subjected to sliding exclusive OR summation with the N frame header sequences to obtain N operation results; Is an integer greater than 1.
  • the logical expression of the exclusive OR operation is: the same is 0, the difference is 1; that is, if a bit of the received sequence is the same as a bit of the sequence of the XOR of the exclusive OR, the result of the exclusive OR operation is 0, if If the bit of the received sequence is different from the bit of the sequence of the XOR that is XORed, the result of the exclusive OR operation is 1. Then, the result of the Sliding XOR and summation can reflect the number of elements in the sequence of the received sequence and the sequence of XORs that are XORed.
  • the threshold decision unit 30 is further configured to compare the operation result of the sliding correlation operation between the receiving sequence and the nth frame header sequence, respectively, with a preset first threshold and a second threshold, when When the operation result is greater than or equal to the first threshold, the threshold decision result is obtained as The receiving sequence is inverted with the nth frame header sequence; when the operation result is less than or equal to the second threshold, the threshold decision result is obtained: the receiving sequence and the nth frame header sequence are not inverted ; 0 ⁇ n ⁇ N, n is an integer.
  • the frame header determination and lane determination unit 40 is further configured to: when the operation result is less than or equal to the second threshold, determine that the location of the received sequence is a frame header position, and obtain the nth part participating in the corresponding operation. The lane number corresponding to the frame header sequence.
  • the hard decision unit 10, the sliding correlation unit 20, the threshold decision unit 30, the frame header determination and channel lane determination unit 40 may be configured by a central processing unit (CPU) of the multiplex frame header detecting device.
  • CPU central processing unit
  • the multiplexer header detection device of the embodiment of the present invention may be located in a data receiving device of the optical communication system. Accordingly, the embodiment of the present invention further provides a receiving device including the multiplex header detecting device.
  • the sequence of N code groups for correlation reception is very strong, the cross-correlation is very low, thereby avoiding the occurrence of missed detection and false alarm, and improving the speed and reliability of synchronization;
  • the two nodes of the optical communication are quickly established to communicate with each other, and the anti-interference ability is strong (the probability of the system being out of synchronization after the channel environment is relatively stable) is low, and the channel frequency offset range is varied, and the frame synchronization is simple to implement.
  • the hardware is easy to implement and the synchronization performance is stable.
  • the method and apparatus for detecting multiple headers in the embodiment of the present invention are further described in detail below by taking the frame synchronization of the 4-way lane as an example.
  • the frame synchronization of this embodiment includes two parts of the transmitting end and the receiving end.
  • the composition of the transmitting end mainly includes: a data grouping module 50, an encoding module 60, and a frame header sequence inserting module 70.
  • the input data of the transmitting end is sent to the four lanes through the data packet processing module, and is distributed to the four lanes as the original data of the optical transmission data.
  • the original data on the four lanes are respectively recorded as XI, XQ, YI and YQ, wherein XI and XQ are in the X-polarization state during light transmission Transmission, YI and YQ are transmitted in the Y polarization state during optical transmission;
  • the encoding module 60 performs data encoding on the four lanes on the data processed by the data packet to improve the anti-interference ability and error correction capability of the data;
  • the frame header sequence inserting module 70 inserts a frame header sequence into the encoded data according to the data frame format, and completes the data frame framing process.
  • the framing data can be sent out from the sender after pre-processing of data transmission.
  • Figure 6 shows a typical data frame format, where a is the input frame header sequence and b is the encoded data frame content.
  • the data parallelism on the four lanes is typically 64. Therefore, the typical value of a in Figure 6 is 64, and the number of 0s in the four headers is 32, which ensures that the insertion of the frame header does not affect.
  • the balance of 0, 1 and the sequence of frame headers on each lane are different, the autocorrelation is very high and the cross-correlation is very low, as shown in Fig. 7.
  • Autocorrelation is the correlation of two different time points in a stochastic process, and the opposite is cross-correlation, which is the correlation of different time points of two stochastic processes.
  • Autocorrelation is a measure of the degree of signal correlation. That is to say, autocorrelation can be regarded as the product of multiplication of the signal with its own delayed signal. The autocorrelation also plays an important role in signal detection. The best acceptance criteria under the principle of minimum error.
  • Cross-correlation is the covariance cov(X,Y) used in statistics to represent two random vectors X and Y. In the field of signal processing, cross-correlation is a measure used to represent the similarity between two signals.
  • FIG. 9a shows the autocorrelation of the frame header sequence corresponding to the original data XI
  • FIG. 9b shows the autocorrelation of the frame header sequence corresponding to the original data XQ
  • FIG. 9c shows the autocorrelation of the frame header sequence corresponding to the original data YI.
  • Figure 9d shows the raw data YQ pair
  • the autocorrelation of the frame header sequence should be
  • FIG. 9e shows the cross-correlation of the frame header sequences of the original data XI and XQ
  • FIG. 9f shows the cross-correlation of the frame header sequences of the original data XI and YI
  • FIG. 9g shows the original data XI.
  • FIG. 9h shows the cross-correlation of the frame header sequences of the original data XQ and YI
  • FIG. 9i shows the cross-correlation of the frame header sequences of the original data XQ and YQ
  • FIG. 9j shows the original data.
  • the frame synchronization principle of the receiving end is shown in Figure 8.
  • the input data of the frame synchronization module is the soft information after the frequency offset phase offset correction and compensation. It can be understood that the data has no influence of frequency offset and phase offset; the frame synchronization input data is first After the hard decision processing, the hard-decised data constitutes a receiving sequence, and the local four-lane frame header sequence (same as the frame end sequence of the four-lane inserted by the transmitting end) is respectively subjected to a correlation operation, and the receiving sequence and the local are calculated.
  • the input data is subjected to hard decision processing, that is, 0/1 is judged according to the sample symbol bit of the input data, and the hard decision result constitutes a receiving sequence;
  • the receiving sequence is XORed with the pre-stored four frame header sequences (corresponding to four lanes respectively) and summed, and the XOR summation length is 64 bits;
  • the OOF state if it is 6 times (according to actual needs, the number of times can be set to The value of the correlation operation reaches the set threshold (ie, A ⁇ 12) at the position of the integer multiple of the interval frame length, and enters the frame synchronization (IF, In Frame) state;
  • the set threshold ie, A ⁇ 12
  • the synchronization frame header cannot be found, indicating that the frame is out of synchronization OOF state, and the frame header is re-searched;
  • the Lost Of Frame (LOF) alarm is reported.
  • the synchronization frame header is found, the IF state is entered, and the LOF alarm state is cleared.
  • the data of the current frame keeps the Lane number and status of the previous frame detection to the subsequent modules (such as the phase blur compensation module);
  • the Lane is out of step alarm; where UI indicates unit interval, and the skew value exceeds [-128UI, +128UI] , indicating that the delay difference is too large, beyond the processing power of the system, reporting an alarm, indicating that the channel conditions are too bad.
  • the embodiment of the present invention further provides a computer readable storage medium, the storage medium comprising a set of computer executable instructions for performing the method for detecting multiple headers provided by the above embodiments of the present invention.
  • the implementation of the embodiment of the present invention enables the two nodes of the optical communication to quickly establish a chain communication, and the anti-interference ability is strong (the probability of the system being out of synchronization after the channel environment is relatively stable) is low.
  • the requirement of variable channel frequency offset range has the advantages of simple frame synchronization, easy implementation of hardware, and stable synchronization performance.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. Instructions are provided for implementation in the stream The steps of a function specified in one or more processes and/or block diagrams in one or more blocks.

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Abstract

本发明公开了一种多路帧头检测的方法和装置，方法包括：对输入数据进行硬判决处理，得到接收序列；将所述接收序列与本地预存的与各通道lane对应的帧头序列分别进行滑动相关运算，得到运算结果；将所述运算结果与预设门限进行比较，得到门限判决结果；根据所述门限判决结果进行帧头判定和lane判定。

Description

一种多路帧头检测的方法和装置 技术领域
本发明涉及数字光通信领域的同步接收技术，尤其涉及一种多路帧头检测的方法和装置。
背景技术
随着承载网市场宽带需求的高速增长，核心路由器将推出100GbE(十万兆位以太网)端口，而100G(Gigabit，千兆比特)设备也是一个明确的发展方向，密集型光波复用(DWDM，Dense Wavelength Division Multiplexing)设备必须支持100G的长距离传输。
帧同步技术在光通信中占据非常重要的位置，帧同步模块在光通信系统接收端的位置如图1所示。信号经过细均衡、频偏估计和相偏估计后进入帧同步模块，帧同步主要完成帧头标记功能，为后续的相位模糊补偿以及删除帧头训练序列操作提供帧头指示信息，同时指示系统的同步状态，反映信道条件的优劣。
帧同步技术是利用信号中插入的群同步码实现帧头的搜索及标记，群同步码的插入有集中插入和分散插入这两种方式，对应的插入信号分别称为码组和码元。根据不同的需求，光通信系统中对这两种方式均有使用，独立使用某一种或者将两者混合使用。100G帧同步方法中，有的是利用码组周期自相关特性进行帧头检测，有的是根据码元出现的周期性进行帧头检测。检测过程一般包括搜索和捕获这两个阶段，对应失步、同步两个状态，当检测到帧头之后标记帧头位置供后续相关模块使用。衡量帧同步方法优劣的指标有帧同步建立时间及同步后系统的稳定度，一个好的帧同步方法应该能够让系统快速同步，同步后如信道条件稳定，没有突发的信道 恶化因素出现，则系统应工作稳定，不能频繁进入失步状态。
传统的光通信帧同步方案如图2所示，该多通道数据传输的同步装置，用于将多路数据源中的多通道数据通过数据发送物理通路同步到接收端电路中，所述多路数据源中包括具有帧同步信号的帧头数据，所述装置包括一多通道数据同步电路，用于实现多通道数据传输同步，所述多通道数据同步电路包括接收帧头提取电路和多路数据同步电路，其中，接收帧头提取电路接收数据发送物理通路上的数据流，从中提取出帧头数据，发送给多路数据同步电路；所述多路数据同步电路根据接收帧头提取电路发送的帧头数据，利用该帧头数据中的帧同步信号将上述数据流转化为同步的数据流。
然而，怎样实现对光通信帧同步方案的不断优化，以实现快速同步、以及不断提高帧同步后系统的稳定度(即使信道环境相对稳定的条件下同步后系统发生失步的概率低)，一直是本领域技术人员长期面对的技术难题。
发明内容
为解决现有存在的技术问题，本发明实施例期望提供一种多路帧头检测的方法和装置。
本发明实施例提供了一种多路帧头检测的方法，所述方法包括：
对输入数据进行硬判决处理，得到接收序列；
将所述接收序列与本地预存的与各通道lane对应的帧头序列分别进行滑动相关运算，得到运算结果；
将所述运算结果与预设门限进行比较，得到门限判决结果；
根据所述门限判决结果进行帧头判定和lane判定。
其中，所述本地预存的对应所有lane的帧头序列中，各帧头序列的自相关性高于第一阈值，且任意两个帧头序列之间的互相关性低于第二阈值。
其中，所述对输入数据进行硬判决处理，得到接收序列，包括：
根据所述输入数据的样点符号位进行硬判决，样点符号位为0，硬判决结果为0，样点符号位为1，硬判决结果为1；硬判决结果组成所述接收序列。
其中，所述将接收序列与本地预存的与各通道lane对应的帧头序列分别进行滑动相关运算，得到运算结果，包括：
将所述接收序列分别与N条lane对应的N个帧头序列进行滑动异或并求和运算，所述异或并求和的长度与所述帧头序列的长度相同，所述运算结果为所述滑动异或并求和的结果；所述接收序列分别与N个帧头序列进行滑动异或并求和运算，得到N个运算结果；N为大于1的整数。
其中，所述将运算结果与预设门限进行比较，得到门限判决结果，包括：
将所述接收序列与第n个帧头序列进行滑动相关运算的运算结果，与预设的第一门限和第二门限分别进行比较，当所述运算结果大于等于第一门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列反相；当所述运算结果小于等于第二门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列未反相；0＜n＜N，n为整数。
其中，所述根据门限判决结果进行帧头判定和lane判定，包括：
当所述运算结果小于等于第二门限时，判定所述接收序列所在的位置是帧头位置，并获取参与相应运算的第n个帧头序列所对应的lane号；否则，判定所述接收序列所在的位置不是帧头位置。
本发明实施例还提供了一种多路帧头检测的装置，所述装置包括：硬判决单元、滑动相关单元、门限判决单元、帧头判定与通道lane判定单元，其中，
所述硬判决单元，配置为对输入数据进行硬判决处理，得到接收序列；
所述滑动相关单元，配置为将所述接收序列与本地预存的帧头序列进行滑动相关运算，得到运算结果；
所述门限判决单元，配置为将所述运算结果与预设门限进行比较，得到门限判决结果；
所述帧头判定与lane判定单元，配置为根据所述门限判决结果进行帧头判定和lane判定。
其中，所述本地预存的对应所有lane的帧头序列中，各帧头序列的自相关性高于第一阈值，且任意两个帧头序列之间的互相关性低于第二阈值。
其中，所述硬判决单元还配置为，根据所述输入数据的样点符号位进行硬判决，样点符号位为0，硬判决结果为0，样点符号位为1，硬判决结果为1；硬判决结果组成所述接收序列。
其中，所述滑动相关单元还配置为，将所述接收序列分别与N条lane对应的N个帧头序列进行滑动异或并求和运算，所述异或并求和的长度与所述帧头序列的长度相同，所述运算结果为所述滑动异或并求和的结果；所述接收序列分别与N个帧头序列进行滑动异或并求和运算，得到N个运算结果；N为大于1的整数。
其中，所述门限判决单元还配置为，将所述接收序列与第n个帧头序列进行滑动相关运算的运算结果，与预设的第一门限和第二门限分别进行比较，当所述运算结果大于等于第一门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列反相；当所述运算结果小于等于第二门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列未反相；0＜n＜N，n为整数。
其中，所述帧头判定与lane判定单元还配置为，在所述运算结果小于等于第二门限时，判定所述接收序列所在的位置是帧头位置，并获取参与相应运算的第n个帧头序列所对应的lane号。
本发明实施例还提供了一种计算机可读存储介质，所述存储介质包括一组计算机可执行指令，所述指令用于执行上述多路帧头检测的方法。
本发明实施例所提供的一种多路帧头检测的方法和装置，能够使光通 信的两个节点快速建链通信，抗干扰能力强(信道环境相对稳定的条件下同步后系统发生失步的概率低)，满足信道频偏范围多变的需求，具有帧同步实现简单，硬件容易实现，同步性能稳定等优点。
由于相关接收用的N个码组序列自相关性非常强，而互相关性很低，这样避免了漏检及虚警的发生，提高了同步的快速性和可靠性；通过对码组序列的差异化处理，在检测到帧头和lane号的同时估计出了链路的大频偏值，加快了大频偏的补偿时间，缩短了系统的建链时间；本地预存四套相关序列，分别对应四种不同的lane，可有效消除各个lane间的干扰对相关检测的影响。
附图说明
图1为现有技术中光通信系统的接收端处理框图；
图2为现有技术中多通道数据传输的同步装置示意图；
图3为本发明实施例的一种多路帧头检测的方法流程图；
图4为本发明实施例的一种多路帧头检测的装置结构图；
图5为本发明实施例的发送端的组成结构示意图；
图6为本发明实施例的一种典型的数据帧格式示意图；
图7为本发明实施例的一种帧头序列的示意图；
图8为本发明实施例的一种接收端的帧同步原理示意图；
图9a为本发明实施例的原始数据XI对应的帧头序列的自相关性示意图；
图9b为本发明实施例的原始数据XQ对应的帧头序列的自相关性示意图；
图9c为本发明实施例的原始数据YI对应的帧头序列的自相关性示意图；
图9d为本发明实施例的原始数据YQ对应的帧头序列的自相关性示意 图；
图9e为本发明实施例的原始数据XI和XQ的帧头序列的互相关性示意图；
图9f为本发明实施例的原始数据XI和YI的帧头序列的互相关性示意图；
图9g为本发明实施例的原始数据XI和YQ的帧头序列的互相关性示意图；
图9h为本发明实施例的原始数据XQ和YI的帧头序列的互相关性示意图；
图9i为本发明实施例的原始数据XQ和YQ的帧头序列的互相关性示意图；
图9j为本发明实施例的原始数据YI和YQ的帧头序列的互相关性示意图。
具体实施方式
下面结合附图和具体实施例对本发明的技术方案进一步详细阐述。
为实现多路帧头检测，本发明实施例提供的一种多路帧头检测的方法，如图3所示，所述方法主要包括：
步骤101，对输入数据进行硬判决处理，得到接收序列。
如图1所示，进行帧同步处理的输入数据是经过频偏相偏纠正和补偿后的软信息，可以理解为该输入数据没有频偏和相偏的影响。
帧同步的输入数据首先经过硬判决处理，即根据输入数据的样点符号位进行硬判决，样点符号位为0，硬判决结果为0，样点符号位为1，硬判决结果为1；由硬判决结果组成所述接收序列。
步骤102，将接收序列与本地预存的与各通道(lane)对应的帧头序列分别进行滑动相关运算，得到运算结果。
多通道数据传输中的lane数量根据实际需要进行选定，例如：lane的数量可以是4、或8、或16等等。
本发明实施例对应每一路lane，分别设定与其对应的帧头序列，这些帧头序列需满足以下条件：各帧头序列的自相关性高于第一阈值，且任意两个帧头序列之间的互相关性低于第二阈值。所述第一阈值和第二阈值的取值可以根据实际应用需要进行选定。
也就是说，对应每一路lane的帧头序列是不同的，而且要保证这些帧头序列的自相关很高、互相关性很低。
自相关为一个随机过程中的两个不同的时间点的相关性，与之相对的是互相关，互相关是两个随机过程的不同时间点的相关性。自相关是对信号相关程度的一种度量，也就是说，自相关可以看作是信号与自身的延迟信号相乘后的乘积进行积分运算，自相关在信号检测中也有很重要的作用，是在误码最小原则下的最佳接收准则。互相关是统计学中用来表示两个随机矢量X和Y之间的协方差cov(X，Y)，在信号处理领域中，互相关是用来表示两个信号之间相似性的一个度量，通常通过与已知信号比较用于寻找未知信号中的特性；它是两个信号之间相对于时间的一个函数，有时也称为滑动点积，也就是说，互相关可以看作是该信号与其它信号的延迟信号相乘后的乘积进行积分运算。自相关性强而互相关性低，是筛选帧头序列必须满足的必要条件。
优选的，所述将接收序列与本地预存的与各lane对应的帧头序列分别进行滑动相关运算，得到运算结果，包括：
将接收序列分别与N条lane对应的N个帧头序列进行滑动异或并求和运算，异或并求和的长度与帧头序列的长度相同，运算结果为滑动异或并求和的结果；接收序列分别与N个帧头序列进行滑动异或并求和运算，得到N个运算结果；N为大于1的整数。
异或运算的逻辑表达是：相同为0，不同为1；也就是说，若接收序列 的某bit位与进行异或的帧头序列的某bit位相同，则异或运算结果为0，若接收序列的某bit位与进行异或的帧头序列的某bit位不同，则异或运算结果为1。那么，滑动异或并求和的结果即能体现接收序列与进行异或的帧头序列中不一致的元素个数。
步骤103，将运算结果与预设门限进行比较，得到门限判决结果。
具体的，将所述接收序列与第n个帧头序列进行滑动相关运算的运算结果，与预设的第一门限和第二门限分别进行比较，当所述运算结果大于等于第一门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列反相；当所述运算结果小于等于第二门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列未反相；0＜n＜N，n为整数。
其中，第一门限和第二门限的取值可以根据实际应用需要进行设定。
步骤104，根据门限判决结果进行帧头判定和lane判定。
具体的，当所述运算结果小于等于第二门限时，判定所述接收序列所在的位置是帧头位置，并获取参与相应运算的第n个帧头序列所对应的lane号；否则，判定所述接收序列所在的位置不是帧头位置。
需要说明的是，上述本发明实施例的多路帧头检测的方法，可应用于光通信系统的数据接收端设备。
对应本发明实施例的多路帧头检测的方法，本发明实施例还提供了一种多路帧头检测的装置，如图4所示，所述装置包括：硬判决单元10、滑动相关单元20、门限判决单元30、帧头判定与通道lane判定单元40；其中，
硬判决单元10，配置为对输入数据进行硬判决处理，得到接收序列；
所述滑动相关单元20，配置为将所述接收序列与本地预存的帧头序列进行滑动相关运算，得到运算结果；
门限判决单元30，配置为将所述运算结果与预设门限进行比较，得到 门限判决结果；
帧头判定与lane判定单元40，配置为根据所述门限判决结果进行帧头判定和lane判定。
本发明实施例对应每一路lane，分别设定与其对应的帧头序列，这些帧头序列需满足以下条件：各帧头序列的自相关性高于第一阈值，且任意两个帧头序列之间的互相关性低于第二阈值。所述第一阈值和第二阈值的取值可以根据实际应用需要进行选定。也就是说，对应每一路lane的帧头序列是不同的，而且要保证这些帧头序列的自相关很高、互相关性很低。
多通道数据传输中的lane数量根据实际需要进行选定，例如：lane的数量可以是4、或8、或16等等。
较佳的，硬判决单元10还配置为，根据所述输入数据的样点符号位进行硬判决，样点符号位为0，硬判决结果为0，样点符号位为1，硬判决结果为1；硬判决结果组成所述接收序列。
较佳的，滑动相关单元20还配置为，将所述接收序列分别与N条lane对应的N个帧头序列进行滑动异或并求和运算，所述异或并求和的长度与所述帧头序列的长度相同，所述运算结果为所述滑动异或并求和的结果；所述接收序列分别与N个帧头序列进行滑动异或并求和运算，得到N个运算结果；N为大于1的整数。
异或运算的逻辑表达是：相同为0，不同为1；也就是说，若接收序列的某bit位与进行异或的帧头序列的某bit位相同，则异或运算结果为0，若接收序列的某bit位与进行异或的帧头序列的某bit位不同，则异或运算结果为1。那么，滑动异或并求和的结果即能体现接收序列与进行异或的帧头序列中不一致的元素个数。
较佳的，门限判决单元30还配置为，将所述接收序列与第n个帧头序列进行滑动相关运算的运算结果，与预设的第一门限和第二门限分别进行比较，当所述运算结果大于等于第一门限时，得到所述门限判决结果为所 述接收序列与所述第n个帧头序列反相；当所述运算结果小于等于第二门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列未反相；0＜n＜N，n为整数。
较佳的，帧头判定与lane判定单元40还配置为，在所述运算结果小于等于第二门限时，判定所述接收序列所在的位置是帧头位置，并获取参与相应运算的第n个帧头序列所对应的lane号。
需要说明的是，上述硬判决单元10、滑动相关单元20、门限判决单元30、帧头判定与通道lane判定单元40可以由多路帧头检测装置的中央处理器(CPU，Central Processing Unit)、微处理器(MPU，Micro Processing Unit)、数字信号处理器(DSP，Digital Signal Processor)或可编程逻辑阵列(FPGA，Field－Programmable Gate Array)实现。本发明实施例的多路帧头检测装置可位于光通信系统的数据接收端设备中，那么相应的，本发明实施例还提供了一种包含所述多路帧头检测装置的接收端设备。
本发明实施例，由于相关接收用的N个码组序列自相关性非常强，而互相关性很低，这样避免了漏检及虚警的发生，提高了同步的快速性和可靠性；能够使光通信的两个节点快速建链通信，抗干扰能力强(信道环境相对稳定的条件下同步后系统发生失步的概率低)，满足信道频偏范围多变的需求，具有帧同步实现简单，硬件容易实现，同步性能稳定等优点。
下面以4路lane的帧同步为例，对本发明实施例的多路帧头检测方法和装置进一步详细阐述。
本实施例的帧同步包括发送端和接收端的两部分实现。发送端的组成结构如图5所示，主要包括：数据分组模块50、编码模块60和帧头序列插入模块70。发送端的输入数据经过数据分组模块50，进行数据分组处理后分发到4个lane上，作为光传输数据的原始数据，4个lane上的原始数据分别记为XI、XQ、YI和YQ，其中，XI和XQ在光传输时在X偏振态上 传输，YI和YQ在光传输时在Y偏振态上传输；编码模块60对经过数据分组处理后的数据，在4个lane上分别进行数据编码，以提高数据的抗干扰能力和纠错能力；帧头序列插入模块70对经过编码后的数据依据数据帧格式插入帧头序列，完成数据帧成帧过程。成帧后的数据经过数据发送的前处理即可从发送端发送出去。
需要说明的是，对应每一路lane的帧头序列是不同的，而且要保证这些帧头序列的自相关很高、互相关性很低。
图6所示为一种典型的数据帧格式，其中，a为输入的帧头序列，b为编码后的数据帧内容。根据传输速率的要求，4个lane上的数据并行度典型值为64，因此，图6中a的典型值为64，4个帧头的0的数量均为32，保证插入帧头后不影响0、1的平衡，并且每个lane上的帧头序列是不同的，自相关很高且互相关性很低，如图7所示。
自相关为一个随机过程中的两个不同的时间点的相关性，与之相对的是互相关，互相关是两个随机过程的不同时间点的相关性。自相关是对信号相关程度的一种度量，也就是说，自相关可以看作是信号与自身的延迟信号相乘后的乘积进行积分运算，自相关在信号检测中也有很重要的作用，是在误码最小原则下的最佳接收准则。互相关是统计学中用来表示两个随机矢量X和Y之间的协方差cov(X，Y)，在信号处理领域中，互相关是用来表示两个信号之间相似性的一个度量，通常通过与已知信号比较用于寻找未知信号中的特性；它是两个信号之间相对于时间的一个函数，有时也称为滑动点积，也就是说互相关可以看作是该信号与其它信号的延迟信号相乘后的乘积进行积分运算。自相关性强而互相关性低是筛选帧头序列必须满足的必要条件，具体如图9a～9j所示，图中的横轴表示延迟，纵轴表示序列中0、1值相同的个数；其中，图9a表示原始数据XI对应的帧头序列的自相关性，图9b表示原始数据XQ对应的帧头序列的自相关性，图9c表示原始数据YI对应的帧头序列的自相关性，图9d表示原始数据YQ对 应的帧头序列的自相关性，图9e表示原始数据XI和XQ的帧头序列的互相关性，图9f表示原始数据XI和YI的帧头序列的互相关性，图9g表示原始数据XI和YQ的帧头序列的互相关性，图9h表示原始数据XQ和YI的帧头序列的互相关性，图9i表示原始数据XQ和YQ的帧头序列的互相关性，图9j表示原始数据YI和YQ的帧头序列的互相关性。
接收端的帧同步原理如图8所示，帧同步模块的输入数据是经过频偏相偏纠正和补偿后的软信息，可以理解为该数据没有频偏和相偏的影响；帧同步输入数据首先经过硬判决处理，硬判决后的数据组成接收序列，与本地的4个lane的帧头序列(与发送端在4个lane插入的帧头序列相同)分别进行相关运算，计算出接收序列与本地4个帧头序列中不一致的元素个数；经过相关运算后进行门限判决，接收序列与帧头序列的相关值达到预定阈值时，判定接收序列所在的位置是帧头位置，并获取参与本相关运算的帧头序列所对应的lane号，否则判定接收序列所在的位置不是帧头位置。接收端的具体实现过程如下：
1、系统上电或复位后等待前端的恒模算法(CMA，Constant Modulus Algorithm)细均衡模块收敛信号，当收到收敛信号后，帧同步/Lane同步模块开始操作，起始状态是帧失步(OOF，Out Of Frame)和lane失步(OOL，Out Of Lane)；
2、首先对输入数据进行硬判决处理，即根据输入数据的样点符号位判断0/1，硬判决结果组成接收序列；
3、接收序列分别与预存的4种帧头序列(分别对应4个lane)做异或并求和，异或求和长度为64bit；
4、帧同步操作，按比特滑动异或窗口，找到A≥52(即第一门限)或A≤12(即第二门限)的位置，A≥52表示数据反相；A≤12表示数据未反相，A为异或并求和的结果；
具体的，在OOF状态下，若6次(根据实际需要，次数可以设定为其 他值)在间隔帧长整数倍的位置上相关运算结果达到设定的阈值(即A≤12)，则进入帧同步(IF，In Frame)状态；
IF状态下，若连续6帧(根据实际需要，次数可以设定为其他值)查找不到同步帧头，表示处于帧失同步OOF状态，重新搜索帧头；
OOF状态下，若连续5ms(根据实际需要，次数可以设定为其他值)不能完成帧同步，则上报丢帧(LOF，Loss Of Frame)告警；
LOF告警状态下，连续5ms(根据实际需要，次数可以设定为其他值)找到同步帧头，进入IF状态，同时清除LOF告警状态。
5、帧同步IF后进行Lane同步操作：
检测和纪录Lane序号和Lane状态，区分X和Y偏振态；
若当前帧检测有Lane序号重复(正常情况下，一个接收序列与N路lane对应的帧头序列进行相关运算，只有一路lane的帧头序列与接收序列的相关运算结果会达到所述设定的阈值)，Lane失步告警，当前帧的数据保持上一帧检测的Lane序号和状态往后续的模块(如相位模糊补偿模块)送；
若当前帧检测出来的skew(抖动、即延迟差)值超过[-128UI，+128UI]，Lane失步告警；其中，UI表示单位间隔(Unit Interval)，skew值超过[-128UI，+128UI]，表示延迟差太大，超出系统的处理能力，上报告警，说明信道条件太差。
本发明实施例还提供了一种计算机可读存储介质，所述存储介质包括一组计算机可执行指令，所述指令用于执行本发明上述实施例提供的多路帧头检测的方法。
综上所述，通过本发明实施例的实施，能够使光通信的两个节点快速建链通信，抗干扰能力强(信道环境相对稳定的条件下同步后系统发生失步的概率低)，满足信道频偏范围多变的需求，具有帧同步实现简单，硬件容易实现，同步性能稳定等优点。
由于相关接收用的N个码组序列自相关性非常强，而互相关性很低，这样避免了漏检及虚警的发生，提高了同步的快速性和可靠性；通过对码组序列的差异化处理，在检测到帧头和lane号的同时估计出了链路的大频偏值，加快了大频偏的补偿时间，缩短了系统的建链时间；本地预存N套相关序列，分别对应N种不同的lane，可有效消除各个lane间的干扰对相关检测的影响。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流 程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (13)

  1. 一种多路帧头检测的方法，所述方法包括：
    对输入数据进行硬判决处理，得到接收序列；
    将所述接收序列与本地预存的与各通道lane对应的帧头序列分别进行滑动相关运算，得到运算结果；
    将所述运算结果与预设门限进行比较，得到门限判决结果；
    根据所述门限判决结果进行帧头判定和lane判定。
  2. 根据权利要求1所述多路帧头检测的方法，其中，所述本地预存的对应所有lane的帧头序列中，各帧头序列的自相关性高于第一阈值，且任意两个帧头序列之间的互相关性低于第二阈值。
  3. 根据权利要求1或2所述多路帧头检测的方法，其中，所述对输入数据进行硬判决处理，得到接收序列，包括：
    根据所述输入数据的样点符号位进行硬判决，样点符号位为0，硬判决结果为0，样点符号位为1，硬判决结果为1；硬判决结果组成所述接收序列。
  4. 根据权利要求3所述多路帧头检测的方法，其中，所述将接收序列与本地预存的与各通道lane对应的帧头序列分别进行滑动相关运算，得到运算结果，包括：
    将所述接收序列分别与N条lane对应的N个帧头序列进行滑动异或并求和运算，所述异或并求和的长度与所述帧头序列的长度相同，所述运算结果为所述滑动异或并求和的结果；所述接收序列分别与N个帧头序列进行滑动异或并求和运算，得到N个运算结果；N为大于1的整数。
  5. 根据权利要求4所述多路帧头检测的方法，其中，所述将运算结果与预设门限进行比较，得到门限判决结果，包括：
    将所述接收序列与第n个帧头序列进行滑动相关运算的运算结果， 与预设的第一门限和第二门限分别进行比较，当所述运算结果大于等于第一门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列反相；当所述运算结果小于等于第二门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列未反相；0＜n＜N，n为整数。
  6. 根据权利要求5所述多路帧头检测的方法，其中，所述根据门限判决结果进行帧头判定和lane判定，包括：
    当所述运算结果小于等于第二门限时，判定所述接收序列所在的位置是帧头位置，并获取参与相应运算的第n个帧头序列所对应的lane号；否则，判定所述接收序列所在的位置不是帧头位置。
  7. 一种多路帧头检测的装置，所述装置包括：硬判决单元、滑动相关单元、门限判决单元、帧头判定与通道lane判定单元，其中，
    所述硬判决单元，配置为对输入数据进行硬判决处理，得到接收序列；
    所述滑动相关单元，配置为将所述接收序列与本地预存的帧头序列进行滑动相关运算，得到运算结果；
    所述门限判决单元，配置为将所述运算结果与预设门限进行比较，得到门限判决结果；
    所述帧头判定与lane判定单元，配置为根据所述门限判决结果进行帧头判定和lane判定。
  8. 根据权利要求7所述多路帧头检测的装置，其中，所述本地预存的对应所有lane的帧头序列中，各帧头序列的自相关性高于第一阈值，且任意两个帧头序列之间的互相关性低于第二阈值。
  9. 根据权利要求7或8所述多路帧头检测的装置，其中，所述硬判决单元还配置为，根据所述输入数据的样点符号位进行硬判决，样点符号位为0，硬判决结果为0，样点符号位为1，硬判决结果为1；硬判决结果组成所述接收序列。
  10. 根据权利要求9所述多路帧头检测的装置，其中，所述滑动相关单元还配置为，将所述接收序列分别与N条lane对应的N个帧头序列进行滑动异或并求和运算，所述异或并求和的长度与所述帧头序列的长度相同，所述运算结果为所述滑动异或并求和的结果；所述接收序列分别与N个帧头序列进行滑动异或并求和运算，得到N个运算结果；N为大于1的整数。
  11. 根据权利要求10所述多路帧头检测的装置，其中，所述门限判决单元还配置为，将所述接收序列与第n个帧头序列进行滑动相关运算的运算结果，与预设的第一门限和第二门限分别进行比较，当所述运算结果大于等于第一门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列反相；当所述运算结果小于等于第二门限时，得到所述门限判决结果为所述接收序列与所述第n个帧头序列未反相；0＜n＜N，n为整数。
  12. 根据权利要求11所述多路帧头检测的装置，其中，所述帧头判定与lane判定单元还配置为，在所述运算结果小于等于第二门限时，判定所述接收序列所在的位置是帧头位置，并获取参与相应运算的第n个帧头序列所对应的lane号。
  13. 一种计算机可读存储介质，所述存储介质包括一组计算机可执行指令，所述指令用于执行权利要求1-6任一项所述的多路帧头检测的方法。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113542168A (zh) * 2020-04-14 2021-10-22 鹤壁天海电子信息系统有限公司 短波同步方法以及相关装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105828363B (zh) * 2016-03-30 2020-04-21 深圳科立讯通信有限公司 窄带无线数字通信时隙对齐的方法和装置
CN107437978B (zh) * 2016-05-27 2020-11-27 上海复旦微电子集团股份有限公司 数据处理方法及接收机
CN114401078B (zh) * 2022-01-14 2023-10-31 上海工程技术大学 一种图像数据帧帧头检测方法
CN115473572B (zh) * 2022-11-14 2023-03-24 南京控维通信科技有限公司 基于双相关算法实现信号到达检测的方法及系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006063424A1 (en) * 2004-12-14 2006-06-22 Nortel Networks Limited Synchronization in a multiple-input/multiple-output (mimo) orthogonal frequency division multiplexing (ofdm) system for wireless applications
CN101079647A (zh) * 2006-05-27 2007-11-28 中国科学技术大学 一种脉冲峰值检波的超宽带接收方法及其接收机
CN102469057A (zh) * 2010-11-11 2012-05-23 上海明波通信技术有限公司 适用于突发式通信系统的帧同步方法和装置
CN102970109A (zh) * 2012-11-16 2013-03-13 中兴通讯股份有限公司 一种高速多通道的数据传输方法、相关装置和系统

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2704196B2 (ja) * 1988-09-07 1998-01-26 国際電信電話 株式会社 ユニークワード検出器
JP2779047B2 (ja) * 1990-07-30 1998-07-23 日本電気ホームエレクトロニクス株式会社 スペクトル拡散通信方式及びその通信システム
KR0170730B1 (ko) * 1996-01-12 1999-03-20 김광호 필드 동기신호 검출회로 및 그 방법
JP3839569B2 (ja) * 1997-11-05 2006-11-01 株式会社日立国際電気 ユニークワード検出方式
JP4198428B2 (ja) * 2002-04-05 2008-12-17 三菱電機株式会社 無線伝送装置
JP4289854B2 (ja) * 2002-09-20 2009-07-01 京セラ株式会社 無線基地装置、移動端末装置、参照信号制御方法および参照信号制御プログラム
US20050185743A1 (en) * 2004-01-14 2005-08-25 Oki Techno Centre (Singapore) Pte Ltd Apparatus for burst and timing synchronization in high-rate indoor wireless communication
JP4590969B2 (ja) * 2004-07-28 2010-12-01 ソニー株式会社 無線通信システム、無線通信装置及び無線通信方法、並びにコンピュータ・プログラム
JP2006140720A (ja) * 2004-11-11 2006-06-01 Nippon Hoso Kyokai <Nhk> Ｍｉｍｏチャンネル応答測定方法及び測定装置
RU2007146445A (ru) * 2005-05-13 2009-06-20 Квэлкомм Инкорпорейтед (US) Способы и устройство для пакетирования контента для передачи по сети
JP4718933B2 (ja) * 2005-08-24 2011-07-06 富士通株式会社 並列信号のスキュー調整回路及びスキュー調整方法
JP4689456B2 (ja) * 2005-12-13 2011-05-25 京セラ株式会社 無線基地局装置及び無線通信制御方法
JP2009118175A (ja) * 2007-11-06 2009-05-28 Japan Radio Co Ltd 受信装置
JP4636162B2 (ja) * 2008-10-10 2011-02-23 ソニー株式会社 無線通信装置及び無線通信方法
EP2456096B1 (en) * 2009-07-17 2018-04-04 Huawei Technologies Co., Ltd. Method and apparatus for recovering optical channel transport unit k frame, and system for transmitting optical channel transport unit k frame
JP4913200B2 (ja) * 2009-11-04 2012-04-11 日本電信電話株式会社 パラレル光伝送方法、パラレル光伝送システム、及びパラレル光送信装置
JP4898897B2 (ja) * 2009-12-22 2012-03-21 インターナショナル・ビジネス・マシーンズ・コーポレーション タイミング相関値を用いた周波数オフセットによるデータのずれの補償
US9036999B2 (en) * 2010-07-31 2015-05-19 Alcatel Lucent Frame/symbol synchronization in coherent optical OFDM
JP2012199855A (ja) * 2011-03-23 2012-10-18 Kddi Corp 光伝送方式の偏波多重信号分離方法および該方法による送受信システム
CN103188195B (zh) * 2011-12-30 2017-05-17 国民技术股份有限公司 粗同步方法及装置
JP5863595B2 (ja) * 2012-08-13 2016-02-16 日本電信電話株式会社 タイムスロットインタリーブ伝送方法及びタイムスロットインタリーブ伝送システム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006063424A1 (en) * 2004-12-14 2006-06-22 Nortel Networks Limited Synchronization in a multiple-input/multiple-output (mimo) orthogonal frequency division multiplexing (ofdm) system for wireless applications
CN101079647A (zh) * 2006-05-27 2007-11-28 中国科学技术大学 一种脉冲峰值检波的超宽带接收方法及其接收机
CN102469057A (zh) * 2010-11-11 2012-05-23 上海明波通信技术有限公司 适用于突发式通信系统的帧同步方法和装置
CN102970109A (zh) * 2012-11-16 2013-03-13 中兴通讯股份有限公司 一种高速多通道的数据传输方法、相关装置和系统

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3163825A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113542168A (zh) * 2020-04-14 2021-10-22 鹤壁天海电子信息系统有限公司 短波同步方法以及相关装置

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