WO2016000271A1 - 液晶显示器的连接垫结构及其制作方法 - Google Patents

液晶显示器的连接垫结构及其制作方法 Download PDF

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Publication number
WO2016000271A1
WO2016000271A1 PCT/CN2014/081769 CN2014081769W WO2016000271A1 WO 2016000271 A1 WO2016000271 A1 WO 2016000271A1 CN 2014081769 W CN2014081769 W CN 2014081769W WO 2016000271 A1 WO2016000271 A1 WO 2016000271A1
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Prior art keywords
connection pad
layer
flat
insulating layer
slope
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Ceased
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PCT/CN2014/081769
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English (en)
French (fr)
Inventor
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/375,629 priority Critical patent/US9535299B2/en
Publication of WO2016000271A1 publication Critical patent/WO2016000271A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance

Definitions

  • the present invention relates to the field of liquid crystal display technology, and more particularly to a connection pad structure of a liquid crystal display and a method of fabricating the same. Background technique
  • the existing solution is to add one after the second layer of metal (ie, the metal for making the source and the drain) of the Array substrate is completed.
  • An overcoat layer with a large layer thickness. The flat layer can increase the distance between the second layer metal and the pixel electrode and the common electrode, thereby reducing the parasitic capacitance.
  • the fabrication of the planarization layer is usually completed simultaneously with the Passivation Layer, and a large open area is formed in the edge region of the array substrate to expose the connection pad structure.
  • the thickness of the flat layer usually 1.5 um to 3.0 um which is formed is large, it is easy to break the conductive layer when the conductive layer is formed on the connection pad structure and the flat layer.
  • connection pad structure is electrically connected to, for example, a Chip on Film (COF) by an anisotropic conductive film (ACF), and the conductive particles are dispersed in the ACF.
  • ACF anisotropic conductive film
  • the conductive particles move around the connection pad structure, and a part of the conductive particles reach the bottom end of the flat layer. Due to the large thickness of the flat layer, it is difficult for the conductive particles to pass over the flat layer, thereby being flat.
  • the bottom ends of the layers are gathered, which in turn causes short circuits between different signal lines (such as scan lines, data lines).
  • an object of the present invention is to provide a method for fabricating a connection pad structure of a liquid crystal display, comprising at least the following steps: A) forming a plurality of connection pads on a portion of the upper surface of the edge region of the substrate ; C) forming a flat layer on a portion of the upper surface of the edge region of the substrate, and covering Covering the connection pad; D) patterning the flat layer with a mask of light transmittance gradation, removing a flat layer formed on a portion of the upper surface of the connection pad, and forming another layer on the connection pad A side surface of a portion of the flat surface of the upper surface forms a slope.
  • the manufacturing method further includes the steps of: B) forming an insulating layer on a portion of the upper surface of the edge region of the substrate, and covering the connection pad.
  • the step D) is replaced by: E) patterning the flat layer and the insulating layer by using a mask of light transmittance grading to remove the flat layer and the insulating layer formed on a portion of the upper surface of the connection pad At the same time, a side surface of the flat layer formed on the upper surface of the other portion of the connection pad is formed as a slope.
  • step D) is replaced by: E) patterning the flat layer and the insulating layer with a mask of light transmittance grading, forming a flat layer and a portion of the insulating layer on a portion of the upper surface of the connection pad While being removed, a side surface of the flat layer formed on the upper surface of the other portion of the connection pad is formed as a slope.
  • the manufacturing method further includes: forming a conductive layer on a portion of the upper surface of the edge region of the substrate, wherein the conductive layer covers a portion of the upper surface of the connection pad, a slope of the flat layer, and a top surface thereof.
  • the manufacturing method further includes: forming a conductive layer on a portion of the upper surface of the edge region of the substrate, wherein the conductive layer covers a portion of the upper surface of the connection pad that is not covered by the remaining portion of the insulating layer, The upper surface of the remaining portion of the insulating layer, the slope of the flat layer, and the top surface thereof.
  • connection pad structure of a liquid crystal display comprising at least: a plurality of connection pads formed on a portion of an upper surface of an edge region of the substrate; a flat layer having a side surface beveled and located at the Connecting another portion of the upper surface of the pad, wherein the bevel is a flat layer covering the connection pad by patterning with a transmittance gradient, and removing a flat layer formed on a portion of the upper surface of the connection pad At the same time formed.
  • the connection pad structure further includes: an insulating layer between the upper surface of the other portion of the connection pad and the planar layer.
  • connection pad structure further includes: an insulating layer, wherein a portion of the insulating layer is located between an upper surface of another portion of the connection pad and the planar layer, and a remaining portion of the insulating layer is located in the Connect the upper surface of the pad.
  • connection pad structure further includes: a conductive layer covering a portion of the upper surface of the connection pad, a slope of the flat layer, and a top surface thereof.
  • connection pad structure further includes: a conductive layer covering a portion of the upper surface of the connection pad not covered by the remaining portion of the insulating layer, an upper surface of the remaining portion of the insulating layer, the planar layer The slope and its top surface.
  • connection pad structure of the present invention is electrically connected to, for example, a chip-on-film (COF) by an anisotropic conductive film (ACF), the ACF is pressed to cause a portion in the ACF.
  • the conductive particles move around the connection pad structure.
  • the conductive particles are easy to pass over the slope of the flat layer, and are not easily gathered at the bottom end of the slope of the flat layer, thereby avoiding different signal lines (such as scanning). Short circuit between line, data line).
  • FIG. 2 is a partial side cross-sectional view of a liquid crystal display according to an embodiment of the present invention
  • FIG. 3 is a partial plan view showing a connection pad structure of a liquid crystal display according to another embodiment of the present invention
  • 4 is a partial side cross-sectional view of a liquid crystal display according to another embodiment of the present invention.
  • FIG. 5 is a flow chart showing a method of fabricating a connection pad structure of a liquid crystal display according to an embodiment of the present invention.
  • FIGS. 1 is a partial top plan view showing a connection pad structure of a liquid crystal display according to an embodiment of the present invention.
  • 2 is a partial side cross-sectional view of a liquid crystal display in accordance with an embodiment of the present invention.
  • a thin film transistor (TFT) 20 is disposed on a portion of the upper surface of a pixel region A of a substrate (for example, a glass substrate) 10; wherein the thin film transistor 20 is included in the pixel region A of the substrate 10.
  • a substrate for example, a glass substrate
  • Electrode layer 28 a portion of the upper surface sequentially formed with the gate electrode 21, the insulating layer 22, an active layer composed of the amorphous silicon layer 23 and the ohmic contact layer 24, a source electrode (metal layer) 25a and a drain electrode (metal layer) on the active layer 25b, a flat layer 26, a via hole 27 formed above the drain electrode 25b and formed in the flat layer 26, and a transparent electrode layer (ie, ITO (Indium Tin Oxide) which is located in the via hole 27 and electrically connected to the drain electrode 25b. ) Electrode layer 28.
  • ITO Indium Tin Oxide
  • connection pad structure 30 is disposed on a portion of the upper surface of the edge region B of the substrate 10; wherein the connection pad structure 30 includes a plurality of connection pads 31, an insulating layer 22, and a flat layer sequentially formed on a portion of the upper surface of the edge region B of the substrate 10. 26 and transparent electrode layer 28. Further, since the flat layer 26 has an insulating function, as another embodiment of the present invention, the insulating layer 22 may not be formed on the upper surface of the connection pad 31.
  • the connection pad 31 is formed simultaneously with the gate electrode 21 of the thin film transistor 20, but the present invention is not limited thereto.
  • One side of the flat layer 26 is a slope 261 and is located on the upper surface of the other portion of the connection pad 31.
  • the slope 261 is a patterning process of the flat layer 26 in the edge region B and covering the connection pad 31 by a mask having a light transmittance gradation, and a flat layer to be formed on a portion of the upper surface of the connection pad 31 26 is formed at the same time as removal.
  • a portion of the insulating layer 22 at the edge region B is located between the upper surface of the other portion of the connection pad 31 and the flat layer 26, and the remaining portion of the insulating layer 22 is located at a portion of the upper surface of the connection pad 31.
  • the transparent electrode layer 28 covers a portion of the upper surface of the connection pad 31 that is not covered by the remaining portion of the insulating layer 22, the remaining upper surface of the insulating layer 22, and the top surface 263 of the planar layer 26 of the edge region B.
  • the slope 261 is formed by using a mask having a light transmittance gradation, the inclination angle of the slope 261 (that is, the angle between the slope 261 of the flat layer 26 and the bottom surface 262) can be greatly reduced, resulting in The slope 261 of the flat layer 26 becomes gentle.
  • the transparent electrode layer 28 is formed, the transparent electrode layer 28 is less likely to be broken.
  • connection pad structure 30 of the present embodiment is electrically connected to, for example, a Chip on Film (COF) by an anisotropic conductive film (ACF)
  • ACF anisotropic conductive film
  • the ACF is squeezed to cause an ACF.
  • Part of the conductive particles to the connection pad structure 30 Moving around, since the slope 261 of the flat layer 26 is relatively gentle, this portion of the conductive particles tends to pass over the slope 261 of the flat layer 26, and is less likely to gather at the bottom end of the slope 261 of the flat layer 26, thereby avoiding different signal lines (for example, scanning) Short circuit between line, data line).
  • the remaining portion of the insulating layer 22 on the upper surface of the portion of the connection pad 31 can also be removed.
  • the transparent electrode layer 28 covers a portion of the upper surface of the connection pad 31 and the top surface 263 of the planar layer 26 of the edge region B.
  • connection pad structure of the liquid crystal display of the present embodiment Since the method of fabricating the thin film transistor 20 in the present embodiment has been known, the method of fabricating the thin film transistor 20 will not be described in order to avoid redundancy. Hereinafter, only a method of manufacturing the connection pad structure of the liquid crystal display of the present embodiment will be described.
  • 5 is a flow chart of a method of fabricating a connection pad structure of a liquid crystal display according to an embodiment of the present invention. Referring to FIGS. 1, 2, and 5, in operation 301, a plurality of connection pads 31 are formed on a portion of the upper surface of the edge region B of the substrate 10.
  • connection pad 31 is formed simultaneously with the gate electrode 21 of the thin film transistor 20, that is, the material used for the connection pad 31 may be the same as that of the gate electrode 21 of the thin film transistor 20, but the present invention Not limited to this.
  • an insulating layer 22 is formed on a portion of the upper surface of the edge region B of the substrate 10, and covers a plurality of connection pads 31.
  • a flat layer 26 is formed on a portion of the upper surface of the edge region B of the substrate 10, and the insulating layer 22 is covered.
  • the planarization layer 26 and the insulating layer 22 are patterned by a transmittance gradient mask, and portions of the planar layer 26 and the insulating layer 22 formed on a portion of the upper surface of the connection pad 31 are removed.
  • a side surface of the flat layer 26 formed on the upper surface of the other portion of the connection pad 31 forms a slope 261.
  • the remaining portion of the insulating layer 22 is located on a portion of the upper surface of the connection pad 31.
  • the light transmittance gradation mask may refer to a portion thereof that is transparent with respect to a portion of the upper surface of the connection pad 31 (ie, a light transmittance of about 100%), and a partial transmittance thereof with respect to the slope 261.
  • the mask of the light transmittance gradation may also be a mask having a slit density gradation (ie, a light transmittance gradation), which refers to a slit thereof with respect to a portion of a portion of the upper surface of the connection pad 31.
  • a transparent electrode layer 28 is formed on a portion of the upper surface of the edge region B of the substrate 10.
  • the transparent electrode layer 28 covers a portion of the upper surface of the connection pad 31 that is not covered by the remaining portion of the insulating layer 22, the remaining upper surface of the insulating layer 22, and the top surface 263 of the planar layer 26 of the edge region B.
  • the operation 302 can be removed, that is, after the operation 301 is performed, the operation 303 is directly performed. Accordingly, in operation 303, operation 304, and operation 305, the operations performed on the insulating layer 22 may be correspondingly removed.
  • the flat layer 26 and the insulating layer 22 are patterned by a transmittance gradient mask, and the flat layer 26 and the insulating layer 22 are formed on the upper surface of the connecting pad 31. While the layer 22 is being removed, a side surface of the flat layer 26 formed on the upper surface of the other portion of the connection pad 31 is formed with a slope 261.
  • a transparent electrode layer 28 is formed on a portion of the upper surface of the edge region B of the substrate 10.
  • the transparent electrode layer 28 covers a portion of the upper surface of the connection pad 31 and a top surface 263 of the planar layer 26 of the edge region B.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种液晶显示器的连接垫结构及其制作方法，其至少包括：多个连接垫(31)，形成在基板(10)边缘区域的部分上表面；平坦层(26)，其一侧面为斜面(261)，并位于该连接垫（31）的另一部分上表面，其中，斜面（261）是在利用透光率渐变的掩膜图案化覆盖连接垫（31）的平坦层（26），将形成在连接垫（31）的部分上表面的平坦层去除的同时形成。通过将平坦层的一侧面形成为斜面，并使平坦层的斜面的倾斜角大幅度减小，致使平坦层的斜面变得平缓，这样在形成导电层时，不易使导电层断裂，同时避免了不同信号线之间的短路。

Description

说 明 书 液晶显示器的连接垫结构及其制作方法 技术领域
本发明涉及液晶显示技术领域， 更具体地讲， 涉及一种液晶显示器的连接 垫结构及其制作方法。 背景技术
随着液晶显示器（LCD ) 的尺寸的增大， 液晶显示器中的各种信号线的阻 容延迟 （RC Delay)变的愈加严重， 导致像素充电变差， 从而影响液晶显示器 的显示品质。 为了降低信号线之间的寄生电容， 减小阻容延迟， 现有的解决方案是在阵 列 （Array ) 基板的第二层金属 （即制作源极、 漏极的金属） 制作完成之后， 增加一层厚度很大的平坦层 （Overcoat Layer )。 该平坦层可以增加第二层金属 和像素电极、 公共电极之间的距离， 从而起到减小寄生电容的作用。
此外，为了节省制作成本，平坦层的制作通常与防护层（Passivation Layer) 同时完成， 并且在阵列基板的边缘区域制作一较大的开口区来使连接垫结构露 出。 然而， 由于制作完成的平坦层厚度 （通常为 1.5 um〜3.0um) 较大， 所以 在连接垫结构与平坦层上制作导电层时， 极易使导电层断裂。
此外， 连接垫结构通过异向性导电膜 （Anisotropic conductive film, ACF) 与例如软性电路板 （Chip on Film, COF) 电连结， 导电粒子分散在 ACF中。 当 ACF受到挤压后， 导电粒子会向连接垫结构周围移动， 其中一部分导电粒 子会到达平坦层的底端， 由于平坦层厚度较大， 因此这部分导电粒子很难越过 平坦层，从而在平坦层的底端处聚集起来，进而引起不同信号线（例如扫描线、 数据线） 之间短路。 发明内容 为了解决上述现有技术存在的问题， 本发明的目的在于提供一种液晶显示 器的连接垫结构的制作方法， 其至少包括步骤： A) 在基板边缘区域的部分上 表面形成多个连接垫； C ) 在该基板边缘区域的部分上表面形成平坦层， 并覆 盖所述连接垫； D) 利用透光率渐变的掩膜图案化所述平坦层， 将形成在所述 连接垫的部分上表面的平坦层去除的同时， 将形成在所述连接垫的另一部分上 表面的平坦层的一侧面形成斜面。 进一步地， 在执行步骤 C ) 之前， 所述制作方法还包括步骤： B ) 在该基 板边缘区域的部分上表面形成绝缘层， 并覆盖所述连接垫。 进一步地， 所述步骤 D) 替换为： E) 利用透光率渐变的掩膜图案化所述 平坦层和绝缘层，将形成在所述连接垫的部分上表面的平坦层和绝缘层去除的 同时， 将形成在所述连接垫的另一部分上表面的平坦层的一侧面形成斜面。 进一步地， 所述步骤 D) 替换为： E) 利用透光率渐变的掩膜图案化所述 平坦层和绝缘层，将形成在所述连接垫的部分上表面的平坦层和绝缘层的部分 去除的同时， 将形成在所述连接垫的另一部分上表面的平坦层的一侧面形成斜 面。 进一步地， 所述制作方法还包括： 在该基板边缘区域的部分上表面形成导 电层， 其中， 所述导电层覆盖所述连接垫的部分上表面、 所述平坦层的斜面及 其顶面。 进一步地， 所述制作方法还包括： 在该基板边缘区域的部分上表面形成导 电层， 其中， 所述导电层覆盖所述连接垫的未被所述绝缘层的其余部分覆盖的 部分上表面、 所述绝缘层的其余部分上表面、 所述平坦层的斜面及其顶面。 本发明的另一目的还在于提供一种液晶显示器的连接垫结构， 其至少包 括： 多个连接垫， 形成在基板边缘区域的部分上表面； 平坦层， 其一侧面为斜 面， 并位于所述连接垫的另一部分上表面， 其中， 所述斜面是在利用透光率渐 变的掩膜图案化覆盖所述连接垫的平坦层， 将形成在所述连接垫的部分上表面 的平坦层去除的同时形成。 进一步地， 所述连接垫结构还包括： 绝缘层， 位于所述连接垫的另一部分 上表面与所述平坦层之间。 进一步地， 所述连接垫结构还包括： 绝缘层， 其中， 所述绝缘层的部分位 于所述连接垫的另一部分上表面与所述平坦层之间， 所述绝缘层的其余部分位 于所述连接垫的部分上表面。 进一步地， 所述连接垫结构还包括： 导电层， 覆盖所述连接垫的部分上表 面、 所述平坦层的斜面及其顶面。 进一步地， 所述连接垫结构还包括： 导电层， 其覆盖所述连接垫的未被所 述绝缘层的其余部分覆盖的部分上表面、 所述绝缘层的其余部分上表面、 所述 平坦层的斜面及其顶面。 本发明通过将平坦层的一侧面形成为斜面， 并使平坦层的斜面的倾斜角 (即平坦层的斜面与底面之间的夹角）大幅度减小， 致使平坦层的斜面变得平 缓。 这样， 在形成导电层时， 不易使导电层断裂。 此外， 当本发明的连接垫结 构通过异向性导电膜 （Anisotropic conductive film, ACF) 与例如软性电路板 ( Chip on Film, COF) 电连结之后， ACF受到挤压后会导致 ACF中的部分导 电粒子向连接垫结构周围移动， 由于平坦层的斜面较为平缓， 因此这部分导电 粒子易于越过平坦层的斜面， 不易在平坦层的斜面的底端聚集起来， 从而避免 了不同信号线 （例如扫描线、 数据线） 之间的短路。
附图说明 通过结合附图进行的以下描述， 本发明的实施例的上述和其它方面、 特点 和优点将变得更加清楚， 附图中： 图 1是根据本发明的实施例的液晶显示器的连接垫结构的部分俯视示意 图； 图 2是根据本发明的实施例的液晶显示器的部分侧向剖视示意图； 图 3是根据本发明的另一实施例的液晶显示器的连接垫结构的部分俯视示 意图； 图 4是根据本发明的另一实施例的液晶显示器的部分侧向剖视示意图； 图 5是根据本发明的实施例的液晶显示器的连接垫结构的制作方法的流程 图。
具体实施方式 以下， 将参照附图来详细描述本发明的实施例。 然而， 可以以许多不同的 形式来实施本发明， 并且本发明不应该被解释为限制于这里阐述的具体实施 例。 相反， 提供这些实施例是为了解释本发明的原理及其实际应用， 从而使本 领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的 各种修改。 图 1是根据本发明的实施例的液晶显示器的连接垫结构的部分俯视示意 图。 图 2是根据本发明的实施例的液晶显示器的部分侧向剖视示意图。 参照图 1和图 2， 薄膜晶体管 （Thin Film Transistor, TFT) 20配置在一基 板 （例如玻璃基板） 10的像素区域 A的部分上表面； 其中， 薄膜晶体管 20包 括在基板 10的像素区域 A的部分上表面依次形成的栅电极 21、 绝缘层 22、由 非晶硅层 23和欧姆接触层 24组成的有源层、有源层上的源电极（金属层） 25a 和漏电极（金属层） 25b、 平坦层 26、 位于漏电极 25b上方并在平坦层 26中形 成的过孔 27以及位于过孔 27中并与漏电极 25b电连结的透明电极层 （即 ITO (Indium Tin Oxide, 氧化铟锡） 电极层） 28。 连接垫结构 30配置在基板 10的边缘区域 B的部分上表面； 其中， 连接垫 结构 30包括在基板 10的边缘区域 B的部分上表面依次形成的多个连接垫 31、 绝缘层 22、 平坦层 26及透明电极层 28。 此外， 由于平坦层 26具有绝缘功能， 所以作为本发明的另一实施方式， 在连接垫 31的上表面可不形成绝缘层 22。 所述连接垫 31是与薄膜晶体管 20的栅电极 21同时形成的， 但本发明并 不限制于此。 平坦层 26的一侧面为斜面 261， 并位于所述连接垫 31的另一部 分上表面。此外，斜面 261是在利用透光率渐变的掩膜对处于边缘区域 B并覆 盖所述连接垫 31的平坦层 26进行图案化处理， 将形成在所述连接垫 31的部 分上表面的平坦层 26去除的同时形成。处于边缘区域 B的绝缘层 22的部分位 于所述连接垫 31的另一部分上表面与平坦层 26之间， 绝缘层 22的其余部分 位于所述连接垫 31的部分上表面。 透明电极层 28覆盖所述连接垫 31的未被 绝缘层 22的其余部分覆盖的部分上表面、绝缘层 22的其余部分上表面以及处 于边缘区域 B的平坦层 26的顶面 263。 在本实施例中，由于采用透光率渐变的掩膜形成斜面 261，并可使斜面 261 的倾斜角 （即平坦层 26的斜面 261与底面 262之间的夹角） 大幅度减小， 致 使平坦层 26的斜面 261变得平缓。 这样， 在形成透明电极层 28时， 不易使透 明电极层 28断裂。 此外， 当本实施例的连接垫结构 30通过异向性导电膜 (Anisotropic conductive film, ACF) 与例如软性电路板 (Chip on Film, COF) 电连结之后， ACF受到挤压后会导致 ACF中的部分导电粒子向连接垫结构 30 周围移动， 由于平坦层 26的斜面 261较为平缓， 因此这部分导电粒子易于越 过平坦层 26的斜面 261， 不易在平坦层 26的斜面 261的底端聚集起来， 从而 避免了不同信号线 （例如扫描线、 数据线） 之间的短路。
作为本发明的另一实施方式，参照图 3和图 4，位于所述连接垫 31的部分 上表面的绝缘层 22的其余部分也可被去除掉。 这样， 透明电极层 28覆盖所述 连接垫 31的部分上表面以及处于边缘区域 B的平坦层 26的顶面 263。 如此， 可使的制作较为简单， 并且可减小未被平坦层 26覆盖的连接垫 31的宽度， 有 利于液晶显示器的窄边框的设计。
由于本实施例中的薄膜晶体管 20的制作方法已成为公知技术， 因此为了 避免重复赘述， 对薄膜晶体管 20的制作方法不作说明。 以下， 只针对本实施 例的液晶显示器的连接垫结构的制作方法进行说明。 图 5是根据本发明的实施例的液晶显示器的连接垫结构的制作方法的流程 图。 参照图 1、 图 2和图 5， 在操作 301中， 在基板 10的边缘区域 B的部分上 表面形成多个连接垫 31。 这里， 所述连接垫 31是与薄膜晶体管 20的栅电极 21同时形成的， 也就是说， 所述连接垫 31所采用的材料可与制作薄膜晶体管 20的栅电极 21的材料相同， 但本发明并不限制于此。 在操作 302中， 在基板 10的边缘区域 B的部分上表面形成绝缘层 22， 并 覆盖多个连接垫 31。 在操作 303中， 在基板 10的边缘区域 B的部分上表面形成平坦层 26， 并 覆盖绝缘层 22。 在操作 304中， 利用透光率渐变的掩膜图案化平坦层 26和绝缘层 22， 将 形成在所述连接垫 31的部分上表面的平坦层 26和绝缘层 22的部分去除的同 时，将形成在所述连接垫 31的另一部分上表面的平坦层 26的一侧面形成斜面 261。 这里， 需要说明的是， 绝缘层 22的其余部分位于所述连接垫 31的部分上 表面。 所述透光率渐变的掩膜可指的是其相对于所述连接垫 31的部分上表面 的部分为透明（即透光率约为 100%)，其相对于斜面 261的部分透光率渐变（即 从相对于斜面 261的底端至相对于斜面 261的顶端透光率逐渐减小）， 其相对 于平坦层 26的顶面 263的部分的透光率约为 0的掩膜。 此外， 所述透光率渐 变的掩膜还可是狭缝密度渐变（即透光率渐变） 的掩膜， 其指的是其相对于所 述连接垫 31的部分上表面的部分的狭缝的密度较大， 其相对于斜面 261的部 分狭缝的密度渐变（即从相对于斜面 261的底端至相对于斜面 261的顶端狭缝 的密度逐渐减小），其相对于平坦层 26的顶面 263的部分的狭缝的密度最小（或 者没有狭缝） 的掩膜。 在操作 305中，在基板 10的边缘区域 B的部分上表面形成透明电极层 28。 这里， 透明电极层 28覆盖所述连接垫 31的未被绝缘层 22的其余部分覆盖的 部分上表面、绝缘层 22的其余部分上表面以及处于边缘区域 B的平坦层 26的 顶面 263。 此外， 在上述操作中， 操作 302可以被移除， 即在进行完操作 301之后， 直接进行操作 303。 相应的， 在操作 303、 操作 304以及操作 305中， 对绝缘 层 22进行的操作可相应的被移除。 作为本发明的另一实施方式， 在操作 304中， 利用透光率渐变的掩膜图案 化平坦层 26和绝缘层 22， 将形成在所述连接垫 31的部分上表面的平坦层 26 和绝缘层 22去除的同时， 将形成在所述连接垫 31的另一部分上表面的平坦层 26的一侧面形成斜面 261。 在操作 305中， 在基板 10的边缘区域 B的部分上 表面形成透明电极层 28。这里，透明电极层 28覆盖所述连接垫 31部分上表面 以及处于边缘区域 B的平坦层 26的顶面 263。 这样， 可使的制作较为简单， 并且可减小未被平坦层 26覆盖的连接垫 31的宽度， 有利于液晶显示器的窄边 框的设计。 虽然已经参照特定实施例示出并描述了本发明， 但是本领域的技术人员将 理解： 在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下， 可在此进行形式和细节上的各种变化。

Claims

权利要求书
1、 一种液晶显示器的连接垫结构的制作方法， 其中， 至少包括步骤：
A) 在基板边缘区域的部分上表面形成多个连接垫；
C) 在该基板边缘区域的部分上表面形成平坦层， 并覆盖所述连接垫；
D ) 利用透光率渐变的掩膜图案化所述平坦层， 将形成在所述连接垫的部 分上表面的平坦层去除的同时，将形成在所述连接垫的另一部分上表面的平坦 层的一侧面形成斜面。
2、 根据权利要求 1所述的制作方法， 其中， 在执行步骤 C) 之前， 所述 制作方法还包括步骤：
B ) 在该基板边缘区域的部分上表面形成绝缘层， 并覆盖所述连接垫。
3、 根据权利要求 2所述的制作方法， 其中， 所述步骤 D) 替换为：
E) 利用透光率渐变的掩膜图案化所述平坦层和绝缘层， 将形成在所述连 接垫的部分上表面的平坦层和绝缘层去除的同时， 将形成在所述连接垫的另一 部分上表面的平坦层的一侧面形成斜面。
4、 根据权利要求 2所述的制作方法， 其中， 所述步骤 D) 替换为：
E) 利用透光率渐变的掩膜图案化所述平坦层和绝缘层， 将形成在所述连 接垫的部分上表面的平坦层和绝缘层的部分去除的同时， 将形成在所述连接垫 的另一部分上表面的平坦层的一侧面形成斜面。
5、 根据权利要求 3所述的制作方法， 其中， 还包括： 在该基板边缘区域 的部分上表面形成导电层， 其中， 所述导电层覆盖所述连接垫的部分上表面、 所述平坦层的斜面及其顶面。
6、 根据权利要求 4所述的制作方法， 其中， 还包括： 在该基板边缘区域 的部分上表面形成导电层， 其中， 所述导电层覆盖所述连接垫的未被所述绝缘 层的其余部分覆盖的部分上表面、 所述绝缘层的其余部分上表面、 所述平坦层 的斜面及其顶面。
7、 一种液晶显示器的连接垫结构， 其中， 至少包括: 多个连接垫， 形成在基板边缘区域的部分上表面； 平坦层， 其一侧面为斜面， 并位于所述连接垫的另一部分上表面， 其中， 所述斜面是在利用透光率渐变的掩膜图案化覆盖所述连接垫的平坦层， 将形成 在所述连接垫的部分上表面的平坦层去除的同时形成。
8、 根据权利要求 7所述的连接垫结构， 其中， 还包括： 绝缘层， 位于所 述连接垫的另一部分上表面与所述平坦层之间。
9、 根据权利要求 7所述的连接垫结构， 其中， 还包括： 绝缘层， 其中， 所述绝缘层的部分位于所述连接垫的另一部分上表面与所述平坦层之间， 所述 绝缘层的其余部分位于所述连接垫的部分上表面。
10、 根据权利要求 8所述的连接垫结构， 其中， 还包括： 导电层， 覆盖所 述连接垫的部分上表面、 所述平坦层的斜面及其顶面。
11、 根据权利要求 8所述的连接垫结构， 其中， 还包括： 导电层， 其覆盖 所述连接垫的未被所述绝缘层的其余部分覆盖的部分上表面、所述绝缘层的其 余部分上表面、 所述平坦层的斜面及其顶面。
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