WO2015180408A1 - 封装装置和封装设备 - Google Patents

封装装置和封装设备 Download PDF

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Publication number
WO2015180408A1
WO2015180408A1 PCT/CN2014/089893 CN2014089893W WO2015180408A1 WO 2015180408 A1 WO2015180408 A1 WO 2015180408A1 CN 2014089893 W CN2014089893 W CN 2014089893W WO 2015180408 A1 WO2015180408 A1 WO 2015180408A1
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WO
WIPO (PCT)
Prior art keywords
mask
substrate
power source
switch
release
Prior art date
Application number
PCT/CN2014/089893
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English (en)
French (fr)
Inventor
藤野诚治
黄国东
张小磊
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/891,880 priority Critical patent/US10026635B2/en
Publication of WO2015180408A1 publication Critical patent/WO2015180408A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833—Details of electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/841—Self-supporting sealing arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a packaging device and a packaging device.
  • OLED display screen has self-luminous characteristics, using a very thin organic material coating and a glass substrate. When an electric current passes, these organic materials emit light, and OLED The display screen has a large viewing angle and can save significant power. Therefore, with the development of display technology, the application of OLED display technology is more and more extensive. For example, as an important application of OLED display technology, Active Matrix Organic Light Emitting Diode (AMOLED) display screens are widely used due to their fast response speed, high contrast ratio and wide viewing angle. use.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the prepared first substrate and the second substrate need to be packaged by a packaging device to form a display screen, wherein the packaging device is an ultraviolet (ultra-violet) illumination integrated package device.
  • the packaging device may include an upper quartz platform and a lower quartz platform, a second substrate may be disposed on the upper quartz platform, a mask plate may be disposed on the lower quartz platform, and the first substrate is disposed on the mask plate, wherein the first substrate is The second substrate is packaged to form a display screen.
  • the first substrate is aligned by a mechanically fixed alignment mechanism, and after the alignment, the first substrate is fixed on the mask, and the stress generated by the mechanically fixed alignment mechanism is complicated. It is easy to cause deformation of the first substrate;
  • the invention provides a packaging device and a packaging device, which can avoid deformation of a first substrate during a packaging process, avoid generation of air bubbles between the first substrate and the second substrate, improve alignment precision, and avoid the process of pressing The first substrate slides off the mask.
  • the present invention provides a package device including a mask and a control circuit electrically connected to the mask, the control circuit for controlling the mask to The mask plate electrostatically adsorbs the first substrate or releases the first substrate.
  • the mask comprises a substrate, a patterned layer over the substrate, and an insulating layer over the patterned layer, the patterned layer comprising a graphic structure and an opening between the graphic structures
  • the structure is electrically connected to the control circuit.
  • the mask further includes a first connection structure on a side of the substrate and at least one second connection structure in each of the opening structures, wherein the first connection structure is used for The graphic structure is electrically connected to the control circuit, and the second connection structure is for electrically connecting a graphic structure located outside the opening structure and a graphic structure located inside the opening structure.
  • the length of the second connecting structure is greater than or equal to the width of the opening structure.
  • a positive voltage is applied to the mask through the control circuit to cause the mask to adsorb the first substrate, and then a negative voltage is applied to the mask through the control circuit or Release a positive charge on the mask to cause the mask to release the first substrate; or pass a negative voltage to the mask through the control circuit to cause the mask to adsorb
  • the first substrate is then passed through the control circuit to apply a positive voltage to the mask or to release a negative charge on the mask to cause the mask to release the first substrate.
  • control circuit includes a first power source and a second power source connected in parallel,
  • the first power source is used to pass a positive voltage to the mask, and the second power source is used to pass a negative voltage to the mask.
  • the positive electrode of the first power source and the negative electrode of the second power source are both connected to the mask board, and the negative electrode of the first power source is grounded through the first switch, the second power source The positive electrode is grounded through a second switch, the first power source is configured to pass a positive voltage to the mask when the first switch is closed and the second switch is open, the second power source is used when The second switch is closed and a negative voltage is applied to the mask when the first switch is turned off.
  • control circuit includes a third power supply and a release branch connected in parallel, wherein: the third power supply is used to pass a positive voltage to the mask, and the release branch is used to release the A positive charge on the mask; or the third power source is used to pass a negative voltage to the mask, the release branch for releasing a negative charge on the mask.
  • the third power source is used to apply a positive voltage to the mask and the release branch is used to release a positive charge on the mask
  • the third power source One end of the positive electrode and the release branch are connected to the mask, the negative electrode of the third power source is grounded through a third switch, and the other end of the release branch is grounded through a fourth switch, a three power source for applying a positive voltage to the mask when the third switch is closed and the fourth switch is open, the release branch being used when the fourth switch is closed and the third The positive charge on the mask is released when the switch is turned off.
  • the third power source is used to pass a negative voltage to the mask and the release branch is used to release a negative charge on the mask
  • the third power source One end of the negative electrode and the release branch are connected to the mask, the positive electrode of the third power source is grounded through a third switch, and the other end of the release branch is grounded through a fourth switch, a three power source for applying a negative voltage to the mask when the third switch is closed and the fourth switch is open, the release branch being used when the fourth switch is closed and the third The negative charge on the mask is released when the switch is turned off.
  • the present invention further provides a packaging apparatus comprising: an upper platform, a lower platform, and the above packaging device, wherein: the mask is disposed on the lower platform, and the upper platform is configured to a second substrate; or the mask is disposed on the upper platform, and the lower platform is configured to set a second substrate.
  • the mask is controlled by the control circuit to electrostatically adsorb the first substrate or release the first substrate, and the first substrate is not fixed by using a mechanical fixing alignment mechanism.
  • the electrostatic adsorption method realizes complete adsorption of the mask plate on the first substrate, thereby avoiding deformation of the first substrate, avoiding generation of air bubbles between the first substrate and the second substrate, improving alignment accuracy, and avoiding The first substrate slides off the mask during the pressing process.
  • FIG. 1 is a schematic structural diagram of a packaging device according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic plan view of the mask of FIG. 1.
  • FIG. 3a is a schematic diagram of an operational state of the control circuit of FIG. 1.
  • FIG. 3b is a schematic diagram of another working state of the control circuit of FIG. 1.
  • FIG. 3b is a schematic diagram of another working state of the control circuit of FIG. 1.
  • FIG. 4 is a schematic structural diagram of a packaging device according to Embodiment 2 of the present invention.
  • Figure 5a is a schematic diagram of an operational state of the control circuit of Figure 4.
  • FIG. 5b is a schematic diagram of another working state of the control circuit of FIG. 4.
  • FIG. 6 is a schematic structural diagram of a packaging device according to Embodiment 3 of the present invention.
  • Figure 7a is a schematic illustration of the curing of the sealant during the packaging process using the packaging device of Figure 6.
  • FIG. 7b is a schematic diagram of the sealant after being packaged by the packaging device of FIG. 6.
  • FIG. 7b is a schematic diagram of the sealant after being packaged by the packaging device of FIG. 6.
  • the packaging device includes: a mask 1 and a control circuit 2 electrically connected to the mask 1 , and the control circuit 2 It is used to control the mask 1 so that the mask 1 electrostatically adsorbs the first substrate 3 or releases the first substrate 3.
  • the mask 1 includes a substrate 11, a pattern layer 12 over the substrate 11, and an insulation over the pattern layer 12.
  • Layer 13 The graphics layer 12 includes a graphics structure 121 and an opening structure 122 between the graphics structures 121.
  • the graphics structure 121 is electrically coupled to the control circuitry 2.
  • the graphic structure 121 is used to block the UV, and the opening structure 122 is disposed corresponding to the frame sealant.
  • the UV is irradiated onto the sealant by the opening structure 122 to achieve curing of the sealant.
  • the shape of the opening structure is annular.
  • the material of the pattern structure 121 is a metal, for example, Cr or Al.
  • the substrate 11 is quartz glass.
  • the material of the insulating layer 13 includes Al 2 O 3 , SiO 2 or SiON.
  • the mask 1 further includes a first connection structure 14 (shown in FIG. 1) on the side of the substrate 11 and at least one second connection structure 15 (shown in FIG. 2) in each of the opening structures 122.
  • the first connection structure 14 is for electrically connecting the graphic structure 121 to the control circuit 2.
  • the second connecting structure 15 is for electrically connecting the graphic structure 121 located outside the opening structure 122 and the graphic structure 121 located inside the opening structure 122, so that all the graphic structures 121 above the entire substrate 11 can be realized by the second connecting structure 15. Electrical connection.
  • the number of the second connecting structures 15 may be one or more.
  • the number of the second connecting structures 15 is two, and the two second connecting structures 15 are diagonally disposed, and two second connections are adopted in each of the opening structures 122.
  • the structure 15 can ensure the electrical connection characteristics of the graphic structure 121 and ensure the simple patterning of the entire graphic layer.
  • the material of the second connecting structure 15 is metal.
  • the materials of the second connecting structure 15 and the graphic structure 121 are the same and formed synchronously.
  • the materials of the second connecting structure 15 and the graphic structure 121 are both Cr or Al.
  • the shape of the second connecting structure 15 in the opening structure 122 is linear, and the second connecting structure 15 in the shape of the wire can occupy less than the area of the opening structure 122, thereby effectively ensuring the transmittance of the opening structure 122. .
  • the length d2 of the second connecting structure 15 may be greater than or equal to The width d1 of the opening structure 122.
  • the length of the second connecting structure 15 and the width of the opening structure 122 can be set according to product requirements.
  • the control circuit 2 includes a first power source S1 and a second power source S2 connected in parallel.
  • both the positive electrode of the first power source S1 and the negative electrode of the second power source S2 are combined with the mask 1 Connected, the negative electrode of the first power source S1 is grounded through the first switch K1, and the positive electrode of the second power source S2 is grounded through the second switch K2.
  • the positive electrode of the first power source S1 and the negative electrode of the second power source S2 are both connected to the first connection structure 14.
  • FIG. 3a is a schematic diagram of an operation state of the control circuit of FIG. 1.
  • the first power source S1 is used to pass to the mask 1.
  • a positive voltage is applied to cause the mask 1 to electrostatically adsorb the first substrate 3.
  • the first power source S1 is configured to apply a positive voltage to the mask 1 when the first switch K1 is closed and the second switch K2 is turned off to cause the mask 1 to electrostatically adsorb the first substrate 3.
  • the first power source S1 passes a positive voltage to the pattern structure 121 through the first connection structure 14, so that the entire mask 1 has a positive charge, and the first substrate 3 is negatively charged by electrostatic induction, with a positive charge.
  • the mask 1 and the negatively charged first substrate 3 are attracted to each other, so that the mask 1 can electrostatically adsorb the first substrate 3.
  • the positive voltage applied to the first power source S1 is greater than 0 kV and less than or equal to 2.0 kV.
  • FIG. 3b is a schematic view showing another working state of the control circuit of FIG. 1.
  • the second power source S2 when it is required to release the first substrate 3 fixed on the mask 1, the second power source S2 is used for the mask.
  • the board 1 is supplied with a negative voltage to cause the mask 1 to release the first substrate 3.
  • the second power source S2 is configured to pass a negative voltage to the mask 1 when the second switch K2 is closed and the first switch K1 is turned off to cause the mask 1 to release the first substrate 3.
  • the second power source S2 passes a negative voltage to the pattern structure 121 through the first connection structure 14, so that the entire mask 1 having a positive charge has a negative charge, and the mask 1 and the strip with a negative charge are charged.
  • the negatively charged first substrates 3 repel each other, so that the mask 1 releases the first substrate 3.
  • the negative voltage to which the second power source S2 is applied is greater than or equal to -2.0 kV and less than 0 kV.
  • the mask 1 and the first substrate 3 may be respectively connected to the ground (GND) to completely discharge static electricity, while the first power source S1 and the second power source S2 are both disconnected. Prevent static electricity from occurring and ensure safety.
  • the second power source S2 can be used to apply a negative voltage to the mask 1 to electrostatically adsorb the mask 1 .
  • the first substrate 3 is adsorbed.
  • the first power source S1 can be used to apply a positive voltage to the mask 1 to release the mask 1 to release the first substrate 3, specifically, A power source S1 is used to apply a positive voltage to the mask 1 when the first switch K1 is closed and the second switch K2 is turned off to cause the mask 1 to release the first substrate 3.
  • a power source S1 is used to apply a positive voltage to the mask 1 when the first switch K1 is closed and the second switch K2 is turned off to cause the mask 1 to release the first substrate 3.
  • static electricity is released, thereby preventing static electricity from occurring, ensuring safety.
  • the schematic diagram of the working state of the control circuit is not specifically drawn.
  • the control circuit controls the mask to enable the mask to electrostatically adsorb the first substrate or release the first substrate, without using a mechanical fixed alignment mechanism to fix the first substrate.
  • the electrostatic adsorption method is adopted to enable the mask plate to completely absorb the first substrate, thereby avoiding deformation of the first substrate, avoiding generation of bubbles between the first substrate and the second substrate, improving alignment accuracy, and avoiding pressure.
  • the first substrate slides off the mask during the bonding process.
  • FIG. 4 is a schematic structural diagram of a packaging device according to Embodiment 2 of the present invention.
  • the packaging device is different from the packaging device of the first embodiment in that the control circuit 2 includes a third power supply connected in parallel. S3 and release branch S4.
  • the positive electrode of the third power source S3 and one end of the release branch S4 are both connected to the mask 1.
  • the negative electrode of the third power source S3 is grounded through the third switch K3, and the other end of the release branch S4 is passed through the fourth switch. K4 is grounded.
  • FIG. 5a is a schematic diagram of an operation state of the control circuit of FIG. 4.
  • the third power source S3 is used to pass to the mask 1.
  • a positive voltage is applied to cause the mask 1 to electrostatically adsorb the first substrate 3.
  • the third power source S3 is configured to apply a positive voltage to the mask 1 when the third switch K3 is closed and the fourth switch K4 is turned off to cause the mask 1 to electrostatically adsorb the first substrate 3.
  • the third power source S3 passes a positive voltage to the pattern structure 121 through the first connection structure 14, so that the entire mask 1 has a positive charge, and the first substrate 3 is negatively charged by electrostatic induction, with a positive charge.
  • the mask 1 and the negatively charged first substrate 3 are attracted to each other, so that the mask 1 can electrostatically adsorb the first substrate 3.
  • the positive voltage applied to the third power source S3 is greater than 0 kV and less than or equal to 2.0 kV.
  • FIG. 5b is a schematic diagram of another working state of the control circuit of FIG. 4, as shown in FIG. 5b.
  • the release branch S4 is used to release the positive charge on the mask 1 to release the first substrate 3.
  • the release branch S4 is for releasing the positive charge on the mask 1 when the fourth switch K4 is closed and the third switch K3 is turned off to cause the mask 1 to release the first substrate 3.
  • the release branch S4 releases the positive charge on the mask 1
  • the first substrate 3 is no longer negatively charged, so that the mask 1 and the first substrate 3 are no longer attracted to each other, thereby making the mask The board 1 releases the first substrate 3.
  • the negative electrode of the third power source and one end of the release branch are connected to the mask, the positive electrode of the third power source is grounded through the third switch, and the other end of the release branch is passed through the fourth switch. Ground.
  • the third power source is used to pass a negative voltage to the mask plate to electrostatically adsorb the first substrate, specifically, the third power source is used as the third switch.
  • the fourth switch is turned off and the fourth switch is turned off, a negative voltage is applied to the mask to electrostatically adsorb the first substrate.
  • the release branch is used to release the negative charge on the mask to release the first substrate, specifically, the release branch is used when the fourth switch is closed and The negative charge on the mask is released when the three switches are open.
  • the specific structure and working state diagram of the control circuit in this case are not specifically drawn.
  • the negative voltage to which the third power source S3 is supplied is greater than or equal to -2.0 kV and less than 0 kV.
  • the control circuit controls the mask to enable the mask to electrostatically adsorb the first substrate or release the first substrate, without using a mechanical fixed alignment mechanism to fix the first substrate.
  • the electrostatic adsorption method is adopted to enable the mask plate to completely absorb the first substrate, thereby avoiding deformation of the first substrate, avoiding generation of bubbles between the first substrate and the second substrate, improving alignment accuracy, and avoiding pressure.
  • the first substrate slides off the mask during the bonding process.
  • FIG. 6 is a schematic structural diagram of a packaging device according to Embodiment 3 of the present invention.
  • the packaging device includes: an upper platform 4, a lower platform 5, and a packaging device.
  • the package device may be the package device provided in the first embodiment and the second embodiment, and is not described here again.
  • the mask plate 1 is disposed on the lower platform 5, and the upper platform 4 is used for setting.
  • the packaging apparatus in this embodiment is for packaging the oppositely disposed first substrate 3 and second substrate 6 such that the first substrate 3 and the second substrate 6 form a display screen.
  • the packaging device further includes: an upper and lower mechanism 7 located above the upper platform 4.
  • the upper and lower mechanisms 7 are used to control the upper platform 4 to move up and down.
  • the packaging device further includes: a registration camera 8.
  • the alignment camera 8 is for aligning the first substrate 3 and the second substrate 6.
  • the alignment camera 8 can be a Charge-coupled Device (CCD) camera.
  • CCD Charge-coupled Device
  • the packaging device further includes: a substrate receiving jig 9.
  • the substrate receiving jig 9 is used to feed the first substrate 3 onto the lower stage 5 and the second substrate 6 to the upper stage 4.
  • the packaging device further includes: a positioning mechanism 10.
  • the positioning mechanism 10 is for fixing the position of the mask 1.
  • the packaging device further includes: a UV light source 15 located below the lower platform 5.
  • the UV light source 15 is used to cure the sealant between the first substrate 3 and the second substrate 6 through the mask 1.
  • the substrate receiving jig 9 acquires the second substrate 6 and the second substrate 6 is placed thereon; the substrate receiving jig 9 sends the second substrate 6 onto the upper stage 4, and the upper stage 4 adsorbs the second substrate 6 to fix the second substrate 6 to On the upper platform 4; the substrate receiving jig 9 is lowered, the first substrate 3 is obtained and the first substrate 3 is placed thereon; the substrate receiving jig 9 sends the first substrate 3 to the mask 1; the alignment mechanism (not shown) It is shown that the mask 1 and the first substrate 3 located thereon are aligned in cooperation with the alignment camera 8; after the alignment is completed, the control circuit 2 controls the mask 1 to electrostatically adsorb the mask 1 The first substrate 3, at which time the first substrate 3 is fixed on the mask 1; the vacuuming device (not shown) performs vacuum processing to place the packaging device in a vacuum environment; and the upper and lower mechanisms 7 control the upper platform 4 Lower movement to drive the second substrate 6 to move downward; when the distance between the first substrate 3 and the second substrate 6
  • the vacuum environment is inflated to the first substrate. 3 and the second substrate 6 is pressed together, after pressing for a certain time, the UV light source 15 irradiates the sealant between the first substrate 3 and the second substrate 6 through the mask 1 to realize the sealing of the sealant.
  • the first substrate 3 and the second substrate 6 form a display screen; the upper platform 4 releases the adsorption of the second substrate 6 and moves upward for a small distance, and then the alignment camera 8 confirms the accuracy of the display screen;
  • the circuit 2 controls the mask 1 to cause the mask 1 to release the first substrate 3, thereby realizing the release of the display screen; the display screen is carried out by a handling tool (not shown).
  • FIG. 7a is a schematic diagram of curing the sealant during the packaging process using the packaging device of FIG. 6.
  • a UV light source (not shown) passes through the mask 1 to the first substrate.
  • the frame sealant 16 between the 3 and the second substrate 6 is irradiated.
  • the UV emitted by the UV light source is irradiated onto the sealant 16 through the opening structure 122.
  • the sealant 16 is disposed in a peripheral region around the display region 17, and the sealant 16 has a certain distance from the display region 17.
  • the width of the sealant 16 can be narrow.
  • the width d3 of the sealant 16 can be 0.2 mm to 0.4. Between mm.
  • FIG. 7b is a schematic view of the sealant after forming the display screen by using the package device of FIG. 6, as shown in FIG. 7b, although the first substrate 3 and the second substrate 6 are pressed during the packaging process, so that the frame is sealed.
  • the glue 16 is widened, but since the width of the front sealant 16 is narrow, the width d4 of the sealant 16 after the package can be maintained between 0.8 mm and 1.0 mm.
  • the display screen with the width of the sealant can be manufactured within 1.0 mm, thereby realizing the manufacture of the narrow sealant, and thus the display screen of the narrow bezel can be realized.
  • the alignment accuracy between the first substrate and the second substrate may be within ⁇ 2 ⁇ m, thereby improving the comparison with the prior art. Bit precision.
  • the alignment mechanism only aligns the first substrate 3, and then the first substrate 3 is fixed on the mask 1 by the control circuit 2, and the first substrate 3 is not required to be fixed by the alignment mechanism. Compared with the mechanical fixed alignment mechanism in the prior art, the structure of the alignment mechanism in this embodiment is more Add simple.
  • the first substrate 3 may be an OLED substrate
  • the second substrate 6 may be a package substrate; or the first substrate 3 is a package substrate, and the second substrate 6 is an OLED substrate.
  • the mask can be disposed on the upper platform, and the lower platform is used to set the second substrate. This situation is no longer specifically drawn.
  • the packaging device shown in FIG. 1 preferably, the positive voltage applied to the first power source S1 is greater than 0 kV and less than or equal to 6.0 kV, and the negative voltage applied to the second power source S2 is greater than or equal to -6.0 kV and less than 0 kV.
  • the packaging device shown in FIG. 4 preferably, the positive voltage applied to the third power source S3 is greater than 0 kV and less than or equal to 6.0 kV.
  • the third power source S3 may also be supplied with a negative voltage, and the negative voltage applied is greater than or equal to -6.0 kV and less than 0 kV, which is not specifically illustrated.
  • the control circuit controls the mask to enable the mask to electrostatically adsorb the first substrate or release the first substrate, without using a mechanical fixed alignment mechanism to fix the first substrate.
  • the electrostatic adsorption method is adopted to enable the mask plate to completely absorb the first substrate, thereby avoiding deformation of the first substrate, avoiding generation of bubbles between the first substrate and the second substrate, improving alignment accuracy, and avoiding pressure.
  • the first substrate slides off the mask during the bonding process.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

一种封装装置和封装设备。封装装置可包括掩膜板（1）和与掩膜板电连接的控制电路（2）；控制电路，用于控制掩膜板以使掩膜板静电吸附第一基板（3）或者释放第一基板。无需采用机械固定对位机构对第一基板进行固定，而是通过静电吸附方式使得掩膜板实现对第一基板的完全吸附，从而避免了第一基板变形，避免了第一基板和第二基板（6）之间产生气泡，提高了对位精度，以及避免了压合过程中第一基板从掩膜板滑落。

Description

封装装置和封装设备 技术领域
本发明涉及显示技术领域，特别涉及封装装置和封装设备。
背景技术
有机发光二极管(Organic Light-Emitting Diode，简称：OLED)显示屏幕具有自发光的特性，采用了非常薄的有机材料涂层和玻璃基板，当有电流通过时，这些有机材料就会发光，而且OLED显示屏幕的可视角度大，并且能够显著节省电能。因此，随着显示技术的发展，OLED显示技术的应用越来越广泛。例如作为OLED显示技术的一种重要应用，有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，简称：AMOLED)显示屏幕由于反应速度较快、对比度更高、视角较广等特点而被广泛地采用。
在OLED显示屏幕的制造过程中，需要通过封装设备将制备完成的第一基板和第二基板进行封装，以形成显示屏幕，其中，封装设备为UV(ultra-violet，紫外线)照射一体封装设备。该封装设备可包括上石英平台和下石英平台，上石英平台上可设置第二基板，下石英平台上可设置掩膜板，而第一基板设置于掩膜板上，其中，对第一基板和第二基板进行封装来形成显示屏幕。
现有技术存在如下技术问题：
1)在封装过程中，需要通过机械固定对位机构对第一基板进行对位，并在对位之后保持第一基板固定于掩膜板上，而结构复杂的机械固定对位机构产生的应力容易造成第一基板变形；
2)需要在掩膜板上采用机械固定对位方式对位第一基板，而且，在随后的第一基板和第二基板的压合过程中，机械固定对位机构会干涉上石英平台，这样会造成第一基板和第二基板之间产生气泡以及对位精度低，通常对位精度为±7μm；
3)若在压合过程中机械固定对位机构后退，则机械固定对位机构不会干涉上石英平台，但是机械固定对位机构在后退的过程中 容易造成第一基板从掩膜板上滑落。
发明内容
本发明提供一种封装装置和封装设备，所述封装装置能够避免在封装过程中第一基板变形，避免第一基板和第二基板之间产生气泡，提高对位精度，以及避免压合过程中第一基板从掩膜板上滑落。
为实现上述目的，本发明提供了一种封装装置，所述封装装置包括掩膜板和与所述掩膜板电连接的控制电路，所述控制电路用于控制所述掩膜板以使所述掩膜板静电吸附第一基板或者释放所述第一基板。
可选地，所述掩膜板包括基底、位于所述基底之上的图形层和位于所述图形层之上的绝缘层，所述图形层包括图形结构和位于所述图形结构之间的开口结构，所述图形结构与所述控制电路电连接。
可选地，所述掩膜板还包括位于所述基底侧边的第一连接结构和位于每个所述开口结构中的至少一个第二连接结构，其中，所述第一连接结构用于将所述图形结构与所述控制电路电连接，所述第二连接结构用于将位于开口结构外部的图形结构和位于所述开口结构内部的图形结构电连接。
可选地，所述第二连接结构的长度大于或者等于所述开口结构的宽度。
可选地，通过所述控制电路为所述掩膜板通入正电压以使所述掩膜板吸附所述第一基板，之后通过所述控制电路为所述掩膜板通入负电压或释放所述掩膜板上的正电荷以使所述掩膜板释放所述第一基板；或者，通过所述控制电路为所述掩膜板通入负电压以使所述掩膜板吸附所述第一基板，之后通过所述控制电路为所述掩膜板通入正电压或释放所述掩膜板上的负电荷以使所述掩膜板释放所述第一基板。
可选地，所述控制电路包括并联连接的第一电源和第二电源， 其中，所述第一电源用于向所述掩膜板通入正电压，所述第二电源用于向所述掩膜板通入负电压。
可选地，所述第一电源的正电极和所述第二电源的负电极均与所述掩膜板连接，所述第一电源的负电极通过第一开关接地，所述第二电源的正电极通过第二开关接地，所述第一电源用于当所述第一开关闭合且所述第二开关断开时向所述掩膜板通入正电压，所述第二电源用于当所述第二开关闭合且所述第一开关断开时向所述掩膜板通入负电压。
可选地，所述控制电路包括并联连接的第三电源和释放支路，其中：所述第三电源用于向所述掩膜板通入正电压，所述释放支路用于释放所述掩膜板上的正电荷；或者，所述第三电源用于向所述掩膜板通入负电压，所述释放支路用于释放所述掩膜板上的负电荷。
可选地，在所述第三电源用于向所述掩膜板通入正电压且所述释放支路用于释放所述掩膜板上的正电荷的情况下，所述第三电源的正电极和所述释放支路的一端均与所述掩膜板连接，所述第三电源的负电极通过第三开关接地，所述释放支路的另一端通过第四开关接地，所述第三电源用于当所述第三开关闭合且所述第四开关断开时向所述掩膜板通入正电压，所述释放支路用于当所述第四开关闭合且所述第三开关断开时释放所述掩膜板上的正电荷。
可选地，在所述第三电源用于向所述掩膜板通入负电压且所述释放支路用于释放所述掩膜板上的负电荷的情况下，所述第三电源的负电极和所述释放支路的一端均与所述掩膜板连接，所述第三电源的正电极通过第三开关接地，所述释放支路的另一端通过第四开关接地，所述第三电源用于当所述第三开关闭合且所述第四开关断开时向所述掩膜板通入负电压，所述释放支路用于当所述第四开关闭合且所述第三开关断开时释放所述掩膜板上的负电荷。
为实现上述目的，本发明还提供了一种封装设备，其包括：上平台、下平台和上述封装装置，其中：所述掩膜板设置于所述下平台上，所述上平台用于设置第二基板；或者，所述掩膜板设置于所述上平台上，所述下平台用于设置第二基板。
本发明提供的封装装置和封装设备的技术方案中，通过控制电路控制掩膜板以使掩膜板静电吸附第一基板或者释放第一基板，无需采用机械固定对位机构对第一基板进行固定，而是通过静电吸附方式实现掩膜板对第一基板的完全吸附，从而避免了第一基板变形，避免了第一基板和第二基板之间产生气泡，提高了对位精度，以及避免了压合过程中第一基板从掩膜板上滑落。
附图说明
图1为本发明的实施例一提供的一种封装装置的结构示意图。
图2为图1中的掩膜板的平面示意图。
图3a为图1中的控制电路的一种工作状态示意图。
图3b为图1中的控制电路的另一种工作状态示意图。
图4为本发明的实施例二提供的一种封装装置的结构示意图。
图5a为图4中的控制电路的一种工作状态示意图。
图5b为图4中的控制电路的另一种工作状态示意图。
图6为本发明的实施例三提供的一种封装设备的结构示意图。
图7a为在利用图6中的封装设备的封装过程中固化封框胶的示意图。
图7b为在利用图6中的封装设备封装后封框胶的示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的封装装置和封装设备进行详细描述。
图1为本发明的实施例一提供的一种封装装置的结构示意图，如图1所示，该封装装置包括：掩膜板1和与掩膜板1电连接的控制电路2，控制电路2用于控制掩膜板1以使掩膜板1静电吸附第一基板3或者释放第一基板3。
图2为图1中的掩膜板的平面示意图，结合图1和图2所示，掩膜板1包括：基底11、位于基底11之上的图形层12和位于图形层12之上的绝缘层13。图形层12包括：图形结构121和位于图形 结构121之间的开口结构122，图形结构121与控制电路2电连接。在对封框胶进行UV固化时，图形结构121用于阻挡UV，开口结构122与封框胶相对应地设置，UV通过开口结构122照射到封框胶上以实现对封框胶的固化。优选地，开口结构的形状为环形。优选地，图形结构121的材料为金属，例如，为Cr或者Al。优选地，基底11为石英玻璃。优选地，绝缘层13的材料包括Al2O3、SiO2或者SiON。
掩膜板1还包括：位于基底11侧边的第一连接结构14(如图1所示)和位于每个开口结构122中的至少一个第二连接结构15(如图2所示)。第一连接结构14用于将图形结构121与控制电路2电连接。第二连接结构15用于将位于开口结构122外部的图形结构121和位于开口结构122内部的图形结构121电连接，从而通过第二连接结构15可实现整个基底11之上的所有图形结构121的电连接。每个开口结构122中，第二连接结构15的数量可以为一个或者多个。本实施例中，优选地，每个开口结构122中，第二连接结构15的数量为两个，且两个第二连接结构15对角设置，每个开口结构122中采用两个第二连接结构15既可以保证图形结构121的电连接特性，又能保证整个图形层构图简单。第二连接结构15的材料为金属，优选地，第二连接结构15和图形结构121的材料相同且同步形成，例如，第二连接结构15和图形结构121的材料均为Cr或者Al。优选地，开口结构122中的第二连接结构15的形状为线状，采用线状的第二连接结构15可以较少的占用开口结构122的面积，从而有效保证了开口结构122的透光率。
本实施例中，为保证第二连接结构15能够有效的将位于开口结构122外部的图形结构121和位于开口结构122内部的图形结构121电连接，第二连接结构15的长度d2可大于或者等于开口结构122的宽度d1。在实际应用中，第二连接结构15的长度以及开口结构122的宽度可根据产品需要进行设定。
控制电路2包括：并联连接的第一电源S1和第二电源S2。优选地，第一电源S1的正电极和第二电源S2的负电极均与掩膜板1 连接，第一电源S1的负电极通过第一开关K1接地，第二电源S2的正电极通过第二开关K2接地。具体地，第一电源S1的正电极和第二电源S2的负电极均与第一连接结构14连接。
图3a为图1中的控制电路的一种工作状态示意图，如图3a所示，当需要将第一基板3固定于掩膜板1上时，第一电源S1用于向掩膜板1通入正电压以使掩膜板1静电吸附第一基板3。具体地，第一电源S1用于当第一开关K1闭合且第二开关K2断开时向掩膜板1通入正电压以使掩膜板1静电吸附第一基板3。此时，第一电源S1通过第一连接结构14向图形结构121通入正电压，使得整个掩膜板1带有正电荷，并通过静电感应使得第一基板3带有负电荷，带有正电荷的掩膜板1和带有负电荷的第一基板3相互吸引，从而使得掩膜板1能够静电吸附第一基板3。优选地，第一电源S1通入的正电压大于0kV且小于或等于2.0kV。
图3b为图1中的控制电路的另一种工作状态示意图，如图3b所示，当需要将固定于掩膜板1上的第一基板3释放时，第二电源S2用于向掩膜板1通入负电压以使掩膜板1释放第一基板3。具体地，第二电源S2用于当第二开关K2闭合且第一开关K1断开时向掩膜板1通入负电压以使掩膜板1释放第一基板3。此时，第二电源S2通过第一连接结构14向图形结构121通入负电压，使得原本带有正电荷的整个掩膜板1带有负电荷，带有负电荷的掩膜板1和带有负电荷的第一基板3相互排斥，从而使得掩膜板1释放第一基板3。优选地，第二电源S2通入的负电压大于或等于-2.0kV且小于0kV。在掩膜板1和第一基板3分开时，通常静电已被释放。为防止残留静电的影响，在将第一电源S1和第二电源S2均断开的前提下，可将掩膜板1和第一基板3分别连接到地线(GND)以彻底释放静电，从而防止静电发生，保证了安全性。
在实际应用中，可选地，当需要将第一基板3固定于掩膜板1上时，第二电源S2可以用于向掩膜板1通入负电压以使掩膜板1静电吸附第一基板3，具体地，第二电源S2用于当第二开关K2闭合且第一开关K1断开时向掩膜板1通入负电压以使掩膜板1静电 吸附第一基板3。当需要将固定于掩膜板1上的第一基板3释放时，第一电源S1可以用于向掩膜板1通入正电压以使掩膜板1释放第一基板3，具体地，第一电源S1用于当第一开关K1闭合且第二开关K2断开时向掩膜板1通入正电压以使掩膜板1释放第一基板3。在掩膜板1和第一基板3分开时，释放静电，从而防止静电发生，保证了安全性。此种情况下控制电路的工作状态示意图不再具体画出。
本实施例提供的封装装置的技术方案中，控制电路通过控制掩膜板以使掩膜板静电吸附第一基板或者释放第一基板，无需采用机械固定对位机构对第一基板进行固定，而是通过静电吸附方式使得掩膜板实现对第一基板的完全吸附，从而避免了第一基板变形，避免了第一基板和第二基板之间产生气泡，提高了对位精度，以及避免了压合过程中第一基板从掩膜板上滑落。
图4为本发明的实施例二提供的一种封装装置的结构示意图，如图4所示，该封装装置与上述实施例一的封装装置的区别在于：控制电路2包括并联连接的第三电源S3和释放支路S4。优选地，第三电源S3的正电极和释放支路S4的一端均与掩膜板1连接，第三电源S3的负电极通过第三开关K3接地，释放支路S4的另一端通过第四开关K4接地。
图5a为图4中的控制电路的一种工作状态示意图，如图5a所示，当需要将第一基板3固定于掩膜板1上时，第三电源S3用于向掩膜板1通入正电压以使掩膜板1静电吸附第一基板3。具体地，第三电源S3用于当第三开关K3闭合且第四开关K4断开时向掩膜板1通入正电压以使掩膜板1静电吸附第一基板3。此时，第三电源S3通过第一连接结构14向图形结构121通入正电压，使得整个掩膜板1带有正电荷，并通过静电感应使得第一基板3带有负电荷，带有正电荷的掩膜板1和带有负电荷的第一基板3相互吸引，从而使得掩膜板1能够静电吸附第一基板3。优选地，第三电源S3通入的正电压大于0kV且小于或等于2.0kV。
图5b为图4中的控制电路的另一种工作状态示意图，如图5b 所示，当需要将固定于掩膜板1上的第一基板3释放时，释放支路S4用于释放掩膜板1上的正电荷以释放第一基板3。具体地，释放支路S4用于当第四开关K4闭合且第三开关K3断开时释放掩膜板1上的正电荷以使掩膜板1释放第一基板3。此时，由于释放支路S4释放了掩膜板1上的正电荷，因此第一基板3不再带有负电荷，使得掩膜板1和第一基板3不再相互吸引，从而使得掩膜板1释放第一基板3。
在实际应用中，可选地，第三电源的负电极和释放支路的一端均与掩膜板连接，第三电源的正电极通过第三开关接地，释放支路的另一端通过第四开关接地。当需要将第一基板固定于掩膜板上时，第三电源用于向掩膜板通入负电压以使掩膜板静电吸附第一基板，具体地，第三电源用于当第三开关闭合且第四开关断开时向掩膜板通入负电压以使掩膜板静电吸附第一基板。当需要将固定于掩膜板上的第一基板释放时，释放支路用于释放掩膜板上的负电荷以释放第一基板，具体地，释放支路用于当第四开关闭合且第三开关断开时释放掩膜板上的负电荷。此种情况下控制电路的具体结构和工作状态示意图均不再具体画出。优选地，第三电源S3通入的负电压大于或等于-2.0kV且小于0kV。
本实施例中，对封装装置中的其余结构的具体描述可参见上述实施例一，此处不再重复描述。
本实施例提供的封装装置的技术方案中，控制电路通过控制掩膜板以使掩膜板静电吸附第一基板或者释放第一基板，无需采用机械固定对位机构对第一基板进行固定，而是通过静电吸附方式使得掩膜板实现对第一基板的完全吸附，从而避免了第一基板变形，避免了第一基板和第二基板之间产生气泡，提高了对位精度，以及避免了压合过程中第一基板从掩膜板上滑落。
图6为本发明的实施例三提供的一种封装设备的结构示意图，如图6所示，该封装设备包括：上平台4、下平台5和封装装置。封装装置可采用上述实施例一和实施例二提供的封装装置，此处不再赘述，其中，掩膜板1设置于下平台5上，则上平台4用于设置 第二基板6。
本实施例中的封装设备用于对相对设置的第一基板3和第二基板6进行封装以使第一基板3和第二基板6形成显示屏幕。
进一步地，该封装设备还包括：位于上平台4之上的上下机构7。该上下机构7用于控制上平台4进行上下运动。
进一步地，该封装设备还包括：对位相机8。该对位相机8用于对第一基板3和第二基板6进行对位。例如，该对位相机8可以为电荷耦合元件(Charge-coupled Device，简称：CCD)相机。
进一步地，该封装设备还包括：基板接受夹具9。该基板接受夹具9用于将第一基板3送至下平台5上以及将第二基板6送至上平台4上。
进一步地，该封装设备还包括：定位机构10。该定位机构10用于对掩膜板1的位置进行固定。
进一步地，该封装设备还包括：位于下平台5之下的UV光源15。UV光源15用于通过掩膜板1对位于第一基板3和第二基板6之间的封框胶进行固化。
下面通过一个具体的例子对利用本实施例提供的封装设备的封装过程进行详细描述。
基板接受夹具9获取第二基板6并使第二基板6位于其上；基板接受夹具9将第二基板6送至上平台4上，上平台4吸附第二基板6以使第二基板6固定于上平台4上；基板接受夹具9下降，获取第一基板3并使第一基板3位于其上；基板接受夹具9将第一基板3送至掩膜板1上；对位机构(图中未示出)在对位相机8的配合下对掩膜板1和位于其上的第一基板3进行对位；完成对位后，控制电路2控制掩膜板1以使掩膜板1静电吸附第一基板3，此时第一基板3固定于掩膜板1上；抽真空装置(图中未示出)进行抽真空处理，使封装设备处于真空环境中；上下机构7控制上平台4向下运动以带动第二基板6向下运动；当第一基板3与第二基板6之间的距离小于一定距离，例如，当第一基板3与第二基板6之间的距离为2mm时，采用对位相机8对第一基板3和第二基板6进行 对位；上下机构7继续控制上平台4向下运动以带动第二基板6向下运动，当第一基板3和第二基板6接近到接合状态时，对真空环境进行充气以对第一基板3和第二基板6进行压合，压合一定时间后UV光源15通过掩膜板1对位于第一基板3和第二基板6之间的封框胶进行照射，以实现对封框胶进行固化，照射结束后第一基板3和第二基板6形成显示屏幕；上平台4解除对第二基板6的吸附，并向上移动一小段距离，然后由对位相机8确认显示屏幕的精度；控制电路2控制掩膜板1以使掩膜板1释放第一基板3，从而实现释放显示屏幕；通过搬运工具(图中未示出)将显示屏幕搬出。
图7a为在利用图6中的封装设备的封装过程中固化封框胶的示意图，如图7a所示，封装过程中，UV光源(图中未画出)通过掩膜板1对第一基板3和第二基板6进行之间的封框胶16进行照射，具体地，UV光源发出的UV通过开口结构122照射到封框胶16上。封框胶16设置于显示区域17周围的周边区域中，且封框胶16与显示区域17之间具有一定的距离。在封装过程中，由于第一基板3和第二基板6的对位精度均较高，因此，封框胶16的宽度可以较窄，例如，封框胶16的宽度d3可以为0.2mm至0.4mm之间。
图7b为在利用图6中的封装设备封装形成显示屏幕后封框胶的示意图，如图7b所示，虽然在封装过程中对第一基板3和第二基板6进行压合会使得封框胶16变宽，但由于封装前封框胶16的宽度很窄，因此封装后封框胶16的宽度d4可以保持在0.8mm至1.0mm之间。采用本实施例的封装设备可制造出封框胶的宽度为1.0mm以内的显示屏幕，从而实现了制造出窄封框胶，进而可实现窄边框的显示屏幕。
采用本实施例提供的封装设备对第一基板和第二基板进行封装后，第一基板和第二基板之间的对位精度可以为±2μm以内，从而与现有技术相比，提高了对位精度。本实施例中，对位机构仅对第一基板3进行对位，而后由控制电路2实现将第一基板3固定于掩膜板1上，无需对位机构对第一基板3进行固定，因此与现有技术中的机械固定对位机构相比，本实施例中的对位机构的结构更 加简单。
本实施例中，第一基板3可以为OLED基板，第二基板6可以为封装基板；或者，第一基板3为封装基板，第二基板6为OLED基板。
在实际应用中，可选地，掩膜板可设置于上平台上，则下平台用于设置第二基板。此种情况不再具体画出。若采用图1中所示的封装装置，优选地，第一电源S1通入的正电压大于0kV且小于或等于6.0kV，第二电源S2通入的负电压大于或等于-6.0kV且小于0kV。若采用图4中所示的封装装置，优选地，第三电源S3通入的正电压大于0kV且小于或等于6.0kV。或者，第三电源S3还可以通入负电压，通入的负电压大于或等于-6.0kV且小于0kV，此种情况未具体画出。
本实施例提供的封装设备的技术方案中，控制电路通过控制掩膜板以使掩膜板静电吸附第一基板或者释放第一基板，无需采用机械固定对位机构对第一基板进行固定，而是通过静电吸附方式使得掩膜板实现对第一基板的完全吸附，从而避免了第一基板变形，避免了第一基板和第二基板之间产生气泡，提高了对位精度，以及避免了压合过程中第一基板从掩膜板上滑落。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (11)

  1. 一种封装装置，其特征在于，所述封装装置包括掩膜板和与所述掩膜板电连接的控制电路，
    所述控制电路用于控制所述掩膜板以使所述掩膜板静电吸附第一基板或者释放所述第一基板。
  2. 根据权利要求1所述的封装装置，其特征在于，所述掩膜板包括基底、位于所述基底之上的图形层和位于所述图形层之上的绝缘层，所述图形层包括图形结构和位于所述图形结构之间的开口结构，所述图形结构与所述控制电路电连接。
  3. 根据权利要求2所述的封装装置，其特征在于，所述掩膜板还包括位于所述基底侧边的第一连接结构和位于每个所述开口结构中的至少一个第二连接结构，其中，
    所述第一连接结构用于将所述图形结构与所述控制电路电连接，
    所述第二连接结构用于将位于开口结构外部的图形结构和位于所述开口结构内部的图形结构电连接。
  4. 根据权利要求3所述的封装装置，其特征在于，所述第二连接结构的长度大于或者等于所述开口结构的宽度。
  5. 根据权利要求1所述的封装装置，其特征在于，
    通过所述控制电路为所述掩膜板通入正电压以使所述掩膜板吸附所述第一基板，之后通过所述控制电路为所述掩膜板通入负电压或释放所述掩膜板上的正电荷以使所述掩膜板释放所述第一基板；或者
    通过所述控制电路为所述掩膜板通入负电压以使所述掩膜板 吸附所述第一基板，之后通过所述控制电路为所述掩膜板通入正电压或释放所述掩膜板上的负电荷以使所述掩膜板释放所述第一基板。
  6. 根据权利要求5所述的封装装置，其特征在于，所述控制电路包括并联连接的第一电源和第二电源，其中，所述第一电源用于向所述掩膜板通入正电压，所述第二电源用于向所述掩膜板通入负电压。
  7. 根据权利要求6所述的封装装置，其特征在于，所述第一电源的正电极和所述第二电源的负电极均与所述掩膜板连接，所述第一电源的负电极通过第一开关接地，所述第二电源的正电极通过第二开关接地，
    所述第一电源用于当所述第一开关闭合且所述第二开关断开时向所述掩膜板通入正电压，所述第二电源用于当所述第二开关闭合且所述第一开关断开时向所述掩膜板通入负电压。
  8. 根据权利要求5所述的封装装置，其特征在于，所述控制电路包括并联连接的第三电源和释放支路，其中：
    所述第三电源用于向所述掩膜板通入正电压，所述释放支路用于释放所述掩膜板上的正电荷；或者
    所述第三电源用于向所述掩膜板通入负电压，所述释放支路用于释放所述掩膜板上的负电荷。
  9. 根据权利要求8所述的封装装置，其特征在于，在所述第三电源用于向所述掩膜板通入正电压且所述释放支路用于释放所述掩膜板上的正电荷的情况下，所述第三电源的正电极和所述释放支路的一端均与所述掩膜板连接，所述第三电源的负电极通过第三开关接地，所述释放支路的另一端通过第四开关接地，所述第三电源用于当所述第三开关闭合且所述第四开关断开时向所述掩膜板 通入正电压，所述释放支路用于当所述第四开关闭合且所述第三开关断开时释放所述掩膜板上的正电荷。
  10. 根据权利要求8所述的封装装置，其特征在于，在所述第三电源用于向所述掩膜板通入负电压且所述释放支路用于释放所述掩膜板上的负电荷的情况下，所述第三电源的负电极和所述释放支路的一端均与所述掩膜板连接，所述第三电源的正电极通过第三开关接地，所述释放支路的另一端通过第四开关接地，所述第三电源用于当所述第三开关闭合且所述第四开关断开时向所述掩膜板通入负电压，所述释放支路用于当所述第四开关闭合且所述第三开关断开时释放所述掩膜板上的负电荷。
  11. 一种封装设备，其特征在于，包括：上平台、下平台和权利要求1至10中任一项所述的封装装置，其中：
    所述掩膜板设置于所述下平台上，所述上平台用于设置第二基板；或者
    所述掩膜板设置于所述上平台上，所述下平台用于设置第二基板。
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