WO2015176893A1 - Kommutierungszelle - Google Patents
Kommutierungszelle Download PDFInfo
- Publication number
- WO2015176893A1 WO2015176893A1 PCT/EP2015/058559 EP2015058559W WO2015176893A1 WO 2015176893 A1 WO2015176893 A1 WO 2015176893A1 EP 2015058559 W EP2015058559 W EP 2015058559W WO 2015176893 A1 WO2015176893 A1 WO 2015176893A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- commutation cell
- semiconductor switch
- controllable semiconductor
- circuit carrier
- circuit
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Inverter Devices (AREA)
- Power Conversion In General (AREA)
- Combinations Of Printed Boards (AREA)
- Electronic Switches (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP15718847.5A EP3146563A1 (de) | 2014-05-21 | 2015-04-21 | Kommutierungszelle |
JP2016568889A JP6486390B2 (ja) | 2014-05-21 | 2015-04-21 | コミュテーションセル |
US15/308,287 US9871025B2 (en) | 2014-05-21 | 2015-04-21 | Commutation cell |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102014209690.1 | 2014-05-21 | ||
DE102014209690.1A DE102014209690B4 (de) | 2014-05-21 | 2014-05-21 | Kommutierungszelle |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015176893A1 true WO2015176893A1 (de) | 2015-11-26 |
Family
ID=53008477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2015/058559 WO2015176893A1 (de) | 2014-05-21 | 2015-04-21 | Kommutierungszelle |
Country Status (5)
Country | Link |
---|---|
US (1) | US9871025B2 (de) |
EP (1) | EP3146563A1 (de) |
JP (1) | JP6486390B2 (de) |
DE (1) | DE102014209690B4 (de) |
WO (1) | WO2015176893A1 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102018212436A1 (de) | 2018-07-25 | 2020-01-30 | Infineon Technologies Ag | Halbleitergehäuse mit symmetrisch angeordneten leisungsanschlüssen und verfahren zu dessen herstellung |
DE102018212443A1 (de) * | 2018-07-25 | 2020-01-30 | Infineon Technologies Ag | Halbleitergehäuse mit passivem elektrischem Bauteil und Verfahren zu dessen Herstellung |
DE102018212438A1 (de) | 2018-07-25 | 2020-01-30 | Infineon Technologies Ag | Halbleitergehäuse mit elektromagnetischer abschirmstruktur und verfahren zu dessen herstellung |
DE102018126972A1 (de) | 2018-07-25 | 2020-01-30 | Infineon Technologies Ag | Halbleitergehäuse mit überlappenden elektrisch leitfähigen bereichen und verfahren zu dessen herstellung |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005303018A (ja) * | 2004-04-13 | 2005-10-27 | Fuji Electric Holdings Co Ltd | 半導体装置 |
JP2006134990A (ja) * | 2004-11-04 | 2006-05-25 | Fuji Electric Holdings Co Ltd | 半導体装置 |
US20070090814A1 (en) * | 2005-10-24 | 2007-04-26 | Takayuki Hashimoto | Semiconductor device and power supply device using the same |
WO2013167321A1 (de) * | 2012-05-08 | 2013-11-14 | Robert Bosch Gmbh | Zweistufiges verfahren zum fügen eines halbleiters auf ein substrat mit verbindungsmaterial auf silberbasis |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4239580B2 (ja) * | 2002-12-13 | 2009-03-18 | 株式会社デンソー | 半導体装置 |
JP4552810B2 (ja) * | 2005-09-06 | 2010-09-29 | 株式会社デンソー | 半導体装置 |
JP5253430B2 (ja) * | 2009-03-23 | 2013-07-31 | 株式会社豊田中央研究所 | パワーモジュール |
JP2010251665A (ja) * | 2009-04-20 | 2010-11-04 | Nippon Soken Inc | 電力変換用半導体装置 |
FR2981200B1 (fr) * | 2011-10-10 | 2017-01-13 | Centre Nat De La Rech Scient (Cnrs) | Cellule monolithique de circuit integre et notamment cellule de commutation monolithique |
JP2013153010A (ja) * | 2012-01-24 | 2013-08-08 | Denso Corp | 半導体モジュール及び半導体装置 |
US10587257B2 (en) * | 2013-04-04 | 2020-03-10 | Tm4 Inc. | Commutation cell and compensation circuit therefor |
DE202013104510U1 (de) * | 2013-10-04 | 2013-11-14 | Abb Technology Ag | Halbleiterstapel für Umrichter mit Snubber-Kondensatoren |
US9774244B2 (en) * | 2013-11-01 | 2017-09-26 | Tm4 Inc. | Power converter configured for limiting switching overvoltage |
WO2015070347A1 (en) * | 2013-11-14 | 2015-05-21 | Tm4 Inc. | Commutation cell, power converter and compensation circuit having dynamically controlled voltage gains |
KR20160086344A (ko) * | 2013-11-14 | 2016-07-19 | 티엠4 인코포레이티드 | 전력 전자 스위치의 턴-온 및 턴-오프를 제어하는 보상 회로, 커뮤테이션 셀 및 전력 변환기 |
-
2014
- 2014-05-21 DE DE102014209690.1A patent/DE102014209690B4/de active Active
-
2015
- 2015-04-21 JP JP2016568889A patent/JP6486390B2/ja active Active
- 2015-04-21 WO PCT/EP2015/058559 patent/WO2015176893A1/de active Application Filing
- 2015-04-21 EP EP15718847.5A patent/EP3146563A1/de not_active Withdrawn
- 2015-04-21 US US15/308,287 patent/US9871025B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005303018A (ja) * | 2004-04-13 | 2005-10-27 | Fuji Electric Holdings Co Ltd | 半導体装置 |
JP2006134990A (ja) * | 2004-11-04 | 2006-05-25 | Fuji Electric Holdings Co Ltd | 半導体装置 |
US20070090814A1 (en) * | 2005-10-24 | 2007-04-26 | Takayuki Hashimoto | Semiconductor device and power supply device using the same |
WO2013167321A1 (de) * | 2012-05-08 | 2013-11-14 | Robert Bosch Gmbh | Zweistufiges verfahren zum fügen eines halbleiters auf ein substrat mit verbindungsmaterial auf silberbasis |
Also Published As
Publication number | Publication date |
---|---|
EP3146563A1 (de) | 2017-03-29 |
DE102014209690B4 (de) | 2020-02-20 |
US9871025B2 (en) | 2018-01-16 |
US20170069608A1 (en) | 2017-03-09 |
JP6486390B2 (ja) | 2019-03-20 |
JP2017523596A (ja) | 2017-08-17 |
DE102014209690A1 (de) | 2015-11-26 |
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