WO2015173995A1 - Soi基板の評価方法 - Google Patents
Soi基板の評価方法 Download PDFInfo
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- WO2015173995A1 WO2015173995A1 PCT/JP2015/000943 JP2015000943W WO2015173995A1 WO 2015173995 A1 WO2015173995 A1 WO 2015173995A1 JP 2015000943 W JP2015000943 W JP 2015000943W WO 2015173995 A1 WO2015173995 A1 WO 2015173995A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000005259 measurement Methods 0.000 claims abstract description 23
- 238000011156 evaluation Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 3
- 229910052753 mercury Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- WQGWDDDVZFFDIG-UHFFFAOYSA-N pyrogallol Chemical compound OC1=CC=CC(O)=C1O WQGWDDDVZFFDIG-UHFFFAOYSA-N 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Definitions
- the present invention relates to an SOI (Silicon On Insulator) substrate manufactured by bonding a silicon single crystal wafer, and more particularly to evaluation of an SOI substrate used for manufacturing a device for high frequency.
- SOI Silicon On Insulator
- RF Radio Frequency
- the crosstalk is an undesired propagation of an electric signal between devices, for example, an electric signal is propagated through a capacitor between device wirings or a wafer.
- the wafer resistivity of the device forming portion cannot be extremely increased.
- an intermediate layer such as a polysilicon layer or a nitride oxide is introduced at the interface between the BOX layer and the base wafer, so that an inversion layer is not formed, and good high frequency characteristics are obtained.
- a technique capable of obtaining an SOI wafer is known (for example, Patent Documents 1 and 2 and Non-Patent Document 1).
- Patent Document 3 a method of preventing deterioration of high frequency characteristics by using a silicon wafer having a plane orientation different from that of the silicon wafer to be an SOI layer as a base wafer has been introduced (for example, Patent Document 3).
- the technology as described above is essential for obtaining good high frequency characteristics.
- the substrate resistance can be spread and measured by resistance measurement or other methods, but there is no method for directly measuring and evaluating the characteristics of the trap layer (functional layer) immediately below the BOX layer. For this reason, there is a problem that there is only a method for evaluating high frequency characteristics by measuring leakage power after manufacturing an actual device.
- the present invention has been made in view of the above-described problems.
- a method for evaluating high frequency characteristics when a high frequency is applied to an SOI substrate to be evaluated A device is formed in advance on an SOI substrate for measurement, the relationship between the interface state density of the SOI substrate for measurement and leakage power at the time of applying a high frequency, or the interface state density is converted into resistance, and the converted resistance And a process of obtaining a relationship between the leakage power and Measuring an interface state density of the SOI substrate to be evaluated to obtain an interface state density, or obtaining a resistance converted based on the interface state density; From the measured interface state density of the evaluation target SOI substrate, the leakage power of the evaluation target SOI substrate is evaluated or measured based on the relationship between the interface state density and the leakage power determined in advance. A step of evaluating leakage power of the evaluation target SOI substrate based on the relationship between the resistance and leakage power obtained in advance from the resistance converted from the interface state density of the evaluation target SOI substrate.
- a characteristic SOI substrate evaluation method is
- the SOI substrate is suitable for a high-frequency device without producing an actual device.
- First embodiment In the first embodiment, first, using a measurement SOI substrate, a step of obtaining in advance a relationship between the interface state density and the leakage power when applying a high frequency is performed.
- As an SOI substrate for measurement the generation of carriers is suppressed at the interface between the SOI layer 1 as shown in FIG. 1, the BOX layer 2 that is a silicon oxide film, the base wafer 4, and the BOX layer 2 and the base wafer 4.
- the same SOI substrate 5 for evaluation having the trap layer 3 to be prepared is prepared.
- the interface state density of the measurement SOI substrate 5 is measured to obtain the interface state density.
- the interface state density can be measured by a pseudo MOSFET method using a mercury electrode described in Non-Patent Documents 2 and 3.
- the interface state density can be measured by the CV method described in Non-Patent Document 2 after removing the SOI layer with an alkaline solution.
- a device is formed on a measurement SOI substrate, a high frequency is applied, and leakage power at that time is measured. Using the interface state density of the SOI substrate 5 and the leakage power when applying a high frequency, measured in this way, the correlation between the two is obtained in advance.
- an SOI substrate to be evaluated is prepared.
- the SOI substrate to be evaluated is also an SOI substrate 5 having an SOI layer 1, a BOX layer 2, a trap layer 3 and a base wafer 4 as shown in FIG.
- the interface state density of the SOI substrate 5 to be evaluated is measured to obtain the interface state density.
- the interface state density can be measured by the pseudo MOSFET method using a mercury electrode or the CV method as described above.
- a step of evaluating leakage power of the evaluation target SOI substrate is performed.
- the evaluation SOI is calculated from the measured interface state density of the evaluation SOI substrate based on the relationship obtained in advance with respect to the relationship between the interface state density of the measurement SOI substrate and the leakage power.
- the leakage power of the substrate can be predicted and evaluated.
- the step of first obtaining the relationship between the resistance and leakage power converted based on the measurement result of the interface state density of the SOI substrate for measurement is performed in advance.
- the interface state density can be converted to resistance by the following method. From the relationship of Equation 1, the SSL (Subthreshold Slope) value can be obtained from the interface state density.
- SSL is defined as a change in voltage (V g ) when the current (I d ) increases by an order of magnitude as shown in FIG.
- C OX represents the BOX layer capacitance
- C Si represents the SOI layer capacitance.
- This SSL is defined as a resistance RD (corresponding to V / I of the resistance component of Formula 2) obtained from the interface state density, and is converted into a normal resistance from this resistance RD.
- the conversion factor at this time can be obtained from the result of the high frequency measurement (Equations 2 and 3).
- ⁇ represents resistivity
- R SP represents spreading resistance.
- a device is formed on a measurement SOI substrate, a high frequency is applied, and leakage power at that time is measured.
- the correlation between the two is obtained in advance by using the resistance converted based on the measurement result of the interface state density and the leakage power at the time of applying the high frequency obtained by the measurement.
- the step of evaluating the leakage power of the evaluation target SOI substrate is performed based on the relationship between the resistance and the leakage power obtained in advance. At this time, the interface state density of the SOI substrate to be evaluated is measured, and the obtained interface state density is converted into resistance in the same manner as described above.
- the leakage of the SOI substrate to be evaluated is determined based on the relationship between the resistance of the SOI substrate for measurement and the leakage power obtained in advance from the resistance converted from the interface state density of the evaluation SOI substrate. Electric power can be predicted and evaluated.
- the leakage power of the SOI substrate can be evaluated without actually manufacturing a device on the evaluation SOI substrate.
- the interface state density is converted into resistance, it is possible to indicate the substrate characteristics by one standard of resistance.
- a silicon single crystal wafer having a diameter of 200 mm doped with boron having a resistivity of 1000 ⁇ ⁇ cm was used as a base wafer, and a polycrystalline layer was grown to 3 ⁇ m on this base wafer using trichlorosilane as a source gas at 1150 ° C. for a growth time of 3 minutes. . Thereafter, a polycrystalline layer was grown to 0.5 ⁇ m using monosilane as a raw material at 570 ° C. and a growth time of 90 minutes to form a trap layer.
- a silicon wafer having a diameter of 200 mm doped with boron having a resistivity of 1000 ⁇ ⁇ cm is bonded to a bond wafer having a BOX layer formed by forming a 1000 nm oxide film in a Pyro atmosphere at 1150 ° C. for 6 hours. Bonding heat treatment was performed. Thereafter, the SOI layer was made 160 nm by thinning by polishing, and an SOI substrate was manufactured. In the same manner, a plurality of SOI substrates were manufactured.
- the interface state density of a plurality of SOI substrates with different interface state densities was measured by a pseudo MOSFET method using mercury electrodes described in Non-Patent Documents 2 and 3.
- the SOI layer of the SOI substrate was removed by alkaline etching, and then Al was vapor deposited to a thickness of 2 ⁇ m. Further, photolithography was performed to form CPW (Coplanar Waveguides).
- CPW Coplanar Waveguides
- the high frequency was applied to the SOI substrate for a measurement which formed the device, and the leakage power between Al electrodes with respect to input power was measured.
- the frequency of the applied high frequency was measured in the range of 1 ⁇ 10 8 to 1 ⁇ 10 11 Hz. From the data on the frequency dependence of leakage power, 1 GHz (1 ⁇ 10 9 Hz), which is considered to reflect the difference in the board as a representative value of leakage power, was adopted, and the relationship of FIG. 3 was obtained.
- the SOI layer capacitance Csi having a thickness of 160 nm is 6.53 ⁇ 10 ⁇ 8 F
- the BOX layer capacitance Cox having a thickness of 1000 nm is 7.195 ⁇ 10 ⁇ 8 F.
- the coefficient when converting SSL into resistance was set to 10,000 in this case, and SSL was converted into resistance.
- the converted resistance was determined based on the interface state density between the BOX layer and the base wafer measured when 1 GHz was applied. Then, the relationship between the converted resistance and leakage power was obtained and shown in FIG.
- the interface state density of the SOI substrate to be evaluated was measured by a pseudo MOSFET method. Based on the measured interface state density, the leakage current when a high frequency is applied to the SOI substrate to be evaluated can be evaluated based on the relationship between the interface state density of FIG. did it.
- the converted resistance was obtained in the same manner as described above. From the converted resistance, it was possible to evaluate the leakage current when a high frequency was applied to the SOI substrate to be evaluated based on the relationship between the resistance of FIG. 4 and the leakage power obtained in advance.
- the leakage power due to the difference in the presence or absence of the trap layer as shown in FIG. Without forming a device, the difference was predicted from the interface state density of the evaluation SOI substrate or the resistance converted from the interface state density, and the evaluation could be performed accurately. As a result, accurate evaluation can be performed in a simple way.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.
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Abstract
Description
このような技術として、例えば、BOX層とベースウェーハの界面にポリシリコン層や窒化酸化物のような中間層(トラップ層)を導入して、反転層が形成されないようにして、良好な高周波特性のSOIウェーハを得ることができる技術が知られている(例えば特許文献1,2、非特許文献1)。
予め測定用のSOI基板にデバイスを形成し、該測定用のSOI基板の界面準位密度と高周波印加時の漏れ電力との関係、または前記界面準位密度を抵抗に換算し、該換算した抵抗と前記漏れ電力との関係を求めておく工程と、
前記評価対象のSOI基板の界面準位密度を測定して界面準位密度を求める、または該界面準位密度に基づき換算される抵抗を求める工程と、
前記測定した前記評価対象のSOI基板の前記界面準位密度から、前記予め求めた界面準位密度と漏れ電力の関係に基づき、前記評価対象のSOI基板の漏れ電力を評価する、または前記測定した前記評価対象のSOI基板の前記界面準位密度より換算される抵抗から、前記予め求めた抵抗と漏れ電力の関係に基づき、前記評価対象のSOI基板の漏れ電力を評価する工程とを有することを特徴とするSOI基板の評価方法を提供する。
第1の実施態様では、最初に測定用のSOI基板を用いて、界面準位密度と高周波印加時の漏れ電力との関係を予め求めておく工程を行う。
測定用のSOI基板としては、図1に示すようなSOI層1と、シリコン酸化膜であるBOX層2と、ベースウェーハ4と、BOX層2とベースウェーハ4との界面でキャリアの発生を抑制するトラップ層3とを有する評価用のSOI基板5と同じものを用意する。
このようにして測定された、SOI基板5の界面準位密度と、高周波印加時の漏れ電力とを用いて、両者の間の相関関係を予め求めておく。
まず、評価対象となるSOI基板を用意する。評価対象となるSOI基板も図1に示すようなSOI層1と、BOX層2と、トラップ層3、及び、ベースウェーハ4とを有するSOI基板5である。この評価対象SOI基板5の界面準位密度を測定し、界面準位密度を求める。なお、界面準位密度の測定には、前述したように水銀電極を使用した疑似MOSFET法、あるいはCV法によって測定することができる。
前述したように、測定用のSOI基板の界面準位密度と漏れ電力との関係を予め求めておいた関係に基づいて、測定した評価用のSOI基板の界面準位密度から、評価用のSOI基板の漏れ電力を予想して評価することができる。
このように、本発明によれば、評価用のSOI基板に実際にデバイスを作製することなく、SOI基板の漏れ電力すなわち、高周波特性を評価をすることができる。
第2の実施態様では、最初に測定用のSOI基板の界面準位密度の測定結果に基づいて換算した抵抗と漏れ電力との関係を求めておく工程を予め行う。
界面準位密度を抵抗に換算するには、以下のような方法で行うことができる。
数式1の関係から、界面準位密度からSSL(Subthreshold Slope)の値を求めることができる。このとき、SSLは図5に示すような電流(Id)が一桁増加する際の電圧(Vg)の変化と定義されている。なお、COXはBOX層容量、CSiはSOI層容量を示す。
このSSLを界面準位密度から求めた抵抗RD(数式2の抵抗成分のV/Iに相当)として定義し、この抵抗RDから、通常の抵抗に換算する。このときの換算係数は、高周波測定の結果から求めておくことができる(数式2、3)。なお、ρは抵抗率、RSPは広がり抵抗を示す。
このようにして界面準位密度の測定結果に基づいて換算した抵抗と、測定により求められた高周波印加時の漏れ電力とを用いて、両者の間の相関関係を予め求めておく。
この際、評価対象のSOI基板の界面準位密度を測定して、得られた界面準位密度から、前述したのと同様にして、抵抗に換算する。
抵抗率1000Ω・cmのボロンをドープした直径200mmのシリコン単結晶ウェーハをベースウェーハとして、このベースウェーハに対してトリクロロシランを原料ガスとして1150℃、成長時間3分間で多結晶層を3μm成長させた。この後、モノシランを原料として570℃、成長時間90分で多結晶層を0.5μm成長させ、トラップ層とした。
これらのSOI基板について、450℃、1%水素添加の窒素雰囲気でアニール時間を5分から30分の間で変化させて、BOX層とベースウェーハの界面準位密度を変化させた、複数のSOI基板を作製した。
漏れ電力を測定するデバイスは、測定用のSOI基板に150μm×50μmのAl電極を電極間の間隔が100μmとなるように形成したものとした。
このときに、厚さ160nmのSOI層容量Csiは6.53×10-8F、厚さ1000nmのBOX層容量Coxは7.195×10-8Fとなる。数1から、界面準位密度が1×1012cm-2eV-1のときSSLは、0.15、界面準位密度が1×1011cm-2eV-1のときは、SSLは0.015、界面準位密度が1×1010cm-2eV-1のときはSSLは0.0015と求められた。
Claims (1)
- 評価対象のSOI基板に高周波を印加したときの高周波特性を評価する方法であって、
予め測定用のSOI基板にデバイスを形成し、該測定用のSOI基板の界面準位密度と高周波印加時の漏れ電力との関係、または前記界面準位密度を抵抗に換算し、該換算した抵抗と前記漏れ電力との関係を求めておく工程と、
前記評価対象のSOI基板の界面準位密度を測定して界面準位密度を求める、または該界面準位密度に基づき換算される抵抗を求める工程と、
前記測定した前記評価対象のSOI基板の前記界面準位密度から、前記予め求めた界面準位密度と漏れ電力の関係に基づき、前記評価対象のSOI基板の漏れ電力を評価する、または前記測定した前記評価対象のSOI基板の前記界面準位密度より換算される抵抗から、前記予め求めた抵抗と漏れ電力の関係に基づき、前記評価対象のSOI基板の漏れ電力を評価する工程とを有することを特徴とするSOI基板の評価方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/305,989 US9780006B2 (en) | 2014-05-14 | 2015-02-25 | Method for evaluating SOI substrate |
KR1020167030635A KR102185647B1 (ko) | 2014-05-14 | 2015-02-25 | Soi 기판의 평가 방법 |
SG11201608834SA SG11201608834SA (en) | 2014-05-14 | 2015-02-25 | Method for evaluating soi substrate |
CN201580024451.1A CN106415806B (zh) | 2014-05-14 | 2015-02-25 | Soi基板的评估方法 |
EP15793091.8A EP3144965B1 (en) | 2014-05-14 | 2015-02-25 | Method for evaluating soi substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2014100758A JP6102823B2 (ja) | 2014-05-14 | 2014-05-14 | Soi基板の評価方法 |
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JP2006013100A (ja) * | 2004-06-25 | 2006-01-12 | Shin Etsu Handotai Co Ltd | Soiウエーハの評価方法 |
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JPH0233946A (ja) * | 1988-07-23 | 1990-02-05 | Nec Corp | 半導体装置 |
JP2001060676A (ja) * | 1999-08-20 | 2001-03-06 | Mitsubishi Materials Silicon Corp | 界面準位密度の算出方法 |
JP4492783B2 (ja) | 2001-09-12 | 2010-06-30 | 日本電気株式会社 | 半導体装置及びその製造方法 |
FR2860341B1 (fr) | 2003-09-26 | 2005-12-30 | Soitec Silicon On Insulator | Procede de fabrication de structure multicouche a pertes diminuees |
WO2005031842A2 (en) | 2003-09-26 | 2005-04-07 | Universite Catholique De Louvain | Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses |
US20080054920A1 (en) * | 2004-06-25 | 2008-03-06 | Shin-Etsu Handotai Co., Ltd. | Method For Evaluating Soi Wafer |
CN101506810B (zh) * | 2005-10-24 | 2013-06-05 | 卡德思设计规划公司 | 集成电路的时序、噪声和功率分析 |
JP2007324194A (ja) * | 2006-05-30 | 2007-12-13 | Shin Etsu Handotai Co Ltd | Soiウエーハの評価方法 |
JP2009231376A (ja) | 2008-03-19 | 2009-10-08 | Shin Etsu Handotai Co Ltd | Soiウェーハ及び半導体デバイスならびにsoiウェーハの製造方法 |
JP5532680B2 (ja) * | 2009-05-27 | 2014-06-25 | 信越半導体株式会社 | Soiウェーハの製造方法およびsoiウェーハ |
CN101702627B (zh) * | 2009-10-29 | 2012-10-03 | 华东师范大学 | 一种基于绝缘体上硅工艺的cmos射频开关 |
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KR102185647B1 (ko) | 2020-12-02 |
KR20170003554A (ko) | 2017-01-09 |
CN106415806A (zh) | 2017-02-15 |
EP3144965B1 (en) | 2020-11-25 |
US9780006B2 (en) | 2017-10-03 |
EP3144965A1 (en) | 2017-03-22 |
TWI609189B (zh) | 2017-12-21 |
JP2015220257A (ja) | 2015-12-07 |
JP6102823B2 (ja) | 2017-03-29 |
SG11201608834SA (en) | 2016-11-29 |
US20170047258A1 (en) | 2017-02-16 |
CN106415806B (zh) | 2019-06-04 |
EP3144965A4 (en) | 2018-01-10 |
TW201543049A (zh) | 2015-11-16 |
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