CN103633140A - 两步式浅沟槽隔离（sti）工艺 - Google Patents

两步式浅沟槽隔离（sti）工艺 Download PDF

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CN103633140A
CN103633140A CN201210540747.7A CN201210540747A CN103633140A CN 103633140 A CN103633140 A CN 103633140A CN 201210540747 A CN201210540747 A CN 201210540747A CN 103633140 A CN103633140 A CN 103633140A
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洪敏皓
周友华
李志聪
张简旭珂
廖茂成
葛翔翔
黄振铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路器件和一种用于制造集成电路器件的工艺。该集成电路器件包括具有在其中形成沟槽的衬底，占据沟槽的第一隔离材料层，形成在第一隔离材料层上的第二隔离材料层，位于衬底上并且水平地与第二隔离材料层相邻的外延生长硅层，以及形成在外延生长硅层上的栅极结构，其中栅极结构限定沟道。本发明还公开一种两步式浅沟槽隔离(STI)工艺。

Description

两步式浅沟槽隔离(STI)工艺
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及一种两步式浅沟槽隔离(STI)工艺。 
背景技术
半导体器件用于诸如计算机、手机等的大量电子设备。半导体器件包括形成在半导体晶圆上的集成电路，通过在半导体晶圆上方沉积许多类型的材料薄膜并且图案化这些材料薄膜以形成集成电路。集成电路包括诸如金属氧化物半导体(MOS)晶体管的场效应晶体管(FET)。 
半导体产业的一个目标是继续缩减单独FET的尺寸并且提高单独FET的速度。然而，这对FET(具有65nm以下晶体管节点)中的隔离器件提出挑战。例如，蚀刻浅沟槽隔离(STI)区沟槽和用绝缘材料填充STI沟槽变得更加困难。 
一种克服这些挑战的尝试涉及使用正硅酸乙酯(TEOS)作为隔离材料。然而，TEOS的使用可能导致不想要的湿度吸收问题。在更先进的FET技术中，使用用于器件隔离的高纵横比工艺(HAPP)或旋涂式玻璃(SOG)工艺在STI沟槽中沉积氧化物。然而，为了取得成功，这些方法可能需要特定的沟槽轮廓。例如，STI沟槽的纵横比(即，深度与宽度的比)可能相对较高(例如，5或以上)。此外，沟槽的倾斜度可能限于例如87度或以下。 
除了上述以外，当使用HAPP工艺用绝缘材料填充STI沟槽时，在FET的沟道中引起拉伸应力，并且FET事实上只适合用作NMOS器件。另一方面，当使用高密度等离子体(HDP)工艺填充STI沟槽时，在FET的沟道中引起压缩压力，并且FET事实上只适合用作PMOS器件。 
发明内容
根据本发明的第一方面，提供一种集成电路器件，包括：衬底，具有形成在所述衬底中的沟槽；第一隔离材料层，占据所述沟槽；第二隔离材料层，形成在所述第一隔离材料层上方；外延生长硅层，位于所述衬底上并且水平地与所述第二隔离材料层相邻；以及栅极结构，形成在所述外延生长硅上，所述栅极结构限定沟道。 
优选地，所述第一隔离材料层是高密度等离子体氧化物。 
优选地，所述第二隔离材料层是高密度等离子体氧化物。 
优选地，所述第二隔离材料层覆盖所述第一隔离材料层。 
优选地，所述第二隔离材料层邻接所述衬底。 
优选地，所述第一隔离材料层突出到所述衬底的表面上方。 
优选地，所述外延生长硅层包括硅锗。 
优选地，所述外延生长硅层包括掺杂III-V半导体材料。 
优选地，所述外延生长硅层具有<100>晶体结构、<110>晶体结构以及<111>晶体结构中的一种。 
优选地，所述第二隔离材料层的底面邻接所述第一隔离材料层的顶面和所述衬底的顶面。 
优选地，所述第二隔离材料层的侧壁邻接所述外延生长硅层。 
优选地，所述第二隔离材料层的宽度大于在任何深度下测量的所述第一隔离材料层的宽度。 
优选地，所述衬底由硅形成。 
根据本发明的第二方面，，提供一种集成电路器件，包括：硅衬底，具有形成在所述硅衬底中的沟槽；两部分式隔离结构，由所述衬底支撑，所述两部分式隔离结构包括第一氧化物层和第二氧化物层，所述第一氧化物层填充所述沟槽并且突出到所述硅衬底上方，所述第二氧化物层覆盖所述第一氧化物层；外延生长硅层，位于所述硅衬底上并且水平地与所述两部分式隔离结构相邻；以及栅极结构，形成在所述外延生长硅上，所述栅极结构限定沟道。 
优选地，所述第一氧化物层和所述第二氧化物层由高密度等离子体氧 化物形成。 
优选地，所述外延生长硅层包括硅锗和掺杂III-V半导体材料中的一种。 
优选地，所述外延生长硅层具有<100>晶体结构、<110>晶体结构和<111>晶体结构中的一种。 
优选地，所述第二氧化物层的宽度大于在任何深度下测量的所述第一氧化物层的宽度。 
根据本发明的又一方面，提供一种形成集成电路器件的方法，包括：在硅衬底中蚀刻沟槽；在所述沟槽中沉积第一隔离材料层，所述第一隔离材料层突出到所述硅衬底的表面上方；通过沉积第二隔离材料层覆盖所述第一隔离材料层；在所述硅衬底上外延生长硅层，所述硅层水平地与所述第二隔离材料层相邻；以及在所述硅层上形成栅极结构，所述栅极结构限定沟道。 
优选地，所述第一隔离材料层和所述第二隔离材料层通过高密度氧化物沉积工艺形成。 
附图说明
为了更完整地理解本发明及其优点，现在将参考结合附图所进行的以下描述，其中： 
图1是具有两步式STI区的FET器件的实施例的截面图； 
图2至图17共同示出形成图1的FET器件的方法； 
除非另有说明，不同附图中的相应标号和符号通常指相应部件。将附图绘制成清楚地示出实施例的相关方面而不必须成比例绘制。 
具体实施方式
在下面详细讨论实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅仅是示例性的，而不用于限制本发明的范围。 
将就具体环境中的实施例描述本发明，也就是金属氧化物半导体 (MOS)场效应晶体管(FET)。然而，本发明构思还可以应用到其他集成电路和电子结构中。 
现参考图1，示出FET器件10的实施例。正如以下更详细地阐述的，FET器件10包括使用两步式工艺形成的隔离区。这样，可允许FET器件10的隔离区具有相对较低的纵横比(例如，约为3或更小)并且不存在限制性STI沟槽轮廓要求。而且，隔离区可以通过高密度等离子体(HDP)形成，并且还可以使用N90或者N65HDP-STI工艺。事实上，还可以使用CO11 HDP-STI工艺。 
仍参考图1，FET器件10通常包括衬底12、沟槽14、第一隔离材料层16、第二隔离材料层18、外延生长硅层20以及栅极结构22。在实施例中，衬底12可以由诸如硅的各种合适的半导体材料形成。 
如图1所示，第一隔离材料层16占据或填充沟槽14。在实施例中，第一隔离材料层16突出到衬底12的顶面24上方。在实施例中，第一隔离材料层16是使用HDP工艺沉积的高密度等离子体(HDP)氧化物。 
第二隔离材料层18通常形成在第一隔离材料层16上方。如图1所示，第二隔离材料层18垂直设置在第一隔离材料层16上方。在实施例中，第二隔离材料层18覆盖第一隔离材料层16。换句话说，第二隔离材料层18将第一隔离材料层16的上部封装。在实施例中，第二隔离材料层18是使用HDP工艺沉积的高密度等离子体(HDP)氧化物。 
如图1所示，第二隔离材料层18可以具有底面26，底面26邻接或者位于衬底12的顶面24和第一隔离材料层16的顶面28上。此外，第二隔离材料层18的侧壁30可以邻接外延生长硅层20。在实施例中，不管在哪儿测量第一隔离材料层的宽度，第二隔离材料层18的宽度32都大于第一隔离材料层16的宽度34。在其他实施例中，在第一隔离材料层16任意深度36处，第二隔离材料层18的宽度32大于第一隔离材料层16的宽度34。 
第一隔离材料层16和第二隔离材料层18共同形成两部分式隔离结构38。通常使用该两部分式隔离结构38将FET器件10彼此电隔离。当然，该两部分式隔离结构38通常形成并且可以称为浅沟槽隔离(STI)区。 
仍参考图1，外延生长硅层20通常生长在衬底12上。如图所示，在 实施例中，外延生长硅层20水平地与第二隔离材料层18相邻。在实施例中，外延生长硅层包括硅锗(SiGe)或掺杂III-V半导体材料。在实施例中，外延生长硅层20具有<100>晶体结构、<110>晶体结构或者<111>晶体结构。还可以使用具有其他晶体结构的其他半导体材料。 
在实施例中，栅极结构22(即，栅极叠层)包括例如设置在栅极介电层42之上的多晶硅层40。栅极结构22还可以制造成包括诸如间隔件、金属层等的其他部件。为便于说明，图1中并没有清楚地描述这些部件。 
现参考图2至图17，共同示出形成图1的FET器件10的方法的实施例。关于图2，该方法开始于硅衬底12的清洗。之后，如图3所示，氮化物层44沉积在硅衬底12上。如图4所示，光刻胶46设置在部分氮化物层44之上以限定出用于浅沟槽隔离(STI)蚀刻的图案。 
现参考图4至图5，实施蚀刻工艺以去除氮化物层44和硅衬底12的未被光刻胶46保护的选择部分，从而形成沟槽14。在实施例中，沟槽14具有小于3的纵横比。转向图6，用第一隔离材料层16(例如，通过HDP氧化物沉积工艺沉积的HDP氧化物)填充沟槽14。之后，如图7所示，实施化学机械抛光(CMP)工艺以去除部分第一隔离材料层16。确实，如图7所示，在CMP工艺之后，占据沟槽14的第一隔离材料层16和氮化物层44通常是共面的。 
现参考图7至图8，去除氮化物层44。如图所示，氮化物层44的去除使得第一隔离材料层16突出到硅衬底12的顶面24上方。接下来，如图9所示，第二隔离材料层18(例如，通过HDP氧化物沉积工艺沉积的HDP氧化物)覆盖沉积在第一隔离材料层16和硅衬底12的上方。此后，如图10所示，额外的氮化物层44形成在第二隔离材料18层上方。 
如图11所示，另一光刻胶46设置在该额外的氮化物层44上以限定出用于形成两部分式STI结构38(见图1)的图案。现参考图11至图12，实施蚀刻工艺以去除氮化物层44和第二隔离材料层18的未被光刻胶46保护的部分以限定出位于额外的氮化物层44的剩余部分下方的两部分式STI结构38。 
现参考图13，硅层20外延生长在相邻的两部分式STI结构38之间的 硅衬底12上。此后，如图14所示，实施另一CMP工艺以去除部分外延生长的硅层20和剩余在第一隔离材料层16上方的氮化物层44。如图14所示，在CMP工艺之后，外延生长的硅层20和第二隔离材料层18通常是共面的。此后，实施氢退火工艺以修复和释放外延生长层20。如上所述，取决于FET器件10(见图1)期望的性能特点，可以提供<100>晶体结构、<110>晶体结构或者<111>晶体结构的外延生长硅层20。 
现参考图15，实施栅极材料清洗和沉积工艺。如图所示，在该工艺期间栅极介电层42和多晶硅层40以及其他部件可以形成在两部分式STI结构38的上方。此后，如图16所示，另一光刻胶46设置在多晶硅层40上以限定出用于形成栅极结构22(见图1)的图案。现参考图16至图17，实施蚀刻工艺以去除多晶硅层40和栅极介电层42的未被光刻胶46保护的部分进而限定出位于外延生长硅层20上方的栅极结构22，从而形成图1的FET器件10。应该理解，可以实施进一步或额外的生产或制造步骤或工艺以形成或增加图1的FET器件10。然而，为简洁起见在此省略这些额外的步骤或工艺。 
图1和图17的FET器件10相对于传统的或已知的FET器件具有数个优点。例如，FET器件10减轻或消除了STI沟槽蚀刻和绝缘材料空隙填充的难度。FET器件10还可以包括在40nm节点以下使用HDP氧化物和HDP氧化物工艺形成的STI区。 
除以上所述之外，FET器件10具有较低的纵横比(例如，约为3)，而传统的FET器件要求较高的纵横比(例如，约为5)。而且，FET器件10并不局限于传统的STI沟槽轮廓要求。此外，FET器件10在设置在栅极结构22下方的沟道48(见图17)中产生较小的压力，这使得FET器件10适合于PMOS和NMOS的应用。确实，FET器件10避免对沟道48的STI压力影响以及引起的漏极饱和电流(Idsat)的性能损失。 
在实施例中，集成电路器件包括：衬底，其中形成有沟槽；占据该沟槽的第一隔离材料层；形成在第一隔离材料层上的第二隔离材料层；位于衬底上并且水平地与第二隔离材料层相邻的外延生长硅层；以及形成在外延生长硅层上的栅极结构(其限定沟道)。 
在实施例中，集成电路器件包括：硅衬底，其中形成有沟槽；由该衬底支撑的两部分式隔离结构，其包括第一氧化层和第二氧化层，第一氧化层填充该沟槽并且突出到硅衬底上方，第二氧化层覆盖第一氧化层；位于硅衬底上并且水平邻接两部分式隔离结构的外延生长硅层；以及形成在外延生长硅层上的栅极结构(其限定沟道)。 
在实施例中，一种形成集成电路器件的方法包括：在硅衬底中蚀刻沟槽；在该沟槽中沉积第一隔离材料层，第一隔离材料层突出到硅衬底的表面上方；通过沉积第二隔离材料层覆盖第一隔离材料层；在硅衬底上外延生长硅层，硅层水平邻接第二隔离材料层；以及在硅层上形成栅极结构(其限定沟道)。 
尽管本发明提供示例性实施例，但并旨在对说明书作限制性解释。对本领域普通技术人员来说，在参考本说明书的基础上，示例性实施例的各种修改和组合以及其他的实施例将是显而易见的。因此，所附权利要求包括任何这样的修改或实施例。 

Claims (10)

1.一种集成电路器件，包括：
衬底，具有形成在所述衬底中的沟槽；
第一隔离材料层，占据所述沟槽；
第二隔离材料层，形成在所述第一隔离材料层上方；
外延生长硅层，位于所述衬底上并且水平地与所述第二隔离材料层相邻；以及
栅极结构，形成在所述外延生长硅上，所述栅极结构限定沟道。
2.根据权利要求1所述的集成电路器件，其中，所述第一隔离材料层是高密度等离子体氧化物。
3.根据权利要求1所述的集成电路器件，其中，所述第二隔离材料层是高密度等离子体氧化物。
4.根据权利要求1所述的集成电路器件，其中，所述第二隔离材料层覆盖所述第一隔离材料层。
5.根据权利要求1所述的集成电路器件，其中，所述第二隔离材料层邻接所述衬底。
6.根据权利要求1所述的集成电路器件，其中，所述第一隔离材料层突出到所述衬底的表面上方。
7.根据权利要求1所述的集成电路器件，其中，所述外延生长硅层包括硅锗。
8.根据权利要求1所述的集成电路器件，其中，所述外延生长硅层包括掺杂III-V半导体材料。
9.一种集成电路器件，包括：
硅衬底，具有形成在所述硅衬底中的沟槽；
两部分式隔离结构，由所述衬底支撑，所述两部分式隔离结构包括第一氧化物层和第二氧化物层，所述第一氧化物层填充所述沟槽并且突出到所述硅衬底上方，所述第二氧化物层覆盖所述第一氧化物层；
外延生长硅层，位于所述硅衬底上并且水平地与所述两部分式隔离结构相邻；以及
栅极结构，形成在所述外延生长硅上，所述栅极结构限定沟道。
10.一种形成集成电路器件的方法，包括：
在硅衬底中蚀刻沟槽；
在所述沟槽中沉积第一隔离材料层，所述第一隔离材料层突出到所述硅衬底的表面上方；
通过沉积第二隔离材料层覆盖所述第一隔离材料层；
在所述硅衬底上外延生长硅层，所述硅层水平地与所述第二隔离材料层相邻；以及
在所述硅层上形成栅极结构，所述栅极结构限定沟道。
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