CN106158723A - 填充集成电路中的凹穴及其结果装置 - Google Patents

填充集成电路中的凹穴及其结果装置 Download PDF

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CN106158723A
CN106158723A CN201610320059.8A CN201610320059A CN106158723A CN 106158723 A CN106158723 A CN 106158723A CN 201610320059 A CN201610320059 A CN 201610320059A CN 106158723 A CN106158723 A CN 106158723A
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hard mask
interlayer dielectric
protection cover
depression
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CN106158723B (zh
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J·L·鲁利安
S·K·辛格
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GlobalFoundries US Inc
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Abstract

本发明涉及填充集成电路中的凹穴及其结果装置，揭露一种方法，能够在集成电路装置及该结果装置中填充高深宽比的凹穴，而不具有孔隙或间隙。实施例包含于第一层间介电层中提供主动区域及/或栅极接触；形成选择性保护覆盖层于该接触的上表面上；形成第二层间介电层于该保护覆盖层的上表面上及该第一层间介电层的上表面上；形成硬掩膜堆迭于该第二层间介电层上；在该第二层间介电层及硬掩膜堆迭中，形成曝露出一个或多个保护覆盖层的凹穴；在该堆迭中移除选择性层以减少该凹穴的深度；以及以金属层填充该凹穴，其中，在一个或多个凹穴中的该金属层连接至经曝露的该一个或多个保护覆盖层的上表面。

Description

填充集成电路中的凹穴及其结果装置
技术领域
本发明揭露大致关于设计及制造集成电路(IC，Integrated Circuit)装置。本发明揭露适用在22纳米技术节点及更超越的技术中填充集成电路装置中的凹陷而不具有空隙或间隙。
背景技术
一般而言，在集成电路装置的制造中，光学微影制程可被用在转印/图案化用于建立各种装置、元件及电路的凹穴、沟槽及/或凹陷区域上。不同类型的凹穴可以在该制造流程的不同的阶段形成。例如，该凹穴可以具有不同的形状、深度及/或尺寸并且可以建立在衬底的不同区域中。例如，用以形成接触的凹穴可能具有一种尺寸及深宽比(例如，深度对宽度的比)、可能位在该衬底中的特定位置及可能以诸如钨(W，Tungsten)的特定材料填充，而用于金属线路的沟槽可能具有不同的尺寸及深宽比并且可能以诸如铜(Cu，Copper)的不同的材料来填充。在金属层中的该金属线路沟槽或通道可以用在该集成电路中内用于连接不同的装置的铜来填充，而浅沟槽隔离(STI，Shallow Trench Isolation)区域可用氧化物填充以用于将各种装置彼此电性绝缘。在该半导体工业上，先进的技术被用来设计及制造可能包含具有较小的几何的电路元件(例如，晶体管、互连线路、导通孔等等)的较小的集成电路装置。然而，在较小的集成电路装置中，以不同材料所填充的凹穴可能收缩，该收缩会带来各种挑战。例如，填充有材料(例如，铜)的沟槽可能经由填充而使得可能发展出孔隙斑点/区域，该孔隙斑点/区域可能由于该材料的不充足/不规则的填充所造成。该孔隙可能会降低集成电路装置中的各层或元件之间的互连性及造成性能或可靠度问题。例如，该孔隙可能因为沟槽(例如，太深)具有高深宽比，使得该填充材料可能无法完全填充该沟槽。
图1A为在例示性集成电路装置中的各层的横截面图示。图1A说明包含在硅(Si，Silicon)衬底(为了说明方便而未图示)上方的层间介电层(ILD，Interlayer Dielectric)101、主动区域及栅极接触(例如，钨)103a至103d、蚀刻终止层105、另一层层间介电层107、介电质硬掩膜(DHM，Dielectric Hard-Mask)层109(诸如氮氧化硅(SiON，SiliconOxynitride))、金属硬掩膜(MHM，Metal Hard-Mask)层111(例如，氮化钛(TiN，TitaniumNitride))及形成在该金属硬掩膜层111的上表面上的金属(例如，铜)层113的堆迭100。此外，该金属层可以填充可能已经通过各种集成电路制造(例如，微影-蚀刻)流程所形成的凹穴/沟槽115及117(例如，导通孔或金属线路沟槽)。在用金属填充之前，可以形成薄阻障/种子层119于该凹穴内。
图1B及1C说明在例示性集成电路装置中的结构的横截面视图。在图1B中，影像121包含沟槽115，该沟槽115是以材料(例如，铜)填充；然而，存在着可能因为填充材料不充足所导致的孔隙123。再者，图1C描绘的是说明该孔隙123的不同视角的影像125。
如所说明者，不同的凹穴/沟槽(例如，115或117)可以在不同的深度产生不同的深宽比。在深沟槽(例如，高深宽比)的例子中，有可能该沟槽没有完全地以想要的材料填充，其中可能存在孔隙或间隙。如同所提到的，此类的孔隙或间隙可能造成在集成电路装置中的效能或可靠度上的问题。
因此，在集成电路装置及其结果装置中，对于能够对高深宽比凹穴填充而不会有孔隙或间隙的方法将存在着需求。
发明内容
本发明揭露的一方面是包含在衬底中的凹穴的降低的深宽比的集成电路装置，其中，该凹穴可以个别的材料填充并且于该填充材料中不具有孔隙或间隙。
本发明揭露的另一个方面为用于减少在衬底中的凹穴的深宽比的方法，其中，该凹穴可以个别的材料填充而不会有孔隙或间隙于该填充材料中。
本发明揭露的额外方面及其它特征将在后续说明中提出并且有一部分对于具有一般熟习该项技艺中的人士当审视下文或可能由本发明揭露的实施而学会之后将是显而易见的。如附加的权利要求书中所明确指出者，可以实现并获得本发明揭露的优点。
依据本发明揭露，某些技术功效可以通过一种方法而部分达成，该方法包含：在第一层间介电层中提供主动区域及/或栅极接触；形成选择性保护覆盖层于该接触的上表面上；形成第二层间介电层于该保护覆盖层的上表面上及该第一层间介电层的上表面上；形成硬掩膜堆迭于该第二层间介电层上；在该第二层间介电层及硬掩膜堆迭中，形成曝露一个或多个保护覆盖层的凹穴；在该堆迭中移除选择性层以降低该凹穴的深度；以及以金属层填充该凹穴，其中，在一个或多个凹穴中的该金属层连接至经曝露的该一个或多个保护覆盖层的上表面。
其中一个方面包含在形成该选择性保护覆盖层之前，执行化学机械研磨(CMP，Chemical Mechanical Polishing)。另一个方面包含在形成该第二层间介电层之前，形成蚀刻终止层。
在其中一个方面中，该硬掩膜堆迭的形成包含形成第一介电质硬掩膜(DHM1，Dielectric Hard-Mask)层、金属硬掩膜(MHM，Metal Hard-Mask)层、第二介电质硬掩膜(DHM2，Dielectric Hard-Mask)层、旋涂式硬掩膜(SOH，Spin-On Hard-Mask)层及抗反射涂布(Anti-Reflective Coating，ARC)硬掩膜层。
在某些方面中，该选择性层包含该金属硬掩膜层、该第二介电质硬掩膜层、该旋涂式硬掩膜层及该抗反射涂布层。
在另一个方面中，该方法包含在形成该金属层之前，共形地形成阻障金属/种子层于该第一介电质硬掩膜层及层间介电层的曝露表面上。在其中一个方面中，该方法包含移除经曝露的该一个或多个保护覆盖层的上方部分。
在某些方面中，该金属硬掩膜层的移除速率较快于经曝露的该一个或多个保护覆盖层的该上方部分的移除速率。在另一个方面中，该方法包含在以该金属层填充后，执行化学机械研磨到达该第二层间介电层的上表面。在其中一个方面中，该保护覆盖层包括钌覆盖层。在另一个方面中，该接触为以钨填充的凹穴。
在另一个方面中，该凹穴包含互连导通孔及沟槽。
在其中一个方面中，该金属包含铜，并且该方法更包含通过电化学电镀(ECP，Electrochemical Plating)以铜填充该凹穴。
依据本发明揭露，某些技术功效通过一种装置而部分达成，该装置包含：在第一层间介电层中的主动区域及/或栅极接触；于该接触的上表面上的选择性保护覆盖层；于该保护覆盖层的上表面上及该第一层间介电层的上表面上的第二层间介电层；以及穿越该第二层间介电层到达该保护覆盖层的导通孔。
在其中一个方面中，该装置包含在该第二层间介电层中的金属线路沟槽。
在另一个方面中，该装置包含在该第二层间介电层下方的蚀刻终止层。在其中一个方面中，该保护覆盖层包含钌。
本发明揭露的额外方面及技术功效对于熟习该项技艺的人士由下文的详细说明将立即变得显而易见，其中，本发明揭露的实施例仅是通过经过考量的最佳模式的说明的方式而做描述以实施本发明揭露。如同将会了解的是，本发明揭露能够使用于其它及不同的实施例，并且该发明的几个细节能够以各种明显的方面而做修改，所有修改并不会脱离违反本发明揭露。因此，该图式及描述将视为在本质上说明的目的，而非视为限定。
附图说明
本发明揭露通过在该附加描绘中的图式的例子而作说明，并且并非用以限定，并且其中，相同的元件符号意指类似的元件，并且其中：
图1A为在例示性的集成电路装置中的各种材料层的横截面图式；
图1B及1C说明在例示性的集成电路装置中具有孔隙的结构的横截面图式；以及
图2A至2I为依据例示性的实施例，概要性说明用于减少在集成电路装置中的凹穴的深宽比及能够无缺陷地填充该凹穴的制造流程。
符号说明
100 堆迭 101 层间介电层
103a 主动区域及栅极接触 103b 主动区域及栅极接触
103c 主动区域及栅极接触 103d 主动区域及栅极接触
105 蚀刻终止层 107 层间介电层
109 介电质硬掩膜、第一介电质硬掩膜
111 金属硬掩膜层 113 金属层
115 凹穴、沟槽 117 凹穴、沟槽
119 阻障/种子层 121 影像
123 孔隙 125 影像
201a 保护覆盖层 201b 保护覆盖层
201c 保护覆盖层 201d 保护覆盖层
203 第二介电质硬掩膜层 205 旋涂式硬掩膜层
207 抗反射涂布层 209 凹穴
211 氮氧化硅层 213 底部-抗反射-涂布层
215 光阻层 217 凹穴
219 凹穴 221a 深度
221b 深度 221c 深度
221d 深度 223 宽度
225 覆盖层 227 覆盖层。
具体实施方式
在下文的说明中，为了解释的目的，将提出各种特定的细节以提供例示性的实施例的完整的了解。然而，显然该例示性实施例可不以这些特定细节实施或者以等效的配置实施。在其它例子中，众所周知的结构及装置是以方块图形式显示，以避免非必要地模糊例示性实施例。此外，除非另外指示，否则该说明书及权利要求书内所使用的所有表示数量、比例及要素的数字性质、反应条件等等的数字应当理解为在所有例子中以名词＂大约＂来做修饰。
本发明揭露着重及解决在以个别的材料填充凹穴时所伴随的在集成电路装置中的凹穴内有孔隙及不规则的间隙的问题。本发明揭露着重及解决此类问题，例如(但不限于)通过移除在该集成电路中的一层或一层以上的材料以减少在衬底中的凹穴的深宽比(例如，深度)，使得该凹穴可以个别的材料填充并且在该填充中不会具有孔隙或间隙。
图2A至2I为依据例示性实施例，概要地说明用于减少在集成电路装置中的凹穴的深宽比及能够无缺陷地填充该凹穴的制造流程。
图2A说明包含该主动区域及可用诸如钨的材料形成的栅极接触103a至103d的该层间介电层101。在平坦化(例如，通过化学机机械研磨制程)该接触达到该层间介电层101的该上表面之后，如图2B所示，钌(Ru)保护覆盖层201a至201d可以选择性地沉积在该钨接触103a至103d的上表面上。该钌覆盖层201a至201d的沉积可以通过使用热化学气相沉积制程。在图2C中，蚀刻终止层105为形成在该层间介电层101的上表面及该钌覆盖层201a至201d的上表面上。接着，形成层间介电层107(例如，诸如氧碳氮化硅的低k介电材料)。金属线路沟槽及导通孔将形成于该层间介电层107之内及穿越该层间介电层107。接着，第一介电质硬掩膜(DHM1)层109、金属硬掩膜层111、第二介电质硬掩膜(DHM2)层203、旋涂式硬掩膜层205及用于蚀刻转移及反射控制的抗反射涂布层(例如，氮氧化硅)207为连续地形成于该层间介电层107的上方。
在图2D中，各种可获得的集成电路制造流程(例如，微影-蚀刻双图案化)可被用来产生用于金属线路沟槽图案化的凹穴209。接着，该旋涂式硬掩膜层205及抗反射涂布硬掩膜层207可以移除。在图2E中，另一个旋涂式硬掩膜层205可以沉积在该凹穴209中及该第二介电质硬掩膜层203的剩余区段的上表面上。额外的材料层(例如，氮氧化硅层211)、底部-抗反射-涂布(BARC，Bottom-AntiReflective-Coating)层213及光阻层215为个别地形成于该旋涂式硬掩膜层205的上表面上而用于导通孔图案化。
在图2F中，各种集成电路制造流程可被用以产生凹穴217及219，其中该凹穴217(例如，金属线路沟槽)可以延伸进入该层间介电层107中。该凹穴219(例如，导通孔)可以延伸较深入，穿越该层间介电层107，到达该钌覆盖层201c及201d并曝露出该钌覆盖层201c及201d的上表面。在金属线路沟槽217及导通孔219的完全蚀刻期间，该第二介电质硬掩膜层203的剩余区段、旋涂式硬掩膜层205、氮氧化硅层211、底部-抗反射-涂布层213及光阻215将被移除而留下该金属硬掩膜层111的区段于该堆迭的顶部上。如图所示，凹穴217可以位在221a的深度及223的宽度。同样地，凹穴219可以结合221b的深度及类似于宽度223的宽度。
在图2G中，各种集成电路制造制程(例如，湿式清洁)可被用来蚀刻及移除该金属硬掩膜层111的剩余区段及每一个该钌覆盖层201c及201d的上方部分而留下部分钌覆盖层225及227。应该留意的是使用于该蚀刻制程的化学物可能以较快于该钌覆盖层201c及201d(例如，低于1纳米/分钟)的速率(例如，320纳米/分钟)蚀刻该金属硬掩膜/氮化钛层111；因此，即使在蚀刻移除该氮化钛层111之后，该部分钌覆盖层225及227仍然存在以保护该钨接触103c及103d。如图所示，图2F的该氮化钛层111的移除可以减少从221a至221c的凹穴217的深度，该深度可以减少对于该凹穴的深宽比达到一定百分比(例如，17％)。同样地，凹穴219的深度可以减少从221b至221d的深度，该深度可以减少对于该凹穴的深宽比达到关联的百分比(例如，11％)。在图2H中，薄阻障金属/种子层119为形成在该介电质硬掩膜层109的该剩余区段的上表面上以及形成在包含有侧壁于其中的该凹穴217及219中；然而，该部分钌覆盖层225及227的上表面仍然维持曝露而不具有阻障金属/种子层119在其上表面上。接着，金属层113通过电化学电镀(ECP，ElectroChemical Plating)形成于该阻障金属/种子层119的上表面上的该凹穴/沟槽217及219中。该金属层113可以与该部分钌覆盖层225及227形成直接接触。在图2I中，该金属层113的上方部分及该第一介电质硬掩膜层109的剩余区段为通过平坦化(例如，化学机械研磨)而被移除达到该层间介电层107的上表面而留下以该金属层113的剩余部分填充的该凹穴217及219。
应该留意的是，可以使用其它典型的材料及集成电路制造制程。该制程可以使用于所有金属层及接触层，其中该导通孔底部可以是钨或铜。
本发明揭露的实施例可以达到数种技术上的功效，包含减少在衬底中的凹穴的深宽比，使得能够用个别的材料无缺陷地填充该凹穴，以及保护导通孔底部免受湿式氮化钛移除。再者，该实施例具有在各种工业应用上的利用性，例如，微处理器、智慧手机、移动装置、移动手持装置、数字视讯转换盒、数字多功能影音光碟烧录器及播放器、汽车导航、印表机及周边、网络及电路设备、游戏机系统、数字相机或使用逻辑或高电压技术节点的其它装置。本发明揭露因此在各种类型的高度集成化半导体装置中享有产业利用性，包含使用静态随机存取内存单元(例如，液晶显示器(LCD，Liquid Crystal Display)驱动器、同步随机存取内存(SRAM，Synchronous Random Access Memories)、数字处理器等等)的装置，尤是是用于22纳米技术节点装置及更超越的技术。
在先前的描述中，本发明揭露参考本发明的特定地例示性实施例做描述。然而，显而易见的是各种修改及变更可以据以实施而不会脱离本发明揭露的较广义的精神及范畴，如同在权利要求书中所提出的。该说明书及图式因此应视为说明的目的并且不在于限定。应该了解的是，本发明揭露能够使用各种其它的组合及实施例并且如同在此所陈述的本发明概念的范畴内能够做任何变更或修改。

Claims (20)

1.一种方法，包括：
提供主动区域及/或栅极接触于第一层间介电层(ILD，Interlayer Dielectric)中；
形成选择性保护覆盖层于该接触的上表面上；
形成第二层间介电层于该保护覆盖层的上表面上及该第一层间介电层的上表面上；
形成硬掩膜堆迭于该第二层间介电层上；
在该第二层间介电层及硬掩膜堆迭中，形成曝露出一个或多个保护覆盖层的凹穴；
在该堆迭中移除选择性层以减少该凹穴的深度；以及
以金属层填充该凹穴，其中，在一个或多个凹穴中的该金属层连接至经曝露的该一个或多个保护覆盖层的上表面。
2.如权利要求1所述的方法，包括在形成该选择性保护覆盖层之前，执行化学机械研磨(CMP，Chemical Mechanical Polishing)。
3.如权利要求1所述的方法，包括在形成该第二层间介电层之前，形成蚀刻终止层。
4.如权利要求1所述的方法，其中，该硬掩膜堆迭的形成包括：
形成第一介电质硬掩膜(DHM1，Dielectric Hard-Mask)层、金属硬掩膜(MHM，MetalHard-Mask)层、第二介电质硬掩膜(DHM2，Dielectric Hard-Mask)层、旋涂式硬掩膜(SOH，Spin-On Hard-Mask)层及抗反射涂布(Anti-Reflective Coating，ARC)硬掩膜层。
5.如权利要求4所述的方法，其中，该选择性层包含该金属硬掩膜层、该第二介电质硬掩膜层、该旋涂式硬掩膜层及该抗反射涂布硬掩膜层。
6.如权利要求4所述的方法，更包括：
在形成该金属层之前，共形地形成阻障金属/种子层于该第一介电质硬掩膜层及层间介电层的曝露表面上。
7.如权利要求4所述的方法，更包括：
移除经曝露的该一个或多个保护覆盖层的上方部分。
8.如权利要求7所述的方法，其中，该金属硬掩膜层的移除速率较快于经曝露的该一个或多个保护覆盖层的该上方部分的移除速率。
9.如权利要求4所述的方法，包括在以该金属层填充之后，执行化学机械研磨到达该第二层间介电层的上表面。
10.如权利要求1所述的方法，其中，该保护覆盖层包括钌覆盖层。
11.如权利要求1所述的方法，其中，该接触为以钨填充的凹穴。
12.如权利要求1所述的方法，其中，该凹穴包含互连导通孔及沟槽。
13.如权利要求1所述的方法，其中，该金属包括铜，该方法更包括通过电化学电镀(ECP，ElectroChemical Plating)以该铜填充该凹穴。
14.一种装置，包括：
主动区域及/或栅极接触，位于第一层间介电层(ILD，InterLayer Dielectric)中；
选择性保护覆盖层，位于该接触的上表面上；
第二层间介电层，位于该保护覆盖层的上表面上及该第一层间介电层的上表面上；以及
导通孔，其穿越该第二层间介电层到达该保护覆盖层。
15.如权利要求14所述的装置，更包括金属线路沟槽，位于该第二层间介电层中。
16.如权利要求14所述的装置，更包括蚀刻终止层，位于该第二层间介电层下方。
17.如权利要求14所述的装置，其中，该保护覆盖层包括钌。
18.一种方法，包括：
提供主动区域及/或栅极接触于第一层间介电层(ILD，Interlayer Dielectric)中；
形成选择性保护覆盖层于该接触的上表面上；
形成第二层间介电层于该保护覆盖层的上表面上及该第一层间介电层的上表面上；
形成硬掩膜堆迭于该第二层间介电层上，其中，该硬掩膜包含第一介电质硬掩膜(DHM1，Dielectric Hard-Mask)层、金属硬掩膜(MHM，Metal Hard-Mask)层、第二介电质硬掩膜(DHM2，Dielectric Hard-Mask)层、旋涂式硬掩膜(SOH，Spin-On Hard-Mask)层及抗反射涂布(Anti-Reflective Coating，ARC)硬掩膜层；
在该第二层间介电层及硬掩膜堆迭中，形成曝露出一个或多个保护覆盖层的凹穴；
在该堆迭中移除选择性层以减少该凹穴的深度，其中，该选择性层包含该金属硬掩膜层、该第二介电质硬掩膜层、该旋涂式硬掩膜层及该抗反射涂布硬掩膜层；
以金属层填充该凹穴，其中，在一个或多个凹穴中的该金属层连接至经曝露的该一个或多个保护覆盖层的上表面；以及
在形成该金属层之前，共形地形成阻障金属/种子层于该第一介电质硬掩膜层及层间介电层的曝露表面上。
19.如权利要求18所述的方法，更包括：
移除经曝露的该一个或多个保护覆盖层的上方部分。
20.如权利要求18所述的方法，其中，该保护盖包括钌覆盖层，该接触为以钨填充的凹穴，以及其中，该金属硬掩膜层的移除速率较快于经曝露的该一个或多个保护覆盖层的该上方部分的移除速率。
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