TWI619670B - 填充積體電路中之凹穴之方法及其結果裝置 - Google Patents

填充積體電路中之凹穴之方法及其結果裝置 Download PDF

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TWI619670B
TWI619670B TW105105409A TW105105409A TWI619670B TW I619670 B TWI619670 B TW I619670B TW 105105409 A TW105105409 A TW 105105409A TW 105105409 A TW105105409 A TW 105105409A TW I619670 B TWI619670 B TW I619670B
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hard mask
interlayer dielectric
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納森強 李 魯爾蘭
尚尼爾 庫瑪爾 辛
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格羅方德半導體公司
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Abstract

本發明揭露一種方法，能夠在積體電路裝置及該結果裝置中填充高深寬比之凹穴，而不具有孔隙或間隙。實施例包含於第一層間介電層中提供主動區域及/或閘極接觸；形成選擇性保護覆蓋層於該接觸之上表面上；形成第二層間介電層於該保護覆蓋層之上表面上及該第一層間介電層之上表面上；形成硬遮罩堆疊於該第二層間介電層上；在該第二層間介電層及硬遮罩堆疊中，形成曝露出一個或多個保護覆蓋層之凹穴；在該堆疊中移除選擇性層以減少該凹穴之深度；以及以金屬層填充該凹穴，其中在一個或多個凹穴中之該金屬層連接至經曝露的該一個或多個保護覆蓋層之上表面。

Description

填充積體電路中之凹穴之方法及其結果裝置
本發明揭露大致係關於設計及製造積體電路(IC，Integrated Circuit)裝置。本發明揭露適用在22奈米技術節點的技術中填充積體電路裝置中之凹陷而不具有空隙或間隙。
一般而言，在積體電路裝置之製造中，光學微影製程可被用在轉印/圖案化用於建立各種裝置、元件及電路之凹穴、溝槽或凹陷區域上。不同類型的凹穴可以在該製造流程之不同的階段形成。例如，該凹穴可以具有不同的形狀、深度或尺寸並且可以建立在基板的不同區域中。例如，用以形成接觸之凹穴可能具有一種尺寸及深寬比(例如，深度對寬度之比)、可能位在該基板中之特定位置及可能以諸如鎢(W，Tungsten)之特定材料填充，而用於金屬線路之溝槽可能具有不同的尺寸及深寬比並且可能以諸如銅(Cu，Copper)之不同的材料來填充。在金屬層中之該金屬線路溝槽或通道可以用在該積體電路中內用於連接不同的裝置之銅來填充，而淺溝槽隔離(STI，Shallow Trench Isolation)區域可用氧化物填充以用於將各種裝置彼此電性絕緣。在該半導體工業上，先進的技術被用來設計及製造可能包含具有較的幾何之電路元件(例如，電晶體、互連線路、導通孔等等)之較小的積體電路裝置。然而，在較小的積體電路裝置中，以不同材料所填充之凹穴可能收縮，該收縮會帶來各種挑戰。例如，填充有材料(例如，銅)之溝槽可能經由填充而使得可能發展出孔隙斑點或區域，該孔隙斑點或區域可能由於該材料之不充足或不規則的填充所造成。該孔隙可能會降低積體電路裝置中之各層或元件之間的互連性及造成性能或可靠度問題。例如，該孔隙可能因為溝槽(例如，太深)具有高深寬比，使得該填充材料可能無法完全填充該溝槽。
第1A圖為在例示性積體電路裝置中之各層之横截面圖示。第1A圖說明包含在矽(Si，Silicon)基板(為了說明方便而未圖示)上方之層間介電層(ILD，Interlayer Dielectric)101、主動區域及閘極接觸(例如，鎢)103a至103d、蝕刻終止層105、另一層層間介電層107、介電質硬遮罩(DHM，Dielectric Hard-Mask)層109(諸如氮氧化矽(SiON，Silicon Oxynitride))、金屬硬遮罩(MHM，Metal Hard-Mask)層111(例如，氮化鈦(TiN，Titanium Nitride))及形成在該金屬硬遮罩層111之上表面上之金屬(例如，銅)層113的堆疊100。此外，該金屬層可以填充可能已經藉由各種積體電路製造(例如，微影-蝕刻)流程所形成之凹穴115及溝槽117(例如，導通孔或金屬線 路溝槽)。在用金屬填充之前，可以形成薄阻障或種子層119於該凹穴內。
第1B及1C圖說明在例示性積體電路裝置中之結構之橫截面視圖。在第1B圖中，影像121包含溝槽115，該溝槽115係以材料(例如，銅)填充；然而，存在著可能因為填充材料不充足所導致之孔隙123。再者，第1C圖描繪的是說明該孔隙123之不同視角之影像125。
如所說明者，不同的凹穴115或溝槽117可以在不同的深度產生不同的深寬比。在深溝槽(例如，高深寬比)之例子中，有可能該溝槽沒有完全地以想要的材料填充，其中可能存在孔隙或間隙。如同所提到的，此類的孔隙或間隙可能造成在積體電路裝置中之效能或可靠度上的問題。
因此，在積體電路裝置及其結果裝置中，對於能夠對高深寬比凹穴填充而不會有孔隙或間隙的方法將存在著需求。
本發明揭露之一態樣係包含在基板中之凹穴之降低的深寬比之積體電路裝置，其中，該凹穴可以個別的材料填充並且於該填充材料中不具有孔隙或間隙。
本發明揭露之另一個態樣為用於減少在基板中之凹穴之深寬比之方法，其中，該凹穴可以個別的材料填充而不會有孔隙或間隙於該填充材料中。
本發明揭露之額外態樣及其它特徵將在後續 說明中提出並且有一部分對於具有一般熟習該項技藝中之人士當審視下文或可能由本發明揭露之實施而學會之後將是顯而易見的。如附加的申請專利範圍中所明確指出者，可以實現並獲得本發明揭露之優點。
依據本發明揭露，某些技術功效可以藉由一種方法而部分達成，該方法包含：在第一層間介電層中提供主動區域及閘極接觸；形成選擇性保護覆蓋層於該接觸之上表面上；形成第二層間介電層於該保護覆蓋層之上表面上及該第一層間介電層之上表面上；形成硬遮罩堆疊於該第二層間介電層上；在該第二層間介電層及硬遮罩堆疊中，形成曝露一個或多個保護覆蓋層之凹穴；在該堆疊中移除選擇性層以降低該凹穴之深度；以及以金屬層填充該凹穴，其中，在一個或多個凹穴中之該金屬層連接至經曝露的該一個或多個保護覆蓋層之上表面。
其中一個態樣包含在形成該選擇性保護覆蓋層之前，執行化學機械研磨(CMP，Chemical Mechanical Polishing)。另一個態樣包含在形成該第二層間介電層之前，形成蝕刻終止層。
在其中一個態樣中，該硬遮罩堆疊之形成包含形成第一介電質硬遮罩(DHM1，Dielectric Hard-Mask)層、金屬硬遮罩(MHM，Metal Hard-Mask)層、第二介電質硬遮罩(DHM2，Dielectric Hard-Mask)層、旋塗式硬遮罩(SOH，Spin-On Hard-Mask)層及抗反射塗佈(Anti-Reflective Coating，ARC)硬遮罩層。
在某些態樣中，該選擇性層包含該金屬硬遮罩層、該第二介電質硬遮罩層、該旋塗式硬遮罩層及該抗反射塗佈層。
在另一個態樣中，該方法包含在形成該金屬層之前，共形地形成阻障金屬或種子層於該第一介電質硬遮罩層及層間介電層之曝露表面上。在其中一個態樣中，該方法包含移除經曝露的該一個或多個保護覆蓋層之上方部分。
在某些態樣中，該金屬硬遮罩層的移除速率較快於經曝露的該一個或多個保護覆蓋層之該上方部分的移除速率。在另一個態樣中，該方法包含在以該金屬層填充後，執行化學機械研磨到達該第二層間介電層的上表面。在其中一個態樣中，該保護覆蓋層包括釕覆蓋層。在另一個態樣中，該接觸為以鎢填充之凹穴。
在另一個態樣中，該凹穴包含互連導通孔及溝槽。
在其中一個態樣中，該金屬包含銅，並且該方法更包含藉由電化學電鍍(ECP，Electrochemical Plating)以銅填充該凹穴。
依據本發明揭露，某些技術功效藉由一種裝置而部分達成，該裝置包含：在第一層間介電層中之主動區域及閘極接觸；於該接觸之上表面上之選擇性保護覆蓋層；於該保護覆蓋層之上表面上及該第一層間介電層之上表面上之第二層間介電層；以及穿越該第二層間介電層到 達該保護覆蓋層之導通孔。
在其中一個態樣中，該裝置包含在該第二層間介電層中之金屬線路溝槽。
在另一個態樣中，該裝置包含在該第二層間介電層下方之蝕刻終止層。在其中一個態樣中，該保護覆蓋層包含釕。
本發明揭露之額外態樣及技術功效對於熟習該項技藝之人士由下文的詳細說明將立即變得顯而易見，其中本發明揭露之實施例僅是藉由經過考量之最佳模式之說明的方式而做描述以實施本發明揭露。如同將會瞭解的是，本發明揭露能夠使用於其它及不同的實施例，並且該發明的幾個細節能夠以各種明顯的態樣而做修正，所有修正並不會脫離違反本發明揭露。因此，該圖式及描述將視為在本質上說明之目的，而非視為限定。
100‧‧‧堆疊
101‧‧‧層間介電層
103a‧‧‧主動區域及閘極接觸
103b‧‧‧主動區域及閘極接觸
103c‧‧‧主動區域及閘極接觸
103d‧‧‧主動區域及閘極接觸
105‧‧‧蝕刻終止層
107‧‧‧層間介電層
109‧‧‧介電質硬遮罩、第一介電質硬遮罩
111‧‧‧金屬硬遮罩層
113‧‧‧金屬層
115‧‧‧凹穴、溝槽
117‧‧‧凹穴、溝槽
119‧‧‧阻障/種子層
121‧‧‧影像
123‧‧‧孔隙
125‧‧‧影像
201a‧‧‧保護覆蓋層
201b‧‧‧保護覆蓋層
201c‧‧‧保護覆蓋層
201d‧‧‧保護覆蓋層
203‧‧‧第二介電質硬遮罩層
205‧‧‧旋塗式硬遮罩層
207‧‧‧抗反射塗佈層
209‧‧‧凹穴
211‧‧‧氮氧化矽層
213‧‧‧底部-抗反射-塗佈層
215‧‧‧光阻層
217‧‧‧凹穴
219‧‧‧凹穴
221a‧‧‧深度
221b‧‧‧深度
221c‧‧‧深度
221d‧‧‧深度
223‧‧‧寬度
225‧‧‧覆蓋層
227‧‧‧覆蓋層
本發明揭露藉由在該附加描繪中之圖式之例子而作說明，並且並非用以限定，並且其中相同的元件符號意指類似的元件，並且其中：第1A圖為在例示性的積體電路裝置中之各種材料層之横截面圖式；第1B及1C圖說明在例示性的積體電路裝置中具有孔隙之結構之横截面圖式；以及第2A至2I圖，依據例示性的實施例，概要性說明用於減少在積體電路裝置中之凹穴之深寬比及能夠 無缺陷地填充該凹穴之製造流程。
在下文的說明中，為了解釋之目的，將提出各種特定的細節以提供例示性的實施例之完整的瞭解。然而，顯然該例示性實施例可不以這些特定細節實施或者以等效的配置實施。在其它例子中，眾所周知的結構及裝置係以方塊圖形式顯示，以避免非必要地模糊例示性實施例。此外，除非另外指示，否則該說明書及申請專利範圍內所使用之所有表示數量、比例及要素之數字性質、反應條件等等的數字應當理解為在所有例子中以名詞”大約”來做修飾。
本發明揭露著重及解決在以個別的材料填充凹穴時所伴隨之在積體電路裝置中之凹穴內有孔隙及不規則的間隙之問題。本發明揭露著重及解決此類問題，例如(但不限於)藉由移除在該積體電路中之一層或一層以上之材料以減少在基板中之凹穴之深寬比(例如，深度)，使得該凹穴可以個別的材料填充並且在該填充中不會具有孔隙或間隙。
第2A至2I圖係依據例示性實施例，概要地說明用於減少在積體電路裝置中之凹穴之深寬比及能夠無缺陷地填充該凹穴之製造流程。
第2A圖說明包含該主動區域及可用諸如鎢之材料形成之閘極接觸103a至103d之該層間介電層101。在平坦化(例如，藉由化學機機械研磨製程)該接觸達到 該層間介電層101之該上表面之後，如第2B圖所示，釕(Ru)保護覆蓋層201a至201d可以選擇性地沉積在該鎢接觸103a至103d之上表面上。該釕覆蓋層201a至201d之沉積可以藉由使用熱化學氣相沉積製程。在第2C圖中，蝕刻終止層105為形成在該層間介電層101之上表面及該釕覆蓋層201a至201d之上表面上。接著，形成層間介電層107(例如，諸如氧碳氮化矽之低k介電材料)。金屬線路溝槽及導通孔將形成於該層間介電層107之內及穿越該層間介電層107。接著，第一介電質硬遮罩(DHM1)層109、金屬硬遮罩層111、第二介電質硬遮罩(DHM2)層203、旋塗式硬遮罩層205及用於蝕刻轉移及反射控制之抗反射塗佈層(例如，氮氧化矽)207為連續地形成於該層間介電層107之上方。
在第2D圖中，各種可獲得的積體電路製造流程(例如，微影-蝕刻雙圖案化)可被用來產生用於金屬線路溝槽圖案化之凹穴209。接著，該旋塗式硬遮罩層205及抗反射塗佈硬遮罩層207可以移除。在第2E圖中，另一個旋塗式硬遮罩層205可以沉積在該凹穴209中及該第二介電質硬遮罩層203之剩餘區段之上表面上。額外的材料層(例如，氮氧化矽層211)、底部-抗反射-塗佈(BARC，Bottom-AntiReflective-Coating)層213及光阻層215為個別地形成於該旋塗式硬遮罩層205之上表面上而用於導通孔圖案化。
在第2F圖中，各種積體電路製造流程可被用 以產生凹穴217及219，其中該凹穴217(例如，金屬線路溝槽)可以延伸進入該層間介電層107中。該凹穴219(例如，導通孔)可以延伸較深入，穿越該層間介電層107，到達該釕覆蓋層201c及201d並曝露出該釕覆蓋層201c及201d之上表面。在金屬線路溝槽217及導通孔219之完全蝕刻期間，該第二介電質硬遮罩層203之剩餘區段、旋塗式硬遮罩層205、氮氧化矽層211、底部-抗反射-塗佈層213及光阻215將被移除而留下該金屬硬遮罩層111之區段於該堆疊之頂部上。如圖所示，凹穴217可以位在221a之深度及223之寬度。同樣地，凹穴219可以結合221b之深度及類似於寬度223之寬度。
在第2G圖中，各種積體電路製造製程(例如，濕式蝕刻)可被用來蝕刻及移除該金屬硬遮罩層111之剩餘區段及每一個該釕覆蓋層201c及201d之上方部分而留下部分釕覆蓋層225及227。應該留意的是使用於該蝕刻製程之化學物可能以較快於該釕覆蓋層201c及201d(例如，低於1奈米/分鐘)的速率(例如，320奈米/分鐘)蝕刻該金屬硬遮罩/氮化鈦層111；因此，即使在蝕刻移除該氮化鈦層111之後，該部分釕覆蓋層225及227仍然存在以保護該鎢接觸103c及103d。如圖所示，第2F圖之該氮化鈦層111之移除可以減少從221a至221c之凹穴217之深度，該深度可以減少對於該凹穴之深寬比達到一定百分比(例如，17%)。同樣地，凹穴219之深度可以減少從221b至221d之深度，該深度可以減少對於該凹穴之深寬 比達到關聯的百分比(例如，11%)。在第2H圖中，薄阻障金屬或種子層119為形成在該介電質硬遮罩層109之該剩餘區段之上表面上以及形成在包含有側壁於其中之該凹穴217及219中；然而，該部分釕覆蓋層225及227之上表面仍然維持曝露而不具有阻障金屬或種子層119在其上表面上。接著，金屬層113藉由電化學電鍍(ECP，ElectroChemical Plating)形成於該阻障金屬或種子層119之上表面上之該凹穴217及219及溝槽中。該金屬層113可以與該部分釕覆蓋層225及227形成直接接觸。在第2I圖中，該金屬層113之上方部分及該第一介電質硬遮罩層109之剩餘區段為藉由平坦化(例如，化學機械研磨)而被移除達到該層間介電層107之上表面而留下以該金屬層113之剩餘部分填充之該凹穴217及219。
應該留意的是，可以使用其它典型的材料及積體電路製造製程。該製程可以使用於所有金屬層及接觸層，其中該導通孔底部可以是鎢或銅。
本發明揭露之實施例可以達到數種技術上的功效，包含減少在基板中之凹穴之深寬比，使得能夠用個別的材料無缺陷地填充該凹穴，以及保護導通孔底部免受濕式氮化鈦移除。再者，該實施例具有在各種工業應用上之利用性，例如，微處理器、智慧手機、行動裝置、移動手持裝置、數位視訊轉換盒、數位多功能影音光碟燒錄器及播放器、汽車導航、印表機及週邊、網路及電路設備、遊戲機系統、數位相機或使用邏輯或高電壓技術節點之其 它裝置。本發明揭露因此在各種類型的高度積體化半導體裝置中享有產業利用性，包含使用靜態隨機存取記憶體單元(例如，液晶顯示器(LCD，Liquid Crystal Display)驅動器、同步隨機存取記憶體(SRAM，Synchronous Random Access Memories)、數位處理器等等)之裝置，尤是是用於22奈米技術節點裝置及更超越的技術。
在先前的描述中，本發明揭露參考本發明之特定地例示性實施例做描述。然而，顯而易見的是各種修正及變更可以據以實施而不會脫離本發明揭露之較廣義的精神及範疇，如同在該申請專利範圍中所提出的。該說明書及圖式因此應視為說明之目的並且不在於限定。應該瞭解的是本發明揭露能夠使用各種其它的組合及實施例並且如同在此所陳述之本發明概念之範疇內能夠做任何變更或修正。

Claims (20)

  1. 一種製造積體電路的方法，該方法包括：提供主動區域及閘極接觸於第一層間介電層(ILD，Interlayer Dielectric)中；形成選擇性保護覆蓋層於該主動區域及閘極接觸之上表面上；形成第二層間介電層於該選擇性保護覆蓋層之上表面上及該第一層間介電層之上表面上；形成硬遮罩堆疊於該第二層間介電層上；在該第二層間介電層及硬遮罩堆疊中，形成曝露出一個或多個保護覆蓋層之凹穴；在該硬遮罩堆疊中移除選擇性層以減少該凹穴之深度；以及以金屬層填充該凹穴，其中，在一個或多個凹穴中之該金屬層連接至經曝露的該一個或多個保護覆蓋層之上表面。
  2. 如申請專利範圍第1項之方法，包括在形成該選擇性保護覆蓋層之前，執行化學機械研磨(CMP，Chemical Mechanical Polishing)。
  3. 如申請專利範圍第1項之方法，包括在形成該第二層間介電層之前，形成蝕刻終止層。
  4. 如申請專利範圍第1項之方法，其中，該硬遮罩堆疊之形成包括：形成第一介電質硬遮罩(DHM1，Dielectric Hard-Mask)層、金屬硬遮罩(MHM，Metal Hard-Mask)層、第二介電質硬遮罩(DHM2，Dielectric Hard-Mask)層、旋塗式硬遮罩(SOH，Spin-On Hard-Mask)層及抗反射塗佈(Anti-Reflective Coating，ARC)硬遮罩層。
  5. 如申請專利範圍第4項之方法，其中，該選擇性層包含該金屬硬遮罩層、該第二介電質硬遮罩層、該旋塗式硬遮罩層及該抗反射塗佈硬遮罩層。
  6. 如申請專利範圍第4項之方法，更包括：在形成該金屬層之前，共形地形成阻障金屬或種子層於該第一介電質硬遮罩層及該第二層間介電層之曝露表面上。
  7. 如申請專利範圍第4項之方法，更包括：移除經曝露的一個或多個該選擇性保護覆蓋層之上方部分。
  8. 如申請專利範圍第7項之方法，其中，該金屬硬遮罩層的移除速率較快於經曝露的一個或多個該選擇性保護覆蓋層之該上方部分的移除速率。
  9. 如申請專利範圍第4項之方法，包括在以該金屬層填充之後，執行化學機械研磨到達該第二層間介電層之上表面。
  10. 如申請專利範圍第1項之方法，其中，該選擇性保護覆蓋層包括釕覆蓋層。
  11. 如申請專利範圍第1項之方法，其中，該主動區域及閘極接觸為以鎢填充之凹穴。
  12. 如申請專利範圍第1項之方法，其中，該凹穴包含互連導通孔及溝槽。
  13. 如申請專利範圍第1項之方法，其中，該金屬層包括銅，該方法更包括藉由電化學電鍍(ECP，ElectroChemical Plating)以該銅填充該凹穴。
  14. 一種積體電路裝置，包括：主動區域及閘極接觸，係於第一層間介電層(ILD，InterLayer Dielectric)中；選擇性保護覆蓋層，係在該主動區域及閘極接觸之上表面上；第二層間介電層，係在該選擇性保護覆蓋層之上表面上及該第一層間介電層之上表面上；以及導通孔，係穿越該第二層間介電層到達該選擇性保護覆蓋層。
  15. 如申請專利範圍第14項之積體電路裝置，更包括金屬線路溝槽，係於該第二層間介電層中。
  16. 如申請專利範圍第14項之積體電路裝置，更包括蝕刻終止層，係在該第二層間介電層下方。
  17. 如申請專利範圍第14項之積體電路裝置，其中，該選擇性保護覆蓋層包括釕。
  18. 一種製造積體電路的方法，該方法包括：提供主動區域及閘極接觸於第一層間介電層(ILD，Interlayer Dielectric)中；形成選擇性保護覆蓋層於該主動區域及閘極接觸 之上表面上；形成第二層間介電層於該選擇性保護覆蓋層之上表面上及該第一層間介電層之上表面上；形成硬遮罩堆疊於該第二層間介電層上，其中，該硬遮罩包含第一介電質硬遮罩(DHM1，Dielectric Hard-Mask)層、金屬硬遮罩(MHM，Metal Hard-Mask)層、第二介電質硬遮罩(DHM2，Dielectric Hard-Mask)層、旋塗式硬遮罩(SOH，Spin-On Hard-Mask)層及抗反射塗佈(Anti-Reflective Coating，ARC)硬遮罩層；在該第二層間介電層及硬遮罩堆疊中，形成曝露出一個或多個保護覆蓋層之凹穴；在該硬遮罩堆疊中移除選擇性層以減少該凹穴之深度，其中，該選擇性層包含該金屬硬遮罩層、該第二介電質硬遮罩層、該旋塗式硬遮罩層及該抗反射塗佈硬遮罩層；以金屬層填充該凹穴，其中，在一個或多個凹穴中之該金屬層連接至經曝露的該一個或多個保護覆蓋層之上表面；以及在形成該金屬層之前，共形地形成阻障金屬或種子層於該第一介電質硬遮罩層及第二層間介電層之曝露表面上。
  19. 如申請專利範圍第18項之方法，更包括：移除經曝露的一個或多個該選擇性保護覆蓋層之上方部分。
  20. 如申請專利範圍第18項之方法，其中，該選擇性保護蓋包括釕覆蓋層，該主動區域及閘極接觸為以鎢填充之凹穴，以及其中，該金屬硬遮罩層的移除速率較快於經曝露的該一個或多個保護覆蓋層之該上方部分的移除速率。
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