WO2018195408A1 - Self-aligned via process flow - Google Patents

Self-aligned via process flow Download PDF

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Publication number
WO2018195408A1
WO2018195408A1 PCT/US2018/028548 US2018028548W WO2018195408A1 WO 2018195408 A1 WO2018195408 A1 WO 2018195408A1 US 2018028548 W US2018028548 W US 2018028548W WO 2018195408 A1 WO2018195408 A1 WO 2018195408A1
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WO
WIPO (PCT)
Prior art keywords
dielectric material
fill metal
dielectric
metal
deposition
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PCT/US2018/028548
Other languages
French (fr)
Inventor
Gaurav THAREJA
Gill Lee
Praburam Gopalraja
Abhijit Basu MALLIK
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Micromaterials Llc
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Publication of WO2018195408A1 publication Critical patent/WO2018195408A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

Processing methods may be performed to form semiconductor structures that may include self-aligned via structures. The methods may include depositing a first dielectric material on the semiconductor substrate. The first dielectric material may be selectively deposited on a second dielectric material relative to exposed regions of fill metal. The methods may further include subsequently depositing a cap material over the fill metal. The cap material may be selectively deposited on the fill metal relative to exposed regions of the first dielectric material.

Description

SELF- ALIGNED VIA PROCESS FLOW
RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Application No. 62/487,714, filed April 20, 2017, the disclosure of which is hereby incorporated by reference in its entirety for all purposes.
TECHNICAL FIELD
[0002] The present technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to systems and methods for selectively etching and selectively depositing material layers on a semiconductor device.
BACKGROUND
[0003] Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods for removal of exposed material. Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers, or thinning lateral dimensions of features already present on the surface. Often it is desirable to have an etch process that etches one material faster than another facilitating, for example, a pattern transfer process or individual material removal. Such an etch process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etch processes have been developed with a selectivity towards a variety of materials. Deposition processes, however, continue to be performed across substrates generally utilizing a blanket coat or a conformal fill.
[0004] As device sizes continue to shrink in next-generation devices, selectivity may play a larger role when only a few nanometers of material are formed in a particular layer, especially when the material is critical in the transistor formation. Many different etch process selectivities have been developed between various materials, although standard selectivities may no longer be suitable at current and future device scale. Additionally, queue times for processes continue to rise based on the number of masking, formation, and removal operations needed to form and protect the various critical dimensions of features across a device while patterning and formation are performed elsewhere on a substrate.
[0005] Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present technology.
SUMMARY
[0006] Processing methods may be performed to form semiconductor structures that may include self-aligned via structures. The methods may include depositing a first dielectric material on the semiconductor substrate. The first dielectric material may be selectively deposited on a second dielectric material relative to exposed regions of fill metal. The methods may further include subsequently depositing a cap material over the fill metal. The cap material may be selectively deposited on the fill metal relative to exposed regions of the first dielectric material. [0007] In some embodiments, the fill metal may be or include copper or cobalt. The first dielectric material may be or include silicon oxycarbide, silicon nitride, tungsten oxide, or aluminum oxide, and the second dielectric material may be or include silicon oxide. The cap material may be or include a metal nitride or a metal oxide. The method may be performed without conducting a reactive ion etching operation. The first dielectric material deposition may be performed with a selectivity towards the second dielectric material relative to the fill metal greater than or about 2: 1. The cap material deposition may be performed with a selectivity towards the fill metal relative to the first dielectric material greater than or about 2: 1. In some embodiments, the methods may further include depositing a third dielectric material on exposed regions of the fill metal. The third dielectric material may be selectively deposited on the fill metal relative to the first dielectric material and the second dielectric material.
[0008] The present technology also encompasses methods of forming a semiconductor structure. The methods may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a processing chamber. The methods may include contacting a semiconductor substrate with effluents of the plasma. The semiconductor substrate may be housed in a processing region of the processing chamber. The methods may include selectively etching a fill metal below a height of exposed regions of a first dielectric material on the semiconductor substrate. The methods may also include subsequently depositing a cap material over the fill metal. The cap material may be selectively deposited on the fill metal relative to exposed regions of the first dielectric material. [0009] In embodiments, the methods may also include depositing a second dielectric material. The second dielectric material may be selectively deposited on the fill metal relative to the cap material and the first dielectric material. The cap material may be or include a different material from the second dielectric material. The cap material may be selected from the group consisting of a carbon-containing material, a nitrogen-containing material, and an oxygen-containing material. The second dielectric material may be selected from the group consisting of a carbon- containing material, a nitrogen-containing material, and an oxygen-containing material. The second dielectric material may be different from the cap material in embodiments. The oxygen- containing materials may be or include silicon oxide, tungsten oxide, or aluminum oxide. The etching may be performed in a first processing chamber, and the depositing may be performed in a second processing chamber. The methods may further include transferring the semiconductor substrate from the first processing chamber to the second processing chamber. In embodiments, the transferring may be performed without breaking vacuum. The etching may be performed with a selectivity towards the fill metal relative to the first dielectric material greater than or about 10: 1. The deposition may be performed with a selectivity towards the fill metal relative to the first dielectric material greater than or about 2: 1.
[0010] The present technology also encompasses methods of forming a semiconductor structure. The methods may include depositing a first metal over a fill metal. The first metal may be selectively deposited on the fill metal relative to exposed regions of a first dielectric material. The methods may also include subsequently depositing a cap material over the first metal. The cap material may be selectively deposited on the first metal relative to exposed regions of the first dielectric material. In embodiments, the methods may also include depositing a second dielectric material. The second dielectric material may be selectively deposited on the first metal relative to the first dielectric material.
[0011] Such technology may provide numerous benefits over conventional systems and techniques. For example, the processes may protect critical dimensions by utilizing techniques that do not include a reactive ion etch, and provide improved selectivity. Additionally, by performing selective operations, fewer masking and removal operations may be performed, which may reduce fabrication queue times dramatically. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the below description and attached figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [0013] FIG. 1 shows a top plan view of an exemplary processing system according to embodiments of the present technology.
[0014] FIG. 2A shows a schematic cross-sectional view of an exemplary processing chamber according to embodiments of the present technology.
[0015] FIG. 2B shows a detailed view of an exemplary faceplate according to embodiments of the present technology.
[0016] FIG. 3 shows a bottom plan view of an exemplary showerhead according to embodiments of the present technology.
[0017] FIG. 4 shows a schematic cross-sectional view of an exemplary processing chamber according to embodiments of the present technology. [0018] FIG. 5 shows selected operations in a method of forming a semiconductor structure according to embodiments of the present technology.
[0019] FIGS. 6A-6E show schematic cross-sectional views of exemplary substrates according to embodiments of the present technology.
[0020] FIG. 7 shows selected operations in a method of forming a semiconductor structure according to embodiments of the present technology.
[0021] FIGS. 8A-8E show schematic cross-sectional views of exemplary substrates according to embodiments of the present technology. [0022] FIG. 9 shows selected operations in a method of forming a semiconductor structure according to embodiments of the present technology.
[0023] FIGS. 10A-10F show schematic cross-sectional views of exemplary substrates according to embodiments of the present technology. [0024] Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes. [0025] In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter.
DETAILED DESCRIPTION
[0026] The present technology includes systems and components for semiconductor processing of small pitch features. In traditional self-aligned formation processes, materials on a substrate may be formed and etched next to structures having similar or different materials that are to be maintained. Because cap layers and spacers may be formed of similar materials, such as silicon nitride, for example, the etching processes to remove these layers may not provide sufficient selectivity relative to other critical features. During various opening processes, the multiple critical dimension sizes may cause a loading effect to etch beyond budget availability of material. For example, traditional processes may include a mask layer followed by a reactive-ion etch ("RIE") process that allows opening of the structure for a gap fill layer. Despite being a relatively anisotropic process, the RIE etch may still have selectivity causing sidewall losses. Although budgeting for this loss may be considered during formation, such as with over- formation of material, because regions within the structure being etched have different dimensions, calculating for the amount of loss in one area may not be suitable for the amount of loss in a larger area. Accordingly, although 5 nm of loss may occur in one section that is budgeted, loss in a larger section of 6-7 nm may still occur, causing mismatches during fabrication.
[0027] Additionally, RIE processes produce an etch byproduct or polymer residue that is generally removed with a wet etching process. This wet etch often over-etches sidewall protection layers beyond critical dimensions, which can cause problems with formation and spacing of adjacent transistor layers, and further etches low-k nitride spacers and inter-layer dielectric oxide. Moreover, the removal of metal materials and dielectrics is often performed with an anisotropic etch that may further reduce exposed regions of cap materials and spacer materials in other regions, unless additional masking or protective layers are formed. Because the selectivity of such RIE removal may be in the range of 10: 1, the amount of masking required may be substantial.
[0028] Deposition of both masking material and other material layers may be performed in conventional technologies that utilizes either a blanket coating of material or a conformal development of material across all exposed areas on a semiconductor substrate. These types of deposition may require further patterning and removal operations that can substantially increase queue times for the device fabrication. Between the additional operations and deficiencies of RIE removal, and the multiple operations utilized in conventional deposition, queue times may be increased by hours for individual device layers. Additionally, in order to access vias with fill metal that interconnects layers of structure, while maintaining particular structure lines within each layer, additional patterning and lithography may be needed. When not performed sufficiently, subsequent via formation may misalign with underlying vias, and may cause shorting with other metal layers.
[0029] The present technology overcomes these issues by modifying the processes for removal and formation. By utilizing selective etch processes performed in particular equipment, the processes may be utilized to etch at higher selectivity than conventional RIE, which may allow additional patterning operations that may not previously have been capable, and may provide additional protection to critical feature dimensions. Additionally, by performing selective deposition operations in particular equipment, reduced masking, patterning, and removal may be utilized in the structure formation. These processes may enable particular masking to be used to protect certain metal lines, while exposing vias and forming landings in between individual device layers. Additionally, by removing many of the patterning operations and utilizing alternative etching, these processes may save hours over conventional processes utilizing RIE and standard deposition. [0030] Although the remaining disclosure will routinely identify specific etching and deposition processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other etching, deposition, and cleaning processes as may occur in the described chambers. Accordingly, the technology should not be considered to be so limited as for use with the described etching and deposition processes alone. The disclosure will discuss one possible system and chambers that can be used with the present technology to perform certain of the removal and deposition operations before describing operations of an exemplary process sequence according to the present technology.
[0031] FIG. 1 shows a top plan view of one embodiment of a processing system 100 of deposition, etching, baking, and curing chambers according to embodiments. In the figure, a pair of front opening unified pods (FOUPs) 102 supply substrates of a variety of sizes that are received by robotic arms 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f, positioned in tandem sections 109a- c. A second robotic arm 1 10 may be used to transport the substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes and selective deposition described herein in addition to cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etch, pre-clean, degas, orientation, and other substrate processes.
[0032] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing and/or etching a dielectric film on the substrate wafer. In one configuration, two pairs of the processing chambers, e.g., 108c-d and 108e-f, may be used to deposit dielectric material or metal-containing material on the substrate, and the third pair of processing chambers, e.g., 108a-b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to etch a dielectric film on the substrate. Any one or more of the processes described may be carried out in chamber(s) separated from the fabrication system shown in different embodiments.
[0033] In some embodiments the chambers specifically include at least one etching chamber as described below as well as at least one deposition chamber as described below. By including these chambers in combination on the processing side of the factory interface, all etching and deposition processes discussed below may be performed in a controlled environment. For example, a vacuum environment may be maintained on the processing side of holding area 106, so that all chambers and transfers are maintained under vacuum in embodiments. This may also limit water vapor and other air components from contacting the substrates being processed. It will be appreciated that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are contemplated by system 100.
[0034] FIG. 2A shows a cross-sectional view of an exemplary process chamber system 200 with partitioned plasma generation regions within the processing chamber. During film etching, e.g., titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, poly silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxy carbide, etc., a process gas may be flowed into the first plasma region 215 through a gas inlet assembly 205. A remote plasma system (RPS) 201 may optionally be included in the system, and may process a first gas which then travels through gas inlet assembly 205. The inlet assembly 205 may include two or more distinct gas supply channels where the second channel (not shown) may bypass the RPS 201, if included.
[0035] A cooling plate 203, faceplate 217, ion suppressor 223, showerhead 225, and a substrate support 265, having a substrate 255 disposed thereon, are shown and may each be included according to embodiments. The pedestal 265 may have a heat exchange channel through which a heat exchange fluid flows to control the temperature of the substrate, which may be operated to heat and/or cool the substrate or wafer during processing operations. The wafer support platter of the pedestal 265, which may comprise aluminum, ceramic, or a combination thereof, may also be resistively heated in order to achieve relatively high temperatures, such as from up to or about 100°C to above or about 1100°C, using an embedded resistive heater element. [0036] The faceplate 217 may be pyramidal, conical, or of another similar structure with a narrow top portion expanding to a wide bottom portion. The faceplate 217 may additionally be flat as shown and include a plurality of through-channels used to distribute process gases.
Plasma generating gases and/or plasma excited species, depending on use of the RPS 201, may pass through a plurality of holes, shown in FIG. 2B, in faceplate 217 for a more uniform delivery into the first plasma region 215.
[0037] Exemplary configurations may include having the gas inlet assembly 205 open into a gas supply region 258 partitioned from the first plasma region 215 by faceplate 217 so that the gases/species flow through the holes in the faceplate 217 into the first plasma region 215.
Structural and operational features may be selected to prevent significant backflow of plasma from the first plasma region 215 back into the supply region 258, gas inlet assembly 205, and fluid supply system 210. The faceplate 217, or a conductive top portion of the chamber, and showerhead 225 are shown with an insulating ring 220 located between the features, which allows an AC potential to be applied to the faceplate 217 relative to showerhead 225 and/or ion suppressor 223. The insulating ring 220 may be positioned between the faceplate 217 and the showerhead 225 and/or ion suppressor 223 enabling a capacitively coupled plasma (CCP) to be formed in the first plasma region. A baffle (not shown) may additionally be located in the first plasma region 215, or otherwise coupled with gas inlet assembly 205, to affect the flow of fluid into the region through gas inlet assembly 205. [0038] The ion suppressor 223 may comprise a plate or other geometry that defines a plurality of apertures throughout the structure that are configured to suppress the migration of ionically- charged species out of the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 into an activated gas delivery region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may comprise a perforated plate with a variety of aperture configurations. These uncharged species may include highly reactive species that are transported with less reactive carrier gas through the apertures. As noted above, the migration of ionic species through the holes may be reduced, and in some instances completely suppressed. Controlling the amount of ionic species passing through the ion suppressor 223 may advantageously provide increased control over the gas mixture brought into contact with the underlying wafer substrate, which in turn may increase control of the deposition and/or etch characteristics of the gas mixture. For example, adjustments in the ion concentration of the gas mixture can significantly alter its etch selectivity, e.g., SiNx:SiOx etch ratios, Si:SiOx etch ratios, etc. In alternative embodiments in which deposition is performed, it can also shift the balance of conformal-to-flowable style depositions for dielectric materials. [0039] The plurality of apertures in the ion suppressor 223 may be configured to control the passage of the activated gas, i.e., the ionic, radical, and/or neutral species, through the ion suppressor 223. For example, the aspect ratio of the holes, or the hole diameter to length, and/or the geometry of the holes may be controlled so that the flow of ionically-charged species in the activated gas passing through the ion suppressor 223 is reduced. The holes in the ion suppressor 223 may include a tapered portion that faces the plasma excitation region 215, and a cylindrical portion that faces the showerhead 225. The cylindrical portion may be shaped and dimensioned to control the flow of ionic species passing to the showerhead 225. An adjustable electrical bias may also be applied to the ion suppressor 223 as an additional means to control the flow of ionic species through the suppressor. [0040] The ion suppressor 223 may function to reduce or eliminate the amount of ionically charged species traveling from the plasma generation region to the substrate. Uncharged neutral and radical species may still pass through the openings in the ion suppressor to react with the substrate. It should be noted that the complete elimination of ionically charged species in the reaction region surrounding the substrate may not be performed in embodiments. In certain instances, ionic species are intended to reach the substrate in order to perform the etch and/or deposition process. In these instances, the ion suppressor may help to control the concentration of ionic species in the reaction region at a level that assists the process.
[0041] Showerhead 225 in combination with ion suppressor 223 may allow a plasma present in first plasma region 215 to avoid directly exciting gases in substrate processing region 233, while still allowing excited species to travel from chamber plasma region 215 into substrate processing region 233. In this way, the chamber may be configured to prevent the plasma from contacting a substrate 255 being etched. This may advantageously protect a variety of intricate structures and films patterned on the substrate, which may be damaged, dislocated, or otherwise warped if directly contacted by a generated plasma. Additionally, when plasma is allowed to contact the substrate or approach the substrate level, the rate at which oxide species etch may increase. Accordingly, if an exposed region of material is oxide, this material may be further protected by maintaining the plasma remotely from the substrate.
[0042] The processing system may further include a power supply 240 electrically coupled with the processing chamber to provide electric power to the faceplate 217, ion suppressor 223, showerhead 225, and/or pedestal 265 to generate a plasma in the first plasma region 215 or processing region 233. The power supply may be configured to deliver an adjustable amount of power to the chamber depending on the process performed. Such a configuration may allow for a tunable plasma to be used in the processes being performed. Unlike a remote plasma unit, which is often presented with on or off functionality, a tunable plasma may be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow
development of particular plasma characteristics such that precursors may be dissociated in specific ways to enhance the etching profiles produced by these precursors.
[0043] A plasma may be ignited either in chamber plasma region 215 above showerhead 225 or substrate processing region 233 below showerhead 225. In embodiments, the plasma formed in substrate processing region 233 may be a DC biased plasma formed with the pedestal acting as an electrode. Plasma may be present in chamber plasma region 215 to produce the radical precursors from an inflow of, for example, a fluorine-containing precursor or other precursor. An AC voltage typically in the radio frequency (RF) range may be applied between the conductive top portion of the processing chamber, such as faceplate 217, and showerhead 225 and/or ion suppressor 223 to ignite a plasma in chamber plasma region 215 during deposition. An RF power supply may generate a high RF frequency of 13.56 MHz but may also generate other frequencies alone or in combination with the 13.56 MHz frequency.
[0044] FIG. 2B shows a detailed view 253 of the features affecting the processing gas distribution through faceplate 217. As shown in FIGS. 2A and 2B, faceplate 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas supply region 258 into which process gases may be delivered from gas inlet 205. The gases may fill the gas supply region 258 and flow to first plasma region 215 through apertures 259 in faceplate 217. The apertures 259 may be configured to direct flow in a substantially unidirectional manner such that process gases may flow into processing region 233, but may be partially or fully prevented from backflow into the gas supply region 258 after traversing the faceplate 217. [0045] The gas distribution assemblies such as showerhead 225 for use in the processing chamber section 200 may be referred to as dual channel showerheads (DCSH) and are additionally detailed in the embodiments described in FIG. 3. The dual channel showerhead may provide for etching processes that allow for separation of etchants outside of the processing region 233 to provide limited interaction with chamber components and each other prior to being delivered into the processing region.
[0046] The showerhead 225 may comprise an upper plate 214 and a lower plate 216. The plates may be coupled with one another to define a volume 218 between the plates. The coupling of the plates may be so as to provide first fluid channels 219 through the upper and lower plates, and second fluid channels 221 through the lower plate 216. The formed channels may be configured to provide fluid access from the volume 218 through the lower plate 216 via second fluid channels 221 alone, and the first fluid channels 219 may be fluidly isolated from the volume 218 between the plates and the second fluid channels 221. The volume 218 may be fluidly accessible through a side of the gas distribution assembly 225. [0047] FIG. 3 is a bottom view of a showerhead 325 for use with a processing chamber according to embodiments. Showerhead 325 may correspond with the showerhead 225 shown in FIG. 2A. Through-holes 365, which show a view of first fluid channels 219, may have a plurality of shapes and configurations in order to control and affect the flow of precursors through the showerhead 225. Small holes 375, which show a view of second fluid channels 221, may be distributed substantially evenly over the surface of the showerhead, even amongst the through-holes 365, and may help to provide more even mixing of the precursors as they exit the showerhead than other configurations.
[0048] Turning to FIG. 4 is shown a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology. The system 400 may include a load lock chamber 10 and a processing chamber 20. The processing chamber 20 may be generally a sealable enclosure, which may be operated under vacuum, or at least low pressure. The processing chamber 20 may be isolated from the load lock chamber 10 by an isolation valve 15. The isolation valve 15 may seal the processing chamber 20 from the load lock chamber 10 in a closed position and may allow a substrate 60 to be transferred from the load lock chamber 10 through the valve to the processing chamber 20 and vice versa in an open position.
[0049] The system 400 may include a gas distribution plate 30 capable of distributing one or more gases across a substrate 60. The gas distribution plate 30 may be any suitable distribution plate known to those skilled in the art, and specific gas distribution plates described should not be taken as limiting the scope of the technology. The output face of the gas distribution plate 30 may face the first surface 61 of the substrate 60.
[0050] The gas distribution plate 30 may include a plurality of gas ports configured to transmit one or more gas streams to the substrate 60 and a plurality of vacuum ports disposed between each gas port and configured to transmit the gas streams out of the processing chamber 20. As illustrated in FIG. 4, the gas distribution plate 30 may include a first precursor injector 420, a second precursor injector 430 and a purge gas injector 440. The injectors 420, 430, 440 may be controlled by a system computer (not shown), such as a mainframe, or by a chamber-specific controller, such as a programmable logic controller. The precursor injector 420 may be configured to inject a continuous or pulse stream of a reactive precursor of compound A into the processing chamber 20 through a plurality of gas ports 425. The precursor injector 430 may be configured to inject a continuous or pulse stream of a reactive precursor of compound B into the processing chamber 20 through a plurality of gas ports 435. The purge gas injector 440 may be configured to inject a continuous or pulse stream of a non-reactive or purge gas into the processing chamber 20 through a plurality of gas ports 445. The purge gas may be configured to remove reactive material and reactive by-products from the processing chamber 20. The purge gas may typically be an inert gas, such as nitrogen, argon or helium. Gas ports 445 may be disposed in between gas ports 425 and gas ports 435 so as to separate the precursor of compound A from the precursor of compound B, thereby avoiding cross-contamination between the precursors.
[0051] In another aspect, a remote plasma source (not shown) may be connected to the precursor injector 420 and the precursor injector 430 prior to injecting the precursors into the processing chamber 20. The plasma of reactive species may be generated by applying an electric field to a compound within the remote plasma source. Any power source that is capable of activating the intended compounds may be used. For example, power sources using DC, radio frequency, and microwave based discharge techniques may be used. If an RF power source is used, it can be either capacitively or inductively coupled. The activation may also be generated by a thermally based technique, a gas breakdown technique, a high intensity light source, such as ultraviolet light, or exposure to an x-ray source. [0052] The system 400 may further include a pumping system 450 connected to the processing chamber 20. The pumping system 450 may be generally configured to evacuate the gas streams out of the processing chamber 20 through one or more vacuum ports 455. The vacuum ports 455 may be disposed between each gas port so as to evacuate the gas streams out of the processing chamber 20 after the gas streams react with the substrate surface and to further limit cross- contamination between the precursors.
[0053] The system 400 may include a plurality of partitions 460 disposed on the processing chamber 20 between each port. A lower portion of each partition may extend close to the first surface 61 of substrate 60, such as, for example, about 0.5 mm or greater from the first surface 61. In this manner, the lower portions of the partitions 460 may be separated from the substrate surface by a distance sufficient to allow the gas streams to flow around the lower portions toward the vacuum ports 455 after the gas streams react with the substrate surface. Arrows 498 indicate the direction of the gas streams. Since the partitions 460 may operate as a physical barrier to the gas streams, they may also limit cross contamination between the precursors. The arrangement shown is merely illustrative and should not be taken as limiting the scope of the technology. It will be understood by those skilled in the art that the gas distribution system shown is merely one possible distribution system and that other types of showerheads may be employed.
[0054] In operation, a substrate 60 may be delivered, such as by a robot, to the load lock chamber 10 and may be placed on a shuttle 65. After the isolation valve 15 is opened, the shuttle 65 may be moved along the track 70. Once the shuttle 65 enters in the processing chamber 20, the isolation valve 15 may close, sealing the processing chamber 20. The shuttle 65 may then be moved through the processing chamber 20 for processing. In one embodiment, the shuttle 65 may be moved in a linear path through the chamber.
[0055] As the substrate 60 moves through the processing chamber 20, the first surface 61 of substrate 60 may be repeatedly exposed to the precursor of compound A coming from gas ports 425 and the precursor of compound B coming from gas ports 435, with the purge gas coming from gas ports 445 in between. Injection of the purge gas may be designed to remove unreacted material from the previous precursor prior to exposing the substrate surface 61 to the next precursor. After each exposure to the various gas streams, the gas streams may be evacuated through the vacuum ports 455 by the pumping system 450. Since a vacuum port may be disposed on both sides of each gas port, the gas streams may be evacuated through the vacuum ports 455 on both sides. Thus, the gas streams may flow from the respective gas ports vertically downward toward the first surface 61 of the substrate 60, across the first surface 410 and around the lower portions of the partitions 460, and finally upward toward the vacuum ports 455. In this manner, each gas may be uniformly distributed across the substrate surface 61. Substrate 60 may also be rotated while being exposed to the various gas streams. Rotation of the substrate may be useful in preventing the formation of strips in the formed layers. Rotation of the substrate may be continuous or in discreet steps.
[0056] The extent to which the substrate surface 61 is exposed to each gas may be determined by, for example, the flow rates of each gas coming out of the gas port and the rate of movement of the substrate 60. In one embodiment, the flow rates of each gas may be configured so as not to remove adsorbed precursors from the substrate surface 61. The width between each partition, the number of gas ports disposed on the processing chamber 20, and the number of times the substrate may be passed back and forth may also determine the extent to which the substrate surface 61 is exposed to the various gases. Consequently, the quantity and quality of a deposited film may be optimized by varying the above-referenced factors.
[0057] In another embodiment, the system 400 may include a precursor injector 420 and a precursor injector 430, without a purge gas injector 440. Consequently, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 may be alternately exposed to the precursor of compound A and the precursor of compound B, without being exposed to purge gas in between.
[0058] The embodiment shown in FIG. 4 has the gas distribution plate 30 above the substrate. While the embodiments have been described and shown with respect to this upright orientation, it will be understood that the inverted orientation is also possible. In that situation, the first surface 61 of the substrate 60 may face downward, while the gas flows toward the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 may be positioned to heat the second side of the substrate.
[0059] In some embodiments, the shuttle 65 may be susceptor 66 for carrying the substrate 60. Generally, the susceptor 66 may be a carrier which helps to form a uniform temperature across the substrate. The susceptor 66 may be movable in both directions left-to-right and right-to-left, relative to the arrangement of FIG. 4, between the load lock chamber 10 and the processing chamber 20. The susceptor 66 may have a top surface 67 for carrying the substrate 60. The susceptor 66 may be a heated susceptor so that the substrate 60 may be heated for processing. As an example, the susceptor 66 may be heated by radiant heat source 90, a heating plate, resistive coils, or other heating devices, disposed underneath the susceptor 66. Although illustrated as a lateral transition, embodiments of system 400 may also be utilized in a rotationally based system in which a wheel may rotate clockwise or counter-clockwise to successively treat one or more substrates positioned under the gas distribution system illustrated. Additional modifications are similarly understood to be encompassed by the present technology. [0060] FIG. 5 illustrates a method 500 of forming a semiconductor structure, many operations of which may be performed, for example, in the chambers 200 and 400 as previously described. Method 500 may include one or more operations prior to the initiation of the method, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include a number of optional operations as denoted in the figure, which may or may not be specifically associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below. Method 500 describes the operations shown schematically in FIGS. 6A-6E, the illustrations of which will be described in conjunction with the operations of method 500. It is to be understood that FIG. 6 illustrates only partial schematic views, and a substrate may contain any number of transistor sections having aspects as illustrated in the figures.
[0061] Method 500 may involve operations performed on a substrate having multiple exposed regions, such as on a substrate including regions to be further developed in producing a self- aligned via structures. As illustrated in FIG. 6A, a portion of a processed substrate 600 is shown including an etch stop layer 605, interlay er dielectric 610, and fill metal 615. The fill metal 615 may include lines 615b and 615c, which may be metal interconnects within a single layer. The fill metal may also include material in through-silicon vias, like fill metal 615a, which may extend between structural layers on the substrate. The materials may have been formed in prior operations, and may have been polished to a specific height exposing fill metal 615 and interlay er dielectric 610 on a top surface of the substrate. The operations of method 500 may be performed to limit or eliminate masking operations, RIE processes including ashing and cleaning, and may reduce process queue times for providing a cap material during production of a self-aligned via structure. The process may also provide additional protection to fill metal 615b and fill metal 615c.
[0062] Method 500 may initially include recessing fill metal 615 as illustrated in FIG. 6A. The fill metal 615 may be recessed in an etching chamber similar to chamber 200 previously described. Once positioned within a processing region of the semiconductor processing chamber, the method may include forming a plasma of a fluorine-containing precursor in a remote plasma region of the processing chamber at operation 505. The remote plasma region may be fluidly coupled with the processing region, although it may be physically partitioned to limit plasma at the substrate level, which may damage exposed structures or materials. Effluents of the plasma may be flowed into the processing region, where they may contact the
semiconductor substrate at operation 510. At operation 515, the fill metal material may be selectively etched below a height of the exposed regions of interlay er dielectric 610.
[0063] At optional operation 520, the substrate may be transferred from the etching chamber to a deposition chamber. The transfer may occur under vacuum, and the two chambers may both reside on the same cluster tool to allow the transfer to occur in a controlled environment. For example, vacuum conditions may be maintained during the transfer, and the transfer can occur without breaking vacuum. Once in the deposition chamber, such as chamber 400 described above, a cap material may be formed or deposited over the recessed fill metal 615 at operation 525. As illustrated in FIG. 6B, cap material 620 may be formed directly on or contacting recessed fill metal 615. The deposition operation may be a selective deposition in which the cap material is formed preferentially on the fill metal 615 relative to exposed interlay er dielectric 610. As opposed to conventional technologies that may include additional masking operations, operation 525 may be performed directly subsequent etching operation 515.
[0064] Although transfer of the substrate may occur, no other substrate processing may be performed between the selective etching and the selective deposition. As will be explained in further detail below, the selective deposition may include multiple operations, but the entire deposition process may be performed directly after the etching set of operations, although substrate transfer in between the operations may be performed in embodiments. By performing a selective etch and a selective deposition according to the method 500, queue times may be substantially reduced over conventional technology that may require additional masking and removal techniques due to blanket deposition or formation of the cap material 620. Method 500 may not utilize any RJE operations, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE. Additionally, as further explained below, the etching may be performed at higher or much higher selectivities than RIE, which may reduce critical dimension loss on the gate spacers, and may reduce or eliminate masking of the gate spacers and contact dielectrics.
[0065] Following deposition of cap material 620, optional operation 530 may be performed to selectively remove cap material 620 from metal lines that do not extend through layers of the structure, such as fill metal 615b and 615c, as illustrated in FIG. 6C. This operation may include a lithography operation to cover line 615a, and other interconnect materials across a substrate, while leaving other cap material exposed. Once this has been performed, cap material 620 that is still exposed may be removed selectively from the substrate, while minimal or no material is removed from interlayer dielectric 610. Operation 530 may then expose fill metal 615b and 615c, which may be metal lines within a layer of a structure.
[0066] Method 500 may also include depositing an additional dielectric material on the exposed fill metal 615b and 615c. A second dielectric material 625 may then be deposited over the exposed fill metal 615 at operation 535, as illustrated in FIG. 6D. Operation 535 may also involve a selective deposition where second dielectric material 625 is preferentially deposited on the exposed fill metal 615b and 615c, while having limited to no deposition on dielectric materials, including exposed portions of interlayer dielectric 610 and cap material 620. A contact landing 630 may then be formed in operation 540. The operation may include removing remaining cap material 620. Based on the previous operations, cap material 620 may only remain overlying fill metal 615a, which may be the interconnect metal extending between layers of the structure. Removal of the cap material 620 may expose the underlying fill metal, which may be extended into landing 630. The cap material 620 removal may involve either a selective etch of cap material 620 relative to second dielectric material 625 and interlay er dielectric 610, or may involve an additional lithographic removal. Additionally, the extension of fill metal 615 to contact landing 630 may include a selective deposition of metal material. Because fill metal 615b and 615c may not be exposed due to second dielectric material 625, the metal may be deposited selectively on metal relative to dielectric material. Additional deposition including electroplating and other metal fill deposition may be performed as well.
[0067] A variety of materials may be utilized in the processing, and the etching and deposition may be selective to multiple components. Accordingly, the present technology may not be limited to a single set of materials. For example, fill metal 615 may be several conductive species utilized in semiconductor processing. Fill metal 615 may be or include copper, cobalt, or any other conductive metal that may perform as a fill metal or interconnect metal. Interlay er dielectric 610 may be or include silicon oxide, although other insulative materials may be used. Cap material 620 may include an insulative material, and may include a silicon-containing material, a nitrogen containing material, an oxygen-containing material, a carbon-containing material, or some combination of these materials, such as silicon nitride, silicon oxycarbide, tungsten oxide, aluminum oxide, or other materials. Second dielectric material 625 may also include an insulative material, and may also include a silicon-containing material, a nitrogen containing material, an oxygen-containing material, a carbon-containing material, or some combination of these materials, such as silicon nitride, silicon oxycarbide, tungsten oxide, aluminum oxide, or other materials. [0068] Because the cap material 620 may be exposed during the selective deposition of the second dielectric material 625, the cap material 620 may be a different material than the second dielectric material in embodiments, although the two materials may be similar in additional embodiments. Although being different materials, both cap material 620 and second dielectric material 625 may be one or more materials selected from the group of materials including a carbon-containing material, a nitrogen-containing material, and an oxygen-containing material, and may be any of the materials noted above. However, the cap material 620 may be a different material from that utilized for second dielectric material 625.
[0069] The fill metal etching operations may involve additional precursors along with particular fluorine-containing precursors. Nitrogen trifluoride may be utilized to generate plasma effluents in some embodiments. Additional or alternative fluorine-containing precursors may also be utilized. For example, a fluorine-containing precursor may be flowed into the remote plasma region and the fluorine-containing precursor may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, sulfur hexafluoride, and xenon difluoride. The remote plasma region may be within a distinct module from the processing chamber or a compartment within the processing chamber. As illustrated in FIG. 2, both RPS unit 201 and first plasma region 215 may be utilized as the remote plasma region. An RPS may allow dissociation of plasma effluents without damage to other chamber components, while first plasma region 215 may provide a shorter path length to the substrate during which recombination may occur.
[0070] An additional precursor may also be delivered to the remote plasma region to augment the fluorine-containing precursor. For example, a carbon-and-hydrogen-containing precursor or a hydrogen precursor may be delivered with the fluorine-containing precursor. The additional precursor may also be a fluorine-containing precursor, such as methyl fluoride, for example. The hydrogen-containing or carbon-and-hydrogen-containing precursor may be included to maintain a particular H:F atomic ratio for the plasma effluents. In embodiments the etching may be performed with an H:F ratio greater than 1, which may provide increased selectivity towards tungsten or other metals relative to dielectric materials discussed above. The H:F atomic flow ratio may be maintained greater than 2: 1 or greater than 3 : 1 in embodiments, which may be controlled by adjusting relative flow rates of the fluorine-containing precursor and the hydrogen- containing precursor.
[0071] The selective etching of cap material 620 may be performed relative to interlayer dielectric 610, and may use similar or different precursors from those used in the selective etch of fill metal 615 at operation 515. For example, although the materials may be any as described previously, cap material 620 may be or include silicon nitride in an embodiment and interlayer dielectric 610 may be or include silicon oxide. The selective etch of silicon nitride relative to silicon oxide may utilize a fluorine-containing precursor as previously described, and may also include an oxygen-containing precursor. The oxygen-containing precursor may be delivered to the remote plasma region with the fluorine-containing precursor, or the oxygen-containing precursor may bypass the remote plasma region and be delivered directly into the processing region. In some embodiments, the cap material 620 etching operation may not include a hydrogen-containing precursor during the etch, and may be performed in a hydrogen-free environment.
[0072] The etching operations may be performed below about 10 Torr in embodiments, and may be performed below or about 5 Torr in embodiments. The process may also be performed at a temperature below about 100° C in embodiments, and may be performed below about 50° C. As performed in chamber 200, or a variation on this chamber, or in a different chamber capable of performing similar operations, the process may remove portions of fill metal 615 selective to interlay er dielectric 610. The operations may also remove portions of cap material 620 selective to interlay er dielectric 610.
[0073] The etch selectivity of fill metals such as copper, cobalt, tungsten, or other metals relative to other components exposed on the surface of the substrate when the present methods are performed may be greater than or about 10: 1, greater than or about 20: 1, greater than or about 50: 1, or greater than or about 100: 1, or more, for a variety of materials formed on the substrate, and which may be exposed to plasma effluents. The etch selectivity of fill metal relative to (poly)silicon may be greater than or about 100: 1, greater than or about 150: 1, greater than or about 200: 1 or greater than or about 250: 1 in disclosed embodiments. The etch selectivity of fill metal relative to silicon oxide may be greater than or about 15: 1, greater than or about 25: 1, greater than or about 30: 1 or greater than or about 40: 1 in embodiments. The etch selectivity of fill metal relative to silicon oxy carbide may be greater than or about 10: 1, greater than or about 20: 1, greater than or about 30: 1, or greater than or about 40: 1 in embodiments. The etch selectivity of fill metal relative to other oxides may be greater than or about 10: 1, greater than or about 20: 1, greater than or about 50: 1 or greater than or about 100: 1 in
embodiments. [0074] Accordingly, depending on the feature sizes, fill metal may be removed from the surface of the substrate while the other exposed materials may be reduced by less than 1 nm. For example, the feature width between fill metal lines may be less than or about 100 nm, and may be less including between about 10 nm and about 30 nm. The depth of the recess for the fill metal 615 may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less in embodiments. The amount of fill for the selective deposition operations may be to a height within any of these ranges. Because of this depth of etching, a minimal amount of interlayer dielectric may be removed, which may be less than or about 3 nm, less than or about 1 nm, less than or about 0.5 nm, or the materials may be substantially or essentially maintained. Accordingly, the fill metal etch relative to any exposed dielectric materials may be characterized by any of the selectivities discussed above for the materials that may be utilized for each structure.
[0075] The selective deposition may be performed in a chamber capable of deposition, and which may be capable of atomic layer deposition, including chamber 400 as described above. The deposition may be premised on selectively depositing an insulative material on a metal material relative to another insulative material. For example, the cap material 620 may be formed substantially on fill metal 615, while being minimally formed or limited from interlayer dielectric 610. The selective deposition may be performed by multiple operations, which may include formation of a self-assembled monolayer to facilitate selective deposition, or may include actively inhibiting formation of dielectric on other dielectric materials.
[0076] Self-assembled monolayers may be formed on regions of the structure to tune deposition. For example, a first self-assembled monolayer may be formed over the structure, and then exposed to a lithographic mask to remove the monolayer from fill metal 615. The monolayer may be maintained over interlayer dielectric 610. The monolayer may have termination moieties that may repel or fail to interact with later delivered precursors. For example, the termination moieties may be hydrophobic in embodiments, and may terminate with hydrogen-containing moieties, such as methyl groups, which may not interact with additional precursors. A second self-assembled monolayer may be formed over the fill metal 615, which may be hydrophilic or reactive with one or more precursors utilized to produce cap material 620. The second self-assembled monolayer may be formed selectively over the fill metal 615, as the material may be repelled from the first self-assembled monolayer, or may be drawn selectively to the metal. The second self-assembled monolayer may terminate with hydroxyl or other hydrophilic moieties, or with moieties that interact specifically with additional precursors used to form cap material 620. [0077] An atomic layer deposition may then be performed utilizing two or more precursors to develop cap material 620. The precursors of the deposition may include a metal-containing precursor and a precursor configured to interact with the moieties terminating the second self- assembled monolayer, but not the first self-assembled monolayer. For example, when hydrophilic and hydrophobic terminating monolayers are utilized, one of the atomic layer deposition precursors may include water. In this way, the deposition may not form over the first self-assembled monolayer, which may be hydrophobic. If the cap material includes a metal oxide, such as tungsten oxide or aluminum oxide, the precursors used in the atomic layer deposition may include a tungsten-containing precursor or an aluminum-containing material, as well as water. In other embodiments silicon-containing precursors may be used. The water may then fail to interact with the first self-assembled monolayer formed over the interlay er dielectric 610 during the half reaction with water, and thus the deposition will not form over the first self- assembled monolayer. In this way, the cap material 620 may be selectively formed over the fill metal 615 without a mask layer being formed that may be chemically etched.
[0078] After cap material 620 has been formed to a suitable height, the first self-assembled monolayer may be exposed to UV light and removed from the substrate, or some other removal may be performed. Accordingly, the first self-assembled monolayer may be formed directly subsequent the selective etch of the metal gate, or after transfer to an additional chamber but before additional process operations, and an additional masking layer that requires chemical removal or etching may not be utilized on the structure. Similarly an etch of cap material 620, which may also require additional masking, may not be necessary subsequent the selective deposition to ensure the cap material 620 is formed selectively over the metal gate material. In this way, multiple operations utilized in conventional formation may be obviated, which may reduce queue times significantly, such as by hours. In other embodiments a slight recess may be performed subsequent the selective deposition to remove residual material from interlayer dielectric 610, depending on the operations performed. [0079] Embodiments may also utilize an inhibitor to form cap material 620 selectively over fill metal 615, while not forming cap material 620 over interlay er dielectric 610. For example, a sprayed inhibitor may be applied across a surface of the substrate, which may apply along a top surface of the substrate, but which may not penetrate within recessed portions of the substrate. The inhibitor may be any number of materials that may be characterized by a siloxane backbone, such as silicone, or a tetrafluoroethylene backbone, such as PTFE, along with other oil or surfactant materials. The material may be applied across the surface of the substrate to cover exposed portions of interlay er dielectric 610. By use of a spray or coating application, the material may not be applied within recessed portions of the substrate, and may not contact fill metal 615. Cap material 620 may then be formed, such as by atomic layer deposition or other vapor deposition or physical deposition mechanisms.
[0080] The inhibitor material may prevent adhesion or adsorption of the material, which may form or deposit normally on fill metal 615. Subsequent formation of cap material 620, a removal agent may be applied to the substrate to remove the inhibitor material. The removal agent may be a wet etchant, reactant, or surfactant cleanser that may remove residual inhibitor material exposing the underlying interlay er dielectric 610. Accordingly, the inhibitor may be applied directly subsequent the selective etch, or subsequent transfer of the substrate, but prior to other process operations affecting the substrate. Utilizing an inhibitor may allow formation of the cap material in a defined region that need not be defined via subsequent patterning and/or etching of a blanket film. By removing prior and subsequent patterning operations, the processes may further reduce queue times over conventional processes.
[0081] The inhibitor may also be a product of a plasma application that may neutralize or render inert a surface of the substrate. For example, a modifying plasma may be formed from one or more precursors, which may include inert precursors. The plasma may be applied to a surface of the substrate, which may alter a top surface of a substrate, but which may not penetrate within recessed portions of the substrate. For example, a nitrogen-containing precursor, which may be nitrogen, may be delivered to a plasma processing region of a processing chamber, where a plasma is generated. The plasma effluents, which may include nitrogen-containing plasma effluents, may be delivered to a substrate, and may form a nitrogenized surface along the exposed portions of the substrate along a top surface, which may include interlay er dielectric 610.
[0082] The plasma effluents may not be delivered, or may not flow, within recessed portions of the substrate, which may maintain a neat or unreacted surface of fill metal 615. Cap material 620 may then be formed with one or more deposition techniques, which may include atomic layer deposition or other vapor or physical deposition. For example, an atomic layer deposition technique may be utilized subsequent processing with the plasma effluents. After each cycle of the deposition, a nitrogen-containing plasma may be reapplied to a surface region of the substrate, such as over interlay er dielectric 610. In this way, the surface of interlay er dielectric 610 may be passivated to prevent or limit formation of cap material 620 over those regions. Utilizing these plasma effluents on non-recessed portions of the substrate may allow formation of the cap material in a defined region that need not be defined via subsequent patterning and/or etching of a blanket film. By removing prior and subsequent patterning operations, the processes may further reduce queue times over conventional processes. [0083] Any of these techniques may selectively deposit or form dielectric or insulative materials over a metal-containing region relative to one or more non-metal, dielectric, or insulative regions. The selectivity may be complete in that the cap material forms only over fill metal 615, or an intervening layer, and cap material may not form at all over interlay er dielectric regions. In other embodiments the selectivity may not be complete, and may be in a ratio of deposition on metal-containing materials relative to dielectric or insulative materials greater than about 2: 1. The selectivity may also be greater than or about 5: 1, greater than or about 10: 1, greater than or about 15: 1, greater than or about 20: 1, greater than or about 25: 1, greater than or about 30: 1, greater than or about 35: 1, greater than or about 40: 1, greater than or about 45: 1, greater than or about 50: 1, greater than or about 75: 1, greater than or about 100: 1, greater than or about 200: 1, or more. The cap material may be formed to a height described previously, which may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less. Accordingly, selectivities below 50: 1 may be acceptable to fully deposit cap material 620 while forming a limited amount or essentially not forming material over the interlay er dielectric material 610. [0084] The deposition operations may be performed at any of the temperature or pressures previously described, and may be performed at temperatures greater than or about 50° C, and may be performed greater than or about 100° C, greater than or about 150° C, greater than or about 200° C, greater than or about 250° C, greater than or about 300° C, greater than or about 350° C, greater than or about 400° C, greater than or about 450° C, greater than or about 500° C, or higher. For example, temperatures greater than or about 100° C may be utilized during atomic layer deposition operations in order to activate precursors to interact with one another as layers of material are being formed.
[0085] The present technology additionally encompasses techniques for forming a contact landing and/or a self-aligned via utilizing selective etching and selective deposition. Similar to the techniques described previously, the processes may not utilize reactive-ion etching or the associated operations of ashing or cleaning, which may damage delicate features, and may increase queue times. FIG. 7 illustrates a method 700 of forming a semiconductor structure, many operations of which may be performed, for example, in the chambers 200 and 400 as previously described. Method 700 may include one or more operations prior to the initiation of the method, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The etching processes, deposition processes, and many of the materials from method 700 may be similar to those discussed above with regard to method 500, and any of the operations, materials, or parameters discussed above may be utilized or included within method 700 as will be discussed below.
[0086] The method may include a number of optional operations as denoted in the figure, which may or may not be specifically associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation, but are not critical to the technology, or may be performed by alternative methodology including utilizing any of the selective deposition techniques described above. Method 700 describes the operations shown schematically in FIGS. 8A-8E, the illustrations of which will be described in conjunction with the operations of method 700. It is to be understood that FIG. 8 illustrates only partial schematic views, and a substrate may contain any number of transistor sections having aspects as illustrated in the figures. [0087] Method 700 may involve operations performed on a substrate having multiple exposed regions, such as on a substrate including regions to be further developed in producing self- aligned via structures. As illustrated in FIG. 8A, a portion of a processed substrate 800 is shown including an etch stop layer 805, interlay er dielectric 810, and fill metal 815. The fill metal 815 may include lines 815b and 815c, which may be metal wiring or interconnects within a single layer. The fill metal may also include material in through-silicon vias, like fill metal 815a, which may be an interconnect that extends between structural layers on the substrate. The materials may have been formed in prior operations, and may have been polished to a specific height exposing fill metal 815 and interlayer dielectric 810 on a top surface of the substrate. The operations of method 700 may be performed to limit or eliminate masking operations, RIE processes including ashing and cleaning, and may reduce process queue times for providing a cap material during production of a self-aligned via structure. The process may also provide additional protection to fill metal 815b and fill metal 815c.
[0088] Method 700 may initially include depositing a first dielectric material 820 in operation 705 as illustrated in FIG. 8 A. The first dielectric material may be deposited in a chamber similar to chamber 400 previously described. As illustrated in FIG. 8A, the first dielectric material 820 may be deposited on interlayer dielectric 810. The deposition operation may be a selective deposition in which the first dielectric material is formed preferentially on the interlayer dielectric 810 relative to exposed fill metal 815. [0089] A subsequent selective deposition of cap material 825 may be performed in operation 710, as illustrated in FIG. 8B. Cap material 825 may be selectively deposited on fill metal 615 relative to first dielectric material 820, which may otherwise cover interlayer dielectric 810. In some embodiments, portions of interlayer dielectric 810 may also be exposed, and the cap material deposition may be performed selective to those regions as well. The selective deposition may be similar to operation 525 previously described, although the operation may be modified based on the composition of first dielectric material 820. At optional operation 715, illustrated in FIG. 8C, the cap material 825 may be selectively removed from the fill metal 815b and 815c, which may be metal lines that are maintained within a single level of the structure, although any sections may be uncovered. In some embodiments, cap material 825 may be maintained over fill metal 815a, which may be an interconnect extending between layers of the structure. The removal may be similar to removal operation 530, and may include any of the operations or precursors discussed.
[0090] Method 700 may also include selectively depositing a third dielectric material 830 over exposed fill metal 815b and 815c at operation 720 illustrated in FIG. 8D. The selective deposition may deposit third dielectric material 830 preferentially on fill metal 815, and may produce minimal or no deposition on first dielectric material 820 or cap material 825, which may cover fill metal 815a. The deposition operation 720 may be similar to operation 535 previously described. Subsequently, in optional operation 725, contact landing 835 may be formed, as illustrated in FIG. 8E. Operation 725 may be similar to operation 540 discussed previously, and may include any of the techniques previously described.
[0091] A variety of materials may be utilized in the processing and may include any of the materials previously described, and the etching and deposition may be selective to multiple components. Accordingly, the present technology may not be limited to a single set of materials. For example, fill metal 815 may be several conductive species utilized in semiconductor processing. Fill metal 815 may be or include copper, cobalt, tungsten, or any other conductive metal that may perform as a fill or interconnect metal. Any of the first dielectric material, second dielectric material that may be interlay er dielectric 810, third dielectric material, and cap material may be one or more of the previously noted insulative materials. Each material may be similar or different from any other layer in embodiments. [0092] Other insulative materials may similarly be used in other embodiments, although the selective etching and deposition operations may be adjusted depending on what materials are used relative to other materials being formed or removed. The first dielectric material 820 may include an additional insulative material, and may include a metal oxide or nitride material. For example, first dielectric material 820 may be or include silicon oxide, silicon oxycarbide, silicon nitride, tungsten oxide, aluminum oxide, or other materials that may be selectively deposited over interlay er dielectric 810 relative to the chosen fill metal material. The interlay er dielectric may be silicon oxide in embodiments, and may be any other noted insulative material. In embodiments first dielectric material 820 and interlay er dielectric 810 may be the same materials, although in other embodiments they may be different from one another. Cap material 825 may also include a metal oxide or nitride material. For example, cap material 825 may be or include silicon nitride, silicon oxycarbide, silicon oxide, tungsten oxide, aluminum oxide, or other materials that may be selectively deposited over copper, cobalt, or tungsten relative to the first dielectric material 820, and potentially interlay er dielectric 810, should any remain exposed subsequent the deposition of first dielectric material 820. Third dielectric material 830 may be or include silicon nitride, silicon oxycarbide, silicon oxide, tungsten oxide, aluminum oxide, or other materials that may be selectively deposited over copper, cobalt, or tungsten relative to the first dielectric material 820 and cap material 825.
[0093] In some embodiments, first dielectric material 820, cap material 825, and third dielectric material 830 may be different from one another. Because one or more may be exposed during each deposition, different materials may be utilized to facilitate deposition relative to the other materials, although any of the three materials may be similar in additional embodiments. Although being different materials, each of first dielectric material 820, cap material 825, and third dielectric material 830 may be one or more materials selected from the group of materials including a carbon-containing material, a nitrogen-containing material, and an oxygen- containing material, and in embodiments, any of the three materials may be any of the previously noted materials, or any additional dielectric material that may be selectively deposited relative to another dielectric material.
[0094] Method 700 may be performed without any RIE processes or associated processes. Similarly the method may reduce queue times by removing many patterning and removal operations that may be performed prior to, during, or subsequent to formation in conventional processes. Additionally, the formation of third dielectric material 830 may protect fill metal 815b and 815c, which may reduce shorting during subsequent contact processes with
interconnect material or fill metal 815a. The deposition or etching processes may include any of the aspects of method 500 described above, including operating at any of the selectivities described. Additionally, the deposition processes may include any of the processes previously described, and may include operating at any of the selectivities described. By utilizing the present technology, fabrication may be performed with more selective formation and removal over conventional techniques, and may reduce queue times by hours over conventional processes. [0095] As noted, any of the previously described selective deposition techniques may be utilized in the multiple deposition operations, and may include any of the selectivities previously noted for similar or other materials. Additional selective deposition techniques may also be utilized that may include alternative mechanisms for selectively depositing a dielectric material. For example, while cap material 825 and third dielectric material 830 are deposited on a metal, such as fill metal 815, first dielectric material 820 may be deposited on another dielectric material, such as interlay er dielectric 810. For example, a self-assembled monolayer may be formed as previously described. Any of the previous termination groups may be formed on the interlayer dielectric to facilitate formation of the first dielectric material 820, while maintaining the fill metal 815 without the first dielectric material, or having a separate self-assembled monolayer deposited over fill metal 815 to repel at least one of the precursors used in the deposition. Depending on what material is being used for first dielectric material 820, the self- assembled monolayers may be tuned towards that material. Water may be used as one of the precursors, such as previously described, and the self-assembled monolayers may be structured as previously discussed, such as to include a hydroxyl-terminating material over the interlayer dielectric to facilitate formation on that material relative to the fill metal. Additionally, a nitrogen-containing material may utilized as one of the self-assembled monolayers on a material for which deposition is to occur, such as in one of the termination moieties of the monolayers, which may allow attraction of particular precursors used in the formation of one or more of the materials previously described.
[0096] Because of the structure of the metal, fill metal 815 may also be corroded or passivated to reduce activity relative to a dielectric material, which may allow increased deposition on dielectric material, such as interlayer dielectric, relative to fill metal 815. Passivation of the fill metal may include exposure of the fill metal 815 to silicon-substituted or halogen-substituted materials, which may limit deposition of dielectric materials. Oxidation of the fill metal may utilize oxygen-containing materials or halogen-containing materials, for example, which may allow preferential deposition on the dielectric material. Once oxidized, such as by exposure to an oxygen-containing material, an atomic layer deposition may be performed similarly as described, where one of the precursors may include an oxygen-containing material, which may not interact with the oxidized metal. In this way, as one example, first dielectric material may be or include silicon oxide, which may be selectively deposited on interlay er dielectric 810 relative to fill metal 815.
[0097] The selectivity may be complete in that the first dielectric material forms only over interlay er dielectric 810 and may not form at all over fill metal 815. In other embodiments the selectivity may not be complete, and may be in a ratio of deposition on dielectric or insulative materials relative to metal-containing materials greater than about 2: 1. The selectivity may also be greater than or about 5 : 1, greater than or about 10: 1, greater than or about 15 : 1, greater than or about 20: 1, greater than or about 25 : 1, greater than or about 30: 1, greater than or about 35 : 1, greater than or about 40: 1, greater than or about 45 : 1, greater than or about 50: 1, greater than or about 75 : 1, greater than or about 100: 1, greater than or about 200 : 1 , or more. Any of the dielectric materials may be formed to a height described previously, which may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less. Accordingly, selectivities below 50: 1 may be acceptable to fully deposit first dielectric material 820 while forming a limited amount or essentially not forming material over the fill metal 815.
[0098] The present technology additionally encompasses techniques for forming a contact landing and/or a self-aligned via utilizing selective etching and selective deposition. Similar to the techniques described previously, the processes may not utilize reactive-ion etching or the associated operations of ashing or cleaning, which may damage delicate features, and may increase queue times. FIG. 9 illustrates a method 900 of forming a semiconductor structure, many operations of which may be performed, for example, in the chambers 200 and 400 as previously described. Method 900 may include one or more operations prior to the initiation of the method, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The etching processes, deposition processes, and many of the materials from method 900 may be similar to those discussed above with regard to method 500 or method 700, and any of the operations, materials, or parameters discussed above may be utilized or included within method 900 as will be discussed below.
[0099] The method may include a number of optional operations as denoted in the figure, which may or may not be specifically associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation, but are not critical to the technology, or may be performed by alternative methodology including utilizing any of the selective deposition techniques described above. Method 900 describes the operations shown schematically in FIGS. 10A-10F, the illustrations of which will be described in conjunction with the operations of method 900. It is to be understood that FIG. 10 illustrates only partial schematic views, and a substrate may contain any number of transistor sections having aspects as illustrated in the figures.
[0100] Method 900 may involve operations performed on a substrate having multiple exposed regions, such as on a substrate including regions to be further developed in producing a self- aligned via structures. As illustrated in FIG. 10A, a portion of a processed substrate 1000 is shown including an etch stop layer 1005, interlay er dielectric 1010, and fill metal 1015. The fill metal 1015 may include lines 1015b and 1015c, which may be metal lines within a single layer. The fill metal may also include material in through-silicon vias, like fill metal 1015a, which may be an interconnect that extends between structural layers on the substrate. The materials may have been formed in prior operations, and may have been polished to a specific height exposing fill metal 1015 and interlay er dielectric 1010 on a top surface of the substrate. The operations of method 900 may be performed to limit or eliminate masking operations, RTE processes including ashing and cleaning, and may reduce process queue times for providing a cap material during production of a self-aligned via structure. The process may also provide additional protection to fill metal 1015b and fill metal 1015c.
[0101] Method 900 may initially include depositing a first metal 1020 in operation 905 as illustrated in FIG. 10A. The first metal may be deposited in a chamber similar to chamber 400 previously described. As illustrated in FIG. 10A, the first metal 1020 may be deposited on fill metal 1015. The deposition operation may be a selective deposition in which the first metal is formed preferentially on the exposed fill metal 1015 relative to interlay er dielectric 1010. The formation of a subsequent metal material may facilitate a separation above interlayer dielectric 1010. For example, first metal 1020 may be formed to a height of less than 20 nm, and may be formed to a height of less than or about 15 nm, less than or about 10 nm, less than or about 8 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or less in embodiments. Additionally, the first metal 1020 may be formed to any height within any of these ranges or within a smaller range encompassed within any of these stated ranges.
[0102] A subsequent selective deposition of cap material 1025 may be performed in operation 910, as illustrated in FIG. 10B. Cap material 1025 may be selectively deposited as pillars on first metal 1020 relative to interlay er dielectric 1010. The selective deposition may be similar to operation 525 previously described, although the operation may be modified based on the composition of interlay er dielectric 1010. At optional operation 915, an additional amount of interlay er dielectric 1010 may be deposited to extend the height of interlay er dielectric to the level of cap material 1025, as illustrated in FIG. IOC. In some embodiments, an additional blanket coating may be applied over the structure, followed by a polishing operation to expose cap material 1025.
[0103] At optional operation 920, illustrated in FIG. 10D, the cap material 1025 may be selectively removed from the metal fill 1015b and 1015c, which may be metal lines that are maintained within a single level of the structure, although any sections may be uncovered. In some embodiments, cap material 1025 may be maintained over first metal 1020 and fill metal 1015a, which may be an interconnect extending between layers of the structure. The removal may be similar to removal operation 530, and may include any of the operations or precursors discussed. In embodiments, additional removal of first metal 1020 may be performed to remove first metal from fill metal 1015b and 1015c. [0104] Method 900 may also include selectively depositing a second dielectric material 1030 over exposed fill metal 1015b and 1015c at operation 925 shown in FIG. 10E. The selective deposition may deposit second dielectric material 1030 preferentially on fill metal 1015, and may produce minimal or no deposition on interlay er dielectric 1010 or cap material 1025, which may cover fill metal 1015a. The deposition operation 925 may be similar to operation 535 previously described. Subsequently, in optional operation 930, contact landing 1035 may be formed as shown in FIG. 10F. Operation 930 may be similar to operation 540 discussed previously, and may include any of the techniques previously described.
[0105] A variety of materials may be utilized in the processing and may include any of the materials previously described, and the etching and deposition may be selective to multiple components. Accordingly, the present technology may not be limited to a single set of materials. For example, fill metal 1015 may be several conductive species utilized in semiconductor processing. Fill metal 1015 may be or include copper, cobalt, tungsten, or any other conductive metal that may perform as a fill or interconnect metal. Additionally, first metal 1020 may be any of the same materials, or may be different from fill metal 1015. For example, in one
embodiment, fill metal 1015 may be copper or cobalt, and first metal 1020 may be tungsten. Either of the second dielectric material or cap material may be one or more of the previously noted insulative materials. Each material may be similar or different from the other layer in embodiments.
[0106] Other insulative materials may similarly be used in other embodiments, although the selective etching and deposition operations may be adjusted depending on what materials are used relative to other materials being formed or removed. Cap material 1025 may be or include a metal oxide or nitride material. For example, cap material 1025 may be or include silicon nitride, silicon oxycarbide, silicon oxide, tungsten oxide, aluminum oxide, or other materials that may be selectively deposited over copper, cobalt, or tungsten relative to interlayer dielectric 1010. Second dielectric material 1030 may be or include silicon nitride, silicon oxycarbide, silicon oxide, tungsten oxide, aluminum oxide, or other materials that may be selectively deposited over copper, cobalt, or tungsten relative to the interlayer dielectric 1010 and cap material 1025.
[0107] In some embodiments, cap material 1025 and second dielectric material 1030 may be different from one another. Because one or more may be exposed during each deposition, different materials may be utilized to facilitate deposition relative to the other materials, although the two materials may be similar in additional embodiments. Although being different materials, each of cap material 1025 and second dielectric material 1030 may be one or more materials selected from the group of materials including a carbon-containing material, a nitrogen- containing material, and an oxygen-containing material, and in embodiments, either of the materials may be any of the previously noted materials, or any additional dielectric material that may be selectively deposited relative to another dielectric material.
[0108] Method 900 may be performed without any RIE processes or associated processes. Similarly the method may reduce queue times by removing many patterning and removal operations that may be performed prior to, during, or subsequent to formation in conventional processes. Additionally, the formation of second dielectric material 1030 may protect fill metal 1015b and 1015c, which may reduce shorting during subsequent contact processes with interconnect material or fill metal 1015a. The deposition or etching processes may include any of the aspects of method 500 or method 700 described above, including operating at any of the selectivities described. Additionally, the deposition processes may include any of the processes previously described, and may include operating at any of the selectivities described. By utilizing the present technology, fabrication may be performed with more selective formation and removal over conventional techniques, and may reduce queue times by hours over conventional processes. [0109] Again, any of the previously described selective deposition techniques may be utilized in the multiple deposition operations, and may include any of the selectivities previously noted for similar or other materials. Additional selective deposition techniques may also be utilized that may include alternative mechanisms for selectively depositing a metal material. For example, first metal 1020 may be deposited over fill metal 1015, and may utilize deposition processes particular to a metal-on-metal deposition. Any of the previously described deposition techniques may be utilized as well, including formation of self-assembled monolayers as previously described. Additionally, passivation as previously discussed may be performed. For example, interlay er dielectric 1010 may include silicon dioxide, for example, which may be treated to adjust termination groups to be silicon-containing, hydrogen-based, or halogen- containing. This may allow preferential deposition of a metal material on fill metal 1015. In still other embodiments, nitrogen containing precursors may be used as one or both of an atomic layer deposition process, which may allow preferential deposition on a metal surface relative to a silicon dioxide surface, such as may be used for interlay er dielectric 1010.
[0110] The selectivity may be complete in that the first metal forms only over fill metal 1015 and may not form at all over interlay er dielectric 1010. In other embodiments the selectivity may not be complete, and may be in a ratio of deposition on metal-containing materials relative to dielectric or insulative materials greater than about 2: 1. The selectivity may also be greater than or about 5: 1, greater than or about 10: 1, greater than or about 15: 1, greater than or about 20: 1, greater than or about 25: 1, greater than or about 30: 1, greater than or about 35: 1, greater than or about 40: 1, greater than or about 45: 1, greater than or about 50: 1, greater than or about 75: 1, greater than or about 100: 1, greater than or about 200: 1, or more. The first metal may be formed to a height described previously, which may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, less than or about 3 nm, less than or about 1 nm or less.
Accordingly, selectivities below 50: 1 may be acceptable to fully deposit first metal 1020 while forming a limited amount or essentially not forming material over the interlay er dielectric 1010. By utilizing the present technology, fabrication may be performed with more selective formation and removal over conventional techniques, and may reduce queue times by hours over conventional processes. [0111] In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.
[0112] Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology. [0113] Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included. [0114] As used herein and in the appended claims, the singular forms "a", "an", and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers, and reference to "the precursor" includes reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.
[0115] Also, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

CLAIMS: 1. A method of forming a semiconductor structure, the method comprising: depositing a first dielectric material on a semiconductor substrate, wherein the first dielectric material is selectively deposited on a second dielectric material relative to exposed regions of fill metal; and
subsequently depositing a cap material over the fill metal, wherein the cap material is selectively deposited on the fill metal relative to exposed regions of the first dielectric material.
2. The method of forming a semiconductor structure of claim 1, wherein the fill metal comprises copper or cobalt.
3. The method of forming a semiconductor structure of claim 1, wherein the first dielectric material comprises silicon oxycarbide, silicon nitride, tungsten oxide, or aluminum oxide, and wherein the second dielectric material comprises silicon oxide.
4. The method of forming a semiconductor structure of claim 1, wherein the method is performed without conducting a reactive ion etching operation.
5. The method of forming a semiconductor structure of claim 1, wherein the first dielectric material deposition is performed with a selectivity towards the second dielectric material relative to the fill metal greater than or about 2: 1, and wherein the cap material deposition is performed with a selectivity towards the fill metal relative to the first dielectric material greater than or about 2: 1.
6. The method of forming a semiconductor structure of claim 1, further comprising depositing a third dielectric material on exposed regions of the fill metal, wherein the third dielectric material is selectively deposited on the fill metal relative to the first dielectric material and the second dielectric material.
7. A method of forming a semiconductor structure, the method comprising: forming a plasma of a fluorine-containing precursor in a remote plasma region of a processing chamber; contacting a semiconductor substrate with effluents of the plasma, wherein the semiconductor substrate is housed in a processing region of the processing chamber;
selectively etching a fill metal below a height of exposed regions of a first dielectric material on the semiconductor substrate; and
subsequently depositing a cap material over the fill metal, wherein the cap material is selectively deposited on the fill metal relative to exposed regions of the first dielectric material.
8. The method of forming a semiconductor structure of claim 7, further comprising depositing a second dielectric material, wherein the second dielectric material is selectively deposited on the fill metal relative to the cap material and the first dielectric material.
9. The method of forming a semiconductor structure of claim 8, wherein the cap material comprises a different material from the second dielectric material, and wherein the cap material is selected from the group consisting of a carbon-containing material, a nitrogen- containing material, and an oxygen-containing material.
10. The method of forming a semiconductor structure of claim 9, wherein the second dielectric material is selected from the group consisting of a carbon-containing material, a nitrogen-containing material, and an oxygen-containing material, and wherein the second dielectric material is different from the cap material.
11. The method of forming a semiconductor structure of claim 7, wherein the etching is performed in a first processing chamber, and the depositing is performed in a second processing chamber.
12. The method of forming a semiconductor structure of claim 11, further comprising transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and wherein the transferring is performed without breaking vacuum.
13. The method of forming a semiconductor structure of claim 7, wherein the etching is performed with a selectivity towards the fill metal relative to the first dielectric material greater than or about 10: 1, and wherein the deposition is performed with a selectivity towards the fill metal relative to the first dielectric material greater than or about 2: 1.
14. A method of forming a semiconductor structure, the method comprising: depositing a first metal over a fill metal, wherein the first metal is selectively deposited on the fill metal relative to exposed regions of a first dielectric material; and
subsequently depositing a cap material over the first metal, wherein the cap material is selectively deposited on the first metal relative to exposed regions of the first dielectric material.
15. The method of forming a semiconductor structure of claim 14, further comprising depositing a second dielectric material, wherein the second dielectric material is selectively deposited on the first metal relative to the first dielectric material.
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