TWI778048B - Methods of forming semiconductor structures - Google Patents
Methods of forming semiconductor structures Download PDFInfo
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- TWI778048B TWI778048B TW107113498A TW107113498A TWI778048B TW I778048 B TWI778048 B TW I778048B TW 107113498 A TW107113498 A TW 107113498A TW 107113498 A TW107113498 A TW 107113498A TW I778048 B TWI778048 B TW I778048B
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- Taiwan
- Prior art keywords
- semiconductor
- silicon
- substrate
- forming
- deposition
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/301—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45544—Atomic layer deposition [ALD] characterized by the apparatus
- C23C16/45548—Atomic layer deposition [ALD] characterized by the apparatus having arrangements for gas injection at different locations of the reactor for each ALD half-reaction
- C23C16/45551—Atomic layer deposition [ALD] characterized by the apparatus having arrangements for gas injection at different locations of the reactor for each ALD half-reaction for relative movement of the substrate and the gas injectors or half-reaction reactor compartments
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Abstract
Description
本技術係關於半導體系統、處理、及裝備。更具體而言,本技術係關於用於在半導體裝置上選擇性形成材料層的系統及方法。 This technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to systems and methods for selectively forming layers of materials on semiconductor devices.
可能藉由在基板表面上產生錯綜複雜圖案化的材料層的處理來製成積體電路。在基板上產生圖案化的材料需要用於移除暴露的材料的控制方法。化學蝕刻係用於多種目的,包括將光抗蝕劑中的圖案轉移到底下的層中、減薄層、或已存在於表面上的特徵的減薄橫向尺寸。通常期望具有蝕刻一種材料比另一種更快的蝕刻處理,以促進例如圖案轉移處理或單獨材料移除。據說此種蝕刻處理對於第一材料具有選擇性。由於材料、電路、及處理的多樣性,已開發對多種材料具有選擇性的蝕刻處理。然而,通常使用毯覆塗層或保形填充而繼續跨越基板而執行沉積處理。 Integrated circuits may be fabricated by processes that produce intricately patterned layers of material on the surface of the substrate. Creating a patterned material on a substrate requires a controlled method for removing the exposed material. Chemical etching is used for a variety of purposes, including transferring patterns in photoresist into underlying layers, thinning layers, or thinning lateral dimensions of features already present on a surface. It is often desirable to have an etch process that etches one material faster than another to facilitate, for example, a pattern transfer process or individual material removal. This etching process is said to be selective to the first material. Due to the variety of materials, circuits, and processes, etching processes that are selective for a variety of materials have been developed. Typically, however, the deposition process continues across the substrate using blanket coating or conformal fill.
隨著裝置尺寸在下一代裝置中持續縮小,當形成於特定層中的材料只有幾奈米時,選擇性可以發揮更大的作用(特別是當材料為電晶體形成中的關鍵時)。各種材料之間已開發許多不同的蝕刻處理選擇性,但是標準選擇性可能不再適用於當前及未來的裝置規模。此外,基於形成及保護跨越裝置的特徵的各種關鍵尺寸所需的遮罩、形成、及移除操作的數量,處理的佇列時間繼續增加,同時在基板上的其他處執行圖案化及形成。As device dimensions continue to shrink in next-generation devices, selectivity can play a greater role when the material formed in a given layer is only a few nanometers (especially when the material is critical in transistor formation). Many different etch process selectivities have been developed between various materials, but standard selectivities may no longer apply at current and future device scales. Furthermore, based on the number of masking, forming, and removing operations required to form and protect various critical dimensions of features across the device, queue time for processing continues to increase while patterning and forming are performed elsewhere on the substrate.
因此,需要一種可用於生產高品質的裝置及結構改善的系統及方法。本技術解決了這些及其他需求。Accordingly, there is a need for a system and method that can be used to produce high quality devices and structural improvements. The present technology addresses these and other needs.
可以執行處理方法來形成可包括減少接觸電阻的結構的半導體結構。該方法可包括以下步驟:在半導體基板上沉積第一半導體材料。第一半導體材料可以相對於第二含矽材料而選擇性沉積在第一含矽材料上。該等方法亦可包括以下步驟:在半導體基板上沉積第二半導體材料。第二半導體材料可以相對於第一半導體材料而選擇性沉積在第二含矽材料上。Processing methods may be performed to form semiconductor structures that may include structures that reduce contact resistance. The method may include the steps of depositing a first semiconductor material on a semiconductor substrate. The first semiconductor material may be selectively deposited on the first silicon-containing material relative to the second silicon-containing material. The methods may also include the step of depositing a second semiconductor material on the semiconductor substrate. The second semiconductor material may be selectively deposited on the second silicon-containing material relative to the first semiconductor material.
在一些實施例中,第一半導體材料可以相對於半導體基板的NMOS區域而沉積在半導體基板的PMOS區域上。第一半導體材料可以包括鍺,而第一含矽材料可以包括鍺化矽。第二含矽材料可以包括磷。該方法可以在不進行活性離子蝕刻操作的情況下執行。可以利用第一含矽材料相對於第二含矽材料大於或約2:1的選擇性來執行第一半導體材料沉積。沉積可以相對於半導體基板的PMOS區域而發生在半導體基板的NMOS區域上。可以執行該方法,而並未在PMOS區域上形成光阻。第一半導體材料可以包括銦,而第一含矽材料可以包括磷化矽。第二含矽材料可以包括鍺。第一半導體材料可以是砷化銦鎵,或包括砷化銦鎵。In some embodiments, the first semiconductor material may be deposited on the PMOS region of the semiconductor substrate relative to the NMOS region of the semiconductor substrate. The first semiconductor material may include germanium, and the first silicon-containing material may include silicon germanium. The second silicon-containing material may include phosphorous. The method can be performed without a reactive ion etching operation. The first semiconductor material deposition may be performed with a selectivity of the first silicon-containing material relative to the second silicon-containing material greater than or about 2:1. The deposition may occur on the NMOS region of the semiconductor substrate relative to the PMOS region of the semiconductor substrate. The method can be performed without forming a photoresist on the PMOS region. The first semiconductor material may include indium, and the first silicon-containing material may include silicon phosphide. The second silicon-containing material may include germanium. The first semiconductor material may be indium gallium arsenide, or include indium gallium arsenide.
附加地,本技術亦包括一種形成半導體結構的方法。該方法可包括以下步驟:在第一半導體材料上沉積第一合金材料。合金材料可以相對於氮化物材料或氧化物材料而選擇性沉積於第一半導體材料上。該方法亦可以包括以下步驟:隨後在第二半導體材料上沉積第二合金材料。第二合金材料可以相對於氮化物材料或氧化物材料而選擇性沉積在第二半導體材料上。Additionally, the present technology also includes a method of forming a semiconductor structure. The method may include the step of depositing a first alloy material on the first semiconductor material. The alloy material may be selectively deposited on the first semiconductor material relative to the nitride material or the oxide material. The method may also include the step of subsequently depositing a second alloy material on the second semiconductor material. The second alloy material may be selectively deposited on the second semiconductor material relative to the nitride material or the oxide material.
在一些實施例中,第一合金材料可以沉積在位於半導體基板的NMOS區域中的含銦材料上。第二合金材料可以沉積在位於半導體基板的PMOS區域中的含鍺材料上。氮化物材料可以包括氮化矽,而氧化物材料可以包括氧化矽、碳氧化矽、或金屬氧化物。金屬氧化物可以是氧化鎢或氧化鋁,或包括氧化鎢或氧化鋁。該方法可以在不進行活性離子蝕刻操作的情況下執行。第二合金材料可以是含鎳材料,或包括含鎳材料。第二合金材料可以是鎳矽鍺,或包括鎳矽鍺。第一合金材料可以是含鈦材料,或包括含鈦材料。第一合金材料可以是鈦矽氮化物,或包括鈦矽氮化物。In some embodiments, the first alloy material may be deposited on the indium-containing material in the NMOS region of the semiconductor substrate. The second alloy material may be deposited on the germanium-containing material in the PMOS region of the semiconductor substrate. Nitride materials may include silicon nitride, and oxide materials may include silicon oxide, silicon oxycarbide, or metal oxides. The metal oxide may be or include tungsten oxide or aluminum oxide. The method can be performed without a reactive ion etching operation. The second alloy material may be, or include, a nickel-containing material. The second alloy material may be nickel-silicon-germanium, or include nickel-silicon-germanium. The first alloy material may be, or include, a titanium-containing material. The first alloy material may be titanium silicon nitride, or include titanium silicon nitride.
此類技術可以提供優於習知系統及技術的許多益處。舉例而言,處理可以藉由利用不包括活性離子蝕刻的技術來保護關鍵尺寸,並提供改善的選擇性。此外,藉由執行選擇性操作,可以執行更少的遮罩及移除操作,這可以顯著減少製造佇列時間。結合以下描述及隨附圖式,更詳細地描述這些及其他實施例以及其許多優點及特徵。Such techniques may provide many benefits over conventional systems and techniques. For example, processing can protect critical dimensions and provide improved selectivity by utilizing techniques that do not include reactive ion etching. Furthermore, by performing selective operations, fewer masking and removal operations can be performed, which can significantly reduce manufacturing queue time. These and other embodiments, along with their many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.
本發明的技術包括用於小節距特徵的半導體處理的系統及部件。在傳統的矽化處理中,可以利用光阻阻擋PMOS區域與NMOS區域,而處理其他區域。舉例而言,因為跨越基板的幾種材料可以由類似的材料形成(例如,氮化矽或氧化矽),所以用於移除這些材料以及移除在區域內形成的材料的蝕刻處理可能無法提供相對於其他關鍵特徵的足夠的選擇性。在各種打開處理期間,多個臨界尺寸的大小可能造成負載效應,而蝕刻超過材料的預算可用性。舉例而言,傳統處理可以包括遮罩層,隨後是允許間隙填充層的結構的開口的活性離子蝕刻(「RIE」)處理。儘管RIE蝕刻係為相對各向異性處理,但是RIE蝕刻仍可能具有造成側壁損失的選擇性。儘管可能考慮對於形成期間的此損失進行預算(例如,利用材料的過度形成),但是因為所蝕刻的結構內的區域具有不同的尺寸,因此針對一個區域的損失量的計算可能並不適合針對更大區域的損失量。因此,儘管在預算的一個區段中可能出現5nm的損失,但是仍可能出現6-7nm的較大區段的損失,而造成製造期間的不匹配。The techniques of the present invention include systems and components for semiconductor processing of fine pitch features. In the conventional silicidation process, photoresist can be used to block the PMOS region and the NMOS region, while other regions are processed. For example, because several materials across the substrate may be formed of similar materials (eg, silicon nitride or silicon oxide), the etching process used to remove these materials and remove the material formed in the region may not provide Sufficient selectivity relative to other key features. During various opening processes, multiple critical dimension sizes can cause loading effects that etch over budget availability of materials. For example, a conventional process may include a mask layer followed by a reactive ion etching ("RIE") process that allows opening of the structure of the gapfill layer. Although RIE etch is a relatively anisotropic process, RIE etch may still have selectivity that causes sidewall loss. Although it is possible to consider budgeting for this loss during formation (eg, with over-formation of material), because the regions within the etched structure are of different sizes, the calculation of the amount of loss for one region may not be appropriate for larger area losses. Thus, while a 5nm loss may occur in one segment of the budget, a larger segment of 6-7nm may still be lost, creating a mismatch during manufacturing.
此外,RIE處理產生蝕刻副產物或聚合物殘留物(通常利用濕式蝕刻處理移除)。此濕式蝕刻經常將側壁保護層過度蝕刻而超過臨界尺寸(這會造成相鄰電晶體層的形成及間隔問題),並進一步蝕刻低k氮化物間隔物以及層間介電氧化物。此外,通常利用各向異性蝕刻進行金屬材料與介電質的移除,除非形成附加遮罩或保護層,否則可能進一步減少其他區域中的蓋材料與間隔物材料的暴露區域。由於這種RIE移除的選擇性可能在10:1的範圍內,因此所需的遮罩量可能很大。Additionally, the RIE process produces etch by-products or polymer residues (usually removed using wet etch processes). This wet etch often overetches the sidewall protection layer beyond the critical dimension (which can cause formation and spacing problems for adjacent transistor layers), and further etches low-k nitride spacers and interlayer dielectric oxides. In addition, metal and dielectric removal is typically performed using anisotropic etching, which may further reduce the exposed areas of cap and spacer materials in other areas unless additional masks or protective layers are formed. Since the selectivity of such RIE removal may be in the range of 10:1, the amount of masking required may be large.
在利用跨越半導體基板上的所有暴露區域的材料的毯覆塗層或材料的共形發生的習知技術中,可以進行遮罩材料與其他材料層二者的沉積。該等類型的沉積可能需要進一步的圖案化與移除操作,這會顯著增加裝置製造的佇列時間。在RIE移除的附加操作及缺陷與習知沉積中使用的多種操作之間,單獨裝置層的佇列時間可能增加幾小時。Deposition of both mask material and other material layers can be performed in conventional techniques utilizing blanket coating of material or conformal occurrence of material across all exposed areas on a semiconductor substrate. These types of depositions may require further patterning and removal operations, which can significantly increase the queue time for device fabrication. Between the additional operations and defects of RIE removal and the various operations used in conventional depositions, the queue time of individual device layers may increase by several hours.
本技術藉由修改用於移除及形成的處理而克服這些問題。藉由在特定裝備中執行選擇性沉積操作,可以在結構形成中利用經減少的遮罩、圖案化、及移除。此外,也可以選擇性完成可以執行的移除操作。藉由使用選擇性沉積及利用替代蝕刻來移除許多圖案化操作,相較於利用RIE與標準沉積的習知處理,該等處理可以節省數小時。The present technology overcomes these problems by modifying the process for removal and formation. By performing selective deposition operations in specific equipment, reduced masking, patterning, and removal can be utilized in structure formation. In addition, the removal operations that can be performed can also be done selectively. By using selective deposition and utilizing alternative etching to remove many patterning operations, these processes can save hours compared to conventional processes utilizing RIE and standard deposition.
儘管其餘的揭示將常規地識別利用所揭示的技術的特定的蝕刻及沉積處理,但應理解,系統及方法同樣適用於所描述的腔室中可能發生的各種其他的蝕刻、沉積、及清潔處理。因此,該技術不應視為受限於僅能用於所述的蝕刻及沉積處理。本揭示將討論可以與本技術一起使用的一個可能的系統及腔室,以在根據本技術的示例性處理序列的所描述操作之前執行某些移除及沉積操作。While the remainder of the disclosure will routinely identify specific etching and deposition processes utilizing the disclosed techniques, it should be understood that the systems and methods are equally applicable to various other etching, deposition, and cleaning processes that may occur in the described chambers . Therefore, this technique should not be considered limited to only the etch and deposition processes described. This disclosure will discuss one possible system and chamber that may be used with the present technology to perform certain removal and deposition operations prior to the described operations of an exemplary processing sequence in accordance with the present technology.
第 1 圖
圖示根據實施例的沉積、蝕刻、烘焙、及固化腔室的處理系統100的一個實施例的頂視平面圖。在圖式中,一對前開式晶圓盒(FOUP)102供應各種尺寸的基板,各種尺寸的基板係由機器臂104接收,並在放置到位於串聯區段109a-c中的基板處理腔室108a-f中之一者之前,放置到低壓托持區域106中。第二機器臂110可用於將基板晶圓從托持區域106運輸到基板處理腔室108a-f並返回。除了循環層沉積(CLD)、原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、濕式蝕刻、預清潔、脫氣、定向、及其他基板處理之外,可以配備每一基板處理腔室108a-f,以執行包括本文所述的乾式蝕刻處理及選擇性沉積的大量基板處理操作。 FIG . 1 illustrates a top plan view of one embodiment of a
基板處理腔室108a-f可包括用於沉積、退火、固化、及/或蝕刻基板晶圓上的介電膜的一或更多個系統部件。在一個配置中,可以使用兩對處理腔室(例如,108c-d與108e-f),以在基板上沉積介電材料或含金屬材料,而第三對處理腔室(例如108a-b)可以用於蝕刻所沉積的介電質。在另一配置中,所有三對腔室(例如,108a-f)可經配置以蝕刻基板上的介電膜。可以在與不同實施例中所示的製造系統分離的腔室中執行所述的任何一或更多個處理。The
在一些實施例中,腔室具體包括如下所述的至少一個蝕刻腔室以及如下所述的至少一個沉積腔室。藉由包括該等腔室並組合工廠介面的處理側,可以在受控環境中執行以下所述的所有蝕刻及沉積處理。舉例而言,在托持區域106的處理側可以維持真空環境,而使得在實施例中的所有腔室及轉移均維持在真空下。此舉亦可限制水蒸氣及其他空氣成分接觸處理中的基板。應理解,系統100可以考慮用於介電膜的沉積、蝕刻、退火、及固化腔室的附加配置。In some embodiments, the chamber specifically includes at least one etching chamber as described below and at least one deposition chamber as described below. By including these chambers and incorporating the process side of the factory interface, all the etching and deposition processes described below can be performed in a controlled environment. For example, a vacuum environment may be maintained on the processing side of the holding
第 2A 圖
圖示在處理腔室內具有分隔的電漿產生區域的示例性處理腔室系統200的橫截面圖。在膜蝕刻期間(例如,氮化鈦、氮化鉭、鎢、鈷、氧化鋁、氧化鎢、矽、多晶矽、氧化矽、氮化矽、氮氧化矽、碳氧化矽等),處理氣體可以經由氣體入口組件205流入第一電漿區域215。遠端電漿系統(RPS)201可以可選擇地包括在系統中,並且可以處理隨後行進穿過氣體入口組件205的第一氣體。入口組件205可以包括二或更多個不同的氣體供應通道,其中若包括第二通道(未圖示),則第二通道可以繞過RPS 201。 2A illustrates a cross-sectional view of an exemplary
圖示冷卻板203、面板217、離子消除器223、噴淋頭225、及具有基板255設置其上的基板支撐件265,且每一者可以根據實施例而被包括。台座265可以具有熱交換通道,熱交換流體流經熱交換通道以控制基板的溫度,可在處理操作期間操作基板的溫度,以加熱及/或冷卻基板或晶圓。亦可以使用嵌入式電阻加熱器元件而電阻加熱可以包含鋁、陶瓷、或其組合的台座265的晶圓支撐盤,以實現相對高的溫度,例如從高達或約100℃至高於或約1100℃。
面板217可以是金字塔形、圓錐形、或具有窄的頂部部分擴展到寬的底部部分的其他類似結構。如圖所示,附加地,面板217可以是平坦的,並包括用於分配處理氣體的複數個貫通通道。取決於RPS 201的使用,電漿產生氣體及/或電漿激發物質可以穿過面板217中如第2B圖所示的複數個孔洞,以更均勻地遞送到第一電漿區域215中。The
示例性配置可以包括氣體入口組件205通入由面板217與第一電漿區域215分隔的氣體供應區域258,而使得氣體/物質流經面板217中的孔洞而進入第一電漿區域215。可以選擇結構及操作特徵,以防止來自第一電漿區域215的電漿大量回流到供應區域258、氣體入口組件205、及流體供應系統210中。位於特徵之間的絕緣環220與面板217、或者腔室的導電頂部部分以及噴淋頭225一起示出,以允許相對於噴淋頭225及/或離子消除器223而將AC電位施加到面板217。絕緣環220可以定位於面板217與噴淋頭225及/或離子消除器223之間,以讓電容耦合電漿(CCP)能夠在第一電漿區域中形成。附加地,擋板(未圖示)可以位於第一電漿區域215中,或者另外與氣體入口組件205耦接,以影響流體經由氣體入口組件205進入區域的流動。Exemplary configurations may include the
離子消除器223可以包含定義貫穿結構的複數個孔隙的板狀或其他幾何形狀,複數個孔隙經配置以消除離開第一電漿區域215的離子帶電物質的遷移,同時允許不帶電荷的中性或自由基物質穿過離子消除器223進入消除器與噴淋頭之間的活性氣體遞送區域。在實施例中,離子消除器223可以包含具有各種孔隙配置的多孔板。這些不帶電荷的物質可以包括利用活性較低氣體載體運輸穿過孔隙的高活性物質。如上所述,離子物質經由孔洞的遷移可能減少,並在一些情況下完全消除。控制穿過離子消除器223的離子物質的量可以有利地提供增加對於與底下的晶圓基板接觸的氣體混合物的控制,這又可以增加對氣體混合物的沉積及/或蝕刻特性的控制。舉例而言,氣體混合物的離子濃度的調整可以顯著改變其蝕刻選擇性,例如,SiNx:SiOx蝕刻率、Si:SiOx蝕刻率等。在執行沉積的可替代實施例中,亦可以改變介電材料的共形流動式沉積的平衡。The
離子消除器223中的複數個孔隙可經配置以控制活性氣體(亦即,離子、自由基、及/或中性物質)經由離子消除器223的通路。舉例而言,可以控制孔洞的高寬比、或孔洞直徑對長度、及/或孔洞的幾何形狀,而使得穿過離子消除器223的活性氣體中的離子帶電物質的流動減少。離子消除器223中的孔洞可以包括面對電漿激發區域215的錐形部分以及面對噴淋頭225的圓柱形部分。圓柱形部分可以成形及定尺寸,以控制傳到噴淋頭225的離子物質的流動。作為控制離子物質經由消除器的流動的附加手段,亦可以將可調整的電偏壓施加到離子消除器223。The plurality of apertures in the
離子消除器223可以用於減少或消除從電漿產生區域行進到基板的離子帶電物質的量。不帶電的中性及自由基物質仍然可以穿過離子消除器中的開口而與基板反應。應注意,在實施例中,可以不執行在環繞基板的反應區域中的離子帶電物質的完全消除。在某些情況下,離子物質意欲到達基板,以執行蝕刻及/或沉積處理。在這些情況下,離子消除器可以幫助將反應區域中的離子物質濃度控制在有助於處理的位準處。
與離子消除器223組合的噴淋頭225可以允許存在於第一電漿區域215的電漿,以避免在基板處理區域233中直接激發氣體,同時仍允許激發物質從腔室電漿區域215行進到基板處理區域233。以此方式,腔室可經配置以防止電漿接觸蝕刻中的基板255。此舉可以有利地保護基板上圖案化的各種複雜結構及膜,若直接與所產生的電漿接觸,則各種複雜結構及膜可能損傷、移位、或以其他方式彎曲。此外,當允許電漿接觸基板或接近基板層級時,可能增加氧化物物質蝕刻的速率。因此,若材料的暴露區域為氧化物,則可以藉由遠離基板維持電漿來進一步保護此材料。
處理系統可以進一步包括與處理腔室電耦接的功率供應器240,以提供電功率到面板217、離子消除器223、噴淋頭225、及/或台座265,以在第一電漿區域215或處理區域233中產生電漿。取決於所執行的處理,功率供應器可經配置以向腔室遞送可調整量的功率。這種配置可以允許可調諧電漿用於執行中的處理。與通常呈現為具有開啟或關閉功能的遠端電漿單元不同,可調諧電漿可經配置以向電漿區域215遞送特定量的功率。此舉又可以允許形成特定的電漿特性,而使得前驅物可以利用特定方式解離,以增強由這些前驅物產生的蝕刻輪廓。The processing system may further include a
可以在噴淋頭225上方的腔室電漿區域215或噴淋頭225下方的基板處理區域233中激發電漿。在實施例中,形成於基板處理區域233中的電漿可以是利用作為電極的台座形成的DC偏壓電漿。電漿可以存在於腔室電漿區域215中,以從例如含氟前驅物或其他前驅物的流入產生自由基前驅物。典型地,在射頻(RF)範圍中的AC電壓可以施加於處理腔室的導電頂部部分(例如,面板217)與噴淋頭225及/或離子消除器223之間,以在沉積期間激發腔室電漿區域215中的電漿。RF功率供應器可以產生13.56MHz的高RF頻率,但亦可以單獨產生其他頻率或與13.56MHz頻率組合產生其他頻率。Plasma may be excited in the
第 2B 圖
圖示影響穿過面板217的處理氣體分佈的特徵的詳細視圖253。如第2A圖及第2B圖所示,面板217、冷卻板203、及氣體入口組件205相交,以定義氣體供應區域258,其中處理氣體可以從氣體入口205遞送進入氣體供應區域258。氣體可以填充氣體供應區域258,並經由面板217中的孔隙259流到第一電漿區域215。孔隙259可經配置以基本上單向的方式引導流動,而使得處理氣體可以流入處理區域233中,但是在穿過面板217之後可以被部分或完全防止回流到氣體供應區域258中。 FIG . 2B illustrates a
氣體分配組件(例如,用於處理腔室區段200的噴淋頭225)可以指稱為雙通道噴淋頭(DCSH),並附加地在第3圖所述的實施例中詳細說明。雙通道噴淋頭可以提供蝕刻處理,以允許在處理區域233之外分離蝕刻劑,以在遞送到處理區域之前提供與腔室部件及彼此間的受限的相互作用。The gas distribution assembly (eg,
噴淋頭225可以包含上板214及下板216。這些板可以彼此耦接,以定義這些板之間的容積218。板的耦接可以提供穿過上及下板的第一流體通道219以及穿過下板216的第二流體通道221。所形成的通道可經配置以提供從容積218單獨經由第二流體通道221穿過下板216的流體出入口,而第一流體通道219可以流體隔離於板與第二流體通道221之間的容積218。容積218可以經由氣體分配組件225的一側流體出入。The
第 3 圖
係為根據實施例的與處理腔室一起使用的噴淋頭325的底視圖。噴淋頭325可以對應於第2A圖所示的噴淋頭225。通孔365(圖示第一流體通道219的視圖)可以具有複數種形狀及配置,以控制及影響前驅物經由噴淋頭225的流動。小孔洞375(圖示第二流體通道221的視圖)可以基本均勻地分佈在噴淋頭的表面上(即使在通孔365中),並且可以有助於前驅物在離開噴淋頭時提供比其他配置更均勻的混合。 Figure 3 is a bottom view of a
轉到第 4 圖
,圖示根據本技術的一或更多個實施例的原子層沉積系統400或反應器的示意性橫截面圖。系統400可以包括裝載閘腔室10與處理腔室20。處理腔室20通常可以是可密封的外殼,而可以在真空或至少低壓下操作。處理腔室20可以藉由隔離閥15與裝載閘腔室10隔離。隔離閥15可以將處理腔室20與裝載閘腔室10密封於關閉位置,並可允許在打開位置時將基板60從裝載閘腔室10經由閥轉移至處理腔室20,反之亦然。Turning to Figure 4 , illustrated is a schematic cross-sectional view of an atomic
系統400可包括氣體分配板30,氣體分配板30能夠跨越基板60分配一或更多種氣體。氣體分配板30可以是該領域具有通常知識者已知的任何合適的分配板,且所述之特定氣體分配板不應視為限制本技術之範疇。氣體分配板30之輸出面可以面向基板60的第一表面61。
氣體分配板30可以包括複數個氣體埠與複數個真空埠,複數個氣體埠經配置以傳送一或更多個氣體流到基板60,而複數個真空埠係設置於每一氣體埠之間,並經配置以傳送氣體流到處理腔室20之外。如第4圖所示,氣體分配板30可以包括第一前驅物注射器420、第二前驅物注射器430、及吹掃氣體注射器440。注射器420、430、440可藉由系統電腦(未圖示)(例如,主機)控制,或藉由腔室特定控制器(例如,可程式化邏輯控制器)控制。前驅物注射器420可經配置以將化合物A的活性前驅物之連續或脈衝流注射經由複數個氣體埠425進入處理腔室20。前驅物注射器430可經配置以將化合物B的活性前驅物之連續或脈衝流注射經由複數個氣體埠435進入處理腔室20。吹掃氣體注射器440可經配置以將無活性或吹掃氣體之連續或脈衝流注射經由複數個氣體埠445進入處理腔室20。吹掃氣體可經配置以從處理腔室20移除活性材料及活性副產物。吹掃氣體典型係為惰性氣體,例如,氮氣、氬氣、及氦氣。氣體埠445可設置於氣體埠425及氣體埠435之間,以從化合物B之前軀物分離化合物A之前驅物,藉此避免前驅物之間的交叉汙染。The
在另一態樣中,在將前驅物注射進入處理腔室20之前,遠端電漿源(未圖示)可連接至前驅物注射器420及前驅物注射器430。可以藉由將電場施加到遠端電漿源內的化合物來產生活性物質之電漿。可以使用能夠活化所意欲化合物的任何功率源。舉例而言,使用DC、射頻、及微波型放電技術的功率源可以使用。若使用RF功率源,則可以電容性或電感性耦接該RF功率源。亦可以藉由熱基礎技術、氣體解離技術、高強度光源(例如,紫外光源)、或暴露於x射線源來產生活化。In another aspect, a remote plasma source (not shown) may be connected to
系統400可以進一步包括連接至處理腔室20的泵送系統450。泵送系統450大致上可經配置以經由一或更多個真空埠455將氣體流抽空到處理腔室20之外。真空埠455可設置於每一氣體埠之間,以在氣體流與基板表面反應之後將氣體流抽空到處理腔室20之外,並進一步限制前驅物之間的交叉汙染。
系統400可包括設置於處理腔室20上並在每一埠之間的複數個分區460。每一分區的下部可以延伸靠近基板60的第一表面61(例如,距離第一表面61約0.5mm或更多)。以此方式,分區460的下部可以從基板表面分離一距離,該距離足以允許氣體流在氣體流與基板表面反應之後,流動環繞下部而朝向真空埠455。箭頭498指示氣體流的方向。由於分區460可操作而作為對於氣體流的物理阻隔,所以分區460亦可限制前驅物之間的交叉汙染。所示之配置僅為說明性,且不應視為限制本技術之範疇。該領域具有通常知識者將理解,所示之氣體分配系統僅為一種可能的分配系統,並且可以採用其他類型的噴淋頭。
在操作中,可以將基板60(例如,藉由機器人)遞送到裝載閘腔室10,並可放置於搬運梭65上。在隔離閥15打開之後,搬運梭65可以沿著軌道70移動。一旦搬運梭65進入處理腔室20,隔離閥15可以關閉,以將處理腔室20密封。然後,搬運梭65可以移動穿過處理腔室20,以進行處理。在一個實施例中,搬運梭65可以在直線路徑中移動穿過腔室。In operation,
隨著基板60移動穿過處理腔室20,基板60的第一表面61可以重複暴露到來自氣體埠425的化合物A的前驅物及來自氣體埠435的化合物B的前驅物,其間具有來自氣體埠445的吹掃氣體。吹掃氣體的注入可經設計以在將基板表面61暴露至下一個前驅物之前,移除來自先前前驅物的未反應材料。在對各種氣體流的每一暴露之後,氣體流可以藉由泵送系統450經由真空埠455抽空。由於在每一氣體埠的兩側可以設置真空埠,所以氣體流可以經由在兩側的真空埠455抽空。因此,氣體流可以從個別氣體埠垂直向下流動朝向基板60的第一表面61,跨越第一表面410且環繞分區460之下部,而最後向上朝向真空埠455。以此方式,每一氣體可以均勻地分佈跨越基板表面61。亦可在暴露至各種氣體流時旋轉基板60。基板的旋轉可以對於防止在所形成的層中形成條帶是有用的。基板的旋轉可以是連續或是分開的步驟。As the
可以藉由例如從氣體埠出來的每一氣體的流動速率及基板60的移動速率來決定基板表面61暴露至每一氣體的程度。在一個實施例中,每一氣體的流動速率可經配置,而不會從基板表面61移除所吸收的前驅物。每一分區之間的寬度、設置於處理腔室20上的氣體埠之數量、及基板可能來回傳遞的次數亦可決定基板表面61暴露至各種氣體的程度。因此,沉積膜的數量與品質可藉由改變上述因子來最佳化。The extent to which the
在另一實施例中,系統400可以包括前驅物注入器420與前驅物注入器430,而沒有吹掃氣體注入器440。因此,隨著基板60移動穿過處理腔室20,基板表面61可以交替地暴露於化合物A的前驅物與化合物B的前驅物,而不會暴露於其間的吹掃氣體。In another embodiment,
第4圖所示的實施例具有在基板上方的氣體分配板30。儘管已經針對此直立定向描述及圖示實施例,但應理解,相反的定向亦是可能的。在那種情況下,基板60的第一表面61可以面朝下,而朝向基板流動的氣體可以引導朝上。在一或更多個實施例中,至少一個輻射熱源90可以定位成加熱基板的第二側。The embodiment shown in Figure 4 has a
在一些實施例中,搬運梭65可以是用於承載基板60的基座66。通常,基座66可以是有助於跨越基板形成均勻溫度的載體。基座66可以相對於第4圖的佈置在裝載閘腔室10與處理腔室20之間在左到右及右到左的兩個方向上移動。基座66可以具有用於承載基板60的頂表面67。基座66可以是經加熱的基座,而使得基板60可以加熱以用於處理。作為實例,可以藉由設置在基座66下方的輻射熱源90、加熱板、電阻線圈、或其他加熱裝置來加熱基座66。儘管圖示為橫向轉換,但系統400的實施例亦可用於旋轉式系統,其中輪子可以順時針或逆時針旋轉,以連續加工位於所示氣體分配系統下方的一或更多個基板。應類似地理解,附加修改係包括在本技術中。In some embodiments, the
第 5 圖
圖示形成半導體結構的方法500,其中許多操作可以執行於例如前述腔室200及400中。該方法可以包括基板的NMOS與PMOS區域上的磊晶生長的態樣。方法500可以包括在開始該方法之前的一或更多個操作,而包括前端處理、沉積、蝕刻、研磨、清潔、或可以在所述操作之前執行的任何其他操作。該方法可以包括多個可選擇操作,其可以或可以不特別與根據本技術的方法相關聯。舉例而言,為了提供更廣泛的結構形成範圍而描述許多操作,但是對於該技術而言並非關鍵,或者可以藉由替代方法來執行,這將在下面進一步討論。方法500描述第 6A 圖至第 6B 圖
中示意性圖示的操作,將結合方法500的操作而描述其說明。應理解,第6圖僅圖示局部示意圖,而基板可以包含任何數量的具有如圖式中所示的態樣的電晶體區段。 FIG . 5 illustrates a
第 7 圖
圖示形成半導體結構的方法700,其中許多操作可以執行於例如前述腔室200及400中。該方法可以包括基板的NMOS與PMOS區域上的矽化的態樣。該方法可以包括源極汲極區域上的磊晶生長的態樣。方法700可以包括在開始該方法之前的一或更多個操作,而包括前端處理、沉積、蝕刻、研磨、清潔、或可以在所述操作之前執行的任何其他操作。該方法可以包括多個可選擇操作,其可以或可以不特別與根據本技術的方法相關聯。舉例而言,為了提供更廣泛的結構形成範圍而描述許多操作,但是對於該技術而言並非關鍵,或者可以藉由替代方法來執行,這將在下面進一步討論。方法700描述第 8A 圖至第 8B 圖
中示意性圖示的操作,將結合方法700的操作而描述其說明。應理解,第8圖僅圖示局部示意圖,而基板可以包含任何數量的具有如圖式中所示的態樣的電晶體區段。應理解,方法500與700僅為示例性,而在實施例中可以先處理N區域或P區域中之一者。這兩種處理方式都包含在本技術中。 FIG . 7 illustrates a
方法500可以涉及在具有多個暴露區域的基板上執行的操作,例如在包括進一步發展以產生電晶體結構的區域的基板上。如第6A圖所示,經處理的基板600的一部分係圖示為包括基板605、p區域的源極與汲極610、n區域的源極與汲極615、金屬閘極620、蓋層625、及閘極間隔物630。材料可以在先前的操作中形成,且可以被拋光、蝕刻、或處理以產生所示結構。可以執行方法500的操作,以限制或消除遮罩操作以及包括灰化及清潔的RIE處理,並且可以減少用於在結構的產生期間提供磊晶材料的處理佇列時間,以減少結構的NMOS與PMOS區域中的接觸電阻。
方法700亦可以涉及在具有多個暴露區域的基板上執行的操作,例如在包括進一步發展以產生電晶體結構的區域的基板上。如第8A圖所示,經處理的基板600的一部分係圖示為包括基板605、p區域的源極與汲極610、n區域的源極與汲極615、金屬閘極620、蓋層625、及閘極間隔物630。舉例而言,如同在方法500期間所形成者,該結構亦可以包括第一半導體材料635與第二半導體材料640。材料可以在先前的操作中形成,且可以被拋光、蝕刻、或處理以產生所示結構。可以執行方法700的操作,以限制或消除遮罩操作以及包括灰化及清潔的RIE處理,並且可以減少用於在結構的產生期間提供矽化材料的處理佇列時間,以減少結構的NMOS與PMOS區域中的接觸電阻。The
所使用的材料可以是該領域已知的各種介電材料、金屬材料、及半導體材料。舉例而言,基板605可以是矽或一些含矽材料。p區域的源極與汲極610可以形成於該結構的PMOS區域中,並且可以是鍺化矽或一些其他p通道金屬氧化物半導體材料。n區域的源極與汲極615可以是磷化矽或一些其他n通道金屬氧化物半導體材料。金屬閘極620可以是鎢、鈷、或一些其他導電材料。蓋材料625可以是自對準的接觸蓋,並且可以是氮化矽、碳化矽、或包括金屬氧化物(例如,氧化鎢或氧化鋁)的一些氧化物材料。舉例而言,閘極間隔物630可以是任何介電材料,並且可以例如是含矽材料、含氧材料、含碳材料、或一些組合(例如,碳氧化矽)。The materials used may be various dielectric materials, metallic materials, and semiconductor materials known in the art. For example, the
方法500最初可以包括如第6A圖所示的操作505處的沉積半導體材料635之步驟。半導體材料635可以是任何已知的半導體材料,而在實施例中因為如圖所示可以形成於PMOS源極與汲極材料上,所以可以是沉積為半導體材料635的鍺。半導體材料635的沉積可以選擇性沉積在p區域的源極與汲極區段610上,並且可以不形成於任何其他暴露的材料上(包括蓋材料625、閘極間隔物630、或可能在NMOS區域中保持暴露的任何材料)。在實施例中,可以不用先阻擋NMOS區域而執行沉積(例如藉由形成光阻或硬遮罩)。半導體材料635可以利用任何數量的方式形成,且可以利用前驅物來磊晶生長,以利用下面進一步討論的一或更多個選擇性沉積操作。舉例而言,在示例性半導體材料635為鍺的情況下,可以使用含鍺前驅物與氫化物(例如,包括II族、III族、IV族、或V族金屬氫化物)或有機金屬前驅物(例如,甲基化金屬或其他有機結構)的金屬有機氣相磊晶來執行處理。該處理可以在高於或低於或約500℃的溫度下進行,並且可以在低於約1Torr的壓力下進行,以及可以在低於或約1mTorr的壓力下進行。
方法500亦可以包括如第6B圖所示的操作510處的沉積半導體材料640之步驟。半導體材料640可以是任何已知的半導體材料,而在實施例中因為如圖所示可以形成於NMOS源極與汲極材料上,所以可以是沉積為半導體材料640的III-V半導體(例如,砷化銦鎵)。半導體材料640的沉積可以選擇性沉積在n區域的源極與汲極區段615上,並且可以不形成於任何其他暴露的材料上(包括蓋材料625、閘極間隔物630、或可能在PMOS區域中保持暴露的任何材料)。在實施例中,可以不用先阻擋PMOS區域(例如藉由形成光阻或硬遮罩)而執行沉積。半導體材料640可以利用任何數量的方式形成,且可以利用前驅物來磊晶生長,以利用下面進一步討論的一或更多個選擇性沉積操作。舉例而言,在示例性半導體材料640為砷化銦鎵的情況下,可以使用含銦前驅物、含鎵前驅物、及氫化物(例如,包括II族、III族、IV族、或V族金屬氫化物)或有機金屬前驅物(例如,甲基化金屬或其他有機結構)的金屬有機氣相磊晶來執行處理。在實施例中,附加前驅物可以是含砷前驅物。該處理可以在高於或低於或約500℃的溫度下進行,並且可以在低於約1Torr的壓力下進行,以及可以在低於或約1mTorr的壓力下進行。
方法700可以包括如第8A圖所示的操作715處的沉積第一合金材料845之步驟。舉例而言,先前的操作可以發生於操作712處,其中可以在半導體材料635上方形成含矽材料。含矽材料可以用於藉由隨後的退火操作來產生合金。合金材料可以是包括鎳的合金的任何數量的材料。可以藉由將鎳與含矽材料(例如,鍺化矽)合金化以形成鎳矽鍺,而形成第一合金材料845。鍺化矽最初可以形成於操作712中,然後與鎳一起退火。也可以形成附加的第二與第三含鎳合金或其他金屬合金。舉例而言,因為如圖所示亦可以形成於PMOS源極與汲極材料上方,所以鎳可以作為材料層。第一合金材料845的沉積可以選擇性沉積在第一半導體材料635上,並且可以不形成於任何其他暴露的材料上(包括蓋材料625、閘極間隔物630、或可能在NMOS區域中保持暴露的任何材料)。在實施例中,可以不用先阻擋NMOS區域而執行沉積(例如藉由形成光阻或硬遮罩)。
合金材料可以利用多種方式形成,並且可以藉由產生第一材料層,然後形成合金材料而形成。在形成鎳矽鍺的一個實例中,可以形成鍺化矽層,然後形成鎳層。也可以形成附加的中間層(例如,鍺化矽層與鎳層之間的鈦或鋁層),而有助於合金的形成。然後,可以在高於400℃的溫度下執行退火操作(例如,快速熱退火),以允許鎳滲透鍺化矽,並形成鎳矽鍺。該處理亦可以在低於約1Torr的壓力下進行,以及可以在低於或約1mTorr的壓力下進行。The alloy material can be formed in a variety of ways, and can be formed by creating a first material layer and then forming the alloy material. In one example of forming nickel silicon germanium, a silicon germanium layer may be formed, followed by a nickel layer. Additional intermediate layers (eg, titanium or aluminum layers between the silicon germanium layer and the nickel layer) may also be formed to aid in alloy formation. An annealing operation (eg, rapid thermal annealing) may then be performed at temperatures above 400° C. to allow nickel to penetrate the silicon germanium and form nickel silicon germanium. The treatment can also be carried out at a pressure of less than about 1 Torr, and can be carried out at a pressure of less than or about 1 mTorr.
方法700可以包括如第8B圖所示的操作720處的沉積第二合金材料850之步驟。合金材料可以是包括鈦的合金的任何數量的材料。再次,在操作718處可以首先沉積第二含矽材料,以形成如上所述的合金。可以藉由將鈦與含矽材料(例如,氮化矽)合金化以形成氮化鈦矽,而形成第二合金材料850。也可以形成附加的第二與第三含鈦合金或其他金屬合金。舉例而言,因為如圖所示亦可以形成於NMOS源極與汲極材料上方,所以鈦可以作為材料層。第二合金材料850的沉積可以選擇性沉積在第二半導體材料640上,並且可以不形成於任何其他暴露的材料上(包括蓋材料625、閘極間隔物630、或可能在PMOS區域中保持暴露的任何材料)。
在實施例中,可以不用先阻擋PMOS區域而執行沉積(例如藉由形成光阻或硬遮罩)。合金材料可以利用多種方式形成,並且可以藉由產生第一材料層,然後形成合金材料而形成。在形成氮化鈦矽的一個實例中,可以形成氮化矽層,然後形成鈦層。再次,可以先前描述而形成附加的中間層。然後,可以在高於400℃的溫度下執行退火操作(例如,快速熱退火),以允許鈦滲透氮化矽,並形成氮化鈦矽。該處理亦可以在低於約1Torr的壓力下進行,以及可以在低於或約1mTorr的壓力下進行。In embodiments, deposition may be performed without first blocking the PMOS region (eg, by forming a photoresist or hard mask). The alloy material can be formed in a variety of ways, and can be formed by creating a first material layer and then forming the alloy material. In one example of forming titanium silicon nitride, a silicon nitride layer may be formed followed by a titanium layer. Again, additional intermediate layers may be formed as previously described. Then, an annealing operation (eg, rapid thermal annealing) may be performed at temperatures above 400° C. to allow the titanium to infiltrate the silicon nitride and form titanium silicon nitride. The treatment can also be carried out at a pressure of less than about 1 Torr, and can be carried out at a pressure of less than or about 1 mTorr.
由於許多材料係定位或形成於特定區域中,所以所沉積的層通常可以不同於其他暴露材料層(其上並不發生沉積,或以較小的程度發生)。藉由沉積材料層(由與其他暴露材料不同的材料所組成),可以使用多種選擇性沉積技術來形成層635、640、845、及850中之一或更多者。Since many materials are localized or formed in specific areas, the deposited layers can often be different from other exposed material layers (on which deposition does not occur, or to a lesser extent). By depositing layers of material consisting of a different material than the other exposed materials, one or more of
可以在能夠沉積且能夠原子層沉積的腔室(包括上述的腔室400)中執行任何所揭示材料的選擇性沉積。沉積的前提可以基於相對於包括蓋材料625與閘極間隔物630的介電或絕緣材料以及發生沉積之外的區域中的其他暴露材料來選擇性沉積金屬或半導體材料。舉例而言,第一半導體材料635(在一些實施例中可以是鍺)可以基本上形成於p區域的源極與汲極材料610上(可以是鍺化矽),同時最少地形成於閘極間隔物630或者受限於閘極間隔物630(可以是其他材料中的矽碳氧化物)。第一半導體材料635亦可以最少地形成於或受限於氮化物、碳化物、或氧化物蓋材料625以及NMOS區域中的暴露材料(例如,可以是磷化矽的n區域的源極與汲極材料615)。可以類似地執行下列的選擇性沉積,以相較於在任何其他暴露材料上,在預期位置上沉積更多材料,其他暴露材料亦可以包括基板605,基板605可以是矽或一些其他半導體材料。可以藉由多種操作來執行選擇性沉積,可以包括形成自組裝單層以促進選擇性沉積,或者可以包括主動抑制在其他介電材料上形成材料。Selective deposition of any of the disclosed materials may be performed in a chamber capable of deposition and atomic layer deposition, including
可以在該結構的區域上形成自組裝單層,以調諧沉積。舉例而言,可以在結構上形成第一自組裝單層,然後暴露於光刻遮罩,以從接受沉積(例如,在p區域的源極與汲極材料610或n區域的源極與汲極材料615上)的任何區域移除單層。先前形成於這些區域中的材料亦可以成為後續沉積的目標。單層可以維持在介電或絕緣材料(例如,蓋材料625與閘極間隔物630)上。單層可以具有可能排斥或無法與後來遞送的前驅物相互作用的封端部分。舉例而言,在實施例中,封端部分可以是疏水性,並且可以利用含氫部分(例如,甲基)封端,含氫部分可以不與附加前驅物相互作用。第二自組裝單層可以形成於目標區域上(例如,在p區域的源極與汲極材料610或n區域的源極與汲極材料615上)。此自組裝單層可以是親水的,或與用於產生特定沉積材料(可以是前述材料中之任一者)的一或更多種前驅物反應。因為材料可以與第一自組裝單層排斥,或者可以選擇性吸取到目標區域,所以可以在目標區域上選擇性形成第二自組裝單層。第二自組裝單層可以利用羥基或其他親水部分封端,或是利用特別與用於形成指定沉積材料(例如,金屬或介電材料)的附加前驅物相互作用的部分封端。Self-assembled monolayers can be formed over regions of the structure to tune the deposition. For example, a first self-assembled monolayer can be formed on the structure and then exposed to a lithographic mask to deposit (eg, source and
然後,可以利用二或更多種前驅物執行原子層沉積,以形成沉積材料(可以是用於層635、640、845、850的先前所述的任何材料)。沉積的前驅物可以包括含金屬或含矽前驅物,並包括經配置以與封端第二自組裝單層(而非第一自組裝單層)的部分相互作用的前驅物。舉例而言,當使用親水性及疏水性封端單層時,原子層沉積前驅物中之一者可以包括水。以此方式,沉積可能不會形成於可以是疏水性的第一自組裝單層上。若沉積材料包括金屬氧化物,則用於原子層沉積的前驅物可以包括指定含金屬前驅物以及水。舉例而言,一旦形成完成,可以移除氧化物,以留下金屬層。在其他實施例中,可以使用含矽前驅物。然後,在與水的半反應期間,水可能無法與形成在其他暴露材料上的第一自組裝單層相互作用,而因此沉積可以不在第一自組裝單層上形成。以此方式,可以在目標區域上選擇性形成特定材料,或者優先在目標區域上形成特定材料。應理解,這僅為單一實例,而其他前驅物可以利用類似的操作原理使用,以形成針對每一沉積區域的先前所述的特定材料。Atomic layer deposition may then be performed using two or more precursors to form the deposition material (which may be any of the materials previously described for
在所識別的沉積已經形成為合適的高度之後,第一自組裝單層可以暴露於UV光,並從基板移除,或者可以進行一些其他移除。以此方式,可以排除習知形成中使用的多個操作,這可以顯著減少佇列時間(例如,幾個小時)。在其他實施例中,取決於所執行的操作,可以在選擇性沉積之後執行輕微的凹陷,以從下面討論的其他暴露區域移除殘留材料。應理解,這僅為利用基於一組沉積材料的自組裝單層的實例。After the identified deposits have been formed to a suitable height, the first self-assembled monolayer can be exposed to UV light and removed from the substrate, or some other removal can be performed. In this way, multiple operations used in conventional formations can be eliminated, which can significantly reduce queue time (eg, hours). In other embodiments, depending on the operation performed, a slight undercut may be performed after selective deposition to remove residual material from other exposed areas discussed below. It should be understood that this is only an example of utilizing a self-assembled monolayer based on a set of deposited materials.
取決針對特定沉積材料所使用的材料,自組裝單層可以朝向該材料調整。如前所述,水可以作為前驅物中之一者,而如先前所述,自組裝單層可以結構化(例如,在目標位置上包括羥基封端材料,以相對於其他暴露材料而促進形成於該材料上)。此外,含氮材料可以作為用於沉積發生的材料上的自組裝單層中之一者(例如,單層的封端部分中之一者),而可以允許吸引用於形成先前描述的材料中之一或更多者的特定前驅物。可以使用附加前驅物,而實現或有助於金屬對金屬沉積或半導體沉積。Depending on the material used for a particular deposition material, the self-assembled monolayer can be tuned towards that material. Water can serve as one of the precursors, as previously described, and as previously described, the self-assembled monolayer can be structured (eg, including hydroxyl-terminated materials at targeted sites to facilitate formation relative to other exposed materials) on this material). Furthermore, the nitrogen-containing material may serve as one of the self-assembled monolayers on the material for deposition to occur (eg, one of the capped portions of the monolayer), while allowing attraction to be used in the formation of previously described materials specific precursors of one or more. Additional precursors may be used to enable or facilitate metal-to-metal deposition or semiconductor deposition.
因為一些暴露的金屬或半導體材料的結構,暴露的材料亦可能受到腐蝕或鈍化,以減少相對於其上發生沉積的其他材料的活性,這可允許目標材料上的沉積增加。材料的鈍化可以包括暴露於矽取代或鹵素取代的材料,這可以限制其他材料的沉積。舉例而言,材料的氧化可以利用含氧材料或含鹵材料,這可以允許優先沉積在其他表面上。一旦氧化(例如,藉由暴露於含氧材料),可以類似於所述而進行原子層沉積,其中前驅物中之一者可以包括含氧材料,這可以不與氧化材料相互作用。Because of the structure of some exposed metal or semiconductor materials, the exposed material may also be corroded or passivated to reduce activity relative to other materials on which deposition occurs, which may allow increased deposition on the target material. Passivation of materials can include exposure to silicon-substituted or halogen-substituted materials, which can limit deposition of other materials. For example, oxidation of materials can utilize oxygen-containing materials or halogen-containing materials, which can allow preferential deposition on other surfaces. Once oxidized (eg, by exposure to an oxygen-containing material), atomic layer deposition may be performed similarly to that described, wherein one of the precursors may include the oxygen-containing material, which may not interact with the oxidizing material.
亦可在暴露的絕緣與介電材料上執行鈍化。舉例而言,蓋材料625可以包括氧化物,例如可以經處置以將封端組調整為含矽、氫基、或含鹵素。這可以允許在其他暴露區域上優先沉積金屬材料或半導體材料。在其他實施例中,含氮前驅物可以作為原子層沉積處理中的一或兩種前驅物,這可允許相對於氧化物表面而在金屬表面上的優先沉積。Passivation can also be performed on exposed insulating and dielectric materials. For example, the
實施例亦可以利用抑制劑,以選擇性形成目標表面上的沉積材料中之一者,而不是形成在介電或絕緣材料或其他暴露表面上的沉積材料。舉例而言,可以跨越基板的表面施加所噴塗的抑制劑,並可以沿著基板的頂表面施加,且可以不穿透到基板的凹陷部分內。抑制劑可以是任何數量的材料,材料的特徵可以是矽氧烷主鏈(例如,矽氧烷)或四氟乙烯主鏈(例如,PTFE),以及其他油性或表面活性劑材料。可以跨越基板的頂表面施加材料,以覆蓋蓋材料625與閘極間隔物630的暴露部分。藉由使用噴塗或塗層應用,可以不將材料施加於基板的凹陷部分內,並且可以不接觸其上進行沉積的源極與汲極區域。可以組合使用附加選擇性技術,以例如先前所述在PMOS與NMOS區域上形成自組裝單層,以促進在一個位置而不是另一位置處的沉積。然後,可以例如藉由原子層沉積或其他氣相沉積或物理沉積機制來形成經選擇的材料。Embodiments may also utilize inhibitors to selectively form one of the deposited materials on the target surface rather than on dielectric or insulating materials or other exposed surfaces. For example, the sprayed inhibitor may be applied across the surface of the substrate, and may be applied along the top surface of the substrate, and may not penetrate into recessed portions of the substrate. The inhibitor can be any number of materials that can be characterized by a siloxane backbone (eg, siloxane) or a tetrafluoroethylene backbone (eg, PTFE), as well as other oily or surfactant materials. Material may be applied across the top surface of the substrate to cover exposed portions of
抑制劑材料可以防止在目標位置上可以正常形成或沉積的所沉積的材料的黏附或吸附。形成材料之後,並可以將移除劑施加到基板上,以移除抑制劑材料。移除劑可以是濕式蝕刻劑、反應物、或表面活性劑清潔劑,而可以移除讓底下的介電與絕緣材料暴露的殘留抑制劑材料。利用抑制劑可以允許在定義區域中形成單獨的層,而不需要經由隨後的毯覆膜的圖案化及/或蝕刻定義。藉由移除先前及後續的圖案化操作,處理可以進一步相對於習知處理減少佇列時間。The inhibitor material can prevent adhesion or adsorption of the deposited material that would normally form or deposit on the target site. After the material is formed, a remover may be applied to the substrate to remove the inhibitor material. The remover can be a wet etchant, reactant, or surfactant cleaner, and can remove residual inhibitor material that exposes underlying dielectric and insulating materials. Utilizing an inhibitor may allow individual layers to be formed in defined areas without the need for subsequent patterning and/or etching definition of the blanket film. By removing previous and subsequent patterning operations, the process can further reduce queue time relative to conventional processes.
抑制劑亦可以是可以中和基板的表面或使基板的表面呈現惰性的電漿應用的產物。舉例而言,改性電漿可以由一或更多個前驅物形成,而可以包括惰性前驅物。可以將電漿施加到基板的表面或升起在基板上方的材料,而可以改變暴露材料的頂表面,且可以不穿透到基板的凹陷部分內或基板表面處的部分內。舉例而言,含氮前驅物(可以是氮)可以遞送到產生電漿的處理腔室的電漿處理區域。電漿流出物(可以包括含氮電漿流出物)可以遞送到基板,並且可以沿著頂表面而沿著基板的暴露部分形成氮化表面(可以包括蓋材料625與閘極間隔物630的暴露區域)。The inhibitor can also be the product of a plasma application that can neutralize or render the surface of the substrate inert. For example, the modified plasma can be formed from one or more precursors, and can include inert precursors. The plasma may be applied to the surface of the substrate or material raised above the substrate, while the top surface of the exposed material may be altered and may not penetrate into recessed portions of the substrate or portions at the surface of the substrate. For example, a nitrogen-containing precursor, which may be nitrogen, can be delivered to a plasma processing region of a plasma-generating processing chamber. Plasma effluent (which may include nitrogen-containing plasma effluent) may be delivered to the substrate and a nitrided surface (which may include exposure of
電漿流出物可能不遞送或者可能不流動到基板的表面,而可以維持沿著源極與汲極材料的純的或未反應的表面。然後,可以利用一或更多種沉積技術及/或附加選擇性技術來形成沉積材料(例如,形成自組裝單層),這可以包括原子層沉積或其他氣相或物理沉積。舉例而言,可以利用原子層沉積技術用電漿流出物進行後續處理,並在基板的PMOS與NMOS區域上形成自組裝單層。在沉積的每一循環之後,含氮電漿可以重新施加到基板的表面區域上(例如,在介電或絕緣材料上)。以此方式,介電材料的表面可以鈍化,以防止或限制那些區域上的沉積材料的形成。利用來自基板的升起部分上的這些電漿流出物可以允許沿著基板表面在定義區域中形成沉積材料,而不需要經由後續的毯覆膜的圖案化及/或蝕刻定義。藉由移除先前及後續的圖案化操作,處理可以進一步相對於習知處理減少佇列時間。Plasma effluent may not be delivered or may not flow to the surface of the substrate, but may maintain a pure or unreacted surface along the source and drain materials. The deposition material may then be formed (eg, to form a self-assembled monolayer) using one or more deposition techniques and/or additional selective techniques, which may include atomic layer deposition or other vapor or physical deposition. For example, atomic layer deposition techniques can be used for subsequent processing with plasma effluents and to form self-assembled monolayers on the PMOS and NMOS regions of the substrate. After each cycle of deposition, the nitrogen-containing plasma can be reapplied onto the surface area of the substrate (eg, on a dielectric or insulating material). In this way, the surface of the dielectric material can be passivated to prevent or limit the formation of deposited material on those areas. Utilizing these plasma effluents from the raised portion of the substrate may allow deposition material to form in defined areas along the substrate surface without requiring subsequent patterning and/or etching definition of the blanket film. By removing previous and subsequent patterning operations, the process can further reduce queue time relative to conventional processes.
附加選擇性沉積技術可以利用溫度差,以增強相對於含氧材料的含矽材料上的沉積。舉例而言,利用含矽前驅物的原子層沉積可以在高於或約500℃的溫度下執行,並且可以在高於或約750℃、高於或約900℃、高於或約1000℃、或達到、高於、或約1100℃的溫度下執行。Additional selective deposition techniques may utilize temperature differentials to enhance deposition on silicon-containing materials relative to oxygen-containing materials. For example, atomic layer deposition using silicon-containing precursors can be performed at temperatures above or about 500°C, and can be performed at temperatures above or about 750°C, above or about 900°C, above or about 1000°C, or at a temperature of at, above, or about 1100°C.
隨著溫度在此範圍內增加,可以在某些暴露的材料上以比在含氧材料(例如可以是蓋材料625)上更高的速率發生沉積。然後,可以執行所形成材料的選擇性蝕刻,以從氧化物表面移除第一介電材料。儘管亦可以在目標表面上減少第一半導體材料,但因為厚度可以比氧化物表面上的厚許多倍,所以可以執行氧化物表面的完全移除,同時維持目標表面上的厚度大於或約1nm、大於或約2nm、大於或約3nm、大於或約4nm、大於或約5nm、大於或約6nm、大於或約7nm、大於或約8nm、大於或約9nm、大或約10nm、或更大。此效果可能以習知技術所受限的方式實現本技術。在正常保形或毯覆沉積期間,目標表面的一些部分的厚度將等於蓋材料上的厚度,或者可以小於蓋材料上的厚度。因此,回蝕處理可能過度蝕刻目標區域,或者可能造成層中的穿孔。As the temperature increases within this range, deposition may occur at a higher rate on certain exposed materials than on oxygen-containing materials (eg, which may be cap material 625). Then, a selective etch of the formed material can be performed to remove the first dielectric material from the oxide surface. Although the first semiconductor material can also be reduced on the target surface, since the thickness can be many times thicker than on the oxide surface, complete removal of the oxide surface can be performed while maintaining a thickness on the target surface greater than or about 1 nm, Greater than or about 2 nm, greater than or about 3 nm, greater than or about 4 nm, greater than or about 5 nm, greater than or about 6 nm, greater than or about 7 nm, greater than or about 8 nm, greater than or about 9 nm, greater than or about 10 nm, or greater. This effect may be achieved with the present technology in a manner limited by the prior art. During normal conformal or blanket deposition, the thickness of some portions of the target surface will be equal to the thickness on the cover material, or may be less than the thickness on the cover material. Therefore, the etch-back process may over-etch the target area, or may cause perforations in the layer.
相對於一或更多個其他金屬、半導體、非金屬、介電質、或絕緣區域,這些技術中之任一者可以選擇性沉積或形成先前指定的材料。此外,這些技術中之二或更多者可以組合或者迭代執行,以產生具有可以發生或者可以利用更高速率發生沉積的特定區域的表面。選擇性可以是完全的,其中僅在目標位置(例如,p區域的源極與汲極610或n區域的源極與汲極615,或是中間層)上形成沉積材料,且可以完全不在其他暴露材料上形成沉積材料。在其他實施例中,選擇性可能不是完全的,而目標位置上的沉積相對於其他暴露材料的比率可以大於或約2:1。選擇性亦可以大於或約5:1、大於或約10:1、大於或約15:1、大於或約20:1、大於或約25:1、大於或約30:1、大於或約35:1、大於或約40:1、大於或約45:1、大於或約50:1、大於或約75:1、大於或約100:1、大於或約200:1、或更多。如前所述,材料的沉積的厚度可以小於或約20nm、小於或約10nm、小於或約5nm、小於或約4nm、小於或約3nm、小於或約2nm、小於或約1nm、或更小。因此,低於20:1的選擇性可以是可接受的,以完全沉積單獨的層,同時在其他暴露區域上形成有限量的材料或基本上沒有形成材料。Any of these techniques may selectively deposit or form the previously specified materials relative to one or more other metal, semiconductor, non-metal, dielectric, or insulating regions. Furthermore, two or more of these techniques may be combined or performed iteratively to produce surfaces with specific regions where deposition may occur or may take advantage of higher rates. Selectivity can be complete, where deposition material is formed only on target locations (eg, source and drain 610 in p-regions or source and drain 615 in n-regions, or intermediate layers) and can be completely absent from other A deposition material is formed on the exposed material. In other embodiments, the selectivity may not be complete, and the ratio of deposition on target sites to other exposed materials may be greater than or about 2:1. The selectivity can also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35 : 1, greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more. As previously described, the thickness of the deposition of material may be less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or less. Thus, selectivities below 20:1 may be acceptable to fully deposit individual layers while forming limited or substantially no material on other exposed areas.
沉積操作可以在前述的任何溫度或壓力下執行,並可以在大於或約300℃的溫度下執行,且可以在大於或約400℃、大於或約450℃、大於或約500℃、大於或約600℃、大於或約700℃、大於或約800℃、大於或約900℃、大於或約1000℃、或更高的溫度下執行。舉例而言,在原子層沉積操作期間,可以使用大於或約500℃的溫度,以活化前驅物,以在材料層形成時彼此相互作用。The deposition operation may be performed at any of the aforementioned temperatures or pressures, and may be performed at temperatures greater than or about 300°C, and may be performed at greater than or about 400°C, greater than or about 450°C, greater than or about 500°C, greater than or about Performed at a temperature of 600°C, greater than or about 700°C, greater than or about 800°C, greater than or about 900°C, greater than or about 1000°C, or higher. For example, during atomic layer deposition operations, temperatures greater than or about 500° C. may be used to activate the precursors to interact with each other as material layers are formed.
依據所執行的沉積的類型,可以利用與先前所述不同的順序進行某些操作。舉例而言,若單層(形成以用於抵抗或防止形成)可以與多於一種的材料一起使用,則可以在後續操作期間維持該層以增加效率。舉例而言,方法500係圖示為在方法700的在PMOS區域中的鍺上形成鎳合金材料之前形成砷化銦鎵。然而,若使用自組裝單層來抵抗、減少、或防止在其他暴露材料上形成鍺層,則可以在合金化金屬的後續操作期間維持這些層(例如,形成初始鍺化矽層)。以此方式,在一些實施例中,操作510與715可以顛倒,並且可以連續執行所有PMOS操作,以及可以連續執行所有NMOS操作。Depending on the type of deposition performed, certain operations may be performed in a different order than previously described. For example, if a single layer (formed to resist or prevent formation) can be used with more than one material, the layer can be maintained during subsequent operations to increase efficiency. For example,
依據形成的數量與單獨的沉積的選擇性,也可以執行一或更多個蝕刻操作。蝕刻操作可以利用乾式蝕刻化學品,而在實施例中可以利用電漿化學品。舉例而言,回蝕可以在腔室200中執行,腔室200可以與執行先前沉積的一或更多個沉積腔室在相同的群集工具上。以此方式,幾個沉積及蝕刻操作可以在單一環境中執行(例如,在腔室之間的群集工具共享)。舉例而言,附加腔室可以與一或更多個蝕刻腔室200及沉積腔室400一起,以例如用於執行UV加工,如同可以在下面描述的一些沉積技術中所使用者。每次轉移可以在真空下進行,而腔室中之每一者可以駐留在相同集群工具上,以允許轉移發生在受控環境中。舉例而言,可以在轉移期間維持真空條件,並且可以在不破壞真空的情況下進行轉移。相對於可包括附加遮罩操作、光刻、及可能需要在許多工具之間轉移的其他操作的習知技術,方法500可以在單一工具上執行,其中真空條件在實施例中不受破壞。此外,方法500可以不利用任何RIE操作,這可減少聚合物堆積以及與RIE相關聯的必要的灰化及清潔操作。Depending on the number of formations and the selectivity of the individual depositions, one or more etching operations may also be performed. The etching operation may utilize dry etching chemistries, and in embodiments may utilize plasma chemistries. For example, etch-back can be performed in
蝕刻操作可以利用電漿激發的前驅物來執行,並且可能涉及與特定的含氟前驅物一起的附加前驅物。在一些實施例中,可以使用三氟化氮來產生電漿流出物。亦可以利用附加或可替代的含氟前驅物。舉例而言,含氟前驅物可以流入遠端電漿區域,而含氟前驅物可以包括選自原子氟、雙原子氟、三氟化溴、三氟化氯、三氟化氮、氟化氫、六氟化硫、及二氟化氙的群組的至少一個前驅物。遠端電漿區域可以在與處理腔室不同的模組內或在處理腔室內的隔間內。如第2圖所示,RPS單元201與第一電漿區域215二者可以作為遠端電漿區域。RPS可以允許電漿流出物解離而不會損傷其他腔室部件,而第一電漿區域215可以提供到基板的較短路徑長度,在此期間可能發生重組。Etching operations may be performed using plasma excited precursors and may involve additional precursors along with specific fluorine-containing precursors. In some embodiments, nitrogen trifluoride can be used to generate the plasma effluent. Additional or alternative fluorine-containing precursors may also be utilized. For example, a fluorine-containing precursor can flow into the remote plasma region, and the fluorine-containing precursor can include a fluorine-containing precursor selected from the group consisting of atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, hexafluoride At least one precursor of the group of sulfur fluoride, and xenon difluoride. The distal plasma region may be in a separate module from the processing chamber or in a compartment within the processing chamber. As shown in FIG. 2, both the
附加前驅物亦可以遞送到遠端電漿區域,以增強含氟前驅物。舉例而言,含氮及氫的前驅物、含氧前驅物、或氫前驅物可以與含氟前驅物一起遞送。舉例而言,附加前驅物可以是含氮前驅物(例如,氨),或者可以是氧、氫、或包括一或更多種這些成分的任何數量的前驅物。附加前驅物可以在未激發的狀態中流入處理腔室,以與基板表面相互作用。這些配方可以相對於其他暴露材料中之一或更多者選擇性蝕刻暴露材料中之一者。舉例而言,蝕刻化學品可以相對於暴露的蓋與間隔物材料以及相對於其他形成的材料而用於使一或更多種合金材料以及任何磊晶生長的材料凹陷。蝕刻的選擇性可以大於或約10:1、大於或約20:1、大於或約50:1、大於或約75:1、大於或約為100:1、大於或約為150:1、或更多。以此方式,可以在預期位置所形成的材料損失最小的情況下移除可能在沉積期間已形成的所有附加材料。因為相較於在其他暴露材料上,沉積的選擇性可以在預期位置產生至少兩倍的材料,所以此舉可能發生。Additional precursors can also be delivered to the distal plasmonic region to enhance fluorine-containing precursors. For example, a nitrogen and hydrogen-containing precursor, an oxygen-containing precursor, or a hydrogen-containing precursor can be delivered with a fluorine-containing precursor. For example, the additional precursor may be a nitrogen-containing precursor (eg, ammonia), or may be oxygen, hydrogen, or any number of precursors including one or more of these components. Additional precursors can flow into the processing chamber in an unexcited state to interact with the substrate surface. These formulations can selectively etch one of the exposed materials relative to one or more of the other exposed materials. For example, etching chemistries may be used to recess one or more alloy materials and any epitaxially grown materials with respect to exposed lid and spacer materials and with respect to other formed materials. The selectivity of the etch can be greater than or about 10:1, greater than or about 20:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 150:1, or More. In this way, any additional material that may have formed during deposition can be removed with minimal loss of material formed at the desired location. This may occur because the selectivity of the deposition can yield at least twice as much material at the intended location as on other exposed materials.
在實施例中,蝕刻操作可以在低於約10Torr的情況下執行,以及在實施例中可以在低於或約5Torr的情況下執行。在實施例中,處理亦可以在低於約100℃的溫度下執行,並且可以在低於約50℃的情況下執行。隨著在腔室200或此腔室的變化中執行,或者在能夠執行類似操作的不同腔室中執行,處理可以對於跨越基板的其他暴露材料具有選擇性而移除所沉積的材料的部分。相較於習知技術,藉由利用本技術,可以利用更多的選擇性形成及移除來執行製造,並且可以比習知處理減少數小時的佇列時間。In embodiments, etching operations may be performed below about 10 Torr, and in embodiments below or about 5 Torr. In embodiments, processing may also be performed at temperatures below about 100°C, and may be performed at temperatures below about 50°C. As performed in
在先前描述中,為了解釋之目的,已經闡述許多細節,以提供對於本技術的各種實施例的理解。然而,對於該領域具有通常知識者顯而易見的是,可以在沒有這些細節中之一些或在具有附加細節的情況下實施某些實施例。In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details or with additional details.
已揭示幾個實施例,但應理解,該領域具有通常知識者可以在不悖離實施例的精神的情況下使用各種修改、替代構造、及等同物。此外,為了避免不必要地模糊本技術,並未描述許多已知的處理及元件。因此,上面的描述不應視為限制本技術之範疇。Several embodiments have been disclosed, but it should be understood that various modifications, alternative constructions, and equivalents may be employed by those of ordinary skill in the art without departing from the spirit of the embodiments. Furthermore, many well-known processes and elements have not been described in order to avoid unnecessarily obscuring the technology. Accordingly, the above description should not be construed as limiting the scope of the present technology.
當提供值的範圍時,應理解,除非上下文另有明確說明,亦具體揭示該範圍的上限與下限之間的每一中間值到下限單位的最小部分。包括在所述範圍中的任何所述值或未敘述的中間值與所述範圍中的任何其他所述或中間值之間的任何較窄範圍。這些較小範圍的上限與下限可以獨立地包括在範圍中或排除在外,而包括上下限其中一者、两者或不含上下限的較小範圍中的每一範圍亦包括在本技術內,取決於所述範圍中特別排除的限制。在所述範圍包括一或二個限制的情況下,則亦包括排除這些所包括限制中的一或二者的範圍。When a range of values is provided, it is to be understood that, unless the context clearly dictates otherwise, each intervening value between the upper and lower limit of the range to the smallest part of the unit of the lower limit is also specifically disclosed. Included are any narrower ranges between any stated or unrecited intervening value in a stated range and any other stated or intervening value in that stated range. The upper and lower limits of these smaller ranges may independently be included in or excluded from the range, and each of the smaller ranges including either, both, or exclusive of the upper and lower limits, is also encompassed within the technology, Depends on the limitations specifically excluded in the stated range. Where the stated range includes one or both of the limitations, ranges excluding either or both of those included limitations are also included.
如本文及隨附專利申請範圍中所使用,除非上下文另有明確說明,否則單數形式「一」、「一個」、及「該」包括複數指稱。因此,舉例而言,指稱「一層」包括複數個這樣的層,而指稱「前驅物」包括指稱該領域具有通常知識者已知的一或更多個前驅物及其等同物等等。As used herein and in the scope of the appended patent application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, by way of example, reference to "a layer" includes a plurality of such layers, and reference to a "precursor" includes reference to one or more precursors and equivalents thereof known to those of ordinary skill in the art, and the like.
此外,在本說明書及以下請求項中使用詞語「包含」、「所包含」、「含有」、「所含有」、「包括」、及「所包括」時,意欲在指定所述特徵、整體、部件、或操作的存在,但是不排除一或更多個其他特徵、整體、部件、操作、動作、或群組的存在或附加。Furthermore, when the words "comprises," "includes," "includes," "includes," "includes," and "includes" are used in this specification and the following claims, they are intended to The presence of a component, or operation, does not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.
10‧‧‧裝載閘腔室15‧‧‧隔離閥20‧‧‧處理腔室30‧‧‧氣體分配板60‧‧‧基板61‧‧‧第一表面65‧‧‧搬運梭70‧‧‧軌道90‧‧‧輻射熱源100‧‧‧處理系統102‧‧‧前開式晶圓盒104‧‧‧機器臂106‧‧‧托持區域108a‧‧‧處理腔室108b‧‧‧處理腔室108c‧‧‧處理腔室108d‧‧‧處理腔室108e‧‧‧處理腔室108f‧‧‧處理腔室109a‧‧‧串聯區段109b‧‧‧串聯區段109c‧‧‧串聯區段110‧‧‧第二機器臂200‧‧‧腔室201‧‧‧RPS單元203‧‧‧冷卻板205‧‧‧氣體入口組件210‧‧‧流體供應系統214‧‧‧上板215‧‧‧第一電漿區域216‧‧‧下板217‧‧‧面板218‧‧‧容積219‧‧‧第一流體通道220‧‧‧絕緣環221‧‧‧第二流體通道223‧‧‧離子抑制器225‧‧‧噴淋頭233‧‧‧基板處理區域240‧‧‧功率供應器253‧‧‧詳細視圖255‧‧‧基板258‧‧‧氣體供應區域259‧‧‧孔隙265‧‧‧台座325‧‧‧噴淋頭365‧‧‧通孔375‧‧‧小孔洞400‧‧‧腔室420‧‧‧注射器425‧‧‧氣體埠430‧‧‧注射器435‧‧‧氣體埠440‧‧‧注射器445‧‧‧氣體埠450‧‧‧泵送系統455‧‧‧真空埠460‧‧‧分區498‧‧‧箭頭500‧‧‧方法505‧‧‧操作510‧‧‧操作600‧‧‧基板605‧‧‧基板610‧‧‧p區域的源極與汲極615‧‧‧n區域的源極與汲極620‧‧‧金屬閘極625‧‧‧蓋材料630‧‧‧閘極間隔物635‧‧‧第一半導體材料640‧‧‧第二半導體材料700‧‧‧方法712‧‧‧操作715‧‧‧操作718‧‧‧操作720‧‧‧操作845‧‧‧第一合金材料850‧‧‧第二合金材料10‧‧‧Load Lock Chamber 15‧‧‧Isolation Valve 20‧‧‧Processing Chamber 30‧‧‧Gas Distribution Plate 60‧‧‧Substrate 61‧‧‧First Surface 65‧‧‧Transfer Shuttle 70‧‧‧ Rail 90‧‧‧Radiant heat source 100‧‧‧Processing system 102‧‧‧Front-loading pod 104‧‧‧Robot arm 106‧‧‧Holding area 108a‧‧‧Processing chamber 108b‧‧‧Processing chamber 108c ‧‧‧Processing chamber 108d‧‧‧Processing chamber 108e‧‧‧Processing chamber 108f‧‧‧Processing chamber 109a‧‧‧Series section 109b‧‧‧Series section 109c‧‧‧Series section 110‧ ‧‧Second Robot Arm 200‧‧‧Chamber 201‧‧‧RPS Unit 203‧‧‧Cooling Plate 205‧‧‧Gas Inlet Assembly 210‧‧‧Fluid Supply System 214‧‧‧Top Plate 215‧‧‧First Plasma area 216‧‧‧Lower plate 217‧‧‧Panel 218‧‧‧Volume 219‧‧‧First fluid channel 220‧‧‧Insulating ring 221‧‧‧Second fluid channel 223‧‧‧Ion suppressor 225‧ ‧‧Shower head 233‧‧‧Substrate processing area 240‧‧‧Power supply 253‧‧‧Detailed view 255‧‧‧Substrate 258‧‧‧Gas supply area 259‧‧‧Aperture 265‧‧‧Pedestal 325‧‧ ‧Sprinkler head 365‧‧‧Through hole 375‧‧‧Small hole 400‧‧‧Chamber 420‧‧‧Injector 425‧‧‧Gas port 430‧‧‧Injector 435‧‧‧Gas port 440‧‧‧Injector 445 ‧‧‧Gas Port 450‧‧‧Pumping System 455‧‧‧Vacuum Port 460‧‧‧Zone 498‧‧‧Arrow 500‧‧‧Method 505‧‧‧Operation 510‧‧‧Operation 600‧‧‧Substrate 605‧ ‧‧Substrate 610‧‧‧Source and drain in p region 615‧‧‧Source and drain in n region 620‧‧‧Metal gate 625‧‧‧Cap material 630‧‧‧Gate spacer 635‧ ‧‧First Semiconductor Material 640‧‧‧Second Semiconductor Material 700‧‧‧Method 712‧‧‧Operation 715‧‧‧Operation 718‧‧‧Operation 720‧‧‧Operation 845‧‧‧First Alloy Material 850‧‧ ‧Second alloy material
可以藉由參照說明書及圖式的其餘部分來實現所揭示的技術的本質及優點的進一步理解。A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the remainder of the specification and drawings.
第1圖圖示根據本技術的實施例的示例性處理系統的頂視平面圖。1 illustrates a top plan view of an exemplary processing system in accordance with an embodiment of the present technology.
第2A圖圖示根據本技術的實施例的示例性處理腔室的示意性橫截面圖。2A illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with embodiments of the present technology.
第2B圖圖示根據本技術的實施例的示例性面板的詳細視圖。2B illustrates a detailed view of an exemplary panel in accordance with an embodiment of the present technology.
第3圖圖示根據本技術的實施例的示例性噴淋頭的底視平面圖。3 illustrates a bottom plan view of an exemplary showerhead in accordance with embodiments of the present technology.
第4圖圖示根據本技術的實施例的示例性處理腔室的示意性橫截面圖。4 illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.
第5圖圖示根據本技術的實施例的形成半導體結構的方法中的所選擇操作。5 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.
第6A圖至第6B圖圖示根據本技術的實施例的示例性基板的示意性橫截面圖。6A-6B illustrate schematic cross-sectional views of exemplary substrates in accordance with embodiments of the present technology.
第7圖圖示根據本技術的實施例的形成半導體結構的方法中的所選擇操作。7 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.
第8A圖至第8B圖圖示根據本技術的實施例的示例性基板的示意性橫截面圖。8A-8B illustrate schematic cross-sectional views of exemplary substrates in accordance with embodiments of the present technology.
包括圖式中的幾個作為示意圖。應理解,圖式僅用於說明目的,而除非特別聲明按比例,否則不應視為按比例。此外,作為示意圖,提供圖式為幫助理解,並且可能圖式不包括相較於實際表示的所有態樣或資訊,並且可能包括用於說明目的之誇大材料。Several of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes only and should not be considered to scale unless specifically stated to be to scale. Furthermore, as schematic drawings, the drawings are provided to aid understanding and may not include all aspects or information as compared to actual representations and may include exaggerated material for illustrative purposes.
在隨附圖式中,類似的部件及/或特徵可以具有相同的元件符號。此外,相同類型的各種部件可以藉由在元件符號後利用字母來區分,以區分類似部件。若在說明書中僅使用最前面的元件符號,則該描述係適用於具有相同最前面的元件符號的任何一個類似部件,而與字母無關。In the accompanying drawings, similar components and/or features may have the same reference numerals. In addition, various components of the same type may be distinguished by using a letter after the reference symbol to distinguish similar components. If only the leading reference number is used in the specification, the description applies to any one similar component having the same leading reference symbol, regardless of the letter.
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無Domestic storage information (please note in the order of storage institution, date and number) None
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無Foreign deposit information (please note in the order of deposit country, institution, date and number) None
600:基板 600: Substrate
605:基板 605: Substrate
610:p區域的源極與汲極 610: Source and drain of p region
615:n區域的源極與汲極 615: The source and drain of the n region
620:金屬閘極 620: Metal gate
625:蓋材料 625: Cover material
630:閘極間隔物 630: Gate Spacer
635:第一半導體材料 635: First Semiconductor Materials
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US9406804B2 (en) * | 2014-04-11 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with contact-all-around |
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TW201432847A (en) * | 2013-02-05 | 2014-08-16 | Globalfoundries Us Inc | Integrated circuits including FinFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same |
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