TWI778048B - Methods of forming semiconductor structures - Google Patents

Abstract

Processing methods may be performed to form semiconductor structures that may include structures to reduce contact resistance. The methods may include depositing a first semiconductor material on a semiconductor substrate. The first semiconductor material may be selectively deposited on a first silicon-containing material relative to a second silicon-containing material. The methods may also include depositing a second semiconductor material on the semiconductor substrate. The second semiconductor material may be selectively deposited on the second silicon-containing material relative to the first semiconductor material.

Description

Methods of forming semiconductor structures

This technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to systems and methods for selectively forming layers of materials on semiconductor devices.

Integrated circuits may be fabricated by processes that produce intricately patterned layers of material on the surface of the substrate. Creating a patterned material on a substrate requires a controlled method for removing the exposed material. Chemical etching is used for a variety of purposes, including transferring patterns in photoresist into underlying layers, thinning layers, or thinning lateral dimensions of features already present on a surface. It is often desirable to have an etch process that etches one material faster than another to facilitate, for example, a pattern transfer process or individual material removal. This etching process is said to be selective to the first material. Due to the variety of materials, circuits, and processes, etching processes that are selective for a variety of materials have been developed. Typically, however, the deposition process continues across the substrate using blanket coating or conformal fill.

As device dimensions continue to shrink in next-generation devices, selectivity can play a greater role when the material formed in a given layer is only a few nanometers (especially when the material is critical in transistor formation). Many different etch process selectivities have been developed between various materials, but standard selectivities may no longer apply at current and future device scales. Furthermore, based on the number of masking, forming, and removing operations required to form and protect various critical dimensions of features across the device, queue time for processing continues to increase while patterning and forming are performed elsewhere on the substrate.

Accordingly, there is a need for a system and method that can be used to produce high quality devices and structural improvements. The present technology addresses these and other needs.

Processing methods may be performed to form semiconductor structures that may include structures that reduce contact resistance. The method may include the steps of depositing a first semiconductor material on a semiconductor substrate. The first semiconductor material may be selectively deposited on the first silicon-containing material relative to the second silicon-containing material. The methods may also include the step of depositing a second semiconductor material on the semiconductor substrate. The second semiconductor material may be selectively deposited on the second silicon-containing material relative to the first semiconductor material.

In some embodiments, the first semiconductor material may be deposited on the PMOS region of the semiconductor substrate relative to the NMOS region of the semiconductor substrate. The first semiconductor material may include germanium, and the first silicon-containing material may include silicon germanium. The second silicon-containing material may include phosphorous. The method can be performed without a reactive ion etching operation. The first semiconductor material deposition may be performed with a selectivity of the first silicon-containing material relative to the second silicon-containing material greater than or about 2:1. The deposition may occur on the NMOS region of the semiconductor substrate relative to the PMOS region of the semiconductor substrate. The method can be performed without forming a photoresist on the PMOS region. The first semiconductor material may include indium, and the first silicon-containing material may include silicon phosphide. The second silicon-containing material may include germanium. The first semiconductor material may be indium gallium arsenide, or include indium gallium arsenide.

Additionally, the present technology also includes a method of forming a semiconductor structure. The method may include the step of depositing a first alloy material on the first semiconductor material. The alloy material may be selectively deposited on the first semiconductor material relative to the nitride material or the oxide material. The method may also include the step of subsequently depositing a second alloy material on the second semiconductor material. The second alloy material may be selectively deposited on the second semiconductor material relative to the nitride material or the oxide material.

In some embodiments, the first alloy material may be deposited on the indium-containing material in the NMOS region of the semiconductor substrate. The second alloy material may be deposited on the germanium-containing material in the PMOS region of the semiconductor substrate. Nitride materials may include silicon nitride, and oxide materials may include silicon oxide, silicon oxycarbide, or metal oxides. The metal oxide may be or include tungsten oxide or aluminum oxide. The method can be performed without a reactive ion etching operation. The second alloy material may be, or include, a nickel-containing material. The second alloy material may be nickel-silicon-germanium, or include nickel-silicon-germanium. The first alloy material may be, or include, a titanium-containing material. The first alloy material may be titanium silicon nitride, or include titanium silicon nitride.

Such techniques may provide many benefits over conventional systems and techniques. For example, processing can protect critical dimensions and provide improved selectivity by utilizing techniques that do not include reactive ion etching. Furthermore, by performing selective operations, fewer masking and removal operations can be performed, which can significantly reduce manufacturing queue time. These and other embodiments, along with their many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

The techniques of the present invention include systems and components for semiconductor processing of fine pitch features. In the conventional silicidation process, photoresist can be used to block the PMOS region and the NMOS region, while other regions are processed. For example, because several materials across the substrate may be formed of similar materials (eg, silicon nitride or silicon oxide), the etching process used to remove these materials and remove the material formed in the region may not provide Sufficient selectivity relative to other key features. During various opening processes, multiple critical dimension sizes can cause loading effects that etch over budget availability of materials. For example, a conventional process may include a mask layer followed by a reactive ion etching ("RIE") process that allows opening of the structure of the gapfill layer. Although RIE etch is a relatively anisotropic process, RIE etch may still have selectivity that causes sidewall loss. Although it is possible to consider budgeting for this loss during formation (eg, with over-formation of material), because the regions within the etched structure are of different sizes, the calculation of the amount of loss for one region may not be appropriate for larger area losses. Thus, while a 5nm loss may occur in one segment of the budget, a larger segment of 6-7nm may still be lost, creating a mismatch during manufacturing.

Additionally, the RIE process produces etch by-products or polymer residues (usually removed using wet etch processes). This wet etch often overetches the sidewall protection layer beyond the critical dimension (which can cause formation and spacing problems for adjacent transistor layers), and further etches low-k nitride spacers and interlayer dielectric oxides. In addition, metal and dielectric removal is typically performed using anisotropic etching, which may further reduce the exposed areas of cap and spacer materials in other areas unless additional masks or protective layers are formed. Since the selectivity of such RIE removal may be in the range of 10:1, the amount of masking required may be large.

Deposition of both mask material and other material layers can be performed in conventional techniques utilizing blanket coating of material or conformal occurrence of material across all exposed areas on a semiconductor substrate. These types of depositions may require further patterning and removal operations, which can significantly increase the queue time for device fabrication. Between the additional operations and defects of RIE removal and the various operations used in conventional depositions, the queue time of individual device layers may increase by several hours.

The present technology overcomes these problems by modifying the process for removal and formation. By performing selective deposition operations in specific equipment, reduced masking, patterning, and removal can be utilized in structure formation. In addition, the removal operations that can be performed can also be done selectively. By using selective deposition and utilizing alternative etching to remove many patterning operations, these processes can save hours compared to conventional processes utilizing RIE and standard deposition.

While the remainder of the disclosure will routinely identify specific etching and deposition processes utilizing the disclosed techniques, it should be understood that the systems and methods are equally applicable to various other etching, deposition, and cleaning processes that may occur in the described chambers . Therefore, this technique should not be considered limited to only the etch and deposition processes described. This disclosure will discuss one possible system and chamber that may be used with the present technology to perform certain removal and deposition operations prior to the described operations of an exemplary processing sequence in accordance with the present technology.

FIG . 1 illustrates a top plan view of one embodiment of a processing system 100 for deposition, etch, bake, and cure chambers in accordance with an embodiment. In the figure, a pair of front-opening pods (FOUPs) 102 supplies various sized substrates that are received by robotic arms 104 and placed into substrate processing chambers located in inline sections 109a-c Placed into low pressure holding area 106 prior to one of 108a-f. The second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. In addition to cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etching, pre-cleaning, degassing, orientation, and other substrate treatments, Each substrate processing chamber 108a-f may be equipped to perform a number of substrate processing operations including the dry etch processes and selective deposition described herein.

The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and/or etching dielectric films on substrate wafers. In one configuration, two pairs of processing chambers (eg, 108c-d and 108e-f) may be used to deposit dielectric or metal-containing materials on the substrate, while a third pair of processing chambers (eg, 108a-b) Can be used to etch deposited dielectrics. In another configuration, all three pairs of chambers (eg, 108a-f) may be configured to etch the dielectric film on the substrate. Any one or more of the processes described may be performed in a separate chamber from the manufacturing system shown in the various embodiments.

In some embodiments, the chamber specifically includes at least one etching chamber as described below and at least one deposition chamber as described below. By including these chambers and incorporating the process side of the factory interface, all the etching and deposition processes described below can be performed in a controlled environment. For example, a vacuum environment may be maintained on the processing side of the holding region 106 such that all chambers and transfers in embodiments are maintained under vacuum. This also limits the contact of water vapor and other air components with the substrate being processed. It should be appreciated that system 100 may contemplate additional configurations of chambers for deposition, etching, annealing, and curing of dielectric films.

2A illustrates a cross-sectional view of an exemplary processing chamber system 200 having separate plasma generating regions within the processing chamber. During film etching (eg, titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.), process gases can be The gas inlet assembly 205 flows into the first plasma region 215 . A remote plasma system (RPS) 201 may optionally be included in the system and may process the first gas that then travels through the gas inlet assembly 205 . The inlet assembly 205 may include two or more distinct gas supply channels, where a second channel (not shown), if included, may bypass the RPS 201 .

Cooling plate 203, faceplate 217, ion eliminator 223, showerhead 225, and substrate support 265 with substrate 255 disposed thereon are shown, and each may be included according to embodiments. The pedestal 265 may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate, which may be manipulated during processing operations to heat and/or cool the substrate or wafer. Embedded resistive heater elements may also be used to resistively heat the wafer support tray, which may include a pedestal 265 of aluminum, ceramic, or a combination thereof, to achieve relatively high temperatures, such as from up to or about 100°C to above or about 1100°C .

The panels 217 may be pyramidal, conical, or other similar structures with a narrow top portion extending to a wide bottom portion. As shown, the panel 217 may additionally be flat and include a plurality of through channels for distributing process gases. Depending on the use of RPS 201 , plasma generating gas and/or plasma excitation species may pass through a plurality of holes in panel 217 as shown in FIG. 2B for more uniform delivery into first plasma region 215 .

Exemplary configurations may include the gas inlet assembly 205 opening into the gas supply region 258 separated from the first plasma region 215 by the faceplate 217 such that the gas/substance flows through holes in the faceplate 217 into the first plasma region 215 . The structural and operating characteristics may be selected to prevent substantial backflow of plasma from the first plasma region 215 into the supply region 258 , the gas inlet assembly 205 , and the fluid supply system 210 . Insulation ring 220 between features is shown with panel 217, or conductive top portion of the chamber, and showerhead 225 to allow AC potential to be applied to the panel relative to showerhead 225 and/or ion eliminator 223 217. Insulation ring 220 may be positioned between panel 217 and showerhead 225 and/or ion eliminator 223 to allow capacitively coupled plasma (CCP) to form in the first plasma region. Additionally, a baffle (not shown) may be located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid into the region via the gas inlet assembly 205 .

The ion eliminator 223 may comprise a plate or other geometric shape defining a plurality of apertures throughout the structure, the plurality of apertures being configured to eliminate migration of ionically charged species exiting the first plasmonic region 215 while allowing uncharged neutrality Or free radical species pass through the ion eliminator 223 into the reactive gas delivery area between the eliminator and the showerhead. In embodiments, the ion eliminator 223 may comprise porous plates with various aperture configurations. These uncharged species may include highly reactive species transported through the pores using less reactive gaseous carriers. As mentioned above, the migration of ionic species through the pores may be reduced, and in some cases completely eliminated. Controlling the amount of ionic species passing through ion eliminator 223 may advantageously provide increased control over the gas mixture in contact with the underlying wafer substrate, which in turn may increase control over the deposition and/or etch characteristics of the gas mixture. For example, adjustment of the ion concentration of a gas mixture can significantly alter its etch selectivity, eg, SiNx:SiOx etch rate, Si:SiOx etch rate, and the like. In alternative embodiments where deposition is performed, the balance of conformal flow deposition of dielectric materials may also be altered.

The plurality of apertures in the ion eliminator 223 may be configured to control the passage of reactive gases (ie, ions, radicals, and/or neutral species) through the ion eliminator 223 . For example, the aspect ratio of the holes, or the diameter to length of the holes, and/or the geometry of the holes can be controlled such that the flow of ionically charged species in the reactive gas through the ion eliminator 223 is reduced. The holes in ion eliminator 223 may include a tapered portion facing plasma excitation region 215 and a cylindrical portion facing showerhead 225 . The cylindrical portion may be shaped and dimensioned to control the flow of ionic species to showerhead 225. As an additional means of controlling the flow of ionic species through the eliminator, an adjustable electrical bias may also be applied to the ion eliminator 223.

Ion eliminator 223 may be used to reduce or eliminate the amount of ionically charged species traveling from the plasma generation region to the substrate. Uncharged neutral and free radical species can still pass through the openings in the ion eliminator to react with the substrate. It should be noted that in embodiments, complete elimination of ionically charged species in the reaction region surrounding the substrate may not be performed. In some cases, ionic species are intended to reach the substrate to perform etching and/or deposition processes. In these cases, an ion eliminator can help control the concentration of ionic species in the reaction zone at a level that is helpful for processing.

Showerhead 225 in combination with ion eliminator 223 can allow plasma present in first plasma region 215 to avoid direct excitation of gases in substrate processing region 233 while still allowing excitation species to travel from chamber plasma region 215 to the substrate processing area 233. In this manner, the chamber can be configured to prevent the plasma from contacting the substrate 255 under etching. This can advantageously protect various complex structures and films patterned on the substrate, which may be damaged, displaced, or otherwise bent if in direct contact with the generated plasma. In addition, when the plasma is allowed to contact the substrate or near the substrate level, it is possible to increase the rate of oxide species etching. Thus, if the exposed areas of the material are oxides, the material can be further protected by maintaining the plasma away from the substrate.

The processing system may further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the panel 217, the ion eliminator 223, the showerhead 225, and/or the pedestal 265 for use in the first plasma region 215 or Plasma is generated in the processing region 233 . Depending on the processing performed, the power supply can be configured to deliver an adjustable amount of power to the chamber. This configuration may allow tunable plasma to be used for ongoing processing. Unlike remote plasma cells, which are typically presented with an on or off function, the tunable plasma can be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow for the formation of specific plasmonic properties that allow precursors to dissociate in specific ways to enhance the etch profile produced by these precursors.

Plasma may be excited in the chamber plasma region 215 above the showerhead 225 or in the substrate processing region 233 below the showerhead 225 . In an embodiment, the plasma formed in the substrate processing region 233 may be a DC biased plasma formed using a pedestal as an electrode. Plasma may be present in the chamber plasma region 215 to generate radical precursors from the influx of, for example, fluorine-containing precursors or other precursors. Typically, an AC voltage in the radio frequency (RF) range can be applied between the conductive top portion of the processing chamber (eg, panel 217 ) and the showerhead 225 and/or ion eliminator 223 to excite the chamber during deposition Plasma in chamber plasma region 215 . The RF power supply can generate a high RF frequency of 13.56MHz, but can also generate other frequencies alone or in combination with the 13.56MHz frequency.

FIG . 2B illustrates a detailed view 253 of features that affect the distribution of the process gas through the panel 217. As shown in Figures 2A and 2B, the faceplate 217, the cooling plate 203, and the gas inlet assembly 205 intersect to define a gas supply region 258 into which process gas can be delivered from the gas inlet 205. Gas may fill gas supply region 258 and flow to first plasma region 215 via apertures 259 in panel 217 . Apertures 259 may be configured to direct flow in a substantially unidirectional manner such that process gas may flow into process region 233 , but may be partially or completely prevented from flowing back into gas supply region 258 after passing through panel 217 .

The gas distribution assembly (eg, showerhead 225 for process chamber section 200 ) may be referred to as a dual channel showerhead (DCSH) and is additionally detailed in the embodiment depicted in FIG. 3 . A dual channel showerhead may provide an etch process to allow for etchant separation outside the process area 233 to provide limited interaction with chamber components and each other prior to delivery to the process area.

The showerhead 225 may include an upper plate 214 and a lower plate 216 . The plates can be coupled to each other to define the volume 218 between the plates. The coupling of the plates can provide a first fluid channel 219 through the upper and lower plates and a second fluid channel 221 through the lower plate 216 . The channels formed can be configured to provide fluid access from the volume 218 through the lower plate 216 via the second fluid channel 221 alone, while the first fluid channel 219 can be fluidly isolated from the volume 218 between the plate and the second fluid channel 221. . Volume 218 is fluidly accessible via one side of gas distribution assembly 225 .

Figure 3 is a bottom view of a showerhead 325 for use with a processing chamber, according to an embodiment. The showerhead 325 may correspond to the showerhead 225 shown in FIG. 2A. The through-holes 365 (showing the view of the first fluid channel 219 ) can have a variety of shapes and configurations to control and influence the flow of the precursor through the showerhead 225 . The small holes 375 (showing the view of the second fluid channel 221 ) can be substantially evenly distributed over the surface of the showerhead (even in the through holes 365 ) and can help the precursors provide a specific ratio as they exit the showerhead. Other configurations are more evenly mixed.

Turning to Figure 4 , illustrated is a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology. System 400 may include load lock chamber 10 and process chamber 20 . The process chamber 20 may generally be a sealable enclosure, and may operate under vacuum or at least low pressure. Process chamber 20 may be isolated from load lock chamber 10 by isolation valve 15 . The isolation valve 15 may seal the process chamber 20 from the load gate chamber 10 in the closed position and may allow the transfer of substrates 60 from the load gate chamber 10 to the process chamber 20 through the valve in the open position and vice versa.

System 400 may include gas distribution plate 30 capable of distributing one or more gases across substrate 60 . The gas distribution plate 30 may be any suitable distribution plate known to those of ordinary skill in the art, and the particular gas distribution plate described should not be construed as limiting the scope of the present technology. The output surface of the gas distribution plate 30 may face the first surface 61 of the substrate 60 .

The gas distribution plate 30 may include a plurality of gas ports and a plurality of vacuum ports, the plurality of gas ports are configured to transmit one or more gas flows to the substrate 60, and the plurality of vacuum ports are disposed between each gas port, and is configured to deliver the gas flow out of the processing chamber 20 . As shown in FIG. 4 , the gas distribution plate 30 may include a first precursor injector 420 , a second precursor injector 430 , and a purge gas injector 440 . The injectors 420, 430, 440 may be controlled by a system computer (not shown) (eg, a host computer), or by a chamber-specific controller (eg, a programmable logic controller). The precursor injector 420 may be configured to inject a continuous or pulsed stream of the active precursor of Compound A into the processing chamber 20 through the plurality of gas ports 425 . Precursor injector 430 may be configured to inject a continuous or pulsed stream of the active precursor of Compound B into process chamber 20 through plurality of gas ports 435 . Purge gas injector 440 may be configured to inject a continuous or pulsed flow of inert or purge gas into process chamber 20 through a plurality of gas ports 445 . The purge gas may be configured to remove active materials and active by-products from the processing chamber 20 . Purge gases are typically inert gases such as nitrogen, argon, and helium. The gas port 445 can be disposed between the gas port 425 and the gas port 435 to separate the compound A precursor from the compound B precursor, thereby avoiding cross-contamination between the precursors.

In another aspect, a remote plasma source (not shown) may be connected to precursor injector 420 and precursor injector 430 prior to injecting the precursor into processing chamber 20 . Plasma of active species can be generated by applying an electric field to a compound within a remote plasma source. Any power source capable of activating the desired compound can be used. For example, power sources using DC, radio frequency, and microwave type discharge techniques can be used. If an RF power source is used, the RF power source can be capacitively or inductively coupled. Activation can also be produced by thermal based techniques, gas dissociation techniques, high intensity light sources (eg, UV light sources), or exposure to x-ray sources.

System 400 may further include a pumping system 450 coupled to process chamber 20 . The pumping system 450 may generally be configured to evacuate the gas flow out of the processing chamber 20 via one or more vacuum ports 455 . A vacuum port 455 may be provided between each gas port to evacuate the gas flow out of the processing chamber 20 after the gas flow reacts with the substrate surface and further limit cross-contamination between precursors.

System 400 may include a plurality of partitions 460 disposed on processing chamber 20 and between each port. The lower portion of each partition may extend close to the first surface 61 of the substrate 60 (eg, about 0.5 mm or more from the first surface 61 ). In this manner, the lower portion of the partition 460 may be separated from the substrate surface by a distance sufficient to allow the gas flow to flow around the lower portion toward the vacuum port 455 after the gas flow reacts with the substrate surface. Arrow 498 indicates the direction of gas flow. Since the partitions 460 can operate as physical barriers to gas flow, the partitions 460 can also limit cross-contamination between precursors. The configuration shown is illustrative only and should not be considered as limiting the scope of the present technology. Those of ordinary skill in the art will understand that the gas distribution system shown is only one possible distribution system and that other types of showerheads may be employed.

In operation, substrate 60 may be delivered to load lock chamber 10 (eg, by a robot) and may be placed on transfer shuttle 65 . After the isolation valve 15 is opened, the shuttle 65 can move along the track 70 . Once the shuttle 65 enters the processing chamber 20 , the isolation valve 15 can be closed to seal the processing chamber 20 . The shuttle 65 can then be moved through the processing chamber 20 for processing. In one embodiment, the shuttle 65 can move through the chamber in a straight path.

As the substrate 60 moves through the processing chamber 20, the first surface 61 of the substrate 60 may be repeatedly exposed to the precursor of compound A from the gas port 425 and the precursor of the compound B from the gas port 435, with therebetween 445 purge gas. The injection of the purge gas can be designed to remove unreacted material from the previous precursor before exposing the substrate surface 61 to the next precursor. After each exposure to the various gas streams, the gas streams can be evacuated via vacuum port 455 by pumping system 450 . Since vacuum ports can be provided on both sides of each gas port, the gas flow can be evacuated through the vacuum ports 455 on both sides. Thus, gas flow can flow vertically downward from the individual gas ports towards the first surface 61 of the substrate 60 , across the first surface 410 and around the lower portion of the partition 460 , and finally upward towards the vacuum port 455 . In this way, each gas can be distributed uniformly across the substrate surface 61 . The substrate 60 may also be rotated while exposed to various gas streams. Rotation of the substrate can be useful to prevent banding in the formed layers. The rotation of the substrate can be a continuous or separate step.

The extent to which the substrate surface 61 is exposed to each gas can be determined by, for example, the flow rate of each gas from the gas ports and the rate of movement of the substrate 60 . In one embodiment, the flow rate of each gas can be configured without removing the absorbed precursor from the substrate surface 61 . The width between each partition, the number of gas ports disposed on the processing chamber 20, and the number of times the substrate may be passed back and forth may also determine the extent to which the substrate surface 61 is exposed to the various gases. Therefore, the quantity and quality of deposited films can be optimized by varying the above factors.

In another embodiment, system 400 may include precursor injector 420 and precursor injector 430 without purge gas injector 440 . Thus, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 may be alternately exposed to the compound A precursor and the compound B precursor without being exposed to the purge gas therebetween.

The embodiment shown in Figure 4 has a gas distribution plate 30 above the substrate. Although the embodiment has been described and illustrated for this upright orientation, it should be understood that the opposite orientation is also possible. In that case, the first surface 61 of the substrate 60 may face downward, while the gas flowing towards the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 may be positioned to heat the second side of the substrate.

In some embodiments, the transfer shuttle 65 may be a base 66 for carrying the substrate 60 . In general, the susceptor 66 may be a carrier that helps to create a uniform temperature across the substrate. The susceptor 66 is movable between the load lock chamber 10 and the process chamber 20 in both directions, left to right and right to left, relative to the arrangement of FIG. 4 . The base 66 may have a top surface 67 for carrying the substrate 60 . The susceptor 66 may be a heated susceptor such that the substrate 60 may be heated for processing. As an example, the susceptor 66 may be heated by a radiant heat source 90 disposed below the susceptor 66, a heating plate, a resistive coil, or other heating device. Although illustrated as a lateral translation, embodiments of system 400 may also be used in rotary systems, where the wheels may be rotated clockwise or counterclockwise to continuously process one or more substrates positioned below the gas distribution system shown. It should be similarly understood that additional modifications are included in the present technology.

FIG . 5 illustrates a method 500 of forming a semiconductor structure, in which many operations may be performed in, for example, chambers 200 and 400 previously described. The method may include aspects of epitaxial growth on the NMOS and PMOS regions of the substrate. The method 500 may include one or more operations prior to beginning the method, but may include front-end processing, deposition, etching, grinding, cleaning, or any other operation that may be performed prior to the operations. The method may include a number of optional operations, which may or may not be specifically associated with methods in accordance with the present technology. For example, many operations are described in order to provide a broader scope of structure formation, but are not critical to the technique, or may be performed by alternative methods, as discussed further below. Method 500 describes the operations schematically illustrated in FIGS. 6A- 6B , the description of which will be described in conjunction with the operation of method 500 . It should be understood that Figure 6 shows only a partial schematic view, and that the substrate may contain any number of transistor segments having the aspect shown in the figures.

FIG . 7 illustrates a method 700 of forming a semiconductor structure, many of which may be performed in, for example, chambers 200 and 400 previously described. The method may include aspects of silicidation on the NMOS and PMOS regions of the substrate. The method may include aspects of epitaxial growth on the source-drain regions. Method 700 may include one or more operations prior to beginning the method, but may include front-end processing, deposition, etching, grinding, cleaning, or any other operation that may be performed prior to the operations. The method may include a number of optional operations, which may or may not be specifically associated with methods in accordance with the present technology. For example, many operations are described in order to provide a broader scope of structure formation, but are not critical to the technique, or may be performed by alternative methods, as discussed further below. Method 700 describes the operations schematically illustrated in FIGS. 8A- 8B , the description of which will be described in conjunction with the operation of method 700 . It should be understood that Figure 8 shows only a partial schematic view, and that the substrate may contain any number of transistor segments having the aspect shown in the figures. It should be understood that the methods 500 and 700 are only exemplary, and in an embodiment, either the N region or the P region may be processed first. Both of these processing methods are included in the present technology.

Method 500 may involve operations performed on a substrate having a plurality of exposed regions, eg, on a substrate including regions further developed to produce transistor structures. As shown in FIG. 6A, a portion of processed substrate 600 is illustrated as including substrate 605, p-region source and drain 610, n-region source and drain 615, metal gate 620, cap layer 625 , and gate spacer 630 . The material can be formed in a previous operation and can be polished, etched, or processed to produce the structures shown. The operations of method 500 can be performed to limit or eliminate masking operations and RIE processing including ashing and cleaning, and can reduce processing queue time for providing epitaxial material during generation of the structure to reduce NMOS and NMOS of the structure. Contact resistance in the PMOS region.

The method 700 may also involve operations performed on a substrate having a plurality of exposed regions, such as on a substrate including regions further developed to produce transistor structures. As shown in FIG. 8A, a portion of processed substrate 600 is illustrated as including substrate 605, p-region source and drain 610, n-region source and drain 615, metal gate 620, cap layer 625 , and gate spacer 630 . For example, as formed during method 500 , the structure may also include first semiconductor material 635 and second semiconductor material 640 . The material can be formed in a previous operation and can be polished, etched, or processed to produce the structures shown. The operations of method 700 may be performed to limit or eliminate masking operations and RIE processes including ashing and cleaning, and may reduce process queue time for providing silicided material during generation of structures to reduce NMOS and PMOS of structures contact resistance in the area.

The materials used may be various dielectric materials, metallic materials, and semiconductor materials known in the art. For example, the substrate 605 may be silicon or some silicon-containing material. The p-region source and drain 610 can be formed in the PMOS region of the structure and can be silicon germanium or some other p-channel metal oxide semiconductor material. The source and drain 615 of the n-region may be phosphide or some other n-channel metal oxide semiconductor material. Metal gate 620 may be tungsten, cobalt, or some other conductive material. The cap material 625 may be a self-aligned contact cap, and may be silicon nitride, silicon carbide, or some oxide material including metal oxides (eg, tungsten oxide or aluminum oxide). For example, the gate spacer 630 can be any dielectric material, and can be, for example, a silicon-containing material, an oxygen-containing material, a carbon-containing material, or some combination (eg, silicon oxycarbide).

Method 500 may initially include the step of depositing semiconductor material 635 at operation 505 as shown in FIG. 6A. The semiconductor material 635 may be any known semiconductor material, and in embodiments may be germanium deposited as the semiconductor material 635 since it may be formed on the PMOS source and drain material as shown. The deposition of semiconductor material 635 may be selectively deposited on the source and drain sections 610 of the p-region, and may not be formed on any other exposed material (including cap material 625, gate spacer 630, or possibly in NMOS any material that remains exposed in the area). In embodiments, deposition may be performed without first blocking the NMOS region (eg, by forming a photoresist or hard mask). The semiconductor material 635 may be formed using any number of ways and may be epitaxially grown using precursors to utilize one or more selective deposition operations discussed further below. For example, where the exemplary semiconductor material 635 is germanium, germanium-containing precursors and hydrides (eg, including II, III, IV, or V metal hydrides) or organometallic precursors may be used Metal-organic vapor phase epitaxy (eg, methylated metals or other organic structures) to perform the processing. The treatment can be carried out at a temperature above or below or about 500°C, and can be carried out at a pressure below about 1 Torr, and can be carried out at a pressure below or about 1 mTorr.

Method 500 may also include the step of depositing semiconductor material 640 at operation 510 as shown in FIG. 6B. The semiconductor material 640 may be any known semiconductor material, and in embodiments may be a III-V semiconductor deposited as the semiconductor material 640 (eg, a III-V semiconductor) as it may be formed on NMOS source and drain materials as shown. indium gallium arsenide). The deposition of semiconductor material 640 may be selectively deposited on the source and drain sections 615 of the n-region, and may not be formed on any other exposed materials (including cap material 625, gate spacer 630, or possibly in PMOS any material that remains exposed in the area). In embodiments, deposition may be performed without first blocking the PMOS region (eg, by forming a photoresist or hard mask). The semiconductor material 640 may be formed using any number of ways, and may be epitaxially grown using precursors to utilize one or more selective deposition operations discussed further below. For example, where the exemplary semiconductor material 640 is indium gallium arsenide, indium-containing precursors, gallium-containing precursors, and hydrides (eg, including group II, group III, group IV, or group V) may be used metal hydride) or metal-organic vapor phase epitaxy of organometallic precursors (eg, methylated metals or other organic structures) to perform the treatment. In an embodiment, the additional precursor may be an arsenic-containing precursor. The treatment can be carried out at a temperature above or below or about 500°C, and can be carried out at a pressure below about 1 Torr, and can be carried out at a pressure below or about 1 mTorr.

Method 700 may include the step of depositing a first alloy material 845 at operation 715 as shown in FIG. 8A. For example, previous operations may occur at operation 712 where a silicon-containing material may be formed over semiconductor material 635 . Silicon-containing materials can be used to create alloys by subsequent annealing operations. The alloy material may be any number of materials including an alloy of nickel. The first alloy material 845 may be formed by alloying nickel with a silicon-containing material (eg, silicon germanium) to form nickel silicon germanium. Silicon germanium may initially be formed in operation 712 and then annealed with nickel. Additional second and third nickel-containing alloys or other metal alloys may also be formed. For example, nickel can be used as a material layer since it can also be formed over the PMOS source and drain materials as shown. The deposition of the first alloy material 845 may be selectively deposited on the first semiconductor material 635 and may not be formed on any other exposed materials (including the cap material 625, the gate spacer 630, or may remain exposed in the NMOS region any material). In embodiments, deposition may be performed without first blocking the NMOS region (eg, by forming a photoresist or hard mask).

The alloy material can be formed in a variety of ways, and can be formed by creating a first material layer and then forming the alloy material. In one example of forming nickel silicon germanium, a silicon germanium layer may be formed, followed by a nickel layer. Additional intermediate layers (eg, titanium or aluminum layers between the silicon germanium layer and the nickel layer) may also be formed to aid in alloy formation. An annealing operation (eg, rapid thermal annealing) may then be performed at temperatures above 400° C. to allow nickel to penetrate the silicon germanium and form nickel silicon germanium. The treatment can also be carried out at a pressure of less than about 1 Torr, and can be carried out at a pressure of less than or about 1 mTorr.

Method 700 may include the step of depositing a second alloy material 850 at operation 720 as shown in FIG. 8B. The alloy material can be any number of materials including an alloy of titanium. Again, a second silicon-containing material may be first deposited at operation 718 to form an alloy as described above. The second alloy material 850 may be formed by alloying titanium with a silicon-containing material (eg, silicon nitride) to form titanium silicon nitride. Additional second and third titanium-containing alloys or other metal alloys may also be formed. For example, titanium can be used as a material layer since it can also be formed over the NMOS source and drain materials as shown. The deposition of the second alloy material 850 may be selectively deposited on the second semiconductor material 640 and may not be formed on any other exposed materials (including the cap material 625, the gate spacer 630, or may remain exposed in the PMOS region) any material).

In embodiments, deposition may be performed without first blocking the PMOS region (eg, by forming a photoresist or hard mask). The alloy material can be formed in a variety of ways, and can be formed by creating a first material layer and then forming the alloy material. In one example of forming titanium silicon nitride, a silicon nitride layer may be formed followed by a titanium layer. Again, additional intermediate layers may be formed as previously described. Then, an annealing operation (eg, rapid thermal annealing) may be performed at temperatures above 400° C. to allow the titanium to infiltrate the silicon nitride and form titanium silicon nitride. The treatment can also be carried out at a pressure of less than about 1 Torr, and can be carried out at a pressure of less than or about 1 mTorr.

Since many materials are localized or formed in specific areas, the deposited layers can often be different from other exposed material layers (on which deposition does not occur, or to a lesser extent). By depositing layers of material consisting of a different material than the other exposed materials, one or more of layers 635, 640, 845, and 850 may be formed using a variety of selective deposition techniques.

Selective deposition of any of the disclosed materials may be performed in a chamber capable of deposition and atomic layer deposition, including chamber 400 described above. Prerequisites for deposition may be based on the selective deposition of metal or semiconductor materials relative to dielectric or insulating materials including cap material 625 and gate spacers 630 and other exposed materials in regions other than where deposition occurs. For example, the first semiconductor material 635 (which may be germanium in some embodiments) may be formed substantially over the p-region source and drain material 610 (which may be silicon germanium), while being minimally formed over the gate Spacer 630 is alternatively limited to gate spacer 630 (which may be silicon oxycarbide among other materials). The first semiconductor material 635 may also be minimally formed from or limited to the nitride, carbide, or oxide cap material 625 and exposed material in the NMOS region (eg, the source and drain of the n-region which may be phosphide). pole material 615). The following selective deposition can be similarly performed to deposit more material in the desired locations than on any other exposed material, which may also include substrate 605, which may be silicon or some other semiconductor material. Selective deposition can be performed by a variety of operations, which can include forming a self-assembled monolayer to facilitate selective deposition, or can include actively inhibiting the formation of materials on other dielectric materials.

Self-assembled monolayers can be formed over regions of the structure to tune the deposition. For example, a first self-assembled monolayer can be formed on the structure and then exposed to a lithographic mask to deposit (eg, source and drain material 610 in the p-region or source and drain material in the n-region Any area on the pole material 615) removes the monolayer. Materials previously formed in these regions can also be targeted for subsequent depositions. A single layer may be maintained on a dielectric or insulating material (eg, cap material 625 and gate spacer 630). The monolayer may have capping moieties that may repel or be unable to interact with the precursors that are delivered later. For example, in an embodiment, the capping moiety can be hydrophobic and can be capped with a hydrogen-containing moiety (eg, methyl), which may not interact with additional precursors. A second self-assembled monolayer can be formed on the target region (eg, on the source and drain material 610 of the p region or the source and drain material 615 of the n region). This self-assembled monolayer can be hydrophilic, or reacted with one or more precursors for producing a particular deposition material, which can be any of the foregoing. Because the material can repel the first self-assembled monolayer, or can selectively draw to the target area, the second self-assembled monolayer can be selectively formed on the target area. The second self-assembled monolayer can be terminated with hydroxyl or other hydrophilic moieties, or with moieties that specifically interact with additional precursors used to form a given deposition material (eg, metal or dielectric material).

Atomic layer deposition may then be performed using two or more precursors to form the deposition material (which may be any of the materials previously described for layers 635, 640, 845, 850). The deposited precursor may include a metal- or silicon-containing precursor, and includes a precursor configured to interact with portions of the capped second self-assembled monolayer (rather than the first self-assembled monolayer). For example, when hydrophilic and hydrophobic terminated monolayers are used, one of the atomic layer deposition precursors may include water. In this way, deposition may not form on the first self-assembled monolayer, which may be hydrophobic. If the deposition material includes a metal oxide, the precursor for atomic layer deposition may include the specified metal-containing precursor and water. For example, once formed, the oxide can be removed to leave a metal layer. In other embodiments, silicon-containing precursors may be used. Then, during the half-reaction with water, the water may not be able to interact with the first self-assembled monolayer formed on the otherwise exposed material, and thus the deposition may not form on the first self-assembled monolayer. In this manner, specific materials may be selectively formed on the target area, or preferentially formed on the target area. It should be understood that this is a single example and other precursors may be used with similar operating principles to form the specific materials previously described for each deposition region.

After the identified deposits have been formed to a suitable height, the first self-assembled monolayer can be exposed to UV light and removed from the substrate, or some other removal can be performed. In this way, multiple operations used in conventional formations can be eliminated, which can significantly reduce queue time (eg, hours). In other embodiments, depending on the operation performed, a slight undercut may be performed after selective deposition to remove residual material from other exposed areas discussed below. It should be understood that this is only an example of utilizing a self-assembled monolayer based on a set of deposited materials.

Depending on the material used for a particular deposition material, the self-assembled monolayer can be tuned towards that material. Water can serve as one of the precursors, as previously described, and as previously described, the self-assembled monolayer can be structured (eg, including hydroxyl-terminated materials at targeted sites to facilitate formation relative to other exposed materials) on this material). Furthermore, the nitrogen-containing material may serve as one of the self-assembled monolayers on the material for deposition to occur (eg, one of the capped portions of the monolayer), while allowing attraction to be used in the formation of previously described materials specific precursors of one or more. Additional precursors may be used to enable or facilitate metal-to-metal deposition or semiconductor deposition.

Because of the structure of some exposed metal or semiconductor materials, the exposed material may also be corroded or passivated to reduce activity relative to other materials on which deposition occurs, which may allow increased deposition on the target material. Passivation of materials can include exposure to silicon-substituted or halogen-substituted materials, which can limit deposition of other materials. For example, oxidation of materials can utilize oxygen-containing materials or halogen-containing materials, which can allow preferential deposition on other surfaces. Once oxidized (eg, by exposure to an oxygen-containing material), atomic layer deposition may be performed similarly to that described, wherein one of the precursors may include the oxygen-containing material, which may not interact with the oxidizing material.

Passivation can also be performed on exposed insulating and dielectric materials. For example, the cap material 625 may include an oxide, such as may be treated to adjust the capping group to contain silicon, hydrogen, or halogen. This may allow for preferential deposition of metallic or semiconductor materials over other exposed areas. In other embodiments, nitrogen-containing precursors may be used as one or both precursors in the atomic layer deposition process, which may allow preferential deposition on metal surfaces over oxide surfaces.

Embodiments may also utilize inhibitors to selectively form one of the deposited materials on the target surface rather than on dielectric or insulating materials or other exposed surfaces. For example, the sprayed inhibitor may be applied across the surface of the substrate, and may be applied along the top surface of the substrate, and may not penetrate into recessed portions of the substrate. The inhibitor can be any number of materials that can be characterized by a siloxane backbone (eg, siloxane) or a tetrafluoroethylene backbone (eg, PTFE), as well as other oily or surfactant materials. Material may be applied across the top surface of the substrate to cover exposed portions of cap material 625 and gate spacer 630 . By using a spray or coating application, the material may not be applied within the recessed portions of the substrate, and may not contact the source and drain regions on which the deposition takes place. Additional selective techniques can be used in combination to form self-assembled monolayers on the PMOS and NMOS regions, such as previously described, to facilitate deposition at one location but not the other. The selected material may then be formed, for example, by atomic layer deposition or other vapor deposition or physical deposition mechanisms.

The inhibitor material can prevent adhesion or adsorption of the deposited material that would normally form or deposit on the target site. After the material is formed, a remover may be applied to the substrate to remove the inhibitor material. The remover can be a wet etchant, reactant, or surfactant cleaner, and can remove residual inhibitor material that exposes underlying dielectric and insulating materials. Utilizing an inhibitor may allow individual layers to be formed in defined areas without the need for subsequent patterning and/or etching definition of the blanket film. By removing previous and subsequent patterning operations, the process can further reduce queue time relative to conventional processes.

The inhibitor can also be the product of a plasma application that can neutralize or render the surface of the substrate inert. For example, the modified plasma can be formed from one or more precursors, and can include inert precursors. The plasma may be applied to the surface of the substrate or material raised above the substrate, while the top surface of the exposed material may be altered and may not penetrate into recessed portions of the substrate or portions at the surface of the substrate. For example, a nitrogen-containing precursor, which may be nitrogen, can be delivered to a plasma processing region of a plasma-generating processing chamber. Plasma effluent (which may include nitrogen-containing plasma effluent) may be delivered to the substrate and a nitrided surface (which may include exposure of cap material 625 and gate spacer 630 may be formed along the exposed portion of the substrate along the top surface area).

Plasma effluent may not be delivered or may not flow to the surface of the substrate, but may maintain a pure or unreacted surface along the source and drain materials. The deposition material may then be formed (eg, to form a self-assembled monolayer) using one or more deposition techniques and/or additional selective techniques, which may include atomic layer deposition or other vapor or physical deposition. For example, atomic layer deposition techniques can be used for subsequent processing with plasma effluents and to form self-assembled monolayers on the PMOS and NMOS regions of the substrate. After each cycle of deposition, the nitrogen-containing plasma can be reapplied onto the surface area of the substrate (eg, on a dielectric or insulating material). In this way, the surface of the dielectric material can be passivated to prevent or limit the formation of deposited material on those areas. Utilizing these plasma effluents from the raised portion of the substrate may allow deposition material to form in defined areas along the substrate surface without requiring subsequent patterning and/or etching definition of the blanket film. By removing previous and subsequent patterning operations, the process can further reduce queue time relative to conventional processes.

Additional selective deposition techniques may utilize temperature differentials to enhance deposition on silicon-containing materials relative to oxygen-containing materials. For example, atomic layer deposition using silicon-containing precursors can be performed at temperatures above or about 500°C, and can be performed at temperatures above or about 750°C, above or about 900°C, above or about 1000°C, or at a temperature of at, above, or about 1100°C.

As the temperature increases within this range, deposition may occur at a higher rate on certain exposed materials than on oxygen-containing materials (eg, which may be cap material 625). Then, a selective etch of the formed material can be performed to remove the first dielectric material from the oxide surface. Although the first semiconductor material can also be reduced on the target surface, since the thickness can be many times thicker than on the oxide surface, complete removal of the oxide surface can be performed while maintaining a thickness on the target surface greater than or about 1 nm, Greater than or about 2 nm, greater than or about 3 nm, greater than or about 4 nm, greater than or about 5 nm, greater than or about 6 nm, greater than or about 7 nm, greater than or about 8 nm, greater than or about 9 nm, greater than or about 10 nm, or greater. This effect may be achieved with the present technology in a manner limited by the prior art. During normal conformal or blanket deposition, the thickness of some portions of the target surface will be equal to the thickness on the cover material, or may be less than the thickness on the cover material. Therefore, the etch-back process may over-etch the target area, or may cause perforations in the layer.

Any of these techniques may selectively deposit or form the previously specified materials relative to one or more other metal, semiconductor, non-metal, dielectric, or insulating regions. Furthermore, two or more of these techniques may be combined or performed iteratively to produce surfaces with specific regions where deposition may occur or may take advantage of higher rates. Selectivity can be complete, where deposition material is formed only on target locations (eg, source and drain 610 in p-regions or source and drain 615 in n-regions, or intermediate layers) and can be completely absent from other A deposition material is formed on the exposed material. In other embodiments, the selectivity may not be complete, and the ratio of deposition on target sites to other exposed materials may be greater than or about 2:1. The selectivity can also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35 : 1, greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more. As previously described, the thickness of the deposition of material may be less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or less. Thus, selectivities below 20:1 may be acceptable to fully deposit individual layers while forming limited or substantially no material on other exposed areas.

The deposition operation may be performed at any of the aforementioned temperatures or pressures, and may be performed at temperatures greater than or about 300°C, and may be performed at greater than or about 400°C, greater than or about 450°C, greater than or about 500°C, greater than or about Performed at a temperature of 600°C, greater than or about 700°C, greater than or about 800°C, greater than or about 900°C, greater than or about 1000°C, or higher. For example, during atomic layer deposition operations, temperatures greater than or about 500° C. may be used to activate the precursors to interact with each other as material layers are formed.

Depending on the type of deposition performed, certain operations may be performed in a different order than previously described. For example, if a single layer (formed to resist or prevent formation) can be used with more than one material, the layer can be maintained during subsequent operations to increase efficiency. For example, method 500 is shown forming indium gallium arsenide prior to forming nickel alloy material on germanium in the PMOS region of method 700 . However, if self-assembled monolayers are used to resist, reduce, or prevent the formation of germanium layers on other exposed materials, these layers can be maintained during subsequent operations of alloying the metal (eg, forming an initial silicon germanium layer). In this manner, in some embodiments, operations 510 and 715 may be reversed, and all PMOS operations may be performed continuously, and all NMOS operations may be performed continuously.

Depending on the number of formations and the selectivity of the individual depositions, one or more etching operations may also be performed. The etching operation may utilize dry etching chemistries, and in embodiments may utilize plasma chemistries. For example, etch-back can be performed in chamber 200, which can be on the same cluster tool as one or more deposition chambers that performed previous depositions. In this way, several deposition and etch operations can be performed in a single environment (eg, cluster tool sharing between chambers). For example, additional chambers may be used in conjunction with one or more of etch chamber 200 and deposition chamber 400, eg, for performing UV processing, as may be used in some of the deposition techniques described below. Each transfer can be performed under vacuum, while each of the chambers can reside on the same cluster tool to allow the transfer to take place in a controlled environment. For example, vacuum conditions can be maintained during the transfer, and the transfer can be performed without breaking the vacuum. In contrast to conventional techniques that may include additional masking operations, lithography, and other operations that may require transfer between many tools, method 500 may be performed on a single tool, wherein vacuum conditions are not violated in embodiments. Additionally, method 500 may not utilize any RIE operations, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE.

Etching operations may be performed using plasma excited precursors and may involve additional precursors along with specific fluorine-containing precursors. In some embodiments, nitrogen trifluoride can be used to generate the plasma effluent. Additional or alternative fluorine-containing precursors may also be utilized. For example, a fluorine-containing precursor can flow into the remote plasma region, and the fluorine-containing precursor can include a fluorine-containing precursor selected from the group consisting of atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, hexafluoride At least one precursor of the group of sulfur fluoride, and xenon difluoride. The distal plasma region may be in a separate module from the processing chamber or in a compartment within the processing chamber. As shown in FIG. 2, both the RPS cell 201 and the first plasmonic region 215 may serve as a remote plasmonic region. The RPS can allow the plasmonic effluent to dissociate without damaging other chamber components, while the first plasmonic region 215 can provide a shorter path length to the substrate during which recombination may occur.

Additional precursors can also be delivered to the distal plasmonic region to enhance fluorine-containing precursors. For example, a nitrogen and hydrogen-containing precursor, an oxygen-containing precursor, or a hydrogen-containing precursor can be delivered with a fluorine-containing precursor. For example, the additional precursor may be a nitrogen-containing precursor (eg, ammonia), or may be oxygen, hydrogen, or any number of precursors including one or more of these components. Additional precursors can flow into the processing chamber in an unexcited state to interact with the substrate surface. These formulations can selectively etch one of the exposed materials relative to one or more of the other exposed materials. For example, etching chemistries may be used to recess one or more alloy materials and any epitaxially grown materials with respect to exposed lid and spacer materials and with respect to other formed materials. The selectivity of the etch can be greater than or about 10:1, greater than or about 20:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 150:1, or More. In this way, any additional material that may have formed during deposition can be removed with minimal loss of material formed at the desired location. This may occur because the selectivity of the deposition can yield at least twice as much material at the intended location as on other exposed materials.

In embodiments, etching operations may be performed below about 10 Torr, and in embodiments below or about 5 Torr. In embodiments, processing may also be performed at temperatures below about 100°C, and may be performed at temperatures below about 50°C. As performed in chamber 200 or a variation of this chamber, or in a different chamber capable of performing similar operations, processing may remove portions of the deposited material selectively with respect to other exposed material across the substrate. By utilizing the present technique, fabrication can be performed with more selective formation and removal than conventional techniques, and queue time can be reduced by hours over conventional processes.

In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details or with additional details.

Several embodiments have been disclosed, but it should be understood that various modifications, alternative constructions, and equivalents may be employed by those of ordinary skill in the art without departing from the spirit of the embodiments. Furthermore, many well-known processes and elements have not been described in order to avoid unnecessarily obscuring the technology. Accordingly, the above description should not be construed as limiting the scope of the present technology.

When a range of values is provided, it is to be understood that, unless the context clearly dictates otherwise, each intervening value between the upper and lower limit of the range to the smallest part of the unit of the lower limit is also specifically disclosed. Included are any narrower ranges between any stated or unrecited intervening value in a stated range and any other stated or intervening value in that stated range. The upper and lower limits of these smaller ranges may independently be included in or excluded from the range, and each of the smaller ranges including either, both, or exclusive of the upper and lower limits, is also encompassed within the technology, Depends on the limitations specifically excluded in the stated range. Where the stated range includes one or both of the limitations, ranges excluding either or both of those included limitations are also included.

As used herein and in the scope of the appended patent application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, by way of example, reference to "a layer" includes a plurality of such layers, and reference to a "precursor" includes reference to one or more precursors and equivalents thereof known to those of ordinary skill in the art, and the like.

Furthermore, when the words "comprises," "includes," "includes," "includes," "includes," and "includes" are used in this specification and the following claims, they are intended to The presence of a component, or operation, does not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

10‧‧‧Load Lock Chamber 15‧‧‧Isolation Valve 20‧‧‧Processing Chamber 30‧‧‧Gas Distribution Plate 60‧‧‧Substrate 61‧‧‧First Surface 65‧‧‧Transfer Shuttle 70‧‧‧ Rail 90‧‧‧Radiant heat source 100‧‧‧Processing system 102‧‧‧Front-loading pod 104‧‧‧Robot arm 106‧‧‧Holding area 108a‧‧‧Processing chamber 108b‧‧‧Processing chamber 108c ‧‧‧Processing chamber 108d‧‧‧Processing chamber 108e‧‧‧Processing chamber 108f‧‧‧Processing chamber 109a‧‧‧Series section 109b‧‧‧Series section 109c‧‧‧Series section 110‧ ‧‧Second Robot Arm 200‧‧‧Chamber 201‧‧‧RPS Unit 203‧‧‧Cooling Plate 205‧‧‧Gas Inlet Assembly 210‧‧‧Fluid Supply System 214‧‧‧Top Plate 215‧‧‧First Plasma area 216‧‧‧Lower plate 217‧‧‧Panel 218‧‧‧Volume 219‧‧‧First fluid channel 220‧‧‧Insulating ring 221‧‧‧Second fluid channel 223‧‧‧Ion suppressor 225‧ ‧‧Shower head 233‧‧‧Substrate processing area 240‧‧‧Power supply 253‧‧‧Detailed view 255‧‧‧Substrate 258‧‧‧Gas supply area 259‧‧‧Aperture 265‧‧‧Pedestal 325‧‧ ‧Sprinkler head 365‧‧‧Through hole 375‧‧‧Small hole 400‧‧‧Chamber 420‧‧‧Injector 425‧‧‧Gas port 430‧‧‧Injector 435‧‧‧Gas port 440‧‧‧Injector 445 ‧‧‧Gas Port 450‧‧‧Pumping System 455‧‧‧Vacuum Port 460‧‧‧Zone 498‧‧‧Arrow 500‧‧‧Method 505‧‧‧Operation 510‧‧‧Operation 600‧‧‧Substrate 605‧ ‧‧Substrate 610‧‧‧Source and drain in p region 615‧‧‧Source and drain in n region 620‧‧‧Metal gate 625‧‧‧Cap material 630‧‧‧Gate spacer 635‧ ‧‧First Semiconductor Material 640‧‧‧Second Semiconductor Material 700‧‧‧Method 712‧‧‧Operation 715‧‧‧Operation 718‧‧‧Operation 720‧‧‧Operation 845‧‧‧First Alloy Material 850‧‧ ‧Second alloy material

A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the remainder of the specification and drawings.

1 illustrates a top plan view of an exemplary processing system in accordance with an embodiment of the present technology.

2A illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with embodiments of the present technology.

2B illustrates a detailed view of an exemplary panel in accordance with an embodiment of the present technology.

3 illustrates a bottom plan view of an exemplary showerhead in accordance with embodiments of the present technology.

4 illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.

5 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

6A-6B illustrate schematic cross-sectional views of exemplary substrates in accordance with embodiments of the present technology.

7 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

8A-8B illustrate schematic cross-sectional views of exemplary substrates in accordance with embodiments of the present technology.

Several of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes only and should not be considered to scale unless specifically stated to be to scale. Furthermore, as schematic drawings, the drawings are provided to aid understanding and may not include all aspects or information as compared to actual representations and may include exaggerated material for illustrative purposes.

In the accompanying drawings, similar components and/or features may have the same reference numerals. In addition, various components of the same type may be distinguished by using a letter after the reference symbol to distinguish similar components. If only the leading reference number is used in the specification, the description applies to any one similar component having the same leading reference symbol, regardless of the letter.

Domestic storage information (please note in the order of storage institution, date and number) None

Foreign deposit information (please note in the order of deposit country, institution, date and number) None

600: Substrate

605: Substrate

610: Source and drain of p region

615: The source and drain of the n region

620: Metal gate

625: Cover material

630: Gate Spacer

635: First Semiconductor Materials

Claims (18)

A method of forming a semiconductor structure, the method comprising the steps of: depositing a first semiconductor material on a semiconductor substrate, wherein the first semiconductor material is selectively deposited on a first silicon-containing material relative to a second silicon-containing material and depositing a second semiconductor material on the semiconductor substrate, wherein the second semiconductor material is selectively deposited on the second silicon-containing material relative to the first semiconductor material, wherein the method is not performed performed in the case of a reactive ion etching operation. The method of forming a semiconductor structure of claim 1, wherein the first semiconductor material is deposited on a PMOS region of the semiconductor substrate relative to an NMOS region of the semiconductor substrate. The method of forming a semiconductor structure of claim 1, wherein the first semiconductor material comprises germanium, and wherein the first silicon-containing material comprises silicon germanium. The method of forming a semiconductor structure of claim 3, wherein the second silicon-containing material comprises phosphorous. The method of forming a semiconductor structure of claim 1, wherein using the first silicon-containing material relative to the second silicon-containing material is greater than The first semiconductor material deposition is performed with a selectivity of about 2:1. A method of forming a semiconductor structure as recited in claim 1, wherein the deposition occurs on an NMOS region of the semiconductor substrate relative to a PMOS region of the semiconductor substrate. A method of forming a semiconductor structure as recited in claim 6, wherein the method is performed without forming a photoresist on the PMOS region. The method of forming a semiconductor structure of claim 1, wherein the first semiconductor material comprises indium, and wherein the first silicon-containing material comprises silicon phosphide. The method of forming a semiconductor structure of claim 8, wherein the second silicon-containing material comprises germanium. The method of forming a semiconductor structure as claimed in claim 8, wherein the first semiconductor material is indium gallium arsenide. A method of forming a semiconductor structure, the method comprising the steps of: depositing a first alloy material on a first semiconductor material, wherein the alloy material is selectively deposited on the first relative to a nitride material or an oxide material on a semiconductor material; and subsequently depositing a second alloy material on a second semiconductor material, wherein the second alloy material is selectively deposited on the second semiconductor material relative to the nitride material or the oxide material, Wherein the method is performed without a reactive ion etching operation. The method of forming a semiconductor structure of claim 11, wherein the first alloy material is deposited on an indium-containing material located in an NMOS region of the semiconductor substrate, and wherein the second alloy material is deposited on the on a germanium-containing material in a PMOS region of a semiconductor substrate. The method of forming a semiconductor structure of claim 11, wherein the nitride material comprises silicon nitride, and wherein the oxide material comprises silicon oxide, silicon oxycarbide, or a metal oxide. The method of forming a semiconductor structure of claim 13, wherein the metal oxide comprises tungsten oxide or aluminum oxide. The method of forming a semiconductor structure of claim 11, wherein the second alloy material comprises a nickel-containing material. The method of forming a semiconductor structure of claim 15, wherein the second alloy material comprises nickel silicon germanium. The method of forming a semiconductor structure of claim 11, wherein the first alloy material comprises a titanium-containing material. The method of forming a semiconductor structure of claim 17, wherein the first alloy material comprises titanium silicon nitride.

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