TWI782981B - Conversion of sub-fin to soi - Google Patents

Abstract

Processing methods may be performed to form semiconductor structures that may include fin elements on dielectric materials. The methods may include depositing a first dielectric material on a silicon element on a semiconductor substrate. The first dielectric material may be selectively deposited on the silicon element relative to exposed regions of a second dielectric material. The methods may include converting a portion of the silicon element to silicon oxide. The methods may also include selectively etching the first dielectric material from the silicon element.

Description

Sub-fin to Si-on-insulator conversion

The technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to systems and methods for selectively etching and selectively depositing layers of materials on semiconductor devices.

Integrated circuits may be made by processes that create intricately patterned layers of material on the surface of a substrate. Generating patterned material on a substrate requires a controlled method for removing exposed material. Chemical etching is used for a variety of purposes including transferring the pattern in the photoresist into underlying layers, thinning layers, or thinning the lateral dimensions of features already present on the surface. It is often desirable to have an etch process that etches one material faster than the other to facilitate eg pattern transfer processes or individual material removal. This etching process is said to be selective to the first material. Due to the variety of materials, circuits, and processes, etch processes have been developed that are selective to a variety of materials. Typically, however, the deposition process continues across the substrate using blanket coating or conformal fill.

As device dimensions continue to shrink in next-generation devices, selectivity can play a greater role when the material formed in a particular layer is only a few nanometers (especially when the material is critical in transistor formation). Many different etch process selectivities have been developed between various materials, but standard selectivities may no longer be appropriate for current and future device scales. Furthermore, queue times for processing continue to increase based on the number of masking, forming, and removal operations required to form and protect various critical dimensions of features spanning the device while patterning and forming are performed elsewhere on the substrate.

Therefore, there is a need for a system and method for producing high quality devices and structural improvements. The present technology addresses these and other needs.

Processing methods may be performed to form semiconductor structures that may include fin elements on dielectric materials. The method may include the step of depositing a first dielectric material on a silicon element on a semiconductor substrate. The first dielectric material can be selectively deposited on the silicon element relative to the exposed areas of the second dielectric material. The method may include the step of converting a portion of the silicon element into silicon oxide. The method may also include the step of selectively etching the first dielectric material from the silicon device.

In some embodiments, the first dielectric material may include silicon nitride, and the second dielectric material may include silicon oxide. Deposition may include atomic layer deposition processing. Converting may include performing annealing at a temperature above or about 100°C. The anneal converts a portion of the silicon device on the second dielectric material. Annealing may include wet annealing or dry annealing. The method may also include the step of depositing an additional second dielectric material around the first dielectric material. The method may further include the step of recessing the second dielectric material after switching. Deposition of the first dielectric material may be performed with a selectivity of greater than or about 2:1 for silicon elements relative to the second dielectric material. Silicon devices may include fins characterized by widths of less than 20 nm.

The technology can also include a method of forming a semiconductor structure. The method may include the step of depositing a nitrogen-containing material on a silicon element extending from a semiconductor substrate. The nitrogen-containing material can be selectively deposited on the silicon element relative to the exposed areas of the oxygen-containing material. A first portion of the silicon element may be contained within an oxygen-containing material. Additionally, a nitrogen-containing material may be deposited around a second portion of the silicon element extending from the oxygen-containing material. The method may also include the step of converting the first portion of the silicon device into silicon oxide. The method may include the step of selectively etching nitrogen-containing material from the silicon element.

In some embodiments, the method may further include the step of depositing additional oxygen-containing material around the deposited nitrogen-containing material. Additional oxygen-containing material may extend to an equal height of nitrogen-containing material. Features of the second portion of the silicon device may be up to about 200nm in height. The step of converting the first portion of the silicon element to silicon oxide converts less than 10% of the second portion of the silicon element to silicon oxide. The step of converting the first portion of the silicon device to silicon oxide converts the second portion of the silicon device smaller than 5nm to silicon oxide. Converting may include performing annealing at a temperature greater than or about 500°C. Annealing may include wet annealing or dry annealing.

The technology also includes a method of forming a semiconductor structure. The method may include the step of depositing a nitrogen-containing material on a silicon element extending from a semiconductor substrate. The nitrogen-containing material can be selectively deposited on the silicon element relative to the exposed areas of the oxygen-containing material. A first portion of the silicon element may be contained within an oxygen-containing material. Additionally, a nitrogen-containing material may be deposited around a second portion of the silicon element extending from the oxygen-containing material. The method may include the step of depositing additional oxygen-containing material around the deposited nitrogen-containing material. The method may include the step of: performing an anneal to convert the first portion of the silicon element into silicon oxide. The method may include the step of selectively etching additional oxygen-containing material from the semiconductor structure. The method may also include the step of selectively etching nitrogen-containing material from the silicon device. In some embodiments, each selective etch may utilize the effluent of a fluorine-containing plasma.

Such techniques can provide many benefits over conventional systems and techniques. For example, processing can preserve critical dimensions and provide improved selectivity by utilizing techniques that do not include reactive ion etching. Furthermore, by performing selective operations, a dedicated substrate may not be required. These and other embodiments, along with their many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

The techniques of the present invention include systems and components for semiconductor processing of fine pitch features. In conventional FinFET devices, silicon fins are typically formed on a silicon-on-insulator ("SOI") substrate. The silicon fins operate as gate electrodes to allow multiple gates to operate on a single transistor. Such fins can be developed on SOI wafers. However, SOI wafers are not widely adopted by the industry, and these wafers can be many times more expensive than standard silicon wafers. Silicon structures can include etching fins in the silicon wafer, followed by blanket deposition and recessed dielectric. However, the covered silicon, if not converted to silicon oxide, may cause current leakage during the off state. Converting portions of the silicon fins within the dielectric using conventional techniques may not be feasible due to the additional switching of the fin electrodes extending over the structure.

The present technique overcomes these problems by taking advantage of selective etch processes performed in specific equipment, and can use these processes to etch with higher selectivity than conventional RIE, which allows for additional patterns that may not have been possible before. , and can provide additional protection for critical feature dimensions such as thin fin profiles. By performing selective deposition operations in specific equipment, fin electrodes can be protected during switching of the bottom portion of the fin. These treatments can enable specific masks to be used to protect the fin extensions while performing conversion operations on the bottom portion of the fins.

While the remainder of the disclosure will routinely identify specific etch and deposition processes utilizing the disclosed techniques, it should be understood that the systems and methods are equally applicable to various other etch, deposition, and cleaning processes that may occur in the described chambers . Accordingly, the technique should not be considered limited to use with only the etch and deposition processes described. This disclosure will discuss one possible system and chamber that may be used with the present technology to perform certain removal and deposition operations prior to the described operations according to an exemplary processing sequence of the present technology.

FIG . 1 illustrates a top plan view of one embodiment of a processing system 100 of deposition, etch, bake, and cure chambers according to an embodiment. In the drawings, a pair of front opening unified pods (FOUPs) 102 supply substrates of various sizes, which are received by robotic arms 104 and placed into substrate processing chambers 108a located in serial sections 109a-c. - before one of f, placed in the low pressure holding area 106. The second robotic arm 110 may be used to transport the substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. In addition to cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etch, pre-clean, degassing, orientation, and other substrate treatments, Each substrate processing chamber 108a-f may be equipped to perform a number of substrate processing operations including dry etch processing and selective deposition as described herein.

The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and/or etching dielectric films on substrate wafers. In one configuration, two pairs of process chambers (eg, 108c-d and 108e-f) may be used to deposit dielectric or metal-containing materials on the substrate, while a third pair of process chambers (eg, 108a-b) Can be used to etch deposited dielectrics. In another configuration, all three pairs of chambers (eg, 108a-f) can be configured to etch a dielectric film on a substrate. Any one or more of the processes described may be performed in separate chambers from the fabrication systems shown in the various embodiments.

In some embodiments, the chambers specifically include at least one etching chamber as described below and at least one deposition chamber as described below. By including these chambers and combining the process side of the factory interface, all of the etch and deposition processes described below can be performed in a controlled environment. For example, a vacuum environment may be maintained on the processing side of the holding area 106 such that all chambers and transfers in embodiments are maintained under vacuum. This also limits the exposure of water vapor and other air components to the substrate being processed. It should be understood that the system 100 may contemplate additional configurations of deposition, etching, annealing, and curing chambers for dielectric films.

Figure 2A illustrates a cross-sectional view of an exemplary processing chamber system 200 having separate plasma generation regions within the processing chamber. During film etch (for example, titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.), the process gas can be passed through The gas inlet assembly 205 flows into the first plasma region 215 . A remote plasma system (RPS) 201 may optionally be included in the system and may process the first gas that then travels through the gas inlet assembly 205 . Inlet assembly 205 may include two or more different gas supply channels, where a second channel (not shown), if included, may bypass RPS 201 .

Cooling plate 203 , face plate 217 , ion eliminator 223 , showerhead 225 , and substrate support 265 with substrate 255 disposed thereon are shown, and each may be included according to embodiments. The pedestal 265 may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate, which may be manipulated during processing operations to heat and/or cool the substrate or wafer. Embedded resistive heater elements may also be used to resistively heat the wafer support plate, which may comprise aluminum, ceramic, or a combination of pedestals 265, to achieve relatively high temperatures, for example, from up to or about 100°C to greater than or about 1100°C .

Panel 217 may be pyramidal, conical, or other similar structure having a narrow top portion expanding to a wide bottom portion. As shown, face plate 217 may additionally be flat and include a plurality of through passages for distributing process gases. Depending on the use of the RPS 201 , the plasma generating gas and/or plasma stimulating species may pass through the plurality of holes in the face plate 217 as shown in FIG. 2B for more uniform delivery into the first plasma region 215 .

An exemplary configuration may include gas inlet assembly 205 opening into gas supply region 258 separated from first plasma region 215 by face plate 217 such that gas/substance flows through holes in face plate 217 into first plasma region 215 . Structural and operational features may be selected to prevent substantial backflow of plasma from first plasma region 215 into supply region 258 , gas inlet assembly 205 , and fluid supply system 210 . Panel 217 or conductive top portion of the chamber and showerhead 225 are shown with insulating ring 220 positioned between features to allow AC potential to be applied to panel 217 relative to showerhead 225 and/or ion eliminator 223 . An insulating ring 220 may be positioned between faceplate 217 and showerhead 225 and/or ion eliminator 223 to enable capacitively coupled plasma (CCP) formation in the first plasma region. Additionally, a baffle (not shown) may be located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid through the gas inlet assembly 205 into the region.

Ion eliminator 223 may comprise a plate or other geometric shape defining a plurality of apertures throughout the structure configured to eliminate migration of ionically charged species leaving first plasmonic region 215 while allowing uncharged neutral Or free radical species pass through the ion eliminator 223 into the reactive gas delivery region between the eliminator and the showerhead. In embodiments, ion eliminator 223 may comprise a perforated plate with various pore configurations. These uncharged species may include highly reactive species that utilize less reactive gas carriers to transport through the pores. As noted above, the migration of ionic species through the pores may be reduced, and in some cases eliminated entirely. Controlling the amount of ionic species passing through ion eliminator 223 may advantageously provide increased control over the gas mixture in contact with the underlying wafer substrate, which in turn may increase control over the deposition and/or etch characteristics of the gas mixture. For example, adjustment of the ion concentration of a gas mixture can significantly change its etch selectivity, eg, SiNx:SiOx etch rate, Si:SiOx etch rate, etc. In alternative embodiments where deposition is performed, the balance of conformal flow deposition of dielectric material may also be translated.

The plurality of apertures in ion eliminator 223 may be configured to control the passage of reactive gases (ie, ions, free radicals, and/or neutral species) through ion eliminator 223 . For example, the aspect ratio of the holes, or the hole diameter versus length, and/or the hole geometry can be controlled such that the flow of ionically charged species in the reactive gas passing through the ion eliminator 223 is reduced. The hole in ion eliminator 223 may include a tapered portion facing plasma excitation region 215 and a cylindrical portion facing showerhead 225 . The cylindrical portion can be shaped and dimensioned to control the flow of ionic species to the showerhead 225 . As an additional means of controlling the flow of ionic species through the eliminator, an adjustable electrical bias can also be applied to the ion eliminator 223 .

Ion eliminator 223 may be used to reduce or eliminate the amount of ionically charged species traveling from the plasma generation region to the substrate. Uncharged neutral and radical species can still pass through the openings in the ion eliminator to react with the substrate. It should be noted that in embodiments, complete elimination of ionically charged species in the reaction region surrounding the substrate may not be performed. In some cases, ionic species are intended to reach the substrate for etching and/or deposition processes. In these cases, ion eliminators can help control the concentration of ionic species in the reaction zone at levels that facilitate processing.

Showerhead 225 in combination with ion eliminator 223 may allow plasma present in first plasma region 215 to avoid direct excitation of gases in substrate processing region 233 while still allowing excited species to travel from chamber plasma region 215 to the substrate processing area 233 . In this way, the chamber may be configured to prevent the plasma from contacting the substrate 255 being etched. This advantageously protects the various complex structures and films patterned on the substrate, which may be damaged, displaced, or otherwise bent if in direct contact with the generated plasma. In addition, when the plasma is allowed to contact the substrate or approach the substrate level, the rate at which the oxide species etch can be increased. Thus, if the exposed regions of the material are oxides, the material can be further protected by maintaining the plasma remotely from the substrate.

The processing system may further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the faceplate 217, the ion eliminator 223, the showerhead 225, and/or the pedestal 265 to generate power in the first plasma region 215 or A plasma is generated in the processing region 233 . Depending on the process being performed, the power supply can be configured to deliver an adjustable amount of power to the chamber. This configuration could allow tunable plasmons for in-flight processing. Unlike remote plasma units, which typically appear to have an on or off function, a tunable plasma can be configured to deliver a specific amount of power to the plasma region 215 . This in turn allows for the formation of specific plasmonic properties such that the precursors can be dissociated in specific ways to enhance the etch profile produced by these precursors.

Plasma may be excited in chamber plasma region 215 above showerhead 225 or in substrate processing region 233 below showerhead 225 . In an embodiment, the plasma formed in the substrate processing region 233 may be a DC bias plasma formed using a pedestal as an electrode. A plasma may be present in the chamber plasma region 215 to generate free radical precursors from, for example, the influx of fluorine-containing precursors or other precursors. Typically, an AC voltage in the radio frequency (RF) range may be applied between a conductive top portion of the processing chamber (e.g., face plate 217) and showerhead 225 and/or ion eliminator 223 to excite the chamber during deposition. Plasma in plasma region 215 of the chamber. The RF power supply can generate a high RF frequency of 13.56MHz, but can also generate other frequencies alone or in combination with the 13.56MHz frequency.

FIG . 2B illustrates a detailed view 253 of features that affect process gas distribution through panel 217 . As shown in FIGS. 2A and 2B , face plate 217 , cooling plate 203 , and gas inlet assembly 205 intersect to define gas supply area 258 into which process gases may be delivered from gas inlet 205 . Gas may fill gas supply region 258 and flow through aperture 259 in face plate 217 to first plasma region 215 . Aperture 259 may be configured to direct flow in a substantially unidirectional manner such that process gas may flow into process region 233 but may be partially or completely prevented from backflow into gas supply region 258 after passing through face plate 217 .

The gas distribution assembly (eg, showerhead 225 for processing chamber section 200 ) may be referred to as a dual channel showerhead (DCSH), and is additionally detailed in the embodiment depicted in FIG. 3 . A dual channel showerhead may provide etch processing to allow separation of etchant outside of the processing area 233 to provide limited interaction with chamber components and each other prior to delivery to the processing area.

The shower head 225 can include an upper plate 214 and a lower plate 216 . The plates may be coupled to each other to define a volume 218 between the plates. The coupling of the plates may provide a first fluid channel 219 through the upper and lower plates and a second fluid channel 221 through the lower plate 216 . The channels formed may be configured to provide fluid access from the volume 218 through the lower plate 216 via the second fluid channel 221 alone, while the first fluid channel 219 may be fluidly isolated from the volume 218 between the plate and the second fluid channel 221 . Volume 218 is fluidly accessible through one side of gas distribution assembly 225 .

FIG . 3 is a top view of a showerhead 325 for use with a processing chamber in accordance with an embodiment. Showerhead 325 may correspond to showerhead 225 shown in FIG. 2A. Through holes 365 (showing a view of first fluid channel 219 ) can have a variety of shapes and configurations to control and affect the flow of precursors through showerhead 225 . The small holes 375 (showing a view of the second fluid channel 221) can be distributed substantially evenly over the surface of the showerhead (even in the through-holes 365) and can help to provide a more efficient flow rate for the precursors as they exit the showerhead. Other configurations are more evenly mixed.

Turning to FIG . 4 , a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology is illustrated. System 400 may include a load lock chamber 10 and a processing chamber 20 . The processing chamber 20 may generally be a sealable enclosure and may operate under vacuum or at least low pressure. The processing chamber 20 can be isolated from the load lock chamber 10 by an isolation valve 15 . Isolation valve 15 may seal process chamber 20 from load lock chamber 10 in a closed position and may allow substrate 60 to be transferred through the valve from load lock chamber 10 to process chamber 20 and vice versa when in an open position.

System 400 may include gas distribution plate 30 capable of distributing one or more gases across substrate 60 . The gas distribution plate 30 may be any suitable distribution plate known to those of ordinary skill in the art, and the specific gas distribution plate described should not be considered limiting of the scope of the present technology. The output face of the gas distribution plate 30 may face the first surface 61 of the substrate 60 .

The gas distribution plate 30 may include a plurality of gas ports configured to deliver one or more gas streams to the substrate 60 and a plurality of vacuum ports disposed between each gas port, And configured to convey gas flow out of the processing chamber 20 . As shown in FIG. 4 , the gas distribution plate 30 may include a first precursor injector 420 , a second precursor injector 430 , and a purge gas injector 440 . The injectors 420, 430, 440 may be controlled by a system computer (not shown) (eg, a host computer), or by a chamber-specific controller (eg, a programmable logic controller). Precursor injector 420 may be configured to inject a continuous or pulsed flow of a reactive precursor of Compound A through gas ports 425 into processing chamber 20 . Precursor injector 430 may be configured to inject a continuous or pulsed flow of a reactive precursor of Compound B through gas ports 435 into processing chamber 20 . The purge gas injector 440 may be configured to inject a continuous or pulsed flow of non-reactive or purge gas through a plurality of gas ports 445 into the processing chamber 20 . The purge gas may be configured to remove reactive materials and reaction by-products from the processing chamber 20 . Purge gases are typically inert gases such as nitrogen, argon, and helium. The gas port 445 can be disposed between the gas port 425 and the gas port 435 to separate the compound A precursor from the compound B precursor, thereby avoiding cross-contamination between the precursors.

In another aspect, a remote plasma source (not shown) may be connected to precursor injector 420 and precursor injector 430 before injecting the precursor into processing chamber 20 . Plasmas of reacting species can be generated by applying an electric field to compounds within a remote plasma source. Any power source capable of activating the desired compound can be used. For example, power sources using DC, radio frequency, and microwave type discharge techniques may be used. If an RF power source is used, it can be coupled capacitively or inductively. Activation can also be produced by heat based techniques, gas dissociation techniques, high intensity light sources (eg, ultraviolet light sources), or exposure to x-ray sources.

The system 400 may further include a pumping system 450 connected to the processing chamber 20 . Pumping system 450 may generally be configured to evacuate a gas flow out of processing chamber 20 through one or more vacuum ports 455 . A vacuum port 455 may be provided between each gas port to evacuate the gas flow out of the processing chamber 20 after the gas flow reacts with the substrate surface and further limit cross-contamination between precursors.

System 400 may include a plurality of partitions 460 disposed on processing chamber 20 between each port. The lower portion of each partition may extend close to the first surface 61 of the substrate 60 (eg, about 0.5 mm or more from the first surface 61 ). In this way, the lower portion of the partition 460 may be separated from the substrate surface by a distance sufficient to allow the gas flow to flow around the lower portion toward the vacuum port 455 after the gas flow reacts with the substrate surface. Arrow 498 indicates the direction of gas flow. Because partitions 460 operate as physical barriers to gas flow, partitions 460 can also limit cross-contamination between precursors. The configuration shown is illustrative only and should not be considered as limiting the scope of the technology. Those of ordinary skill in the art will appreciate that the gas distribution system shown is only one possible distribution system and that other types of showerheads may be used.

In operation, substrate 60 may be delivered (eg, by a robot) to load lock chamber 10 and may be placed on shuttle 65 . After the isolation valve 15 is opened, the shuttle 65 can move along the track 70 . Once the shuttle 65 enters the processing chamber 20 , the isolation valve 15 may be closed to seal the processing chamber 20 . The shuttle 65 may then move through the processing chamber 20 for processing. In one embodiment, the shuttle 65 can move through the chamber in a linear path.

As the substrate 60 moves through the processing chamber 20, the first surface 61 of the substrate 60 can be repeatedly exposed to the precursor of compound A from the gas port 425 and the precursor of the compound B from the gas port 435, with the precursor of the compound B from the gas port 445 in between. purge gas. The injection of the purge gas may be designed to remove unreacted material from a previous precursor before exposing the substrate surface 61 to the next precursor. After each exposure to the various gas streams, the gas streams may be evacuated by pumping system 450 through vacuum port 455 . Since vacuum ports can be provided on both sides of each gas port, the gas flow can be evacuated through the vacuum ports 455 on both sides. Thus, the gas flow may flow vertically downward from the individual gas ports toward the first surface 61 of the substrate 60 , across the first surface 410 and around the lower portion of the partition 460 , and finally upward toward the vacuum ports 455 . In this way, each gas can be evenly distributed across the substrate surface 61 . Substrate 60 may also be rotated while being exposed to various gas flows. Rotation of the substrate may be useful to prevent banding from forming in the formed layer. The rotation of the substrate can be a continuous or separate step.

The exposure of the substrate surface 61 to each gas can be determined by, for example, the flow rate of each gas out of the gas ports and the movement rate of the substrate 60 . In one embodiment, the flow rate of each gas can be configured so as not to remove absorbed precursors from the substrate surface 61 . The width between each zone, the number of gas ports provided on the processing chamber 20, and the number of times the substrate may be passed back and forth may also determine the degree of exposure of the substrate surface 61 to the various gases. Therefore, the quantity and quality of the deposited film can be optimized by varying the above factors.

In another embodiment, the system 400 may include the precursor injector 420 and the precursor injector 430 without the purge gas injector 440 . Thus, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 may be alternately exposed to the precursor of compound A and the precursor of compound B without being exposed to the purge gas in between.

The embodiment shown in Figure 4 has a gas distribution plate 30 above the substrate. Although the embodiment has been described and illustrated with respect to this upright orientation, it should be understood that the reverse orientation is also possible. In that case, the first surface 61 of the substrate 60 may face downwards and the gas flowing towards the substrate may be directed upwards. In one or more embodiments, at least one radiant heat source 90 may be positioned to heat the second side of the substrate.

In some embodiments, the shuttle 65 may be a base for carrying the substrate 60 . Typically, the susceptor can be a carrier that helps create a uniform temperature across the substrate. The susceptor is movable in both left-to-right and left-to-right directions between the load lock chamber 10 and the process chamber 20 relative to the arrangement of FIG. 4 . The base may have a top surface 67 for carrying the substrate 60 . The susceptor may be a heated susceptor such that the substrate 60 may be heated for processing. As an example, the susceptor may be heated by a radiant heat source 90 disposed below the susceptor, a heating plate, a resistive coil, or other heating means. Although illustrated as transversal, embodiments of the system 400 can also be used in rotary systems, where the wheels can be rotated clockwise or counterclockwise to continuously process one or more substrates located below the gas distribution system as shown. It should be similarly understood that additional modifications are included in the technology.

FIG. 5 illustrates a method 500 of forming a semiconductor structure, many of which may be performed in chambers 200 and 400 described above, for example. Method 500 may include one or more operations prior to initiating the method, including front-end processing, deposition, etching, grinding, cleaning, or any other operation that may be performed prior to the described operations. The method may include a number of optional operations shown in the figures, which may or may not be specifically associated with methods in accordance with the present technology. For example, many operations are described to provide a broader latitude for structure formation, but are not critical to the technique, or can be performed by alternative methods, as discussed further below. Method 500 describes the operations schematically illustrated in FIGS. 6A- 6E , an illustration of which will be described in conjunction with the operations of method 500 . It should be understood that FIG. 6 shows only a partial schematic view, and that the substrate may contain any number of transistor segments in the manner shown in the figure.

Method 500 may involve operations performed on a substrate having a plurality of exposed regions, for example on a substrate including regions further developed as previously described to produce silicon fin structures. As shown in FIG. 6A , a portion of a processed substrate 600 including a dielectric material 605 and a fin element 610 is shown. Fins may be pre-formed, for example, by performing a recess operation on a silicon substrate to form one or more fin elements 610 . For example, recessing may be performed in the chamber 200 . Subsequent deposition of dielectric material 605 may be performed, eg, in chamber 400 or in another deposition chamber where blanket deposition may be performed. Dielectric material 605 may be formed or deposited around fin element 610 to cover the first portion of fin element 610a. A recessing operation may also occur to create a second portion of the fin element 610b that extends over the dielectric material 605 .

Features of the fin element may be the height above the dielectric material 605 and the thickness of the fin. By way of example, the fin elements may extend greater than or about 5 nm above the dielectric material 605, and may extend, for example, at or about 10 nm, at or about 25 nm, at or about 50 nm, at or above the dielectric material 605 in DRAM applications. At or about 75 nm, at or about 100 nm, at or about 125 nm, at or about 150 nm, at or about 175 nm, at or about 200 nm, at or about 225 nm, at or about 250 nm, or higher. The height can also be anywhere within any of these ranges. The width of the fin elements across the fin may also be less than or about 50 nm, and in embodiments may be less than or about 40 nm, less than or about 30 nm, less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, less than or about 10 nm , less than or about 5 nm, or less.

Method 500 may initially include forming a first dielectric material 615 around fin element 610 at operation 505 . As shown in FIG. 6A, a first dielectric material 615 may be formed in a selective deposition, wherein the first dielectric material 615 may be preferably formed with respect to the exposed dielectric material 605 (which may be a second dielectric material). formed on the fin element 610 . Deposition may be performed in a chamber similar to chamber 400 described above. As explained further below, deposition may not be feasible with conventional techniques that may not form a layer of first dielectric material 615 that completely covers fin element 610 . For example, the etch operation following the blanket coating of the first dielectric material 615 may utilize at least an anisotropic etch to remove the covering of the top of the fin element 610, which may disadvantageously expose the fin element 610 to additional operations described above. Thus, by selectively depositing the first dielectric material 615 on the fin element 610 relative to the dielectric material 605, the present technique can provide the ability to perform subsequent operations.

In optional operation 510, an additional amount of dielectric material 605 may be deposited on the structure as shown in Figure 6B. The additional amount of dielectric material 605 may extend to the height of the fin element 610 , or as much as the height of the first dielectric material 615 covering the fin element 610 . The deposition may be an additional blanket deposition, followed by chemical mechanical polishing or other recessing operations to expose the top surface of the first dielectric material 615 .

A conversion process may be performed at operation 515 to convert a portion of the fin element 610 to oxide. As shown in FIG. 6C , the operation may convert the first portion of fin element 610 a to an oxide or a dielectric material similar to dielectric material 605 . By converting the first portion of the fin element 610a to oxide, the off-state leakage current in the final device can be reduced. Because the first dielectric material 615 can act as a barrier to the switching process, switching can be limited to the first portion of the fin element 610a. Accordingly, the second portion of the fin element 610b may remain in an untransformed or substantially unconverted form.

At operation 520 , an additional amount of dielectric material 605 may be selectively removed around first dielectric material 615 . As shown in FIG. 6D, the dielectric material 605 may be recessed to or below the unconverted second portion of the fin element 610b, while the sidewalls of the first dielectric material 615 may be exposed. Subsequently, in operation 525, as shown in FIG. 6E, the first dielectric material 615 may be selectively removed. The first dielectric material 615 may be selectively removed with respect to the dielectric material 605 and the fin elements 610 . After removal, the structure may remain to include fin elements 610 extending over dielectric material 605 , wherein dielectric material 605 extends laterally below fin elements 610 .

Several deposition and etch operations can be performed in a single environment (eg, sharing of tools among clusters of chambers). For example, additional deposition chambers may be used along with one or more etch chambers 200 and deposition chambers 400 (eg, may be used to fill dielectric material 605 ). Each transfer can be performed under vacuum, while each of the chambers can reside on the same cluster tool, allowing the transfer to occur in a controlled environment. For example, vacuum conditions can be maintained during the transfer, and the transfer can be performed without breaking the vacuum. In contrast to conventional techniques, which may include additional masking operations, photolithography, and other operations that may require transfer between many tools, method 500 may be performed on a single tool where vacuum conditions are not compromised in embodiments. Additionally, method 500 may not utilize any RIE operations, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE.

Various materials can be utilized in processing, and etching and deposition can be selective to multiple components. Therefore, the present technology may not be limited to a single set of materials. For example, the fin element 610 can be silicon (eg, polysilicon), and can also be other silicon-containing materials (including germanium silicide), and can include other materials (including arsenic, indium, gallium, phosphorus, and finally other poor metals and metalloids operating in the structure). The dielectric material 605 may be or include silicon oxide, although other insulating materials may also be used. For example, other oxygen-, nitrogen-, or carbon-containing materials may be used. The first dielectric material 615 may also include an insulating material, and may include a silicon-containing material, a nitrogen-containing material, an oxygen-containing material, a carbon-containing material, or some combination of these materials (eg, silicon nitride, silicon oxycarbide, tungsten oxide , alumina, or other materials).

Dielectric material 605 may be a different material than the first dielectric material in an embodiment since dielectric material 605 may be exposed during selective deposition of first dielectric material 615, but in additional embodiments the two materials can be similar. Although different materials, the first dielectric material 615 and the dielectric material 605 may be one or more materials selected from the material group including carbon-containing materials, nitrogen-containing materials, and oxygen-containing materials, and may is any of the above materials. However, the first dielectric material 615 may be a different material than the material used for the dielectric material 605 .

Selective deposition of the first dielectric material 615 may be performed in a deposition capable and atomic layer deposition capable chamber, including the chamber 400 described above. Deposition may be preset to selectively deposit insulating material on fin elements 610 relative to dielectric material 605 . For example, first dielectric material 615 (which may be silicon nitride in some embodiments) may be formed substantially over fin element 610 (which may be silicon), with minimal formation over dielectric material 605 or limited in the dielectric material 605. Selective deposition can be performed by a variety of operations, which can include forming a self-assembled monolayer to facilitate selective deposition, or can include actively inhibiting the formation of dielectrics on other dielectric materials.

Self-assembled monolayers can be formed on regions of the structure to tune the deposition. For example, a first self-assembled monolayer may be formed on the structure and then exposed to a photolithographic mask to remove the monolayer from the fin element 610 . A single layer may be maintained on the dielectric material 605 . Monolayers may have capping moieties that may repel or fail to interact with later delivered precursors. For example, in embodiments, the capping moiety may be hydrophobic and may be capped with a hydrogen-containing moiety (eg, methyl), which may not interact with the additional precursor. A second self-assembled monolayer may be formed on the fin element 610 and may be hydrophilic or reactive with one or more precursors used to create the first dielectric material 615 . A second self-assembled monolayer may be selectively formed on the fin element 610 because the material may repel the first self-assembled monolayer, or may selectively stretch to the fin element. The second self-assembled monolayer may be terminated with hydroxyl or other hydrophilic moieties, or with moieties that specifically interact with the additional precursors used to form the first dielectric material 615 .

Atomic layer deposition may then be performed using two or more precursors to develop the first dielectric material 615 . The deposited precursors may include metal-containing or silicon-containing precursors, and include precursors configured to interact with portions that terminate the second self-assembled monolayer but not the first self-assembled monolayer. For example, when using hydrophilic and hydrophobic capped monolayers, one of the ALD precursors may include water. In this way, deposits may not form on the first self-assembled monolayer, which may be hydrophobic. If the first dielectric material includes a metal oxide (eg, tungsten oxide or aluminum oxide), the precursor for atomic layer deposition may include a tungsten-containing precursor or an aluminum-containing material and water. In other embodiments, silicon-containing precursors may be used. Then, during the half-reaction with water, the water may not be able to interact with the first self-assembled monolayer formed on the dielectric material 605, and thus deposition may not form on the first self-assembled monolayer. In this way, the first dielectric material 615 may be selectively formed on the fin member 610 .

After the first dielectric material 615 has been formed to a suitable height, the first self-assembled monolayer may be exposed to UV light and removed from the substrate, or some other removal may be performed. Thus, the first self-assembled monolayer may be formed directly after the selective etching of the fin elements, or after transfer to the additional chamber but before the additional processing operations. In this way, several operations used in knowledge formation can be eliminated, which can significantly reduce queue times (eg, several hours). In other embodiments, depending on the operations performed, a slight recess may be performed after the selective deposition to remove residual material from the dielectric material 605 . It should be understood that this is merely an example of utilizing a self-assembled monolayer based on a set of deposited materials. Additional materials that may serve as alternative precursors are discussed further below.

Embodiments may also utilize an inhibitor to selectively form the first dielectric material 615 on the fin element 610 while not forming the first dielectric material 615 on the dielectric material 605 or to limit the amount formed on the dielectric material 605 . For example, the inhibitor may be applied across the surface of the dielectric material, while the inhibitor may not be applied, or may be removed from the fin element 610 . The inhibitor can be any number of materials, and the material can be characterized by a silicone backbone (eg, siloxane) or a tetrafluoroethylene backbone (eg, PTFE), as well as other oily or surfactant materials. Material may be applied across the surface of the substrate to cover exposed portions of the dielectric material 605 .

The suppressor material may prevent adhesion or adsorption of material that would normally form or deposit on the fin element 610 . A first dielectric material 615 is then formed, and a remover may be applied to the substrate to remove the suppressor material. The remover, which may be a wet etchant, a reactant, or a surfactant cleaner, may remove residual suppressor material that exposes the underlying dielectric material 605 . Utilizing an inhibitor may allow the formation of the first dielectric material in defined areas without requiring definition via subsequent patterning and/or etching of the blanket film. The process can further reduce the queue time of conventional processes by removing previous and subsequent patterning operations.

Additional selective deposition techniques (which may include alternative mechanisms) for selectively depositing dielectric materials (eg, nitrogen-containing materials) may also be used. For example, the nitrogen-containing material may act as one of the self-assembled monolayers (eg, one of the capped portions of the monolayer) on the material for deposition to occur, and may allow attraction for the formation of the previously described A particular precursor of one or more of the materials. Other techniques can take advantage of temperature differences to enhance deposition on silicon relative to silicon oxide. For example, atomic layer deposition using silicon-containing precursors and nitrogen-containing precursors can be performed at temperatures above or about 500°C, and can be at or above 750°C, above or about 900°C, above or performed at a temperature of about 1000°C, or at, above, or about 1100°C.

As the temperature is increased in this range, deposition can occur at a higher rate on silicon than on silicon oxide. A nitrogen selective etch can then be performed to remove the first dielectric material from the silicon oxide surface. Although it is also possible to reduce the first dielectric material on the silicon surface, since the thickness can be many times thicker than on the silicon oxide, a complete removal of the silicon oxide can be performed while maintaining a thickness greater than or about 1 nm on the fin element, Greater than or about 2 nm, greater than or about 3 nm, greater than or about 4 nm, greater than or about 5 nm, greater than or about 6 nm, greater than or about 7 nm, greater than or about 8 nm, greater than or about 9 nm, greater than or about 10 nm, or greater. This effect makes it possible for the present technique to be implemented in a manner limited by known techniques. During normal conformal or blanket deposition, the thickness of some parts of the fin element will be equal to the thickness on the oxide layer. Thus, the etch-back process may even utilize a directional etch to expose at least a portion of the fin elements.

Either of these techniques can selectively deposit or form dielectric or insulating material on a fin element relative to one or more non-metallic, dielectric, or insulating regions. The selectivity may be complete, that is, the first dielectric material is formed only on the fin element 610 or the intermediate layer, while the first dielectric material 615 may not be formed on the dielectric material 605 at all. In other embodiments, the selectivity may not be complete and the ratio of deposition on fin element 610 to dielectric material 605 may be greater than about 2:1. Selectivity can also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35 :1, greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more. As previously mentioned, the thickness deposited on the fin element can be less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or more small. Accordingly, a selectivity of less than 20:1 may be acceptable to fully deposit first dielectric material 615 while forming a limited amount of material or substantially no material on dielectric material 605 .

The deposition operation may be performed at any of the aforementioned temperatures or pressures, and may be performed at a temperature of greater than or about 300°C, and may be performed at a temperature of greater than or about 400°C, greater than or about 450°C, greater than or about 500°C, greater than or about 600°C, greater than or about 700°C, greater than or about 800°C, greater than or about 900°C, greater than or about 1000°C, or higher. For example, during atomic layer deposition operations, temperatures greater than or about 500° C. may be used to activate the precursors to interact with each other as the material layer is formed.

Etching operations 520 and 525 may be selective etch operations as previously described. The dielectric material may be recessed in an etch chamber similar to chamber 200 described previously. Once positioned within the processing region of the semiconductor processing chamber, the method may include forming a plasma of the fluorine-containing precursor in the remote plasma region of the processing chamber. The remote plasma region may be fluidly coupled to the processing region, but may be physically separated to confine the plasma at the substrate level, which may damage exposed structures or materials. The effluent of the plasma may flow into the processing region, which may contact the semiconductor substrate and selectively etch material.

Etching operations may involve additional precursors along with specific fluorine-containing precursors. In some embodiments, nitrogen trifluoride may be used to generate plasma effluents. Additional or alternative fluorine-containing precursors may also be utilized. For example, a fluorine-containing precursor may flow into the remote plasma region, and the fluorine-containing precursor may include a group selected from atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, hexa At least one precursor of the group of sulfur fluoride and xenon difluoride. The remote plasma region may be in a different module than the processing chamber or in a compartment within the processing chamber. As shown in FIG. 2 , both the RPS unit 201 and the first plasma region 215 can serve as the remote plasma region. The RPS may allow dissociation of the plasma effluent without damaging other chamber components, while the first plasma region 215 may provide a shorter path length to the substrate during which recombination may occur.

Additional precursors can also be delivered to the distal plasmonic region to enhance the fluorine-containing precursors. For example, a nitrogen and hydrogen containing precursor or a hydrogen precursor can be delivered together with a fluorine containing precursor. For example, the additional precursor may be a nitrogen-containing precursor (eg, ammonia). Additional precursors may flow into the processing chamber in an unexcited state to interact with the substrate surface. These formulations can selectively etch silicon oxide relative to silicon nitride, which can cover fin features 610 . The selectivity of the oxide etch may be greater than or about 100:1, and may be greater than or about 150:1. In this way, all of the additional dielectric material 605 (which may be silicon oxide) can be removed from the first dielectric material 615 with minimal loss of the first dielectric material around the fin element 610 .

A selective etch of the first dielectric material 615 relative to the dielectric material 605 may be performed to remove all of the first dielectric material 615, and may use a method similar to or different from that used for the selective etch of the dielectric material 605. Precursor. For example, although the materials may be any of the materials described above, in an embodiment, the first dielectric material 615 may be or include silicon nitride, and the dielectric material 605 may be or include silicon oxide. Silicon oxide. Selective etching of silicon nitride relative to silicon oxide may utilize fluorine-containing precursors as described above, and may also include oxygen-containing precursors. The oxygen-containing precursor can be delivered to the remote plasma region along with the fluoride-containing precursor, or the oxygen-containing precursor can bypass the remote plasma region and be delivered directly into the treatment region. In some embodiments, the first dielectric material etch operation may not include a hydrogen-containing precursor during the etch, and may be performed in a hydrogen-free environment. The operation may selectively etch silicon nitride to silicon oxide with a selectivity of greater than or about 20:1, and may etch silicon nitride with a selectivity of greater than or about 30:1. Since the amount of first dielectric material 615 can be less than or about 10 nm, less than or about 5 nm, or less, an etch rate of less than or about 20:1 can still sufficiently remove the first dielectric material without substantially The dielectric material 605 will be damaged. The etch may also be selective to silicon nitride relative to silicon, which may be the underlying fin element 610 . The selectivity may be greater than or about 10:1, which may allow removal of all remaining first dielectric material 615 without substantially damaging fin elements 610 .

In an embodiment, the etching operation may be performed at less than about 10 Torr, and may be performed at less than or about 5 Torr in an embodiment. In embodiments, processing may also be performed at temperatures below about 100°C, and may be performed at temperatures below about 50°C. The process may be selective to the first dielectric material 615 removing portions of the dielectric material 605 as performed in chamber 200 or a variation of this chamber, or in a different chamber capable of performing similar operations. The operations may also be selective to the dielectric material 605 and fin elements 610 to remove portions of the first dielectric material 615 .

In an embodiment, converting operation 515 may include oxidation or annealing. Annealing may involve wet or dry annealing, such as with steam or oxygen, respectively. Annealing may be performed at a temperature of greater than or about 100°C, and may be greater than or about 250°C, greater than or about 500°C, greater than or about 750°C, greater than or about 1000°C, greater than or about 1250°C °C or higher. Annealing agents can diffuse through silicon oxide (eg, dielectric material 605). However, silicon nitride (which can be the first dielectric material 615) can act as a barrier to oxidation. Thus, by housing the second portion of the fin element 610b within silicon nitride, that portion of the fin element may not be converted to silicon oxide. There may be some amount of penetration or creep beneath the fin structure, but fins can be formed that account for this latent variable, which can be less than or about 10% of the height of the fin element and can be less than or about 9% , less than or about 8%, less than or about 7%, less than or about 6%, less than or about 5%, less than or about 4%, less than or about 3%, less than or about 2%, less than or about 1%, less than Or about 0.5%, less than or about 0.1%, or less. Latent variables may also extend less than or about 10 nm within the second portion of fin element 610b, and may be less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, less than or about 0.5 nm, less than or about 0.1 nm, or less.

This further explains the relevance of the selective deposition operation 505 . For example, if silicon nitride is not selectively deposited and blanketed or conformally formed on the dielectric material 605, the oxidation process may not penetrate the silicon nitride material and the first portion of the fin element 610a Might not convert. Conversely, if a subsequent etch is performed to remove the first dielectric material 615 from the dielectric material 605 , this removal may also remove the first dielectric material from the top of the fin element 610 . This can expose the fin elements to oxidizing agents which can convert the parts of the fins that should form the electrode fins. In this way, the present technique overcomes the drawbacks of the prior art of developing silicon fins on oxygen pads, while not requiring more expensive substrates (eg, SOI substrates). Although in some embodiments, the present technique can perform an etch back of the deposited silicon nitride to remove any residual nitride from the surface of the dielectric material 605, the first dielectric material 615 on the fin member 610 The thickness of may be at least twice the thickness of the thickness of the first dielectric material 615 on the dielectric material 605 . Thus, the etch-back process can completely remove the residual first dielectric material 615 on the dielectric material 605 while maintaining the full coating on the fin element 610 to any of the previously described thicknesses.

In the previous description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent, however, to one having ordinary skill in the art that certain embodiments may be practiced without some of these details or with additional details.

Several embodiments have been disclosed, but it should be understood that those skilled in the art can employ various modifications, alternative constructions, and equivalents without departing from the spirit of the embodiments. Additionally, many known processes and elements have not been described in order to avoid unnecessarily obscuring the technology. Therefore, the above description should not be taken as limiting the scope of the technology.

When a range of values is provided, it is understood that, unless the context clearly dictates otherwise, each intervening value between the upper and lower limits of that range, to the smallest fraction of the unit of the lower limit, is also specifically disclosed. Any narrower range between any stated value or unrecited intervening value in a stated range as well as any other stated or intervening value in a stated range is included. Subject to any specifically excluded limitations on the stated ranges, the upper and lower limits of these smaller ranges may independently be included in or excluded from the range, and either or both limits may or may not be included in the smaller ranges. Each of the ranges is also included in the technology. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers and reference to "a precursor" includes reference to one or more precursors and equivalents thereof known to those of ordinary skill in the art, and so on.

In addition, when the words "comprises", "includes", "includes", "includes", and "includes" are used in this specification and the claims below, they are intended to be The presence of a component, or an operation, does not preclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

10: Loading lock chamber

15: Isolation valve

20: Processing chamber

30: Gas distribution plate

60: Substrate

61: first surface

65:Shuttle

67: top surface

70: track

90: Radiant heat source

100: Processing system

102: Front Opening Uniform Pod

104: Robot arm

106: Supporting area

108a: processing chamber

108b: processing chamber

108c: processing chamber

108d: processing chamber

108e: processing chamber

108f: processing chamber

109a: Tandem segments

109b: Concatenated segments

109c: Concatenated segments

110: Second robot arm

200: chamber

201: RPS unit

203: cooling plate

205: Gas inlet assembly

210: Fluid supply system

214: upper board

215: The first plasma area

216: lower board

217: panel

218: Volume

219: First fluid channel

220: insulation ring

221: second fluid channel

223: ion eliminator

225: sprinkler head

233: Substrate processing area

240: power supply

253:Detail view

255: Substrate

258: gas supply area

259: porosity

265:Pedestal

325: sprinkler head

365: through hole

375: small hole

400: chamber

420: Syringe

425: gas port

430:Syringe

435: gas port

440:Syringe

445: gas port

450: Pumping system

455: vacuum port

460: partition

498:Arrow

500: method

505: Operation

510: Operation

515: Operation

520: Operation

525: Operation

600: Substrate

605: Dielectric material

610a: fin element

610b: Fin element

615: The first dielectric material

A further understanding of the nature and advantages of the disclosed technology may be realized by referring to the remaining portions of the specification and drawings.

Figure 1 illustrates a top plan view of an exemplary processing system in accordance with an embodiment of the present technology.

Figure 2A illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with embodiments of the present technology.

Figure 2B illustrates a detailed view of an exemplary panel in accordance with an embodiment of the present technology.

Figure 3 illustrates a bottom plan view of an exemplary showerhead in accordance with an embodiment of the present technology.

Figure 4 illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with embodiments of the present technology.

Figure 5 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

Figures 6A-6E illustrate schematic cross-sectional views of exemplary substrates in accordance with embodiments of the present technology.

Several lines in the figures are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes only and should not be considered to scale unless scales are specifically stated. In addition, as schematic diagrams, drawings are provided to aid in understanding and may not include all aspects or information compared to actual representations, and may include exaggerated material for illustrative purposes.

In the accompanying drawings, similar components and/or features may have the same reference number. In addition, various components of the same type can be distinguished by using a letter after the element number to distinguish similar components. If only the first element number is used in the description, the description is applicable to any one of the similar parts with the same first element number, regardless of the letter.

Domestic deposit information (please note in order of depositor, date, and number) None

Overseas storage information (please note in order of storage country, institution, date, number) None

500‧‧‧method

505‧‧‧Operation

510‧‧‧Operation

515‧‧‧Operation

520‧‧‧Operation

525‧‧‧Operation

Claims (19)

A method of forming a semiconductor structure, the method comprising the steps of: providing a semiconductor substrate comprising a second dielectric material and a silicon element extending over the second dielectric material; depositing a first dielectric material on the silicon element, wherein the deposition of the first dielectric material is performed with a selectivity of the silicon element relative to the second dielectric material greater than or about 2:1; converting a portion to silicon oxide; selectively etching the second dielectric material, wherein the second dielectric material is performed with a selectivity of the second dielectric material relative to the first dielectric material of greater than or about 100:1 etching; and selectively etching the first dielectric material from the silicon element. The method of forming a semiconductor structure as claimed in claim 1, wherein the first dielectric material comprises silicon nitride, and the second dielectric material comprises silicon oxide. The method of forming a semiconductor structure as claimed in claim 1, wherein the depositing step comprises an atomic layer deposition process. The method of forming a semiconductor structure as recited in claim 1, wherein the converting step comprises the step of: performing an anneal at a temperature higher than or about 100°C. The method for forming a semiconductor structure as claimed in claim 4, Wherein the anneal converts a portion of the silicon device within the second dielectric material. The method for forming a semiconductor structure as claimed in claim 4, wherein the annealing comprises a wet annealing or a dry annealing. The method of forming a semiconductor structure as recited in claim 1, further comprising the step of: depositing an additional second dielectric material around the first dielectric material. The method of forming a semiconductor structure as recited in claim 7, further comprising the step of: recessing the second dielectric material after the converting step. The method of forming a semiconductor structure as recited in claim 1, wherein the silicon device includes a fin characterized by a width of less than 20 nm. A method of forming a semiconductor structure, the method comprising the steps of: providing a semiconductor substrate comprising an oxygen-containing material and a silicon element extending over the oxygen-containing material; depositing a nitrogen-containing material on the silicon element , wherein the nitrogen-containing material deposition is performed with a selectivity of the silicon element relative to the oxygen-containing material of greater than or about 2:1, wherein a first portion of the silicon element is contained within the oxygen-containing material, and wherein the nitrogen-containing material is deposited around a second portion of the silicon element extending from the oxygen-containing material; converting the first portion of the silicon element to silicon oxide; selectively etching the oxygen-containing material, wherein the oxygen-containing material etching is performed with a selectivity of the oxygen-containing material relative to the nitrogen-containing material of greater than or about 100:1 and selectively etching the nitrogen-containing material from the silicon device. The method of forming a semiconductor structure as recited in claim 10, further comprising the step of depositing additional oxygen-containing material around the deposited nitrogen-containing material. The method of forming a semiconductor structure as recited in claim 11, wherein the additional oxygen-containing material extends to an equal height of the nitrogen-containing material. The method of forming a semiconductor structure of claim 10, wherein the second portion of the silicon device is characterized by a height of up to about 200 nm. The method of forming a semiconductor structure as recited in claim 10, wherein the step of converting the first portion of the silicon element into silicon oxide converts less than 10% of the second portion of the silicon element into silicon oxide. The method of forming a semiconductor structure as claimed in claim 14, wherein the step of converting the first portion of the silicon element into silicon oxide is converting the second portion of the silicon element smaller than 5nm into silicon oxide. The method of forming a semiconductor structure as recited in claim 10, wherein the converting step comprises the step of: performing an anneal at a temperature higher than or about 500°C. The method of forming a semiconductor structure as claimed in claim 16, wherein the annealing comprises a wet annealing or a dry annealing. A method of forming a semiconductor structure, the method comprising the steps of: providing a semiconductor substrate comprising an oxygen-containing material and a silicon element extending over the oxygen-containing material; depositing a nitrogen-containing material on the silicon element , wherein the nitrogen-containing material deposition is performed with a selectivity of the silicon element relative to the oxygen-containing material of greater than or about 2:1, wherein a first portion of the silicon element is contained within the oxygen-containing material, and wherein the nitrogen-containing material is deposited around a second portion of the silicon element extending from the oxygen-containing material; additional oxygen-containing material is deposited around the deposited nitrogen-containing material; an anneal is performed to the silicon element of the first portion converted to silicon oxide; selectively etching the additional oxygen-containing material from the semiconductor structure, wherein the additional oxygen-containing material is performed with a selectivity of greater than or about 100:1 relative to the nitrogen-containing material oxygen-containing material etching; and selectively etching the nitrogen-containing material from the silicon device. The method of forming a semiconductor structure as recited in claim 18, wherein each selective etch utilizes an effluent of a fluorine-containing plasma.

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