TWI798215B - Selective sidewall spacers - Google Patents

Selective sidewall spacers Download PDF

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TWI798215B
TWI798215B TW107113494A TW107113494A TWI798215B TW I798215 B TWI798215 B TW I798215B TW 107113494 A TW107113494 A TW 107113494A TW 107113494 A TW107113494 A TW 107113494A TW I798215 B TWI798215 B TW I798215B
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silicon
dielectric material
forming
semiconductor structure
substrate
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TW201839905A (en
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高拉夫 塔瑞加
吉鏞 李
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美商微材料有限責任公司
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Abstract

Processing methods may be performed to form semiconductor structures that may include spacer materials on dielectric materials. The methods may include depositing a first dielectric material on a silicon element on a semiconductor substrate. The first dielectric material may be selectively deposited on the silicon element relative to exposed regions of a second dielectric material. The methods may also include selectively etching the silicon element from the semiconductor substrate.

Description

選擇性側壁間隔物selective sidewall spacer

本技術係關於半導體系統、處理、及裝備。更具體而言,本技術係關於用於在半導體裝置上選擇性蝕刻及選擇性沉積材料層的系統及方法。The technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to systems and methods for selectively etching and selectively depositing layers of materials on semiconductor devices.

可能藉由在基板表面上產生錯綜複雜圖案化的材料層的處理來製成積體電路。在基板上產生圖案化的材料需要用於移除暴露的材料的控制方法。化學蝕刻係用於多種目的,包括將光抗蝕劑中的圖案轉移到底下的層中、減薄層、或減薄已呈現於表面上的特徵的橫向尺寸。通常期望具有蝕刻一種材料比另一種更快的蝕刻處理,以促進例如圖案轉移處理或單獨材料移除。據說此種蝕刻處理對於第一材料具有選擇性。由於材料、電路、及處理的多樣性,已開發對多種材料具有選擇性的蝕刻處理。然而,通常使用毯覆塗層或保形填充而繼續跨越基板而執行沉積處理。Integrated circuits may be made by processes that create intricately patterned layers of material on the surface of a substrate. Generating patterned material on a substrate requires a controlled method for removing exposed material. Chemical etching is used for a variety of purposes, including transferring patterns in photoresists into underlying layers, thinning layers, or thinning the lateral dimensions of features already present on the surface. It is often desirable to have an etch process that etches one material faster than the other to facilitate eg pattern transfer processes or individual material removal. This etching process is said to be selective to the first material. Due to the variety of materials, circuits, and processes, etch processes have been developed that are selective to a variety of materials. Typically, however, the deposition process continues across the substrate using blanket coating or conformal fill.

隨著裝置尺寸在下一代裝置中持續縮小,當形成於特定層中的材料只有幾奈米時(特別是當材料為電晶體形成中的關鍵時),選擇性可以發揮更大的作用。各種材料之間已開發許多不同的蝕刻處理選擇性,但是標準選擇性可能不再適用於當前及未來的裝置規模。此外,基於形成及保護跨越裝置的特徵的各種關鍵尺寸所需的遮罩、形成、及移除操作的數量,處理的佇列時間繼續增加,同時在基板上的其他處執行圖案化及形成。As device dimensions continue to shrink in next-generation devices, selectivity can play a greater role when the material formed in a particular layer is only a few nanometers long, especially when the material is critical in transistor formation. Many different etch process selectivities have been developed between various materials, but standard selectivities may no longer be appropriate for current and future device scales. Furthermore, queue times for processing continue to increase based on the number of masking, forming, and removal operations required to form and protect various critical dimensions of features spanning the device while patterning and forming are performed elsewhere on the substrate.

因此,需要一種可用於生產高品質的裝置及結構的改善的系統及方法。本技術解決了這些及其他需求。Accordingly, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technology addresses these and other needs.

可以執行處理方法來形成可包括介電材料上的間隔物材料的半導體結構。該方法可包括以下步驟:在半導體基板上的矽元件上沉積第一介電材料。第一介電材料可以相對於第二介電材料的暴露區域而選擇性沉積在矽元件上。該方法亦可包括以下步驟:從半導體基板選擇性蝕刻矽元件。Processing methods may be performed to form semiconductor structures that may include spacer materials on dielectric materials. The method may include the step of depositing a first dielectric material on a silicon element on a semiconductor substrate. The first dielectric material can be selectively deposited on the silicon element relative to the exposed areas of the second dielectric material. The method may also include the step of selectively etching silicon elements from the semiconductor substrate.

在一些實施例中,第一介電材料可以包括氮化矽。沉積可以包括原子層沉積處理。第二介電材料可為氧化矽,或可以包括氧化矽。該方法亦可以包括以下步驟:圍繞矽元件而使第一介電材料選擇性凹陷。凹陷可以相對於第二介電材料移除第一介電材料的頂部部分。可以利用對第一介電材料大於或約20:1的選擇性來執行選擇性蝕刻矽元件之步驟。可以利用對第二介電材料大於或約100:1的選擇性來執行選擇性蝕刻矽元件之步驟。可以利用矽元件相對於第二介電材料大於或約2:1的選擇性來執行第一介電材料沉積。第一介電材料可以包括以小於20nm的寬度為特徵的間隔物。In some embodiments, the first dielectric material may include silicon nitride. Deposition may include atomic layer deposition processing. The second dielectric material may be silicon oxide, or may include silicon oxide. The method may also include the step of selectively recessing the first dielectric material around the silicon element. The recess may remove a top portion of the first dielectric material relative to the second dielectric material. The step of selectively etching silicon elements may be performed with a selectivity to the first dielectric material of greater than or about 20:1. The step of selectively etching silicon elements may be performed with a selectivity to the second dielectric material of greater than or about 100:1. Deposition of the first dielectric material may be performed with a selectivity of greater than or about 2:1 for silicon elements relative to the second dielectric material. The first dielectric material may include spacers characterized by a width of less than 20 nm.

本發明的技術亦可包括一種形成半導體結構的方法。該方法可以包括以下步驟:將含矽元件的表面暴露至抑制劑。該方法可以包括以下步驟:在從半導體基板延伸的含矽元件上沉積含氧材料。含氧材料可以相對於基板上的遮罩層的暴露區域而選擇性沉積在含矽元件上。該方法亦可以包括以下步驟:從矽元件選擇性蝕刻含氧材料。The inventive technique may also include a method of forming a semiconductor structure. The method may include the step of: exposing the surface of the silicon-containing device to the inhibitor. The method may include the step of depositing an oxygen-containing material on a silicon-containing element extending from a semiconductor substrate. The oxygen-containing material can be selectively deposited on the silicon-containing element relative to the exposed areas of the mask layer on the substrate. The method may also include the step of selectively etching oxygen-containing material from the silicon element.

在一些實施例中,抑制劑可以減少含矽元件的表面上的含氧材料的形成。含矽元件的表面可為含矽元件的頂表面。遮罩層可以包括氧化矽或氮化矽。該方法亦可以包括以下步驟:圍繞含矽元件而使含氧材料選擇性凹陷。凹陷可以相對於遮罩層移除含氧材料的頂部部分。可以利用對含氧材料大於或約100:1的選擇性來執行選擇性蝕刻含矽元件之步驟。可以利用對遮罩層大於或約20:1的選擇性來執行選擇性蝕刻含矽元件之步驟。可以利用含矽元件相對於遮罩層大於或約2:1的選擇性來執行含氧材料沉積。含氧材料可以包括以小於20nm的寬度為特徵的間隔物。In some embodiments, the inhibitor can reduce the formation of oxygen-containing material on the surface of the silicon-containing device. The surface of the silicon-containing device may be the top surface of the silicon-containing device. The mask layer may include silicon oxide or silicon nitride. The method may also include the step of selectively recessing the oxygen-containing material around the silicon-containing element. The recess may remove a top portion of the oxygen-containing material relative to the mask layer. The step of selectively etching silicon-containing elements may be performed with a selectivity to oxygen-containing materials of greater than or about 100:1. The step of selectively etching silicon-containing devices may be performed with a selectivity to the mask layer of greater than or about 20:1. Oxygen-containing material deposition may be performed with a selectivity of greater than or about 2:1 for the silicon-containing element to the mask layer. The oxygen-containing material may include spacers characterized by a width of less than 20 nm.

此種技術可以提供優於習知系統及技術的許多益處。舉例而言,處理可以藉由利用不包括反應離子蝕刻的技術來保護關鍵尺寸,並提供改善的選擇性。此外,藉由執行選擇性操作,間隔物特性可以是間隔物之間更均勻,這可以減少節距步移(pitch walking)。結合以下描述及隨附圖式,更詳細地描述這些及其他實施例以及其許多優點及特徵。 Such techniques can provide many benefits over conventional systems and techniques. For example, processing can preserve critical dimensions and provide improved selectivity by utilizing techniques that do not include reactive ion etching. In addition, by performing selective operations, spacer properties can be more uniform between spacers, which can reduce pitch walking. These and other embodiments, along with their many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

本發明的技術包括用於具有小節距特徵的半導體處理的系統及部件。隨著行節距減少,標準微影處理可能受到限制,並可以在圖案化中使用替代機制。在一個此種圖案化操作期間,可以在氧化物表面上方形成氮化物間隔物。在一種形成情況下,氮化物層係沉積在虛多晶矽線上方及墊氧化物上方。為了形成氮化物間隔物,執行蝕刻處理,而可以移除氮化物層以及多晶矽的連續性。為了確保在間隔物之間已經完全移除氮化物,經常執行過度腐蝕。然而,此種處理可能會濺射底下的墊氧化物,其可能沿著氮化物間隔物的側壁重新沉積而作為底腳。若沒有移除此底腳,則核心與間隙之間的線厚度可能不同,這可能造成在後續處理中發生節距步移。習知使用的移除處理包括可以降低對許多部件的選擇性的反應離子刻蝕(「RIE」)。此舉亦可能造成間隔物材料本身圓化及被移除,而當間隔物不再具有統一的高度、寬度、或其他特性時,這可能進一步加劇節距步移。此外,當暴露於RIE的材料含有碳時(諸如低k介電質),相關聯的灰化處理可能從介電質中清除碳,而降低介電能力。The techniques of the present invention include systems and components for semiconductor processing with fine pitch features. As the row pitch decreases, standard lithography processing can be limited and alternative mechanisms can be used in patterning. During one such patterning operation, nitride spacers may be formed over the oxide surface. In one form of formation, a nitride layer is deposited over the dummy polysilicon lines and over the pad oxide. To form the nitride spacers, an etch process is performed which removes the nitride layer and the continuity of the polysilicon. To ensure that the nitride has been completely removed between the spacers, an overetch is often performed. However, such processing may sputter the underlying pad oxide, which may redeposit along the sidewalls of the nitride spacers as footings. If this footing is not removed, the line thickness may differ between the core and the gap, which may cause pitch walking in subsequent processing. Conventionally used removal processes include reactive ion etching ("RIE"), which can reduce selectivity to many features. This can also cause the spacer material itself to be rounded and removed, which can further exacerbate pitch walking when the spacers no longer have a uniform height, width, or other characteristic. Furthermore, when the material exposed to RIE contains carbon (such as a low-k dielectric), the associated ashing process may remove the carbon from the dielectric, reducing the dielectric capability.

習知技術已努力處理可能在製造期間的許多情況下發生的這些問題。舉例而言,可以在前段及後段處理(包括自對準圖案化、鰭間隔物、虛閘極間隔物、及金屬化等)中產生心軸及側壁間隔物形成。由於這些處理中之每一者可能進一步產生並導致間隔物的不規則性,所以需要包括改善的選擇性及改善的間隔物輪廓的改善的處理。Prior art has grappled with these problems that can occur in many situations during manufacturing. For example, mandrel and sidewall spacer formation can occur in front-end and back-end processing including self-aligned patterning, fin spacers, dummy gate spacers, and metallization, among others. As each of these processes may further create and result in spacer irregularities, improved processes including improved selectivity and improved spacer profile are desired.

本技術藉由利用在特定裝備中執行選擇性蝕刻處理而克服這些問題,並且可以使用該等處理以利用比習知RIE更高的選擇性來蝕刻,這可允許先前可能無法進行的附加圖案化操作,並且可以為關鍵特徵尺寸(諸如,薄的間隔物輪廓)提供額外的保護。藉由在特定裝備中執行選擇性沉積操作,可以在間隔物形成及心軸移除期間保護周圍特徵。這些處理可以實現減少的處理,同時跨越基板而產生更均勻的結構。The present technique overcomes these problems by utilizing selective etch processes performed in specific equipment, and can use these processes to etch with higher selectivity than conventional RIE, which can allow additional patterning that may not have been possible previously operation and can provide additional protection for critical feature dimensions such as thin spacer profiles. By performing selective deposition operations in specific equipment, surrounding features can be protected during spacer formation and mandrel removal. These treatments can enable reduced handling while producing a more uniform structure across the substrate.

儘管其餘的揭示內容將常規地識別利用所揭示的技術的特定的蝕刻及沉積處理,但應理解,系統及方法同樣適用於所描述的腔室中可能發生的各種其他的蝕刻、沉積、及清潔處理。因此,該技術不應視為受限於僅能用於所述的蝕刻及沉積處理。本揭示將論述可以與本技術一起使用的一個可能的系統及腔室,以在根據本技術的示例性處理序列的所描述操作之前執行某些移除及沉積操作。While the remainder of the disclosure will routinely identify specific etch and deposition processes utilizing the disclosed techniques, it should be understood that the systems and methods are equally applicable to various other etch, deposition, and clean processes that may occur in the described chambers. deal with. Accordingly, the technique should not be considered limited to use with only the etch and deposition processes described. This disclosure will discuss one possible system and chamber that may be used with the present technology to perform certain removal and deposition operations prior to the described operations according to an exemplary processing sequence of the present technology.

第1圖圖示根據實施例的具有沉積、蝕刻、烘焙、及固化腔室的處理系統100的一個實施例的頂視平面圖。在圖式中,一對前開式晶圓盒(FOUP)102供應各種尺寸的基板,各種尺寸的基板係由機器臂104接收,並在放置到位於串聯區段109a-c中的基板處理腔室108a-f中之一者之前,放置到低壓托持區域106中。第二機器臂110可用於將基板晶圓從托持區域106運輸到基板處理腔室108a-f並返回。除了循環層沉積(CLD)、原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、濕式蝕刻、預清潔、脫氣、定向、及其他基板處理之外,可以配備每一基板處理腔室108a-f,以執行包括本文所述的乾式蝕刻處理及選擇性沉積的大量基板處理操作。FIG. 1 illustrates a top plan view of one embodiment of a processing system 100 having deposition, etch, bake, and cure chambers, according to an embodiment. In the drawing, a pair of front opening pods (FOUPs) 102 supply substrates of various sizes, which are received by robotic arms 104 and placed into substrate processing chambers located in serial sections 109a-c. Placed into the low pressure holding area 106 before one of 108a-f. The second robotic arm 110 may be used to transport the substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. In addition to cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etch, pre-clean, degassing, orientation, and other substrate treatments, Each substrate processing chamber 108a-f may be equipped to perform a number of substrate processing operations including dry etch processing and selective deposition as described herein.

基板處理腔室108a-f可包括用於沉積、退火、固化、及/或蝕刻基板晶圓上的介電膜的一或更多個系統部件。在一個配置中,可以使用兩對處理腔室(例如,108c-d與108e-f),以在基板上沉積介電材料或含金屬材料,而第三對處理腔室(例如108a-b)可以用於蝕刻所沉積的介電質。在另一配置中,所有三對腔室(例如,108a-f)可經配置以蝕刻基板上的介電膜。可以在與不同實施例中所示的製造系統分離的腔室中執行所述的任何一或更多個處理。The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and/or etching dielectric films on substrate wafers. In one configuration, two pairs of process chambers (eg, 108c-d and 108e-f) may be used to deposit dielectric or metal-containing materials on the substrate, while a third pair of process chambers (eg, 108a-b) Can be used to etch deposited dielectrics. In another configuration, all three pairs of chambers (eg, 108a-f) can be configured to etch a dielectric film on a substrate. Any one or more of the processes described may be performed in separate chambers from the fabrication systems shown in the various embodiments.

在一些實施例中,腔室具體包括如下所述的至少一個蝕刻腔室以及如下所述的至少一個沉積腔室。藉由包括與工廠介面的處理側組合的這些腔室,可以在受控環境中執行以下所述的所有蝕刻及沉積處理。舉例而言,在托持區域106的處理側可以維持真空環境,而使得在實施例中的所有腔室及轉移均維持在真空下。此舉亦可限制水蒸氣及其他空氣成分接觸處理中的基板。應理解,系統100可以考慮用於介電膜的具有沉積、蝕刻、退火、及固化腔室的附加配置。In some embodiments, the chambers specifically include at least one etching chamber as described below and at least one deposition chamber as described below. By including these chambers in combination with the process side of the factory interface, all etch and deposition processes described below can be performed in a controlled environment. For example, a vacuum environment may be maintained on the processing side of the holding area 106 such that all chambers and transfers in embodiments are maintained under vacuum. This also limits the exposure of water vapor and other air components to the substrate being processed. It should be understood that system 100 may contemplate additional configurations for dielectric films having deposition, etch, anneal, and cure chambers.

第2A圖圖示在處理腔室內具有分隔的電漿產生區域的示例性處理腔室系統200的橫截面圖。在膜蝕刻期間(例如,氮化鈦、氮化鉭、鎢、鈷、氧化鋁、氧化鎢、矽、多晶矽、氧化矽、氮化矽、氮氧化矽、碳氧化矽等),處理氣體可以通過氣體入口組件205流入第一電漿區域215中。遠端電漿系統(RPS)201可以可選擇地包括在系統中,並且可以處理隨後行進通過氣體入口組件205的第一氣體。入口組件205可以包括二或更多個不同的氣體供應通道,其中若包括第二通道(未圖示),則第二通道可以繞過RPS 201。Figure 2A illustrates a cross-sectional view of an exemplary processing chamber system 200 having separate plasma generation regions within the processing chamber. During film etch (for example, titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.), the process gas can be passed through The gas inlet assembly 205 flows into the first plasma region 215 . A remote plasma system (RPS) 201 may optionally be included in the system and may process the first gas that then travels through the gas inlet assembly 205 . Inlet assembly 205 may include two or more different gas supply channels, where a second channel (not shown), if included, may bypass RPS 201 .

圖示冷卻板203、面板217、離子抑制器223、噴淋頭225、及具有基板255設置其上的基板支撐件265,且每一者可以根據實施例而被包括。台座265可以具有熱交換通道,熱交換流體流經熱交換通道以控制基板的溫度,可在處理操作期間操作基板的溫度,以加熱及/或冷卻基板或晶圓。亦可以使用嵌入式電阻加熱器元件而電阻加熱可以包含鋁、陶瓷、或其組合的台座265的晶圓支撐盤,以實現相對高的溫度,諸如從高達或約100℃至高於或約1100℃。Cooling plate 203 , face plate 217 , ion suppressor 223 , showerhead 225 , and substrate support 265 with substrate 255 disposed thereon are shown, and each may be included according to embodiments. The pedestal 265 may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate, which may be manipulated during processing operations to heat and/or cool the substrate or wafer. Embedded resistive heater elements may also be used to resistively heat the wafer support plate, which may comprise aluminum, ceramic, or a combination of pedestals 265, to achieve relatively high temperatures, such as from up to or about 100°C to greater than or about 1100°C .

面板217可以是金字塔形、圓錐形、或具有窄的頂部部分擴展到寬的底部部分的其他類似結構。如圖所示,附加地,面板217可以是平坦的,並包括用於分配處理氣體的複數個貫通通道。取決於RPS 201的使用,電漿產生氣體及/或電漿激發物質可以穿過面板217中如第2B圖所示的複數個孔洞,以更均勻地遞送到第一電漿區域215中。Panel 217 may be pyramidal, conical, or other similar structure having a narrow top portion expanding to a wide bottom portion. As shown, face plate 217 may additionally be flat and include a plurality of through passages for distributing process gases. Depending on the use of the RPS 201 , the plasma generating gas and/or plasma stimulating species may pass through the plurality of holes in the face plate 217 as shown in FIG. 2B for more uniform delivery into the first plasma region 215 .

示例性配置可以包括使氣體入口組件205通入由面板217從第一電漿區域215分隔的氣體供應區域258,而使得氣體/物質流經面板217中的孔洞而進入第一電漿區域215。可以選擇結構及操作特徵,以防止來自第一電漿區域215的電漿大量回流到供應區域258、氣體入口組件205、及流體供應系統210中。位於特徵之間的絕緣環220與面板217、或者腔室的導電頂部部分以及噴淋頭225一起示出,這允許相對於噴淋頭225及/或離子抑制器223而將AC電位施加到面板217。絕緣環220可以定位於面板217與噴淋頭225及/或離子抑制器223之間,以使得電容耦合電漿(CCP)能夠在第一電漿區域中形成。附加地,擋板(未圖示)可以位於第一電漿區域215中,或者另外與氣體入口組件205耦接,以影響流體通過氣體入口組件205進入區域的流動。An exemplary configuration may include having gas inlet assembly 205 open into gas supply region 258 separated from first plasma region 215 by face plate 217 such that gas/substance flows through apertures in face plate 217 into first plasma region 215 . Structural and operational features may be selected to prevent substantial backflow of plasma from first plasma region 215 into supply region 258 , gas inlet assembly 205 , and fluid supply system 210 . An insulating ring 220 between the features is shown with face plate 217, or the conductive top portion of the chamber, and showerhead 225, which allows an AC potential to be applied to the faceplate with respect to showerhead 225 and/or ion suppressor 223 217. An insulating ring 220 may be positioned between faceplate 217 and showerhead 225 and/or ion suppressor 223 to enable capacitively coupled plasma (CCP) formation in the first plasma region. Additionally, a baffle (not shown) may be located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid through the gas inlet assembly 205 into the region.

離子抑制器223可以包含限定貫穿結構的複數個孔隙的板狀或其他幾何形狀,複數個孔隙經配置以抑制離開第一電漿區域215的離子帶電物質的遷移,同時允許不帶電荷的中性或自由基物質穿過離子抑制器223進入抑制器與噴淋頭之間的活性氣體遞送區域。在實施例中,離子抑制器223可以包含具有各種孔隙配置的多孔板。這些不帶電荷的物質可以包括利用較少的反應載氣運輸通過孔隙的高反應性物質。如上所述,離子物質通過孔洞的遷移可能減少,並在一些情況下完全抑制。控制穿過離子抑制器223的離子物質的量可以有利地提供增加對於與底下的晶圓基板接觸的氣體混合物的控制,這又可以增加對氣體混合物的沉積及/或蝕刻特性的控制。舉例而言,氣體混合物的離子濃度的調整可以顯著改變其蝕刻選擇性,例如,SiNx:SiOx蝕刻率、Si:SiOx蝕刻率等。在執行沉積的可替代實施例中,亦可以平移介電材料的共形流動式沉積的平衡。Ion suppressor 223 may comprise a plate or other geometric shape defining a plurality of apertures throughout the structure configured to suppress migration of ionically charged species exiting first plasmonic region 215 while allowing uncharged neutral Or free radical species pass through the ion suppressor 223 into the reactive gas delivery region between the suppressor and the showerhead. In embodiments, ion suppressor 223 may comprise a perforated plate with various pore configurations. These uncharged species may include highly reactive species that utilize less reactive carrier gas to transport through the pores. As noted above, the migration of ionic species through the pores may be reduced, and in some cases completely inhibited. Controlling the amount of ionic species passing through ion suppressor 223 may advantageously provide increased control over the gas mixture in contact with the underlying wafer substrate, which in turn may increase control over the deposition and/or etch characteristics of the gas mixture. For example, adjustment of the ion concentration of a gas mixture can significantly change its etch selectivity, eg, SiNx:SiOx etch rate, Si:SiOx etch rate, etc. In alternative embodiments where deposition is performed, the balance of conformal flow deposition of dielectric material may also be translated.

離子抑制器223中的複數個孔隙可經配置以控制活性氣體(亦即,離子、自由基、及/或中性物質)通過離子抑制器223的通路。舉例而言,可以控制孔洞的高寬比、或孔洞直徑與長度比、及/或孔洞的幾何形狀,而使得穿過離子抑制器223的活性氣體中的離子帶電物質的流動減少。離子抑制器223中的孔洞可以包括面對電漿激發區域215的錐形部分以及面對噴淋頭225的圓柱形部分。圓柱形部分可以成形及定尺寸,以控制傳到噴淋頭225的離子物質的流動。作為控制離子物質通過抑制器的流動的附加手段,亦可以將可調整的電偏壓施加到離子抑制器223。The plurality of apertures in ion suppressor 223 may be configured to control the passage of reactive gases (ie, ions, free radicals, and/or neutral species) through ion suppressor 223 . For example, the aspect ratio of the pores, or the ratio of the diameter to length of the pores, and/or the geometry of the pores may be controlled such that the flow of ionically charged species in the reactive gas passing through the ion suppressor 223 is reduced. The hole in ion suppressor 223 may include a tapered portion facing plasma excitation region 215 and a cylindrical portion facing showerhead 225 . The cylindrical portion can be shaped and dimensioned to control the flow of ionic species to the showerhead 225 . As an additional means of controlling the flow of ionic species through the suppressor, an adjustable electrical bias can also be applied to the ion suppressor 223 .

離子抑制器223可以用於減少或消除從電漿產生區域行進到基板的離子帶電物質的量。不帶電的中性及自由基物質仍然可以穿過離子抑制器中的開口而與基板反應。應注意,在實施例中,可以不執行在環繞基板的反應區域中的離子帶電物質的完全消除。在某些情況下,離子物質意欲到達基板,以執行蝕刻及/或沉積處理。在這些情況下,離子抑制器可以幫助將反應區域中的離子物質濃度控制在有助於處理的層級處。Ion suppressor 223 may be used to reduce or eliminate the amount of ionically charged species traveling from the plasma generation region to the substrate. Uncharged neutral and radical species can still pass through the openings in the ion suppressor to react with the substrate. It should be noted that in embodiments, complete elimination of ionically charged species in the reaction region surrounding the substrate may not be performed. In some cases, ionic species are intended to reach the substrate for etching and/or deposition processes. In these cases, ion suppressors can help control the concentration of ionic species in the reaction zone at levels that facilitate processing.

與離子抑制器223組合的噴淋頭225可以允許電漿存在於第一電漿區域215中,以避免在基板處理區域233中直接激發氣體,同時仍允許激發物質從腔室電漿區域215行進到基板處理區域233。以此方式,腔室可經配置以防止電漿接觸蝕刻中的基板255。此舉可以有利地保護基板上圖案化的各種複雜結構及膜,若直接與所產生的電漿接觸,則各種複雜結構及膜可能損傷、移位、或以其他方式彎曲。此外,當允許電漿接觸基板或接近基板層級時,可能增加氧化物物質蝕刻的速率。因此,若材料的暴露區域為氧化物,則可以藉由遠離基板維持電漿來進一步保護此材料。Showerhead 225 in combination with ion suppressor 223 may allow plasma to exist in first plasma region 215 to avoid direct excitation of gases in substrate processing region 233 while still allowing excited species to travel from chamber plasma region 215 to the substrate processing area 233 . In this way, the chamber may be configured to prevent the plasma from contacting the substrate 255 being etched. This advantageously protects the various complex structures and films patterned on the substrate, which may be damaged, displaced, or otherwise bent if in direct contact with the generated plasma. In addition, when the plasma is allowed to contact the substrate or approach the substrate level, the rate at which the oxide species etch can be increased. Thus, if the exposed areas of the material are oxides, the material can be further protected by maintaining the plasma away from the substrate.

處理系統可以進一步包括與處理腔室電耦接的功率供應器240,以提供電功率到面板217、離子抑制器223、噴淋頭225、及/或台座265,以在第一電漿區域215或處理區域233中產生電漿。取決於所執行的處理,功率供應器可經配置以向腔室遞送可調整量的功率。此種配置可以允許可調諧電漿用於執行中的處理。與通常呈現為具有開啟或關閉功能的遠端電漿單元不同,可調諧電漿可經配置以向電漿區域215遞送特定量的功率。此舉又可以允許形成特定的電漿特性,而使得前驅物可以利用特定方式解離,以增強由這些前驅物產生的蝕刻輪廓。The processing system may further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the faceplate 217, the ion suppressor 223, the showerhead 225, and/or the pedestal 265 to generate power in the first plasma region 215 or A plasma is generated in the processing region 233 . Depending on the process being performed, the power supply can be configured to deliver an adjustable amount of power to the chamber. Such a configuration could allow tunable plasmas to be used for ongoing processing. Unlike remote plasma units, which typically appear to have an on or off function, a tunable plasma can be configured to deliver a specific amount of power to the plasma region 215 . This in turn allows for the formation of specific plasmonic properties such that the precursors can be dissociated in specific ways to enhance the etch profile produced by these precursors.

可以在噴淋頭225上方的腔室電漿區域215或噴淋頭225下方的基板處理區域233中激發電漿。在實施例中,形成於基板處理區域233中的電漿可以是利用作為電極的台座形成的DC偏壓電漿。電漿可以存在於腔室電漿區域215中,以從例如含氟前驅物或其他前驅物的流入產生自由基前驅物。典型地,在射頻(RF)範圍中的AC電壓可以施加於處理腔室的導電頂部部分(諸如,面板217)與噴淋頭225及/或離子抑制器223之間,以在沉積期間激發腔室電漿區域215中的電漿。RF功率供應器可以產生13.56MHz的高RF頻率,但亦可以單獨產生其他頻率或與13.56MHz頻率組合產生其他頻率。Plasma may be excited in chamber plasma region 215 above showerhead 225 or in substrate processing region 233 below showerhead 225 . In an embodiment, the plasma formed in the substrate processing region 233 may be a DC bias plasma formed using a pedestal as an electrode. A plasma may be present in the chamber plasma region 215 to generate free radical precursors from, for example, the influx of fluorine-containing precursors or other precursors. Typically, an AC voltage in the radio frequency (RF) range may be applied between a conductive top portion of the processing chamber, such as faceplate 217, and showerhead 225 and/or ion suppressor 223 to energize the chamber during deposition. Plasma in plasma region 215 of the chamber. The RF power supply can generate a high RF frequency of 13.56MHz, but can also generate other frequencies alone or in combination with the 13.56MHz frequency.

第2B圖圖示影響通過面板217的處理氣體分佈的特徵的詳細視圖253。如第2A圖及第2B圖所示,面板217、冷卻板203、及氣體入口組件205相交,以界定氣體供應區域258,其中處理氣體可以從氣體入口205遞送進入氣體供應區域258。氣體可以填充氣體供應區域258,並通過面板217中的孔隙259流到第一電漿區域215。孔隙259可經配置以基本上單向的方式引導流動,而使得處理氣體可以流入處理區域233中,但是在穿過面板217之後可以被部分或完全防止回流到氣體供應區域258中。FIG. 2B illustrates a detailed view 253 of features affecting process gas distribution through panel 217 . As shown in FIGS. 2A and 2B , face plate 217 , cooling plate 203 , and gas inlet assembly 205 intersect to define gas supply area 258 into which process gases may be delivered from gas inlet 205 . Gas may fill gas supply region 258 and flow through aperture 259 in face plate 217 to first plasma region 215 . Aperture 259 may be configured to direct flow in a substantially unidirectional manner such that process gas may flow into process region 233 but may be partially or completely prevented from backflow into gas supply region 258 after passing through face plate 217 .

氣體分配組件(諸如,用於處理腔室區段200的噴淋頭225)可以稱為雙通道噴淋頭(DCSH),並附加地在第3圖所述的實施例中詳細說明。雙通道噴淋頭可以提供蝕刻處理,以允許在處理區域233之外分離蝕刻劑,以在遞送到處理區域之前提供與腔室部件及彼此間的受限的相互作用。A gas distribution assembly such as showerhead 225 for process chamber section 200 may be referred to as a dual channel showerhead (DCSH), and is additionally detailed in the embodiment depicted in FIG. 3 . A dual channel showerhead may provide etch processing to allow separation of etchant outside of the processing area 233 to provide limited interaction with chamber components and each other prior to delivery to the processing area.

噴淋頭225可以包含上板214及下板216。這些板可以彼此耦接,以界定這些板之間的容積218。板的耦接可以提供通過上板及下板的第一流體通道219以及通過下板216的第二流體通道221。所形成的通道可經配置以提供從容積218單獨經由第二流體通道221通過下板216的流體出入口,而第一流體通道219可以流體隔離於板與第二流體通道221之間的容積218。容積218可以通過氣體分配組件225的一側流體出入。The shower head 225 can include an upper plate 214 and a lower plate 216 . The plates may be coupled to each other to define a volume 218 between the plates. The coupling of the plates may provide a first fluid channel 219 through the upper and lower plates and a second fluid channel 221 through the lower plate 216 . The channels formed may be configured to provide fluid access from the volume 218 through the lower plate 216 via the second fluid channel 221 alone, while the first fluid channel 219 may be fluidly isolated from the volume 218 between the plate and the second fluid channel 221 . Volume 218 is fluidly accessible through one side of gas distribution assembly 225 .

第3圖為根據實施例的與處理腔室一起使用的噴淋頭325的底視圖。噴淋頭325可以對應於第2A圖所示的噴淋頭225。通孔365(圖示第一流體通道219的視圖)可以具有複數種形狀及配置,以控制及影響前驅物通過噴淋頭225的流動。小孔洞375(圖示第二流體通道221的視圖)可以基本均勻地分佈在噴淋頭的表面上方(即使在通孔365中),並且可以有助於前驅物在離開噴淋頭時提供比其他配置更均勻的混合。FIG. 3 is a bottom view of a showerhead 325 for use with a processing chamber in accordance with an embodiment. Showerhead 325 may correspond to showerhead 225 shown in FIG. 2A. Through holes 365 (showing a view of first fluid channel 219 ) can have a variety of shapes and configurations to control and affect the flow of precursors through showerhead 225 . Small holes 375 (showing a view of second fluid channel 221 ) can be distributed substantially evenly over the surface of the showerhead (even in through-holes 365 ), and can help provide a more efficient flow rate for the precursors as they exit the showerhead. Other configurations are more evenly mixed.

轉到第4圖,圖示根據本技術的一或更多個實施例的原子層沉積系統400或反應器的示意性橫截面圖。系統400可以包括裝載閘腔室10與處理腔室20。處理腔室20通常可以是可密封的外殼,其可以在真空或至少低壓下操作。處理腔室20可以藉由隔離閥15與裝載閘腔室10隔離。隔離閥15可以將處理腔室20與裝載閘腔室10密封於關閉位置,並可允許在打開位置時將基板60從裝載閘腔室10通過閥轉移至處理腔室20,反之亦然。Turning to FIG. 4 , a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology is illustrated. System 400 may include a load lock chamber 10 and a processing chamber 20 . Processing chamber 20 may generally be a sealable enclosure that may operate under vacuum or at least low pressure. The processing chamber 20 can be isolated from the load lock chamber 10 by an isolation valve 15 . Isolation valve 15 may seal process chamber 20 from load lock chamber 10 in a closed position and may allow substrate 60 to be transferred through the valve from load lock chamber 10 to process chamber 20 and vice versa when in an open position.

系統400可包括氣體分配板30,氣體分配板30能夠跨越基板60分配一或更多種氣體。氣體分配板30可以是該領域具有通常知識者已知的任何合適的分配板,且所述之特定氣體分配板不應視為限制本技術之範疇。氣體分配板30之輸出面可以面向基板60的第一表面61。System 400 may include gas distribution plate 30 capable of distributing one or more gases across substrate 60 . The gas distribution plate 30 may be any suitable distribution plate known to those of ordinary skill in the art, and the specific gas distribution plate described should not be considered limiting of the scope of the present technology. The output face of the gas distribution plate 30 may face the first surface 61 of the substrate 60 .

氣體分配板30可以包括複數個氣體埠與複數個真空埠,複數個氣體埠經配置以傳送一或更多個氣體流到基板60,而複數個真空埠係設置於每一氣體埠之間,並經配置以傳送氣體流到處理腔室20之外。如第4圖所示,氣體分配板30可以包括第一前驅物注射器420、第二前驅物注射器430、及吹掃氣體注射器440。注射器420、注射器430、注射器440可藉由系統電腦(未圖示)(諸如,主機)控制,或藉由腔室特定控制器(諸如,可程式化邏輯控制器)控制。前驅物注射器420可經配置以將化合物A的反應前驅物之連續或脈衝流注射通過複數個氣體埠425進入處理腔室20。前驅物注射器430可經配置以將化合物B的反應前驅物之連續或脈衝流注射通過複數個氣體埠435進入處理腔室20。吹掃氣體注射器440可經配置以將無反應性或吹掃氣體之連續或脈衝流注射通過複數個氣體埠445進入處理腔室20。吹掃氣體可經配置以從處理腔室20移除反應材料及反應副產物。吹掃氣體典型係為惰性氣體,諸如,氮氣、氬氣、及氦氣。氣體埠445可設置於氣體埠425及氣體埠435之間,以將化合物B之前軀物與化合物A之前驅物分離,藉此避免前驅物之間的交叉汙染。The gas distribution plate 30 may include a plurality of gas ports configured to deliver one or more gas streams to the substrate 60 and a plurality of vacuum ports disposed between each gas port, And configured to convey gas flow out of the processing chamber 20 . As shown in FIG. 4 , the gas distribution plate 30 may include a first precursor injector 420 , a second precursor injector 430 , and a purge gas injector 440 . Syringe 420, syringe 430, and syringe 440 may be controlled by a system computer (not shown), such as a host computer, or by a chamber-specific controller, such as a programmable logic controller. Precursor injector 420 may be configured to inject a continuous or pulsed flow of a reactive precursor of Compound A through gas ports 425 into processing chamber 20 . Precursor injector 430 may be configured to inject a continuous or pulsed flow of a reactive precursor of Compound B through gas ports 435 into processing chamber 20 . The purge gas injector 440 may be configured to inject a continuous or pulsed flow of non-reactive or purge gas through a plurality of gas ports 445 into the processing chamber 20 . The purge gas may be configured to remove reactive materials and reaction by-products from the processing chamber 20 . The purge gas is typically an inert gas such as nitrogen, argon, and helium. The gas port 445 can be disposed between the gas port 425 and the gas port 435 to separate the compound B precursor from the compound A precursor, thereby avoiding cross-contamination between the precursors.

在另一態樣中,在將前驅物注射進入處理腔室20之前,遠端電漿源(未圖示)可連接至前驅物注射器420及前驅物注射器430。可以藉由將電場施加到遠端電漿源內的化合物來產生反應物質之電漿。可以使用能夠活化所意欲化合物的任何功率源。舉例而言,使用DC、射頻、及微波型放電技術的功率源可以使用。若使用RF功率源,則可以電容性或電感性耦接。亦可以藉由熱基技術、氣體解離技術、高強度光源(諸如,紫外光源)、或暴露於x射線源來產生活化。In another aspect, a remote plasma source (not shown) may be connected to precursor injector 420 and precursor injector 430 before injecting the precursor into processing chamber 20 . Plasmas of reacting species can be generated by applying an electric field to compounds within a remote plasma source. Any power source capable of activating the desired compound can be used. For example, power sources using DC, radio frequency, and microwave type discharge techniques may be used. If an RF power source is used, it can be coupled capacitively or inductively. Activation can also be produced by heat-based techniques, gas dissociation techniques, high intensity light sources such as ultraviolet light sources, or exposure to x-ray sources.

系統400可以進一步包括連接至處理腔室20的泵送系統450。泵送系統450大致上可經配置以通過一或更多個真空埠455將氣體流抽空到處理腔室20之外。真空埠455可設置於每一氣體埠之間,以在氣體流與基板表面反應之後將氣體流抽空到處理腔室20之外,並進一步限制前驅物之間的交叉汙染。The system 400 may further include a pumping system 450 connected to the processing chamber 20 . Pumping system 450 may generally be configured to evacuate a gas flow out of processing chamber 20 through one or more vacuum ports 455 . A vacuum port 455 may be provided between each gas port to evacuate the gas flow out of the processing chamber 20 after the gas flow reacts with the substrate surface and further limit cross-contamination between precursors.

系統400可包括設置於處理腔室20上並在每一埠之間的複數個分區460。每一分區的下部可以延伸靠近基板60的第一表面61(例如,距離第一表面61約0.5mm或更多)。以此方式,分區460的下部可以從基板表面分離一距離,該距離足以允許氣體流在氣體流與基板表面反應之後,流動環繞下部而朝向真空埠455。箭頭498指示氣體流的方向。由於分區460可操作作為對於氣體流的物理阻隔,所以分區460亦可限制前驅物之間的交叉汙染。所示之配置僅為說明性,且不應視為限制本技術之範疇。該領域具有通常知識者將理解,所示之氣體分配系統僅為一種可能的分配系統,並且可以採用其他類型的噴淋頭。System 400 may include a plurality of partitions 460 disposed on processing chamber 20 between each port. The lower portion of each partition may extend close to the first surface 61 of the substrate 60 (eg, about 0.5 mm or more from the first surface 61 ). In this way, the lower portion of the partition 460 may be separated from the substrate surface by a distance sufficient to allow the gas flow to flow around the lower portion toward the vacuum port 455 after the gas flow reacts with the substrate surface. Arrow 498 indicates the direction of gas flow. Because partitions 460 operate as physical barriers to gas flow, partitions 460 can also limit cross-contamination between precursors. The configuration shown is illustrative only and should not be considered as limiting the scope of the technology. Those of ordinary skill in the art will appreciate that the gas distribution system shown is only one possible distribution system and that other types of showerheads may be used.

在操作中,可以將基板60(諸如,藉由機器人)遞送到裝載閘腔室10,並可放置於梭子65上。在隔離閥15打開之後,梭子65可以沿著軌道70移動。一旦梭子65進入處理腔室20,隔離閥15可以關閉,以將處理腔室20密封。然後,梭子65可以移動通過處理腔室20,以進行處理。在一個實施例中,梭子65可以在線性路徑中移動通過腔室。In operation, substrate 60 may be delivered to load lock chamber 10 , such as by a robot, and may be placed on shuttle 65 . After the isolation valve 15 is opened, the shuttle 65 can move along the track 70 . Once the shuttle 65 enters the processing chamber 20 , the isolation valve 15 may be closed to seal the processing chamber 20 . The shuttle 65 may then move through the processing chamber 20 for processing. In one embodiment, the shuttle 65 can move through the chamber in a linear path.

隨著基板60移動通過處理腔室20,基板60的第一表面61可以重複暴露到來自氣體埠425的化合物A的前驅物及來自氣體埠435的化合物B的前驅物,其間具有來自氣體埠445的吹掃氣體。吹掃氣體的注入可經設計以在將基板表面61暴露至下一個前驅物之前,移除來自先前前驅物的未反應材料。在對各種氣體流的每一暴露之後,氣體流可以藉由泵送系統450通過真空埠455抽空。由於在每一氣體埠的兩側可以設置真空埠,所以氣體流可以通過在兩側的真空埠455抽空。因此,氣體流可以從個別氣體埠垂直向下朝向基板60的第一表面61流動,跨越第一表面410且環繞分區460之下部,而最後向上朝向真空埠455。以此方式,每一氣體可以均勻地跨越基板表面61分佈。亦可在暴露至各種氣體流時旋轉基板60。基板的旋轉可以對於防止在所形成的層中形成條帶是有用的。基板的旋轉可以是連續或是離散的步驟。As the substrate 60 moves through the processing chamber 20, the first surface 61 of the substrate 60 can be repeatedly exposed to the precursor of compound A from the gas port 425 and the precursor of the compound B from the gas port 435, with the precursor of the compound B from the gas port 445 in between. purge gas. The injection of the purge gas may be designed to remove unreacted material from a previous precursor before exposing the substrate surface 61 to the next precursor. After each exposure to the various gas streams, the gas streams may be evacuated by pumping system 450 through vacuum port 455 . Since vacuum ports can be provided on both sides of each gas port, the gas flow can be evacuated through the vacuum ports 455 on both sides. Thus, the gas flow may flow from the individual gas ports vertically downward toward the first surface 61 of the substrate 60 , across the first surface 410 and around the lower portion of the partition 460 , and finally upward toward the vacuum port 455 . In this way, each gas can be evenly distributed across the substrate surface 61 . Substrate 60 may also be rotated while being exposed to various gas flows. Rotation of the substrate may be useful to prevent banding from forming in the formed layer. The rotation of the substrate can be continuous or discrete steps.

可以藉由例如從氣體埠出來的每一氣體的流動速率及基板60的移動速率來決定基板表面61暴露至每一氣體的程度。在一個實施例中,每一氣體的流動速率可經配置,而不會從基板表面61移除所吸收的前驅物。每一分區之間的寬度、設置於處理腔室20上的氣體埠之數量、及基板可能來回傳遞的次數亦可決定基板表面61暴露至各種氣體的程度。因此,沉積膜的數量與品質可藉由變化上述因子來最佳化。The exposure of the substrate surface 61 to each gas can be determined by, for example, the flow rate of each gas out of the gas ports and the movement rate of the substrate 60 . In one embodiment, the flow rate of each gas can be configured so as not to remove absorbed precursors from the substrate surface 61 . The width between each zone, the number of gas ports provided on the processing chamber 20, and the number of times the substrate may be passed back and forth may also determine the degree of exposure of the substrate surface 61 to the various gases. Therefore, the quantity and quality of the deposited film can be optimized by varying the above factors.

在另一實施例中,系統400可以包括前驅物注入器420與前驅物注入器430,而沒有吹掃氣體注入器440。因此,隨著基板60移動通過處理腔室20,基板表面61可以交替地暴露於化合物A的前驅物與化合物B的前驅物,而不會暴露於其間的吹掃氣體。In another embodiment, the system 400 may include the precursor injector 420 and the precursor injector 430 without the purge gas injector 440 . Thus, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 may be alternately exposed to the precursor of compound A and the precursor of compound B without being exposed to the purge gas in between.

第4圖所示的實施例具有在基板上方的氣體分配板30。儘管已經針對此直立定向描述及圖示實施例,但應理解,相反的定向亦是可能的。在那種情況下,基板60的第一表面61可以面朝下,而朝向基板流動的氣體可以引導朝上。在一或更多個實施例中,至少一個輻射熱源90可以定位成加熱基板的第二側。The embodiment shown in Figure 4 has a gas distribution plate 30 above the substrate. Although the embodiment has been described and illustrated with respect to this upright orientation, it should be understood that the reverse orientation is also possible. In that case, the first surface 61 of the substrate 60 may face downwards and the gas flowing towards the substrate may be directed upwards. In one or more embodiments, at least one radiant heat source 90 may be positioned to heat the second side of the substrate.

在一些實施例中,梭子65可以是用於承載基板60的基座66。通常,基座66可以是有助於跨越基板形成均勻溫度的載體。基座66可以相對於第4圖的佈置在裝載閘腔室10與處理腔室20之間在左到右及右到左的兩個方向上移動。基座66可以具有用於承載基板60的頂表面67。基座66可以是經加熱的基座,而使得基板60可以加熱以用於處理。作為實例,可以藉由設置在基座66下方的輻射熱源90、加熱板、電阻線圈、或其他加熱裝置來加熱基座66。儘管圖示為橫向轉換,但系統400的實施例亦可用於旋轉式系統,其中輪狀物可以順時針或逆時針旋轉,以連續加工位於所示氣體分配系統下方的一或更多個基板。應類似地理解,附加修改係包括在本技術中。In some embodiments, the shuttle 65 may be a base 66 for carrying the substrate 60 . In general, pedestal 66 may be a carrier that helps create a uniform temperature across the substrate. The pedestal 66 is movable in both left-to-right and right-to-left directions between the load lock chamber 10 and the process chamber 20 relative to the arrangement of FIG. 4 . The base 66 may have a top surface 67 for carrying the substrate 60 . Susceptor 66 may be a heated susceptor such that substrate 60 may be heated for processing. As an example, the susceptor 66 may be heated by a radiant heat source 90 disposed below the susceptor 66, a heating plate, a resistive coil, or other heating means. Although illustrated as transversal, embodiments of the system 400 can also be used in rotary systems, where the wheels can be rotated clockwise or counterclockwise to continuously process one or more substrates located below the gas distribution system as shown. It should be similarly understood that additional modifications are included in the technology.

第5圖圖示形成半導體結構的方法500,其中許多操作可以執行於例如前述腔室200及腔室400中。方法500可以包括在開始該方法之前的一或更多個操作,包括前端處理、沉積、蝕刻、研磨、清潔、或可以在所述操作之前執行的任何其他操作。該方法可以包括圖式中所示的多個可選擇操作,其可以或不可以特別與根據本技術的方法相關聯。舉例而言,為了提供更廣泛的結構形成範圍而描述許多操作,但是對於該技術而言並非關鍵,或者可以藉由替代方法來執行,這將在下面進一步論述。方法500描述第6A圖至第6C圖中示意性圖示的操作,將結合方法500的操作而描述其說明。應理解,第6圖僅圖示局部示意圖,而基板可以包含任何數量的具有如圖式中所示的態樣的電晶體區段。FIG. 5 illustrates a method 500 of forming a semiconductor structure in which many operations may be performed in, for example, chamber 200 and chamber 400 described above. Method 500 may include one or more operations prior to initiating the method, including front-end processing, deposition, etching, grinding, cleaning, or any other operation that may be performed prior to the described operations. The method may include a number of optional operations shown in the figures, which may or may not be specifically associated with methods in accordance with the present technology. For example, many operations are described to provide a broader latitude for structure formation, but are not critical to the technique, or can be performed by alternative methods, as discussed further below. The method 500 describes the operations schematically illustrated in FIGS. 6A-6C , an illustration of which will be described in conjunction with the operations of the method 500 . It should be understood that FIG. 6 shows only a partial schematic view, and that the substrate may contain any number of transistor segments in the manner shown in the figure.

方法500可以涉及在具有多個暴露區域的基板上執行的操作,諸如在包括如前述進一步發展以產生各種結構的區域的基板上。如第6A圖所示,圖示包括介電材料605與含矽材料610的經處理的基板600的一部分。含矽材料610可以包括各種元件(可包括佔位符或虛元件(包括心軸或脊柱)),以供稍後的金屬填充。可以諸如藉由沉積及蝕刻材料的心軸而已經先形成含矽材料。舉例而言,可以已經在腔室200中執行凹陷。可以在先前沉積的介電材料605上已經形成含矽材料610。介電材料605可以是基板材料,或者可以是覆蓋基板的層(諸如,遮罩層或蝕刻停止層)。Method 500 may involve operations performed on a substrate having multiple exposed areas, such as on a substrate including areas further developed as previously described to produce various structures. As shown in FIG. 6A , a portion of a processed substrate 600 including a dielectric material 605 and a silicon-containing material 610 is shown. The silicon-containing material 610 may include various elements, which may include placeholders or dummy elements (including mandrels or spines), for later metal filling. The silicon-containing material may have been previously formed, such as by depositing and etching a mandrel of material. By way of example, recessing may already be performed in the chamber 200 . Silicon-containing material 610 may have been formed on previously deposited dielectric material 605 . The dielectric material 605 may be the substrate material, or may be a layer covering the substrate such as a mask layer or an etch stop layer.

含矽材料610的特徵可以是介電材料605上方的高度以及元件的厚度。舉例而言,含矽材料610可以延伸到介電材料605上方大於或約5nm,並且在各種實例中可以延伸到介電材料605上方達到或約10nm、達到或約25nm、達到或約50nm、達到或約75nm、達到或約100nm、達到或約125nm、達到或約150nm、達到或約175nm、達到或約200nm、達到或約225nm、達到或約250nm、或更高。高度亦可以是任何這些範圍內的任何範圍。含矽材料610跨越每一元件的寬度亦可以小於或約100nm,而在實施例中可以小於或大約小於或約90nm、小於或約80nm、小於或約70nm、小於或約60nm、小於或約50nm、40nm、小於或約30nm、小於或約25nm、小於或約20nm、小於或約15nm、小於或約10nm、小於或約5nm、或更小。Silicon-containing material 610 may be characterized by the height above dielectric material 605 and the thickness of the device. For example, the silicon-containing material 610 can extend above the dielectric material 605 by greater than or about 5 nm, and in various examples can extend above the dielectric material 605 by at or about 10 nm, at or about 25 nm, at or about 50 nm, at or above the dielectric material 605 At or about 75 nm, at or about 100 nm, at or about 125 nm, at or about 150 nm, at or about 175 nm, at or about 200 nm, at or about 225 nm, at or about 250 nm, or higher. The height can also be anywhere within any of these ranges. The width of silicon-containing material 610 across each element may also be less than or about 100 nm, and in embodiments may be less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm , 40 nm, less than or about 30 nm, less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, less than or about 10 nm, less than or about 5 nm, or less.

方法500最初可以包括在操作505處圍繞含矽材料610形成第一介電材料615。如第6B圖所示,可以在選擇性沉積中形成第一介電材料615,其中第一介電材料615可以相對於暴露的介電材料605(可以是第二介電材料)而較佳地在含矽材料610上形成。可以在類似於上述腔室400的腔室中執行沉積。The method 500 may initially include forming a first dielectric material 615 around the silicon-containing material 610 at operation 505 . As shown in FIG. 6B, a first dielectric material 615 may be formed in a selective deposition, wherein the first dielectric material 615 may be preferably formed with respect to the exposed dielectric material 605 (which may be a second dielectric material). formed on silicon-containing material 610 . Deposition may be performed in a chamber similar to chamber 400 described above.

在可選擇的操作510處,可以沿著含矽材料610的頂表面執行第一介電材料615的回蝕或移除。回蝕可以是化學機械研磨操作,或者可以涉及化學蝕刻(諸如,電漿增強蝕刻處理),以暴露含矽材料610。在操作515處,可以圍繞第一介電材料615選擇性移除含矽材料610。如第6C圖所示,可以從第二介電材料605以及在連續的第一介電材料615之間移除含矽材料610。所得到的結構可以跨越第二介電材料605的表面提供連續的間隔物元件。藉由利用下面進一步論述的方法,本技術可以產生更均勻的間隔物,同時最小化對於底下的第二介電材料605的損傷。At optional operation 510 , etch back or removal of first dielectric material 615 may be performed along the top surface of silicon-containing material 610 . The etch back may be a chemical mechanical polishing operation, or may involve chemical etching, such as a plasma enhanced etch process, to expose the silicon-containing material 610 . At operation 515 , the silicon-containing material 610 may be selectively removed around the first dielectric material 615 . As shown in FIG. 6C , silicon-containing material 610 may be removed from second dielectric material 605 and between successive first dielectric materials 615 . The resulting structure can provide continuous spacer elements across the surface of the second dielectric material 605 . By utilizing methods discussed further below, the present technique can produce more uniform spacers while minimizing damage to the underlying second dielectric material 605 .

幾個沉積及蝕刻操作可以在單一環境中執行(諸如,在腔室之間的群集工具共享)。舉例而言,附加的沉積腔室可以與一或更多個蝕刻腔室200及沉積腔室400一起,諸如,可以用於填充第二介電材料605。每次轉移可以在真空下進行,而腔室中之每一者可以駐留在相同群集工具上,以允許轉移發生在受控環境中。舉例而言,可以在轉移期間維持真空條件,並且可以在不破壞真空的情況下進行轉移。相對於可包括附加遮罩操作、微影、及可能需要在許多工具之間轉移的其他操作的習知技術,方法500可以在單一工具上執行,其中真空條件在實施例中不受破壞。此外,方法500可以不利用任何RIE操作,這可減少聚合物堆積以及與RIE相關聯的必要的灰化及清潔操作。由於選擇性降低,所以RIE操作亦可能過度蝕刻含矽材料610,這可能使第二介電材料605變得雜亂。Several deposition and etch operations can be performed in a single environment (eg, cluster tool sharing between chambers). For example, additional deposition chambers may be used with one or more etch chambers 200 and deposition chambers 400 , such as may be used to fill the second dielectric material 605 . Each transfer can be performed under vacuum, while each of the chambers can reside on the same cluster tool, allowing the transfer to occur in a controlled environment. For example, vacuum conditions can be maintained during the transfer, and the transfer can be performed without breaking the vacuum. In contrast to conventional techniques, which may include additional masking operations, lithography, and other operations that may require transfer between many tools, method 500 may be performed on a single tool where vacuum conditions are not compromised in embodiments. Additionally, method 500 may not utilize any RIE operations, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE. The RIE operation may also over-etch the silicon-containing material 610 due to reduced selectivity, which may scramble the second dielectric material 605 .

相較於先前技術,本技術亦可以產生第一介電材料615的平坦輪廓。由於RIE的低選擇性,所以也可能圓化或蝕刻第一介電材料615的暴露的頂部部分,這可能產生第一介電材料的不相似的輪廓。藉由利用根據本技術的研磨或蝕刻,可以產生間隔物與間隔物之間更平坦且一致的輪廓。此蝕刻可以維持每一單獨間隔物的跨越間隔物的高度,並且可以在跨越間隔物或間隔物之間產生小於10nm的高度變化。高度變化亦可以限制為小於或約9nm、小於或約8nm、小於或約7nm、小於或約6nm、小於或約5nm、小於或約4nm、小於或約3nm、小於或約2nm、小於或約1nm、或者可基本上跨越每一間隔物的頂部產生平坦輪廓。Compared with the prior art, the present technique can also produce a flat profile of the first dielectric material 615 . Due to the low selectivity of RIE, it is also possible to round or etch the exposed top portion of the first dielectric material 615, which may result in a dissimilar profile of the first dielectric material. By utilizing grinding or etching according to the present technique, a more flat and consistent profile from spacer to spacer can be produced. This etching can maintain the height across the spacers of each individual spacer and can produce height variations of less than 10 nm across or between spacers. The height variation can also be limited to less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm , or a flat profile may be created substantially across the top of each spacer.

可以在處理中利用各種材料,而蝕刻及沉積可以對於多個部件具有選擇性。因此,本技術可以不限於單組材料。舉例而言,含矽材料610可以是矽(諸如,多晶矽),並且亦可以是其他含矽材料(包括氮化矽)與可以在最終結構中操作的其他非金屬(諸如,後續材料的佔位符)。第二介電材料605可以是或包括氧化矽、氮化矽、氮化鈦,但是亦可以使用其他絕緣材料與遮罩材料。舉例而言,可以使用其他含氧、含氮、或含碳材料。舉例而言,第二介電材料605可以是高品質介電質(諸如,熱氧化物),其可以在其他層與材料之間提供相對緻密的層。第一介電材料615亦可以包括絕緣材料,並且可以包括含矽材料、含氮材料、含氧材料、含碳材料、或這些材料的一些組合(諸如,氮化矽、碳氧化矽,氧化鈦、或其他材料)。Various materials can be utilized in processing, and etching and deposition can be selective to multiple components. Therefore, the present technology may not be limited to a single set of materials. Silicon-containing material 610 can be, for example, silicon (such as polysilicon), and can also be other silicon-containing materials (including silicon nitride) and other non-metals that can operate in the final structure (such as placeholders for subsequent materials). symbol). The second dielectric material 605 can be or include silicon oxide, silicon nitride, titanium nitride, but other insulating materials and masking materials can also be used. For example, other oxygen-, nitrogen-, or carbon-containing materials may be used. For example, the second dielectric material 605 can be a high quality dielectric such as thermal oxide, which can provide a relatively dense layer between other layers and materials. The first dielectric material 615 may also include insulating materials, and may include silicon-containing materials, nitrogen-containing materials, oxygen-containing materials, carbon-containing materials, or some combination of these materials (such as silicon nitride, silicon oxycarbide, titanium oxide , or other materials).

當第一介電材料615包括碳(諸如,具有碳氧化矽或其他低k介電質(例如,具有虛閘極間隔物))時,本技術可以包括優於習知技術的另外的益處。RIE處理隨後進行灰化及清潔,以從經蝕刻的結構移除聚合物殘留物。當暴露的材料亦包括碳或對操作敏感的其他材料時,灰化操作也會從暴露的材料中清除碳。此舉可能移除碳摻雜(諸如,在低k介電質中),其可以增加材料的介電常數,使得材料不適合於預期目的,也可能影響裝置效能及電阻。When the first dielectric material 615 comprises carbon, such as with silicon oxycarbide or other low-k dielectrics (eg, with dummy gate spacers), the present technique may include additional benefits over conventional techniques. The RIE process is followed by ashing and cleaning to remove polymer residues from the etched structure. When the exposed material also includes carbon or other materials that are sensitive to the operation, the ashing operation also removes carbon from the exposed material. This may remove carbon doping (such as in low-k dielectrics), which may increase the dielectric constant of the material, rendering the material unsuitable for its intended purpose, and may also affect device performance and resistance.

由於可以在第一介電材料615的選擇性沉積期間暴露第二介電材料605,所以第二介電材料605可以是與實施例中的第一介電材料不同的材料,但是在附加實施例中,這兩種材料可以類似。儘管是不同的材料,但第一介電材料615與第二介電材料605兩者可以是從包括含碳材料、含氮材料、及含氧材料的材料群組中選擇的一或更多種材料,並且可以是上述任何材料。然而,第一介電材料615可以是與用於第二介電材料605的材料不同的材料。Since the second dielectric material 605 may be exposed during the selective deposition of the first dielectric material 615, the second dielectric material 605 may be a different material than the first dielectric material in the embodiments, but in additional embodiments , the two materials can be similar. Although different materials, both the first dielectric material 615 and the second dielectric material 605 may be one or more selected from the group of materials including carbon-containing materials, nitrogen-containing materials, and oxygen-containing materials. material, and can be any of the above materials. However, the first dielectric material 615 may be a different material than the material used for the second dielectric material 605 .

可以在能夠沉積且能夠原子層沉積的腔室(包括上述的腔室400)中執行第一介電材料615的選擇性沉積。沉積可以預設為在相對於介電材料605的含矽材料610上選擇性沉積絕緣材料。舉例而言,第一介電材料615(在一些實施例中,可以是氮化矽、氧化矽、或一些其他含氧化物材料)可以基本上形成於含矽材料610(可以是矽)上,同時最少地形成於第二介電材料605上或者受限於第二介電材料605。可以藉由多種操作來執行選擇性沉積,該多種操作可以包括形成自組裝單層以促進選擇性沉積,或者可以包括主動抑制在其他介電質或半導體材料上形成介電質。Selective deposition of the first dielectric material 615 may be performed in a deposition capable and atomic layer deposition capable chamber, including the chamber 400 described above. Deposition may be preset to selectively deposit insulating material on silicon-containing material 610 relative to dielectric material 605 . For example, first dielectric material 615 (which in some embodiments may be silicon nitride, silicon oxide, or some other oxide-containing material) may be formed substantially on silicon-containing material 610 (which may be silicon), While being minimally formed on or constrained by the second dielectric material 605 . Selective deposition may be performed by a variety of operations which may include forming a self-assembled monolayer to facilitate selective deposition, or may include actively inhibiting the formation of dielectrics on other dielectric or semiconductor materials.

可以在結構的區域上形成自組裝單層,以調諧沉積。舉例而言,可以在結構上方形成第一自組裝單層,然後將其暴露於微影遮罩,以從含矽材料610移除單層。單層可以維持在第二介電材料605上方。單層可以具有可能排斥或無法與後來遞送的前驅物相互作用的封端部分。舉例而言,在實施例中,封端部分可以是疏水性,並且可以利用含氫部分(諸如,甲基)封端,含氫部分可以不與附加前驅物相互作用。第二自組裝單層可以形成在含矽材料610上方,其可以是親水性或與用於產生第一介電材料615的一或更多種前驅物反應。因為材料可以與第一自組裝單層排斥,或者可以選擇性拉伸到元件,所以可以在含矽材料610上方選擇性形成第二自組裝單層。第二自組裝單層可以利用氫氧基或其他親水部分封端,或是利用特別與用於形成第一介電材料615的附加前驅物相互作用的部分封端。Self-assembled monolayers can be formed on regions of the structure to tune the deposition. For example, a first self-assembled monolayer may be formed over the structure and then exposed to a lithography mask to remove the monolayer from the silicon-containing material 610 . A single layer may be maintained over the second dielectric material 605 . Monolayers may have capping moieties that may repel or fail to interact with later delivered precursors. For example, in embodiments, the capping moiety may be hydrophobic and may be capped with a hydrogen-containing moiety, such as methyl, which may not interact with additional precursors. A second self-assembled monolayer may be formed over the silicon-containing material 610 , which may be hydrophilic or reactive with one or more precursors used to create the first dielectric material 615 . A second self-assembled monolayer may be selectively formed over silicon-containing material 610 because the material may repel the first self-assembled monolayer, or may selectively stretch to the device. The second self-assembled monolayer may be terminated with hydroxyl or other hydrophilic moieties, or with moieties that specifically interact with the additional precursors used to form the first dielectric material 615 .

然後,可以利用二或更多個前驅物執行原子層沉積,以開發第一介電材料615。沉積的前驅物可以包括含金屬或含矽前驅物,並包括經配置以與封端第二自組裝單層(而非第一自組裝單層)的部分相互作用的前驅物。舉例而言,當使用親水性及疏水性封端單層時,原子層沉積前驅物中之一者可以包括水。以此方式,沉積可能不會形成於可以是疏水性的第一自組裝單層上。若第一介電材料包括金屬氧化物(諸如,氧化鈦),則用於原子層沉積的前驅物可以包括含鈦前驅物或一些其他含金屬材料以及水。在其他實施例中,可以使用含矽前驅物來代替含金屬材料。然後,在與水的半反應期間,水可能無法與形成在第二介電材料605上方的第一自組裝單層相互作用,而因此沉積可以不在第一自組裝單層上方形成。以此方式,可以在含矽材料610上方選擇性形成第一介電材料615。Atomic layer deposition may then be performed using two or more precursors to develop the first dielectric material 615 . The deposited precursors may include metal-containing or silicon-containing precursors, and include precursors configured to interact with portions that terminate the second self-assembled monolayer but not the first self-assembled monolayer. For example, when using hydrophilic and hydrophobic capped monolayers, one of the ALD precursors may include water. In this way, deposits may not form on the first self-assembled monolayer, which may be hydrophobic. If the first dielectric material includes a metal oxide such as titanium oxide, the precursors for atomic layer deposition may include a titanium-containing precursor or some other metal-containing material and water. In other embodiments, silicon-containing precursors may be used instead of metal-containing materials. Then, during the half-reaction with water, the water may not be able to interact with the first self-assembled monolayer formed over the second dielectric material 605, and thus deposition may not form over the first self-assembled monolayer. In this way, the first dielectric material 615 can be selectively formed over the silicon-containing material 610 .

第一介電材料615已經形成至合適的高度之後,第一自組裝單層可以暴露於UV光,並從基板移除,或者可以進行一些其他移除。因此,第一自組裝單層可以在含矽材料610的選擇性蝕刻之後直接形成,或者在轉移到附加腔室之後但在附加處理操作之前形成。以此方式,可以排除習知形成中使用的多個操作,這可以顯著減少佇列時間(諸如,幾個小時)。在其他實施例中,取決於所執行的操作,可以在選擇性沉積之後執行輕微的凹陷,以從第二介電材料605移除殘留材料。應理解,這僅為利用基於一組沉積材料的自組裝單層的實例。下文將進一步論述可作為替代前驅物的附加材料。After the first dielectric material 615 has been formed to a suitable height, the first self-assembled monolayer may be exposed to UV light and removed from the substrate, or some other removal may be performed. Thus, the first self-assembled monolayer may be formed directly after the selective etching of the silicon-containing material 610, or after transfer to an additional chamber but before additional processing operations. In this way, several operations used in knowledge formation can be eliminated, which can significantly reduce queue times (such as hours). In other embodiments, depending on the operations performed, a slight recess may be performed after the selective deposition to remove residual material from the second dielectric material 605 . It should be understood that this is merely an example of utilizing a self-assembled monolayer based on a set of deposited materials. Additional materials that may serve as alternative precursors are discussed further below.

實施例亦可以利用抑制劑以在含矽材料610上方選擇性形成第一介電材料615,同時不在第二介電材料605上方形成第一介電材料615或是於介電材料605上形成有限的量。舉例而言,可以跨越介電材料的表面施加抑制劑,該抑制劑可以不施加,或者可以從含矽材料610移除。抑制劑亦可以跨越縱向表面施加,同時維持垂直表面整潔,這可以允許單獨對於垂直表面具有選擇性的材料形成。抑制劑可以是任何數量的材料,材料的特徵可以是矽氧烷主鏈(諸如,矽氧烷)或四氟乙烯主鏈(諸如,PTFE),以及其他油性或表面活性劑材料。可以跨越基板的表面施加材料,以覆蓋介電材料605的暴露部分。Embodiments may also utilize an inhibitor to selectively form the first dielectric material 615 over the silicon-containing material 610 while not forming the first dielectric material 615 over the second dielectric material 605 or forming limited amount. For example, an inhibitor may be applied across the surface of the dielectric material, the inhibitor may not be applied, or may be removed from the silicon-containing material 610 . Inhibitors can also be applied across longitudinal surfaces while maintaining vertical surface cleanliness, which can allow selective material formation for vertical surfaces alone. The inhibitor can be any number of materials, and the material can be characterized by a silicone backbone (such as siloxane) or a tetrafluoroethylene backbone (such as PTFE), as well as other oily or surfactant materials. Material may be applied across the surface of the substrate to cover exposed portions of the dielectric material 605 .

抑制劑材料可以防止在含矽材料610上可以正常形成或沉積的材料的黏附或吸附。隨後形成第一介電材料615,並可以將移除劑施加到基板上,以移除抑制劑材料。移除劑可以是濕式蝕刻劑、反應物、或表面活性劑清潔劑,其可以移除讓底下的介電材料605或含矽材料610的頂表面暴露的殘留抑制劑材料。利用抑制劑可以允許在界定區域中形成第一介電材料,該界定的區域不需要經由隨後的毯覆膜的圖案化及/或蝕刻界定。藉由移除先前及後續的圖案化操作,處理可以進一步減少習知處理的佇列時間。The suppressor material may prevent adhesion or adsorption of materials that would normally form or deposit on the silicon-containing material 610 . A first dielectric material 615 is then formed, and a remover may be applied to the substrate to remove the suppressor material. The remover can be a wet etchant, a reactant, or a surfactant cleaner that can remove residual inhibitor material that exposes the top surface of the underlying dielectric material 605 or silicon-containing material 610 . Utilizing an inhibitor may allow the formation of the first dielectric material in defined areas that do not need to be defined by subsequent patterning and/or etching of the blanket film. The process can further reduce the queue time of conventional processes by removing previous and subsequent patterning operations.

抑制劑亦可以是可以中和基板的表面或使基板的表面呈現惰性的電漿應用的產物。舉例而言,改性電漿可以由一或更多種前驅物形成,該一或更多種前驅物可以包括惰性前驅物。可以將電漿施加到基板的表面,這可以改變含矽材料610或第二介電材料605的頂表面,但是這可能不影響含矽材料610的垂直表面。舉例而言,含氮前驅物(可以是氮)可以遞送到產生電漿的處理腔室的電漿處理區域。電漿流出物(可以包括含氮電漿流出物)可以遞送到基板,並且可以沿著含矽材料610沿著頂表面的暴露部分形成氮化表面。Inhibitors can also be the product of plasma applications that can neutralize or render inert the surface of the substrate. For example, a modified plasma can be formed from one or more precursors, which can include an inert precursor. A plasma may be applied to the surface of the substrate, which may alter the top surface of the silicon-containing material 610 or the second dielectric material 605 , but may not affect the vertical surfaces of the silicon-containing material 610 . For example, a nitrogen-containing precursor (which may be nitrogen) may be delivered to a plasma processing region of a processing chamber where the plasma is generated. Plasma effluents, which may include nitrogen-containing plasma effluents, may be delivered to the substrate and may form a nitrided surface along exposed portions of the top surface along silicon-containing material 610 .

電漿流出物可以不向下遞送(或者可以不向下流動)到第二介電材料605的層級。然後,可以利用一或更多種沉積技術形成第一介電材料615,沉積技術可以包括原子層沉積或其他氣相或物理沉積。相對於含矽材料610的側壁,亦可以將附加阻擋機構應用到第二介電材料,這可以使得能夠僅沿著或主要沿著含矽材料610的側壁沉積。舉例而言,可以利用原子層沉積技術對電漿流出物進行後續處理。在沉積的每一循環之後,含氮電漿可以重新施加到基板的表面區域上(諸如,在含矽材料610上方)。以此方式,含矽材料610的表面可以鈍化,以防止或限制彼等區域上方的第一介電材料615的形成。利用在基板的非凹陷部分上的這些電漿流出物可以允許在界定區域中形成蓋材料,該界定區域不需要經由後續的毯覆膜的圖案化及/或蝕刻界定。藉由移除先前及後續的圖案化操作,處理可以進一步減少習知處理的佇列時間。The plasma effluent may not be delivered (or may not flow) down to the level of the second dielectric material 605 . First dielectric material 615 may then be formed using one or more deposition techniques, which may include atomic layer deposition or other vapor phase or physical deposition. Additional barrier mechanisms may also be applied to the second dielectric material relative to the sidewalls of the silicon-containing material 610 , which may enable deposition only or primarily along the sidewalls of the silicon-containing material 610 . For example, the plasma effluent can be post-treated using atomic layer deposition techniques. After each cycle of deposition, the nitrogen-containing plasma may be reapplied onto the surface region of the substrate (such as over the silicon-containing material 610 ). In this way, the surface of the silicon-containing material 610 can be passivated to prevent or limit the formation of the first dielectric material 615 over those regions. Utilizing these plasma effluents on non-recessed portions of the substrate may allow the formation of cap material in defined areas that do not need to be defined by subsequent patterning and/or etching of the blanket film. The process can further reduce the queue time of conventional processes by removing previous and subsequent patterning operations.

亦可以使用附加選擇性沉積技術,其可以包括用於選擇性沉積介電材料(諸如,含氮材料)的替代機制。舉例而言,含氮材料可以作為沉積將發生的材料上的自組裝單層中之一者(諸如,單層的封端部分中之一者),這可以允許吸引用於形成先前描述的材料中之一或更多者的特定前驅物。又一技術可以利用溫度差異以增強相對於氧化矽的矽上的沉積。舉例而言,利用含矽前驅物與含氮前驅物的原子層沉積可以在高於或約500℃的溫度下執行,並且可以在高於或約750℃、高於或約900℃、高於或約1000℃、或達到、高於、或約1100℃的溫度下執行。Additional selective deposition techniques may also be used, which may include alternative mechanisms for selectively depositing dielectric materials, such as nitrogen-containing materials. For example, the nitrogen-containing material can be one of the self-assembled monolayers (such as one of the capped portions of the monolayer) on the material on which the deposition will occur, which can allow the attraction for forming the previously described materials Specific precursors of one or more of them. Yet another technique may utilize temperature differentials to enhance deposition on silicon relative to silicon oxide. For example, atomic layer deposition using silicon-containing precursors and nitrogen-containing precursors can be performed at temperatures above or about 500°C, and can be at or above 750°C, above or about 900°C, above or performed at a temperature of about 1000°C, or at, above, or about 1100°C.

隨著溫度在此範圍內增加,可以在矽上以比在氧化矽上更高的速率發生沉積。然後,可以執行氮的選擇性蝕刻,以從氧化矽表面移除第一介電材料。儘管亦可以在矽表面上減少第一介電材料,但因為厚度可以比氧化矽上的厚許多倍,所以可以執行從氧化矽的完全移除,同時維持含矽材料610上的厚度大於或約1nm、大於或約2nm、大於或約3nm、大於或約4nm、大於或約5nm、大於或約6nm、大於或約7nm、大於或約8nm、大於或約9nm、大或約10nm、或更大。此效果可使得本技術能夠實現習知技術所受限的方式。在正常保形或毯覆沉積期間,鰭元件的一些部分的厚度將等於氧化層上的厚度。因此,回蝕處理甚至可以利用定向蝕刻來暴露鰭元件的至少一部分。As the temperature is increased in this range, deposition can occur at a higher rate on silicon than on silicon oxide. A nitrogen selective etch can then be performed to remove the first dielectric material from the silicon oxide surface. Although it is also possible to reduce the first dielectric material on the silicon surface, because the thickness can be many times thicker than on the silicon oxide, complete removal from the silicon oxide can be performed while maintaining a thickness on the silicon-containing material 610 greater than or about 1 nm, greater than or about 2 nm, greater than or about 3 nm, greater than or about 4 nm, greater than or about 5 nm, greater than or about 6 nm, greater than or about 7 nm, greater than or about 8 nm, greater than or about 9 nm, greater than or about 10 nm, or greater . This effect may enable the present technique to be implemented in a manner limited by prior art techniques. During normal conformal or blanket deposition, the thickness of some parts of the fin element will be equal to the thickness on the oxide layer. Thus, the etch-back process may even utilize a directional etch to expose at least a portion of the fin elements.

相對於一或更多個非金屬、介電質、或絕緣區域,這些技術中之任一者可以在含矽材料610上方選擇性沉積或形成介電或絕緣材料。此外,亦可以利用組合以調整形成。舉例而言,抑制劑可以施加到含矽材料610的頂表面,或者頂表面可以呈現惰性,然後自組裝單層可以用於含矽材料610的側壁與第二介電材料605。所描述的技術的其他組合亦可以利用,且亦包含於本技術中。選擇性可以是完整的,亦即,第一介電材料僅在含矽材料610或中間層上方形成,而第一介電材料615可以完全不在第二介電材料605上方形成。 Any of these techniques may selectively deposit or form a dielectric or insulating material over silicon-containing material 610 relative to one or more non-metallic, dielectric, or insulating regions. In addition, combinations can also be used to adjust the formation. For example, an inhibitor can be applied to the top surface of the silicon-containing material 610 , or the top surface can be rendered inert, and then a self-assembled monolayer can be applied to the sidewalls of the silicon-containing material 610 and the second dielectric material 605 . Other combinations of the described techniques may also be utilized and are encompassed by the present technique. The selectivity may be complete, ie, the first dielectric material is formed only over the silicon-containing material 610 or the interlayer, while the first dielectric material 615 may not be formed over the second dielectric material 605 at all.

在其他實施例中,選擇性可能不是完整的,而含矽材料610上的沉積相對於介電材料605上的沉積的比率可以是大於約2:1。選擇性亦可以大於或約5:1、大於或約10:1、大於或約15:1、大於或約20:1、大於或約25:1、大於或約30:1、大於或約35:1、大於或約40:1、大於或約45:1、大於或約50:1、大於或約75:1、大於或約100:1、大於或約200:1、或更多。如前所述,取決於所產生的結構,含矽材料610上的沉積厚度可以小於或約20nm、小於或約10nm、小於或約5nm、或更小。因此,低於20:1的選擇性可以是可接受的,以完全沉積第一介電材料615,同時在第二介電材料605上方形成有限量的材料或基本上沒有形成材料。 In other embodiments, the selectivity may not be complete and the ratio of deposition on silicon-containing material 610 to dielectric material 605 may be greater than about 2:1. Selectivity can also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35 :1, greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more. As previously mentioned, the deposited thickness on silicon-containing material 610 may be less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less depending on the structure being produced. Accordingly, a selectivity of less than 20:1 may be acceptable to completely deposit the first dielectric material 615 while forming a limited amount of material or substantially no material over the second dielectric material 605 .

沉積操作可以在前述的任何溫度或壓力下執行,並可以在大於或約300℃的溫度下執行,且可以在大於或約400℃、大於或約450℃、大於或約500℃、大於或約600℃、大於或約700℃、大於或約800℃、大於或約900℃、大於或約1000℃、或更高的溫度下執行。舉例而言,在原子層沉積操作期間,可以使用大於或約500℃的溫度,以活化前驅物,以在材料層形成時彼此相互作用。The deposition operation may be performed at any of the aforementioned temperatures or pressures, and may be performed at a temperature of greater than or about 300°C, and may be performed at a temperature of greater than or about 400°C, greater than or about 450°C, greater than or about 500°C, greater than or about 600°C, greater than or about 700°C, greater than or about 800°C, greater than or about 900°C, greater than or about 1000°C, or higher. For example, during atomic layer deposition operations, temperatures greater than or about 500° C. may be used to activate the precursors to interact with each other as the material layer is formed.

蝕刻或凹陷操作510及515可以是如先前所述的選擇性蝕刻操作,儘管可以取決於沉積或所執行的沉積技術的選擇性而不執行操作510。此外,可以執行研磨(諸如,化學機械研磨),以暴露含矽材料610的頂部表面。可以在類似於先前描述的腔室200的蝕刻腔室中使介電材料與含矽材料或心軸凹陷。一旦定位於半導體處理腔室的處理區域內,該方法可以包括在處理腔室的遠端電漿區域中形成含氟前驅物的電漿。遠端電漿區域可以與處理區域流體耦合,但是可以物理分隔,以將電漿限制在基板層級處,這可能損傷暴露的結構或材料。電漿的流出物可以流入處理區域中,在該處理區域中電漿的流出物可以接觸半導體基板並選擇性蝕刻材料。Etching or recessing operations 510 and 515 may be selective etch operations as previously described, although operation 510 may not be performed depending on the selectivity of the deposition or deposition technique being performed. Additionally, grinding, such as chemical mechanical grinding, may be performed to expose the top surface of the silicon-containing material 610 . The dielectric material and silicon-containing material or mandrels may be recessed in an etch chamber similar to chamber 200 described previously. Once positioned within the processing region of the semiconductor processing chamber, the method may include forming a plasma of the fluorine-containing precursor in a remote plasma region of the processing chamber. The remote plasma region may be fluidly coupled to the processing region, but may be physically separated to confine the plasma at the substrate level, which may damage exposed structures or materials. The effluent of the plasma may flow into a processing region where the effluent of the plasma may contact the semiconductor substrate and selectively etch material.

兩個蝕刻操作可以涉及與特定含氟前驅物一起的附加前驅物。在一些實施例中,可以使用三氟化氮來產生電漿流出物。亦可以利用附加或可替代的含氟前驅物。舉例而言,含氟前驅物可以流入遠端電漿區域,並且含氟前驅物可以包括選自由原子氟、雙原子氟、三氟化溴、四氟化碳、三氟化氯、三氟化氮、氟化氫、六氟化硫、及二氟化氙組成的群組的至少一種前驅物。遠端電漿區域可以在與處理腔室不同的模組內或在處理腔室內的隔間內。如第2圖所示,RPS單元201與第一電漿區域215二者可以作為遠端電漿區域。RPS可以允許電漿流出物解離而不會損傷其他腔室部件,而第一電漿區域215可以提供到基板的較短路徑長度,在此期間可能發生重組。Both etching operations may involve additional precursors along with specific fluorine-containing precursors. In some embodiments, nitrogen trifluoride may be used to generate plasma effluents. Additional or alternative fluorine-containing precursors may also be utilized. For example, a fluorine-containing precursor may flow into the distal plasma region, and the fluorine-containing precursor may include a group selected from atomic fluorine, diatomic fluorine, bromine trifluoride, carbon tetrafluoride, chlorine trifluoride, trifluoride At least one precursor of the group consisting of nitrogen, hydrogen fluoride, sulfur hexafluoride, and xenon difluoride. The remote plasma region may be in a different module than the processing chamber or in a compartment within the processing chamber. As shown in FIG. 2 , both the RPS unit 201 and the first plasma region 215 can serve as the remote plasma region. The RPS may allow dissociation of the plasma effluent without damaging other chamber components, while the first plasma region 215 may provide a shorter path length to the substrate during which recombination may occur.

附加前驅物亦可以遞送到遠端電漿區域,以增強含氟前驅物。舉例而言,在含矽材料的蝕刻期間,可以相對於氧化矽(可以是第二介電材料605)選擇性對矽執行蝕刻。舉例而言,含碳及氫的前驅物或氫前驅物可以與含氟前驅物一起遞送。舉例而言,附加前驅物亦可以是含氟前驅物(諸如,氟甲烷)。可以包括含氫或含碳及氫的前驅物,以維持電漿流出物的特定H:F原子比。在實施例中,可以利用大於1的H:F比執行蝕刻,這可以提供相對於上述介電材料的對於矽的增加的選擇性。H:F原子流量比可以維持為大於或約25:1,而在實施例中,可以維持為大於或約30:1,或者大於或約40:1,這可以藉由調整含氟前驅物與含氫前驅物的相對流率來控制。Additional precursors can also be delivered to the distal plasmonic region to enhance the fluorine-containing precursors. For example, during the etch of silicon-containing materials, the etch may be performed selectively on silicon relative to silicon oxide (which may be the second dielectric material 605). For example, a carbon and hydrogen containing precursor or a hydrogen precursor can be delivered together with a fluorine containing precursor. For example, the additional precursor may also be a fluorine-containing precursor such as fluoromethane. Precursors containing hydrogen or carbon and hydrogen may be included to maintain a specific H:F atomic ratio of the plasma effluent. In an embodiment, etching may be performed with a H:F ratio greater than 1, which may provide increased selectivity for silicon relative to the above-mentioned dielectric materials. The H:F atomic flow ratio can be maintained at greater than or about 25:1, and in an embodiment, can be maintained at greater than or about 30:1, or greater than or about 40:1, which can be achieved by adjusting the fluorine-containing precursor and The relative flow rate of the hydrogen-containing precursor is controlled.

此處理可以藉由大於或約70:1的比率相對於氧化矽與氮化矽選擇性蝕刻矽。在所揭示的實施例中,蝕刻選擇性亦可大於或約100:1、大於或約150:1、大於或約200:1、大於或約250:1、或大於或約300:1,這可以允許在移除操作期間實質上或基本上維持第一介電材料615與第二介電材料605。在第一介電材料615或第二介電材料605包括氮化鈦或氧化鈦的實施例中,矽相對於暴露的含金屬材料的蝕刻選擇性在所揭示的實施例中可以大於或約100:1、大於或約150:1、大於或約200:1、大於或約250:1、大於或約500:1、大於或約1000:1、大於或約2000:1、或大於或約3000:1。以此方式,可以在受限或基本上不移除基板上的其他暴露材料的情況下完全移除矽心軸或其他含矽材料610。This process can selectively etch silicon with respect to silicon oxide and silicon nitride by a ratio of greater than or about 70:1. In disclosed embodiments, the etch selectivity can also be greater than or about 100:1, greater than or about 150:1, greater than or about 200:1, greater than or about 250:1, or greater than or about 300:1, which The first dielectric material 615 and the second dielectric material 605 may be allowed to be substantially or substantially maintained during the removal operation. In embodiments where the first dielectric material 615 or the second dielectric material 605 includes titanium nitride or titanium oxide, the etch selectivity of silicon relative to exposed metal-containing material may be greater than or about 100 in disclosed embodiments. :1, greater than or about 150:1, greater than or about 200:1, greater than or about 250:1, greater than or about 500:1, greater than or about 1000:1, greater than or about 2000:1, or greater than or about 3000 :1. In this manner, the silicon mandrel or other silicon-containing material 610 may be completely removed with limited or substantially no removal of other exposed material on the substrate.

可以執行相對於介電材料605的第一介電材料615的選擇性蝕刻,以移除殘留的第一介電材料615(若存在),並且可以使用別處所使用的類似或不同的前驅物。舉例而言,儘管材料可以是如前所述的任何材料,但在實施例中,第一介電材料615可以是氮化矽或者包括氮化矽,而介電材料605可以是氧化矽或包括氧化矽。氮化矽相對於氧化矽的選擇性蝕刻可以利用如前所述的含氟前驅物,並且亦可以包括含氧前驅物。含氧前驅物可以與含氟化物前驅物一起遞送到遠端電漿區域,或者含氧前驅物可以繞過遠端電漿區域,而直接遞送到處理區域中。A selective etch of first dielectric material 615 relative to dielectric material 605 may be performed to remove residual first dielectric material 615 (if present), and similar or different precursors may be used as used elsewhere. For example, although the materials may be any of the materials described above, in an embodiment, the first dielectric material 615 may be or include silicon nitride, and the dielectric material 605 may be or include silicon oxide. Silicon oxide. Selective etching of silicon nitride relative to silicon oxide may utilize fluorine-containing precursors as described above, and may also include oxygen-containing precursors. The oxygen-containing precursor can be delivered to the remote plasma region along with the fluoride-containing precursor, or the oxygen-containing precursor can bypass the remote plasma region and be delivered directly into the treatment region.

在一些實施例中,第一介電材料蝕刻操作在蝕刻期間可以不包括含氫前驅物,並且可以在無氫的環境下執行。操作可以利用大於或約20:1的選擇性而相對於氧化矽選擇性蝕刻氮化矽,並且可以利用大於或約30:1的選擇性而蝕刻氮化矽。由於可移除的殘留第一介電材料615的量可以小於或約10nm、小於或約5nm、或更小,所以低於或約20:1的蝕刻速率仍然可以充分移除第一介電材料,而實質上不會損傷介電材料605。相對於矽,蝕刻亦可以對氮化矽具有選擇性,矽可以是底下的含矽材料610。選擇性可以大於或約10:1,這可以允許所有殘留的第一介電材料615被移除,而實質上不會損傷含矽材料610,但是當隨後的操作涉及移除含矽材料610時,蝕刻這些材料可以是可接受的。In some embodiments, the first dielectric material etch operation may not include a hydrogen-containing precursor during the etch, and may be performed in a hydrogen-free environment. The operation may selectively etch silicon nitride relative to silicon oxide with a selectivity of greater than or about 20:1, and may etch silicon nitride with a selectivity of greater than or about 30:1. Since the amount of residual first dielectric material 615 that can be removed can be less than or about 10 nm, less than or about 5 nm, or less, an etch rate of less than or about 20:1 can still sufficiently remove the first dielectric material , without substantially damaging the dielectric material 605 . The etch can also be selective to silicon nitride, which can be the underlying silicon-containing material 610 , relative to silicon. The selectivity can be greater than or about 10:1, which can allow all remaining first dielectric material 615 to be removed without substantially damaging silicon-containing material 610, but when subsequent operations involve removal of silicon-containing material 610 , etching these materials may be acceptable.

在實施例中,蝕刻操作可以在低於約10Torr的情況下執行,以及在實施例中可以在低於或約5Torr的情況下執行。在實施例中,處理亦可以在低於約100℃的溫度下執行,並且可以在低於約50℃的情況下執行。隨著在腔室200或此腔室的變體中執行,或者在能夠執行類似操作的不同腔室中執行,處理可以對於第二介電材料605具有選擇性而移除第一介電材料615的部分。這些操作亦可以對於第一介電材料615與第二介電材料605具有選擇性而移除含矽材料610的部分。In an embodiment, the etching operation may be performed at less than about 10 Torr, and may be performed at less than or about 5 Torr in an embodiment. In embodiments, processing may also be performed at temperatures below about 100°C, and may be performed at temperatures below about 50°C. As performed in the chamber 200 or a variation of this chamber, or in a different chamber capable of performing similar operations, the process may be selective to the second dielectric material 605 while removing the first dielectric material 615 part. These operations may also remove portions of the silicon-containing material 610 being selective to the first dielectric material 615 and the second dielectric material 605 .

儘管在一些實施例中,本技術可以執行所沉積的氮化矽的回蝕,以從介電材料605的表面及/或含矽材料610的頂表面移除任何殘留的氮化物,但是含矽材料610的側壁上的第一介電材料615的厚度可以是介電材料605上及/或含矽材料610的頂表面上的第一介電材料615的厚度的厚度的至少兩倍。因此,回蝕處理可以完全移除介電材料605上的殘留第一介電材料615,同時將含矽材料610的側壁上的完整塗層維持為先前描述的任何厚度。以此方式,本技術可以在介電材料上方產生實質上或基本上均勻的間隔物,該介電材料具有最小的移除或並未從形成處理移除。此外,對於包括碳的第一介電材料615的處理,所描述的處理可以產生比使用RIE的習知技術更好的結構,並且可以清除處理操作中的碳。Although in some embodiments, the present technique can perform an etch-back of the deposited silicon nitride to remove any residual nitride from the surface of the dielectric material 605 and/or the top surface of the silicon-containing material 610, the silicon-containing The thickness of the first dielectric material 615 on the sidewalls of the material 610 may be at least twice the thickness of the thickness of the first dielectric material 615 on the dielectric material 605 and/or on the top surface of the silicon-containing material 610 . Thus, the etch-back process can completely remove the residual first dielectric material 615 on the dielectric material 605 while maintaining a complete coating on the sidewalls of the silicon-containing material 610 to any of the previously described thicknesses. In this way, the present technique can produce substantially or substantially uniform spacers over dielectric material with minimal or no removal from the formation process. Furthermore, for processing of the first dielectric material 615 that includes carbon, the described processing can result in a better structure than conventional techniques using RIE, and can remove carbon from the processing operation.

在先前描述中,為了解釋之目的,已經闡述許多細節,以提供對於本技術的各種實施例的理解。然而,對於該領域具有通常知識者顯而易見的是,可以在沒有這些細節中之一些或在具有附加細節的情況下實施某些實施例。In the previous description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent, however, to one having ordinary skill in the art that certain embodiments may be practiced without some of these details or with additional details.

已揭示幾個實施例,但應理解,該領域具有通常知識者可以在不悖離實施例的精神的情況下使用各種修改、替代構造、及等同物。此外,為了避免不必要地模糊本技術,並未描述許多已知的處理及元件。因此,上面的描述不應視為限制本技術之範疇。Several embodiments have been disclosed, but it should be understood that those skilled in the art can employ various modifications, alternative constructions, and equivalents without departing from the spirit of the embodiments. Additionally, many known processes and elements have not been described in order to avoid unnecessarily obscuring the technology. Therefore, the above description should not be taken as limiting the scope of the technology.

當提供值的範圍時,應理解,除非上下文另有明確說明,亦具體揭示該範圍的上限與下限之間的每一中間值,到下限單位的最小部分。包括在所述範圍中的任何所述值或未敘述的中間值與所述範圍中的任何其他所述或中間值之間的任何較窄範圍。這些較小範圍的上限與下限可以獨立地包括在範圍中或排除在外,而包括上下限其中一者、兩者或不含上下限的較小範圍中的每一範圍亦包括在本技術內,取決於所述範圍中特別排除的限制。在所述範圍包括一或二個限制的情況下,則亦包括排除這些所包括限制中的一或二者的範圍。When a range of values is provided, it is understood that, unless the context clearly dictates otherwise, each intervening value between the upper and lower limit of that range, to the smallest fraction of the unit of the lower limit, is also specifically disclosed. Any narrower range between any stated or unrecited intervening value in a stated range and any other stated or intervening value in that stated range is included. The upper and lower limits of these smaller ranges may independently be included in or excluded from the range, and each of the smaller ranges including either, both, or no limits is also encompassed within the technology. subject to the limitations specifically excluded in the stated ranges. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

如本文及隨附專利申請範圍中所使用,除非上下文另有明確說明,否則單數形式「一」、「一個」、及「該」包括複數指稱。因此,舉例而言,指稱「一層」包括複數個這樣的層,而指稱「前驅物」包括指稱該領域具有通常知識者已知的一或更多種前驅物及其等同物等等。As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers and reference to "a precursor" includes reference to one or more precursors and equivalents thereof known to those of ordinary skill in the art, and so on.

此外,在本說明書及以下請求項中使用詞語「包含」、「所包含」、「含有」、「所含有」、「包括」、及「所包括」時,意欲在指定所述特徵、整體、部件、或操作的存在,但是不排除一或更多個其他特徵、整體、部件、操作、動作、或群組的存在或附加。In addition, when the words "comprises", "includes", "includes", "includes", and "includes" are used in this specification and the claims below, they are intended to be The presence of a component, or an operation, does not preclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

10‧‧‧裝載閘腔室15‧‧‧隔離閥20‧‧‧處理腔室30‧‧‧氣體分配板60‧‧‧基板61‧‧‧第一表面65‧‧‧梭子70‧‧‧軌道90‧‧‧輻射熱源100‧‧‧處理系統102‧‧‧前開式晶圓盒104‧‧‧機器臂106‧‧‧托持區域108a‧‧‧處理腔室108b‧‧‧處理腔室108c‧‧‧處理腔室108d‧‧‧處理腔室108e‧‧‧處理腔室108f‧‧‧處理腔室109a‧‧‧串聯區段109b‧‧‧串聯區段109c‧‧‧串聯區段110‧‧‧第二機器臂200‧‧‧腔室201‧‧‧RPS單元203‧‧‧冷卻板205‧‧‧氣體入口組件210‧‧‧流體供應系統214‧‧‧上板215‧‧‧第一電漿區域216‧‧‧下板217‧‧‧面板218‧‧‧容積219‧‧‧第一流體通道220‧‧‧絕緣環221‧‧‧第二流體通道223‧‧‧離子抑制器225‧‧‧噴淋頭233‧‧‧基板處理區域240‧‧‧功率供應器253‧‧‧詳細視圖255‧‧‧基板258‧‧‧氣體供應區域259‧‧‧孔隙265‧‧‧台座325‧‧‧噴淋頭365‧‧‧通孔375‧‧‧小孔洞400‧‧‧腔室420‧‧‧注射器425‧‧‧氣體埠430‧‧‧注射器435‧‧‧氣體埠440‧‧‧注射器445‧‧‧氣體埠450‧‧‧泵送系統455‧‧‧真空埠460‧‧‧分區498‧‧‧箭頭500‧‧‧方法505‧‧‧操作510‧‧‧操作515‧‧‧操作600‧‧‧基板605‧‧‧第二介電材料610‧‧‧含矽材料615‧‧‧第一介電材料10‧‧‧loading lock chamber 15‧‧‧isolating valve 20‧‧‧processing chamber 30‧‧‧gas distribution plate 60‧‧‧substrate 61‧‧‧first surface 65‧‧‧shuttle 70‧‧‧track 90‧‧‧radiant heat source 100‧‧‧processing system 102‧‧‧front opening cassette 104‧‧‧robotic arm 106‧‧‧holding area 108a‧‧‧processing chamber 108b‧‧‧processing chamber 108c‧ ‧‧processing chamber 108d‧‧‧processing chamber 108e‧‧‧processing chamber 108f‧‧‧processing chamber 109a‧‧‧serial section 109b‧‧‧serial section 109c‧‧serial section 110‧‧ ‧Second robot arm 200‧‧‧chamber 201‧‧‧RPS unit 203‧‧‧cooling plate 205‧‧‧gas inlet assembly 210‧‧‧fluid supply system 214‧‧‧upper plate 215‧‧‧first electric Slurry area 216‧‧‧lower plate 217‧‧‧panel 218‧‧‧volume 219‧‧‧first fluid channel 220‧‧‧insulating ring 221‧‧‧second fluid channel 223‧‧‧ion suppressor 225‧‧ ‧Shower head 233‧‧‧substrate processing area 240‧‧‧power supply 253‧‧‧detail view 255‧‧‧substrate 258‧‧‧gas supply area 259‧‧‧pore 265‧‧‧pedestal 325‧‧‧ Sprinkler 365‧‧‧through hole 375‧‧‧small hole 400‧‧‧chamber 420‧‧‧syringe 425‧‧‧gas port 430‧‧‧syringe 435‧‧‧gas port 440‧‧‧syringe 445‧​‧substrate 605‧‧‧second dielectric material 610‧‧‧silicon-containing material 615‧‧‧first dielectric material

可以藉由參照說明書及圖式的其餘部分來實現所揭示的技術的本質及優點的進一步理解。 A further understanding of the nature and advantages of the disclosed technology may be realized by referring to the remaining portions of the specification and drawings.

第1圖圖示根據本技術的實施例的示例性處理系統的頂視平面圖。 Figure 1 illustrates a top plan view of an exemplary processing system in accordance with an embodiment of the present technology.

第2A圖圖示根據本技術的實施例的示例性處理腔室的示意性橫截面圖。 Figure 2A illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with embodiments of the present technology.

第2B圖圖示根據本技術的實施例的示例性面板的詳細視圖。 Figure 2B illustrates a detailed view of an exemplary panel in accordance with an embodiment of the present technology.

第3圖圖示根據本技術的實施例的示例性噴淋頭的底視平面圖。 Figure 3 illustrates a bottom plan view of an exemplary showerhead in accordance with an embodiment of the present technology.

第4圖圖示根據本技術的實施例的示例性處理腔室的示意性橫截面圖。 Figure 4 illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with embodiments of the present technology.

第5圖圖示根據本技術的實施例的形成半導體結構的方法中的所選擇操作。 Figure 5 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

第6A圖至第6C圖圖示根據本技術的實施例的示例性基板的示意性橫截面圖。 6A-6C illustrate schematic cross-sectional views of exemplary substrates in accordance with embodiments of the present technology.

圖式中的幾個係包括作為示意圖。應理解,圖式僅用於說明目的,而除非特別聲明具有標度,否則不應視為比例。此外,作為示意圖,圖式係提供為幫助理解,並且可能不包括相較於實際表示的所有態樣或資訊,並且可能包括用於說明目的之誇大材料。 Several lines in the figures are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes only and should not be considered to scale unless scales are specifically stated. In addition, as schematic diagrams, drawings are provided to aid in understanding and may not include all aspects or information compared to actual representations, and may include exaggerated material for illustrative purposes.

在隨附圖式中,類似的部件及/或特徵可以具有相同的元件符號。此外,相同類型的各種部件可以藉由在元件符號後利用字母來區分,以區分類似部件。若在說明書中僅使用最前面的元件符號,則該描述適用於具有相同最前面的元件符號的任何一個類似部件,而與字母無關。In the accompanying drawings, similar components and/or features may have the same reference number. In addition, various components of the same type can be distinguished by using a letter after the element number to distinguish similar components. If only the first element number is used in the specification, the description is applicable to any one of the similar parts with the same first element number, regardless of the letter.

國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無Domestic deposit information (please note in order of depositor, date, and number) None

國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無Overseas storage information (please note in order of storage country, institution, date, number) None

500‧‧‧方法 500‧‧‧method

505‧‧‧操作 505‧‧‧Operation

510‧‧‧操作 510‧‧‧Operation

515‧‧‧操作 515‧‧‧Operation

Claims (19)

一種形成一半導體結構的方法,該方法包含以下步驟:將一改性電漿施加至具有一第二介電材料的一表面之一半導體基板,其中一矽元件形成於該表面上,其中該矽元件具有側壁及一頂表面,且其中該改性電漿使得該第二介電材料的該表面及該矽元件的該頂表面鈍化;相對於該第二介電材料的該表面及該矽元件的該頂表面,將含有碳之一第一介電材料選擇性沉積在該矽元件的該等側壁上;以及接著藉由使用具有大於或約25:1之一H:F原子流量比之電漿流出物從該半導體基板選擇性蝕刻該矽元件。 A method of forming a semiconductor structure, the method comprising the steps of: applying a modifying plasma to a semiconductor substrate having a surface of a second dielectric material, wherein a silicon element is formed on the surface, wherein the silicon a device having sidewalls and a top surface, and wherein the modifying plasma passivates the surface of the second dielectric material and the top surface of the silicon device; relative to the surface of the second dielectric material and the silicon device A first dielectric material containing carbon is selectively deposited on the sidewalls of the silicon element on the top surface of the silicon element; The slurry effluent selectively etches the silicon device from the semiconductor substrate. 如請求項1所述之形成一半導體結構的方法,其中該第一介電材料包含氮化矽。 The method of forming a semiconductor structure as claimed in claim 1, wherein the first dielectric material comprises silicon nitride. 如請求項1所述之形成一半導體結構的方法,其中該選擇性沉積步驟包含一原子層沉積處理。 The method of forming a semiconductor structure as claimed in claim 1, wherein the selective deposition step comprises an atomic layer deposition process. 如請求項1所述之形成一半導體結構的方法,其中該第二介電材料包含氧化矽。 The method of forming a semiconductor structure as claimed in claim 1, wherein the second dielectric material comprises silicon oxide. 如請求項1所述之形成一半導體結構的方法,進一步包含以下步驟:圍繞該矽元件使該第一介電材料選擇性凹陷。 The method of forming a semiconductor structure as claimed in claim 1, further comprising the step of: selectively recessing the first dielectric material around the silicon device. 如請求項5所述之形成一半導體結構的方法, 其中該凹陷步驟相對於該第二介電材料移除該第一介電材料的一頂部部分。 The method for forming a semiconductor structure as claimed in item 5, Wherein the recessing step removes a top portion of the first dielectric material relative to the second dielectric material. 如請求項1所述之形成一半導體結構的方法,其中以對該第一介電材料大於或約20:1的一選擇性執行選擇性蝕刻該矽元件之步驟。 The method of forming a semiconductor structure as recited in claim 1, wherein the step of selectively etching the silicon element is performed with a selectivity to the first dielectric material greater than or about 20:1. 如請求項7所述之形成一半導體結構的方法,其中以對該第二介電材料大於或約100:1的一選擇性執行選擇性蝕刻該矽元件之步驟。 The method of forming a semiconductor structure as recited in claim 7, wherein the step of selectively etching the silicon element is performed with a selectivity to the second dielectric material greater than or about 100:1. 如請求項1所述之形成一半導體結構的方法,其中以對該矽元件,相對於該第二介電材料,大於或約2:1的一選擇性執行該第一介電材料沉積。 The method of forming a semiconductor structure as recited in claim 1, wherein the deposition of the first dielectric material is performed with a selectivity of greater than or about 2:1 relative to the second dielectric material to the silicon element. 如請求項1所述之形成一半導體結構的方法,其中該第一介電材料包含以小於20nm的一寬度為特徵之一間隔物。 The method of forming a semiconductor structure of claim 1, wherein the first dielectric material comprises spacers characterized by a width of less than 20 nm. 一種形成一半導體結構的方法,該方法包含以下步驟:將一改性電漿施加至具有一介電材料的一表面之一半導體基板,其中一含矽元件形成於該表面上,其中該含矽元件具有側壁及一頂表面,且其中該改性電漿使得該介電材料的該表面及該含矽元件的該頂表面鈍化;相對於該介電材料的該表面及該含矽元件的該頂表面,將一含氧及碳材料選擇性沉積在該含矽元件的該等側壁上; 從該含矽元件選擇性蝕刻該含氧及碳材料;以及接著藉由使用具有大於或約25:1之一H:F原子流量比之電漿流出物從該半導體基板選擇性蝕刻該含矽元件。 A method of forming a semiconductor structure, the method comprising the steps of: applying a modified plasma to a semiconductor substrate having a surface of a dielectric material, wherein a silicon-containing element is formed on the surface, wherein the silicon-containing An element has sidewalls and a top surface, and wherein the modifying plasma passivates the surface of the dielectric material and the top surface of the silicon-containing element; relative to the surface of the dielectric material and the silicon-containing element top surface, an oxygen and carbon containing material is selectively deposited on the sidewalls of the silicon containing element; selectively etching the oxygen and carbon-containing material from the silicon-containing device; and then selectively etching the silicon-containing material from the semiconductor substrate by using a plasma effluent having a H:F atomic flow ratio of greater than or about 25:1 element. 如請求項11所述之形成一半導體結構的方法,進一步包含以下步驟:將該含矽元件的一表面暴露於一抑制劑,其中該抑制劑減少該含矽元件的該表面上之該含氧及碳材料的形成。 The method of forming a semiconductor structure as claimed in claim 11, further comprising the step of: exposing a surface of the silicon-containing element to an inhibitor, wherein the inhibitor reduces the oxygen content on the surface of the silicon-containing element and the formation of carbon materials. 如請求項11所述之形成一半導體結構的方法,其中該介電層包含氧化矽或氮化矽。 The method of forming a semiconductor structure as claimed in claim 11, wherein the dielectric layer comprises silicon oxide or silicon nitride. 如請求項11所述之形成一半導體結構的方法,進一步包含以下步驟:圍繞該含矽元件使該含氧及碳材料選擇性凹陷。 The method of forming a semiconductor structure as claimed in claim 11, further comprising the step of: selectively recessing the oxygen and carbon containing material around the silicon containing device. 如請求項14所述之形成一半導體結構的方法,其中該凹陷步驟相對於該介電層移除該含氧及碳材料的一頂部部分。 The method of forming a semiconductor structure as recited in claim 14, wherein the recessing step removes a top portion of the oxygen and carbon containing material relative to the dielectric layer. 如請求項11所述之形成一半導體結構的方法,其中以對該含氧及碳材料大於或約100:1的一選擇性執行選擇性蝕刻該含矽元件之步驟。 The method of forming a semiconductor structure as recited in claim 11, wherein the step of selectively etching the silicon-containing element is performed with a selectivity to the oxygen- and carbon-containing material of greater than or about 100:1. 如請求項16所述之形成一半導體結構的方法,其中以對該介電層大於或約100:1的一選擇性執行選擇性蝕刻該含矽元件之步驟。 The method of forming a semiconductor structure as recited in claim 16, wherein the step of selectively etching the silicon-containing device is performed with a selectivity to the dielectric layer of greater than or about 100:1. 如請求項11所述之形成一半導體結構的 方法,其中以對該含矽元件,相對於該介電層,大於或約2:1的一選擇性執行該含氧及碳材料沉積。 Forming a semiconductor structure as described in Claim 11 The method wherein the deposition of the oxygen and carbon containing material is performed with a selectivity of greater than or about 2:1 to the silicon containing device relative to the dielectric layer. 如請求項11所述之形成一半導體結構的方法,其中該含氧及碳材料包含以小於20nm的一寬度為特徵之一間隔物。 The method of forming a semiconductor structure as recited in claim 11, wherein the oxygen and carbon containing material comprises spacers characterized by a width of less than 20 nm.
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