TW201903841A - Methods and structures to reduce contact resistance for finfet devices - Google Patents

Abstract

Processing methods may be performed to form semiconductor structures that may include structures to reduce contact resistance. The methods may include depositing a first semiconductor material on a semiconductor substrate. The first semiconductor material may be selectively deposited on a first silicon-containing material relative to a second silicon-containing material. The methods may also include depositing a second semiconductor material on the semiconductor substrate. The second semiconductor material may be selectively deposited on the second silicon-containing material relative to the first semiconductor material.

Description

Method and structure for reducing contact resistance of fin field effect transistor device

This technology relates to semiconductor systems, processing, and equipment. More specifically, the present technology relates to systems and methods for selectively forming a layer of material on a semiconductor device.

It is possible to fabricate an integrated circuit by processing a layer of intricately patterned material on the surface of the substrate. Producing a patterned material on a substrate requires a control method for removing the exposed material. Chemical etching is used for a variety of purposes, including transferring the pattern in the photoresist into the underlying layer, thinning the layer, or the thinned lateral dimension of features already present on the surface. It is generally desirable to have an etching process that etches one material faster than the other to facilitate, for example, pattern transfer processing or separate material removal. This etching process is said to be selective for the first material. Due to the variety of materials, circuits, and processes, etching processes have been developed that are selective for a variety of materials. However, the deposition process is typically performed using a blanket coating or conformal fill to continue across the substrate.

As device sizes continue to shrink in next-generation devices, selectivity can play a greater role when the material formed in a particular layer is only a few nanometers (especially when the material is critical in the formation of the transistor). Many different etch processing options have been developed between various materials, but standard selectivity may no longer be applicable to current and future device sizes. Moreover, based on the number of masking, forming, and removing operations required to form and protect the various critical dimensions of the features across the device, the processing time continues to increase while patterning and formation is performed elsewhere on the substrate.

Therefore, there is a need for a system and method that can be used to produce high quality devices and structural improvements. This technology addresses these and other needs.

A processing method can be performed to form a semiconductor structure that can include a structure that reduces contact resistance. The method can include the step of depositing a first semiconductor material on a semiconductor substrate. The first semiconductor material can be selectively deposited on the first ruthenium-containing material relative to the second ruthenium-containing material. The methods can also include the step of depositing a second semiconductor material on the semiconductor substrate. The second semiconductor material can be selectively deposited on the second ruthenium containing material relative to the first semiconductor material.

In some embodiments, the first semiconductor material can be deposited on the PMOS region of the semiconductor substrate relative to the NMOS region of the semiconductor substrate. The first semiconductor material may include germanium, and the first germanium-containing material may include germanium germanium. The second cerium-containing material may include phosphorus. The method can be performed without performing a reactive ion etching operation. The deposition of the first semiconductor material can be performed using a selectivity of the first ruthenium containing material greater than or about 2: 1 relative to the second ruthenium containing material. The deposition may occur on the NMOS region of the semiconductor substrate relative to the PMOS region of the semiconductor substrate. This method can be performed without forming a photoresist on the PMOS region. The first semiconductor material may include indium, and the first germanium-containing material may include germanium phosphide. The second cerium-containing material may include cerium. The first semiconductor material can be indium gallium arsenide or include indium gallium arsenide.

Additionally, the present technology also includes a method of forming a semiconductor structure. The method can include the step of depositing a first alloy material on the first semiconductor material. The alloy material can be selectively deposited on the first semiconductor material relative to the nitride material or oxide material. The method can also include the step of subsequently depositing a second alloy material on the second semiconductor material. The second alloy material can be selectively deposited on the second semiconductor material relative to the nitride material or oxide material.

In some embodiments, the first alloy material can be deposited on the indium containing material located in the NMOS region of the semiconductor substrate. The second alloy material may be deposited on the ruthenium containing material in the PMOS region of the semiconductor substrate. The nitride material may include tantalum nitride, and the oxide material may include tantalum oxide, tantalum carbonoxide, or a metal oxide. The metal oxide may be tungsten oxide or aluminum oxide or include tungsten oxide or aluminum oxide. The method can be performed without performing a reactive ion etching operation. The second alloy material may be a nickel-containing material or include a nickel-containing material. The second alloy material may be nickel ruthenium or nickel ruthenium. The first alloy material may be a titanium-containing material or include a titanium-containing material. The first alloy material may be titanium niobium nitride or include titanium niobium nitride.

Such techniques can provide many benefits over conventional systems and techniques. For example, processing can protect critical dimensions and provide improved selectivity by utilizing techniques that do not include reactive ion etching. In addition, by performing selective operations, fewer masking and removal operations can be performed, which can significantly reduce manufacturing queue time. These and other embodiments, as well as many of its advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

The techniques of the present invention include systems and components for semiconductor processing of small pitch features. In the conventional deuteration process, the PMOS region and the NMOS region can be blocked by the photoresist while other regions are processed. For example, because several materials spanning the substrate can be formed from similar materials (eg, tantalum nitride or tantalum oxide), etching processes for removing these materials and removing materials formed within the regions may not provide Sufficient selectivity relative to other key features. During various open processes, the size of multiple critical dimensions may cause load effects, while etching exceeds the budget availability of materials. For example, conventional processing can include a masking layer followed by a reactive ion etching ("RIE") process that allows openings in the structure of the gap-filling layer. Although the RIE etch is a relatively anisotropic process, the RIE etch may still have selectivity for sidewall loss. Although it may be considered to budget for this loss during formation (eg, with over-formation of materials), because the regions within the etched structure have different sizes, the calculation of the amount of loss for one region may not be suitable for larger The amount of loss in the area. Thus, although a 5 nm loss may occur in one section of the budget, a loss of a larger section of 6-7 nm may still occur, resulting in a mismatch during manufacturing.

In addition, the RIE process produces etch byproducts or polymer residues (usually removed using a wet etch process). This wet etch often over-etches the sidewall protection layer beyond the critical dimension (which causes problems with the formation and spacing of adjacent transistor layers) and further etches the low-k nitride spacers and the interlayer dielectric oxide. In addition, the removal of metallic materials and dielectrics is typically performed using an anisotropic etch, and unless additional masks or protective layers are formed, it is possible to further reduce the exposed areas of the capping material and spacer material in other regions. Since the selectivity of such RIE removal may be in the range of 10:1, the amount of masking required may be large.

The deposition of both the masking material and other layers of material can be performed in conventional techniques that utilize the blanket coating or conformalization of materials across all exposed areas of the semiconductor substrate. These types of deposition may require further patterning and removal operations, which can significantly increase the queue time of device fabrication. Between the additional operations and defects of the RIE removal and the various operations used in conventional deposition, the stacking time of the individual device layers may increase by several hours.

The present technology overcomes these problems by modifying the processing for removal and formation. Reduced masking, patterning, and removal can be utilized in structure formation by performing selective deposition operations in specific equipment. In addition, it is also possible to selectively perform a removal operation that can be performed. By using selective deposition and using alternative etching to remove many of the patterning operations, such processing can save hours compared to conventional processing using RIE and standard deposition.

While the remainder of the disclosure will routinely identify particular etching and deposition processes utilizing the disclosed techniques, it should be understood that the systems and methods are equally applicable to various other etching, deposition, and cleaning processes that may occur in the described chambers. . Therefore, the technique should not be considered limited to the etching and deposition processes that can be used only. The present disclosure will discuss one possible system and chamber that can be used with the present technology to perform certain removal and deposition operations prior to the described operations of the exemplary processing sequences in accordance with the present technology.

A top plan view of FIG. 1 illustrates a first embodiment in accordance with one embodiment of the processing system embodiment of deposition, etching, baking, and curing chamber 100. In the drawings, a pair of front open pods (FOUPs) 102 are supplied with substrates of various sizes, which are received by robotic arms 104 and placed in a substrate processing chamber located in series sections 109a-c. Prior to one of 108a-f, it is placed into the low pressure holding area 106. The second robotic arm 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. In addition to cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etching, pre-cleaning, degassing, orientation, and other substrate processing, Each of the substrate processing chambers 108a-f can be provided to perform a number of substrate processing operations including dry etching processes and selective deposition as described herein.

The substrate processing chambers 108a-f can include one or more system components for depositing, annealing, curing, and/or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers (eg, 108c-d and 108e-f) can be used to deposit a dielectric material or metal-containing material on the substrate, while a third pair of processing chambers (eg, 108a-b) It can be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (eg, 108a-f) can be configured to etch a dielectric film on the substrate. Any one or more of the processes described may be performed in a chamber separate from the manufacturing system shown in the different embodiments.

In some embodiments, the chamber specifically includes at least one etch chamber as described below and at least one deposition chamber as described below. All of the etching and deposition processes described below can be performed in a controlled environment by including the chambers and combining the processing sides of the factory interface. For example, the vacuum environment can be maintained on the processing side of the holding area 106 such that all of the chambers and transfers in the embodiment are maintained under vacuum. This also limits the contact of water vapor and other air components with the substrate being processed. It should be understood that system 100 can take into account additional configurations for deposition, etching, annealing, and curing of dielectric films.

Figure 2A illustrates a plasma generator having a separated cross-sectional view of an exemplary process chamber system 200 in the processing region of the chamber. During the film etching (for example, titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, tantalum, polycrystalline germanium, antimony oxide, antimony nitride, antimony oxynitride, antimony oxyhydroxide, etc.), the processing gas can be passed through The gas inlet assembly 205 flows into the first plasma region 215. A remote plasma system (RPS) 201 can optionally be included in the system and can process the first gas that subsequently travels through the gas inlet assembly 205. The inlet assembly 205 can include two or more different gas supply passages, wherein if a second passage (not shown) is included, the second passage can bypass the RPS 201.

A cooling plate 203, a panel 217, an ion eliminator 223, a showerhead 225, and a substrate support 265 having a substrate 255 disposed thereon are illustrated, and each may be included in accordance with an embodiment. The pedestal 265 can have a heat exchange channel through which the heat exchange fluid flows to control the temperature of the substrate, and the temperature of the substrate can be manipulated during processing operations to heat and/or cool the substrate or wafer. It is also possible to use an embedded resistive heater element while resistively heating a wafer support disk of pedestal 265 comprising aluminum, ceramic, or a combination thereof to achieve relatively high temperatures, for example from up to or about 100 ° C to above or about 1100 ° C. .

Panel 217 may be pyramidal, conical, or other similar structure having a narrow top portion that extends to a wide bottom portion. Additionally, panel 217 may be flat and include a plurality of through passages for dispensing process gases, as shown. Depending on the use of the RPS 201, the plasma generating gas and/or the plasma exciting material may pass through a plurality of holes in the panel 217 as shown in FIG. 2B for more uniform delivery into the first plasma region 215.

An exemplary configuration may include the gas inlet assembly 205 passing into a gas supply region 258 separated by a panel 217 from the first plasma region 215 such that gas/substance flows through the holes in the panel 217 into the first plasma region 215. Structural and operational features may be selected to prevent large amounts of plasma from the first plasma region 215 from flowing back into the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The insulating ring 220 between the features is shown with the panel 217, or the electrically conductive top portion of the chamber, and the showerhead 225 to allow an AC potential to be applied to the panel relative to the showerhead 225 and/or the ion eliminator 223. 217. Insulation ring 220 can be positioned between panel 217 and showerhead 225 and/or ion eliminator 223 to allow capacitive coupling plasma (CCP) to be formed in the first plasma region. Additionally, a baffle (not shown) may be located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid into the region via the gas inlet assembly 205.

Ion eliminator 223 can include a plate or other geometry defining a plurality of pores throughout the structure, the plurality of pores being configured to eliminate migration of ionically charged species exiting first plasma region 215 while allowing uncharged neutrality Or the radical species pass through the ion eliminator 223 into the active gas delivery zone between the eliminator and the showerhead. In an embodiment, the ion eliminator 223 can comprise a multiwell plate having various pore configurations. These uncharged species can include highly active materials that are transported through the pores using less active gas carriers. As noted above, migration of ionic species through the pores may be reduced and, in some cases, completely eliminated. Controlling the amount of ionic species passing through the ion eliminator 223 can advantageously provide increased control of the gas mixture in contact with the underlying wafer substrate, which in turn can increase control of deposition and/or etch characteristics of the gas mixture. For example, the adjustment of the ion concentration of the gas mixture can significantly change its etch selectivity, for example, SiNx: SiOx etch rate, Si: SiOx etch rate, and the like. In an alternative embodiment of performing deposition, the balance of conformal flow deposition of the dielectric material can also be altered.

The plurality of apertures in ion eliminator 223 can be configured to control the passage of reactive gases (ie, ions, free radicals, and/or neutral species) via ion eliminator 223. For example, the aspect ratio of the holes, or the diameter of the holes to the length, and/or the geometry of the holes can be controlled such that the flow of ionically charged species in the reactive gas passing through the ion eliminator 223 is reduced. The holes in the ion eliminator 223 may include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The cylindrical portion can be shaped and sized to control the flow of ionic species to the showerhead 225. An adjustable electrical bias can also be applied to the ion eliminator 223 as an additional means of controlling the flow of ionic species through the eliminator.

Ion eliminator 223 can be used to reduce or eliminate the amount of ionically charged species traveling from the plasma generating region to the substrate. Uncharged neutral and free radical species can still pass through the openings in the ion eliminator to react with the substrate. It should be noted that in an embodiment, complete elimination of the ionically charged species in the reaction zone surrounding the substrate may not be performed. In some cases, the ionic species are intended to reach the substrate to perform an etching and/or deposition process. In these cases, the ion eliminator can help control the concentration of ionic species in the reaction zone at a level that facilitates processing.

The showerhead 225 in combination with the ion eliminator 223 can allow plasma present in the first plasma region 215 to avoid direct excitation of gas in the substrate processing region 233 while still allowing the excited species to travel from the chamber plasma region 215. Go to substrate processing area 233. In this manner, the chamber can be configured to prevent plasma from contacting the substrate 255 in the etch. This can advantageously protect the various complex structures and films patterned on the substrate, and various complex structures and films can be damaged, displaced, or otherwise bent if directly in contact with the plasma produced. Furthermore, the rate at which the oxide species is etched may be increased when the plasma is allowed to contact the substrate or near the substrate level. Thus, if the exposed area of the material is an oxide, the material can be further protected by maintaining the plasma away from the substrate.

The processing system can further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the panel 217, the ion eliminator 223, the showerhead 225, and/or the pedestal 265 to be in the first plasma region 215 or Plasma is generated in the treatment zone 233. Depending on the processing performed, the power supply can be configured to deliver an adjustable amount of power to the chamber. This configuration can allow tunable plasma for processing in execution. Unlike a remote plasma unit that is typically presented with an on or off function, the tunable plasma can be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow for the formation of specific plasma characteristics such that the precursors may be dissociated in a particular manner to enhance the etch profile created by these precursors.

The plasma may be excited in the chamber plasma region 215 above the showerhead 225 or the substrate processing region 233 below the showerhead 225. In an embodiment, the plasma formed in the substrate processing region 233 may be a DC bias plasma formed using a pedestal as an electrode. A plasma may be present in the chamber plasma region 215 to produce a free radical precursor from the influx of, for example, a fluorine-containing precursor or other precursor. Typically, an AC voltage in the radio frequency (RF) range can be applied between the conductive top portion of the processing chamber (eg, panel 217) and the showerhead 225 and/or ion eliminator 223 to excite the cavity during deposition. The plasma in the chamber plasma region 215. The RF power supply can produce a high RF frequency of 13.56 MHz, but other frequencies can be generated separately or combined with the 13.56 MHz frequency to produce other frequencies.

FIG . 2B illustrates a detailed view 253 of features affecting the distribution of process gases through panel 217. As shown in FIGS. 2A and 2B, panel 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas supply region 258 in which process gas can be delivered from gas inlet 205 into gas supply region 258. The gas may fill the gas supply region 258 and flow to the first plasma region 215 via the apertures 259 in the panel 217. The apertures 259 can be configured to direct flow in a substantially unidirectional manner such that process gases can flow into the processing region 233, but can be partially or completely prevented from flowing back into the gas supply region 258 after passing through the panel 217.

The gas distribution assembly (e.g., showerhead 225 for processing chamber section 200) may be referred to as a dual channel showerhead (DCSH) and is additionally illustrated in detail in the embodiment illustrated in FIG. The dual channel showerhead can provide an etch process to allow separation of the etchant outside of the processing region 233 to provide limited interaction with the chamber components and each other prior to delivery to the processing region.

The showerhead 225 can include an upper plate 214 and a lower plate 216. These plates can be coupled to each other to define a volume 218 between the plates. The coupling of the plates can provide a first fluid passage 219 through the upper and lower plates and a second fluid passage 221 through the lower plate 216. The formed passageway can be configured to provide a fluid inlet and outlet from the volume 218 alone through the second fluid passage 221 through the lower plate 216, while the first fluid passage 219 can be fluidly isolated from the volume 218 between the plate and the second fluid passage 221. . The volume 218 can be fluidized in and out via one side of the gas distribution assembly 225.

FIG. 3 is a system for use with a shower head in accordance with an embodiment of the processing chamber 325 bottom view. The showerhead 325 can correspond to the showerhead 225 shown in FIG. 2A. The through holes 365 (the view of the first fluid passage 219 are illustrated) may have a plurality of shapes and configurations to control and influence the flow of the precursor through the showerhead 225. A small aperture 375 (shown as a view of the second fluid passage 221) can be distributed substantially evenly over the surface of the showerhead (even in the through hole 365) and can help the precursor provide a ratio when exiting the showerhead. Other configurations are more evenly mixed.

Turning to FIG . 4 , a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology is illustrated. System 400 can include a load lock chamber 10 and a processing chamber 20. The processing chamber 20 can generally be a sealable outer casing that can be operated under vacuum or at least low pressure. The processing chamber 20 can be isolated from the load lock chamber 10 by an isolation valve 15. The isolation valve 15 can seal the process chamber 20 and the load lock chamber 10 in a closed position and can allow the substrate 60 to be transferred from the load lock chamber 10 to the process chamber 20 in the open position, and vice versa.

System 400 can include a gas distribution plate 30 that can dispense one or more gases across substrate 60. The gas distribution plate 30 can be any suitable distribution plate known to those skilled in the art, and the particular gas distribution plate should not be considered to limit the scope of the present technology. The output face of the gas distribution plate 30 may face the first surface 61 of the substrate 60.

The gas distribution plate 30 can include a plurality of gas crucibles and a plurality of vacuum crucibles, the plurality of gas crucibles configured to deliver one or more gas streams to the substrate 60, and a plurality of vacuum crucibles disposed between each gas crucible, And configured to deliver a flow of gas out of the processing chamber 20. As shown in FIG. 4, the gas distribution plate 30 can include a first precursor injector 420, a second precursor injector 430, and a purge gas injector 440. The injectors 420, 430, 440 can be controlled by a system computer (not shown) (e.g., a host) or by a chamber specific controller (e.g., a programmable logic controller). The precursor injector 420 can be configured to inject continuous or pulsed flow of the active precursor of Compound A into the processing chamber 20 via a plurality of gas helium 425. The precursor injector 430 can be configured to inject continuous or pulsed flow of the active precursor of Compound B into the processing chamber 20 via a plurality of gas helium 435. The purge gas injector 440 can be configured to inject continuous or pulsed flow of inactive or purge gas into the processing chamber 20 via a plurality of gas ports 445. The purge gas can be configured to remove active material and active byproducts from the processing chamber 20. The purge gas is typically an inert gas such as nitrogen, argon, and helium. A gas crucible 445 may be disposed between the gas crucible 425 and the gas crucible 435 to separate the precursor of the compound A from the precursor of the compound B, thereby avoiding cross-contamination between the precursors.

In another aspect, a distal plasma source (not shown) can be coupled to the precursor injector 420 and the precursor injector 430 prior to injecting the precursor into the processing chamber 20. The plasma of the active material can be produced by applying an electric field to the compound in the remote plasma source. Any power source capable of activating the intended compound can be used. For example, power sources using DC, RF, and microwave-type discharge techniques can be used. If an RF power source is used, the RF power source can be coupled capacitively or inductively. Activation can also be produced by thermal basic techniques, gas dissociation techniques, high intensity light sources (eg, ultraviolet light sources), or exposure to x-ray sources.

System 400 can further include a pumping system 450 coupled to processing chamber 20. The pumping system 450 can be generally configured to evacuate a gas stream out of the processing chamber 20 via one or more vacuum ports 455. A vacuum crucible 455 can be disposed between each gas crucible to evacuate the gas stream out of the processing chamber 20 after the gas stream reacts with the substrate surface and further limit cross-contamination between the precursors.

System 400 can include a plurality of partitions 460 disposed on processing chamber 20 and between each turn. The lower portion of each partition may extend proximate to the first surface 61 of the substrate 60 (eg, about 0.5 mm or more from the first surface 61). In this manner, the lower portion of the partition 460 can be separated from the surface of the substrate by a distance sufficient to allow the flow of gas to flow around the lower portion toward the vacuum crucible 455 after the gas stream reacts with the surface of the substrate. Arrow 498 indicates the direction of the gas flow. Since partition 460 is operable as a physical barrier to gas flow, partition 460 can also limit cross-contamination between precursors. The configurations shown are for illustrative purposes only and are not to be considered as limiting the scope of the technology. Those of ordinary skill in the art will appreciate that the gas distribution system shown is only one possible distribution system and that other types of showerheads can be employed.

In operation, the substrate 60 (e.g., by a robot) can be delivered to the load lock chamber 10 and can be placed on the transport shuttle 65. After the isolation valve 15 is opened, the transport shuttle 65 can move along the rail 70. Once the transfer shuttle 65 enters the processing chamber 20, the isolation valve 15 can be closed to seal the processing chamber 20. The handling shuttle 65 can then be moved through the processing chamber 20 for processing. In one embodiment, the handling shuttle 65 can move through the chamber in a linear path.

As the substrate 60 moves through the processing chamber 20, the first surface 61 of the substrate 60 can be repeatedly exposed to the precursor of the compound A from the gas crucible 425 and the precursor of the compound B from the gas crucible 435 with gas from the gas 445 purge gas. The injection of the purge gas can be designed to remove unreacted material from the previous precursor prior to exposing the substrate surface 61 to the next precursor. After each exposure to various gas streams, the gas stream can be evacuated by pumping system 450 via vacuum crucible 455. Since a vacuum crucible can be placed on either side of each gas crucible, the gas flow can be evacuated via vacuum crucibles 455 on both sides. Thus, the gas flow can flow vertically downward from the individual gas helium toward the first surface 61 of the substrate 60, across the first surface 410 and around the lower portion of the partition 460, and finally upward toward the vacuum crucible 455. In this way, each gas can be evenly distributed across the substrate surface 61. The substrate 60 can also be rotated while exposed to various gas streams. Rotation of the substrate can be useful to prevent strip formation in the formed layer. The rotation of the substrate can be a continuous or separate step.

The extent to which the substrate surface 61 is exposed to each gas can be determined by, for example, the flow rate of each gas from the gas and the rate of movement of the substrate 60. In one embodiment, the flow rate of each gas can be configured without removing the absorbed precursor from the substrate surface 61. The width between each partition, the number of gas imperfections disposed on the processing chamber 20, and the number of times the substrate may be transferred back and forth may also determine the extent to which the substrate surface 61 is exposed to various gases. Therefore, the quantity and quality of the deposited film can be optimized by changing the above factors.

In another embodiment, system 400 can include precursor injector 420 and precursor injector 430 without purge gas injector 440. Thus, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 can be alternately exposed to the precursor of Compound A and the precursor of Compound B without being exposed to the purge gas therebetween.

The embodiment shown in Figure 4 has a gas distribution plate 30 above the substrate. While the embodiments have been described and illustrated with respect to this upright orientation, it should be understood that the opposite orientation is also possible. In that case, the first surface 61 of the substrate 60 may face downward, and the gas flowing toward the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 can be positioned to heat the second side of the substrate.

In some embodiments, the transport shuttle 65 can be a base 66 for carrying the substrate 60. Generally, the pedestal 66 can be a carrier that helps to form a uniform temperature across the substrate. The pedestal 66 can be moved in both left-to-right and right-to-left directions between the load lock chamber 10 and the process chamber 20 with respect to the arrangement of FIG. The pedestal 66 can have a top surface 67 for carrying the substrate 60. The pedestal 66 can be a heated pedestal such that the substrate 60 can be heated for processing. As an example, the pedestal 66 can be heated by a radiant heat source 90 disposed below the susceptor 66, a heater plate, a resistive coil, or other heating device. Although illustrated as a lateral transition, embodiments of system 400 can also be used in a rotary system in which the wheels can be rotated clockwise or counterclockwise to continuously process one or more substrates underneath the gas distribution system shown. It should be similarly understood that additional modifications are included in the present technology.

FIG . 5 illustrates a method 500 of forming a semiconductor structure in which a number of operations can be performed, for example, in the aforementioned chambers 200 and 400. The method can include an aspect of epitaxial growth on the NMOS and PMOS regions of the substrate. Method 500 can include one or more operations prior to initiating the method, including front end processing, deposition, etching, grinding, cleaning, or any other operation that can be performed prior to the operation. The method may include a plurality of selectable operations that may or may not be specifically associated with the method in accordance with the present technology. For example, many operations are described in order to provide a broader range of structure formation, but are not critical to the technology, or may be performed by alternative methods, as discussed further below. Method 500 is described first. 6A through 6B schematically illustrated in FIG operation of the method 500 in conjunction with the operation described in the description. It should be understood that FIG. 6 is only a partial schematic view, and the substrate may include any number of transistor segments having the pattern shown in the figures.

FIG . 7 illustrates a method 700 of forming a semiconductor structure in which a number of operations can be performed, for example, in the aforementioned chambers 200 and 400. The method can include a deuterated aspect on the NMOS and PMOS regions of the substrate. The method can include an aspect of epitaxial growth on the source drain region. Method 700 can include one or more operations prior to initiating the method, including front end processing, deposition, etching, grinding, cleaning, or any other operation that can be performed prior to the operation. The method may include a plurality of selectable operations that may or may not be specifically associated with the method in accordance with the present technology. For example, many operations are described in order to provide a broader range of structure formation, but are not critical to the technology, or may be performed by alternative methods, as discussed further below. Method 700 is described through FIGS. 8A 8B of FIG operation schematically illustrated, in conjunction with the operation of the method 700 described in the description. It should be understood that FIG. 8 is only a partial schematic view, and the substrate may include any number of transistor segments having the pattern shown in the figures. It should be understood that the methods 500 and 700 are merely exemplary, and one of the N regions or P regions may be processed first in an embodiment. Both of these treatments are included in the art.

Method 500 can involve operations performed on a substrate having a plurality of exposed regions, such as on a substrate that includes regions that are further developed to create a transistor structure. As shown in FIG. 6A, a portion of the processed substrate 600 is illustrated as including a substrate 605, a source and a drain 610 of the p region, a source and drain 615 of the n region, a metal gate 620, and a cap layer 625. And gate spacer 630. The material can be formed in previous operations and can be polished, etched, or otherwise processed to produce the structure shown. The operation of method 500 can be performed to limit or eliminate masking operations and RIE processing including ashing and cleaning, and can reduce the processing time for providing epitaxial material during the generation of the structure to reduce the structure of the NMOS and Contact resistance in the PMOS region.

Method 700 can also involve operations performed on a substrate having a plurality of exposed regions, such as on a substrate that includes regions that are further developed to create a transistor structure. As shown in FIG. 8A, a portion of the processed substrate 600 is illustrated as including a substrate 605, a source and a drain 610 of the p region, a source and drain 615 of the n region, a metal gate 620, and a cap layer 625. And gate spacer 630. For example, as formed during method 500, the structure can also include first semiconductor material 635 and second semiconductor material 640. The material can be formed in previous operations and can be polished, etched, or otherwise processed to produce the structure shown. The operation of method 700 can be performed to limit or eliminate masking operations and RIE processing including ashing and cleaning, and can reduce processing queue time for providing deuterated material during generation of the structure to reduce NMOS and PMOS of the structure. Contact resistance in the area.

The materials used may be various dielectric materials, metal materials, and semiconductor materials known in the art. For example, the substrate 605 can be tantalum or some germanium containing material. The source and drain 610 of the p region may be formed in the PMOS region of the structure and may be germanium or some other p-channel metal oxide semiconductor material. The source and drain 615 of the n region may be phosphide or some other n-channel metal oxide semiconductor material. Metal gate 620 can be tungsten, cobalt, or some other electrically conductive material. The cover material 625 can be a self-aligned contact cover and can be tantalum nitride, tantalum carbide, or some oxide material including a metal oxide (eg, tungsten oxide or aluminum oxide). For example, the gate spacer 630 can be any dielectric material and can be, for example, a germanium-containing material, an oxygen-containing material, a carbonaceous material, or some combination (eg, tantalum carbonium oxide).

Method 500 may initially include the step of depositing semiconductor material 635 at operation 505 as shown in FIG. 6A. The semiconductor material 635 can be any known semiconductor material, and in embodiments can be formed on the PMOS source and drain material as shown, and can be deposited as a semiconductor material 635. The deposition of semiconductor material 635 may be selectively deposited on the source and drain regions 610 of the p region and may not be formed on any other exposed material (including cap material 625, gate spacer 630, or possibly NMOS). Any material that remains exposed in the area). In an embodiment, deposition may be performed without first blocking the NMOS region (eg, by forming a photoresist or hard mask). Semiconductor material 635 can be formed in any number of ways and can be epitaxially grown using precursors to utilize one or more selective deposition operations as discussed further below. For example, where the exemplary semiconductor material 635 is germanium, a germanium-containing precursor and a hydride (eg, including a Group II, Group III, Group IV, or Group V metal hydride) or organometallic precursor can be used. Metal organic vapor phase epitaxy (for example, methylated metal or other organic structure) is used to perform the treatment. The treatment can be carried out at a temperature above or below or about 500 ° C, and can be carried out at a pressure below about 1 Torr, and can be carried out at a pressure below or about 1 mTorr.

Method 500 can also include the step of depositing semiconductor material 640 at operation 510 as shown in FIG. 6B. The semiconductor material 640 can be any known semiconductor material, and in embodiments may be formed on the NMOS source and drain material as shown, and may be a III-V semiconductor deposited as a semiconductor material 640 (eg, Indium gallium arsenide). The deposition of semiconductor material 640 may be selectively deposited on the source and drain regions 615 of the n region and may not be formed on any other exposed material (including cap material 625, gate spacer 630, or possibly PMOS). Any material that remains exposed in the area). In an embodiment, deposition may be performed without first blocking the PMOS region (eg, by forming a photoresist or a hard mask). Semiconductor material 640 can be formed in any number of ways and can be epitaxially grown using precursors to utilize one or more selective deposition operations discussed further below. For example, where the exemplary semiconductor material 640 is indium gallium arsenide, an indium containing precursor, a gallium containing precursor, and a hydride (eg, including Group II, Group III, Group IV, or Group V) can be used. The metal organic vapor phase epitaxy of a metal hydride or an organometallic precursor (eg, a methylated metal or other organic structure) is used to perform the treatment. In an embodiment, the additional precursor may be an arsenic-containing precursor. The treatment can be carried out at a temperature above or below or about 500 ° C, and can be carried out at a pressure below about 1 Torr, and can be carried out at a pressure below or about 1 mTorr.

Method 700 can include the step of depositing first alloy material 845 at operation 715 as shown in FIG. 8A. For example, previous operations may occur at operation 712 where a germanium-containing material may be formed over semiconductor material 635. The cerium-containing material can be used to produce an alloy by a subsequent annealing operation. The alloy material can be any number of materials including alloys of nickel. The first alloy material 845 can be formed by alloying nickel with a niobium-containing material (e.g., antimony telluride) to form nickel niobium. The bismuth telluride may initially be formed in operation 712 and then annealed with nickel. Additional second and third nickel-containing alloys or other metal alloys may also be formed. For example, nickel can be used as a material layer because it can also be formed over the PMOS source and drain material as shown. The deposition of the first alloy material 845 may be selectively deposited on the first semiconductor material 635 and may not be formed on any other exposed material (including the cap material 625, the gate spacer 630, or may remain exposed in the NMOS region) Any material). In an embodiment, deposition may be performed without first blocking the NMOS region (eg, by forming a photoresist or hard mask).

The alloy material can be formed in a variety of ways and can be formed by creating a first material layer and then forming an alloy material. In one example of forming nickel ruthenium, a ruthenium telluride layer may be formed and then a nickel layer is formed. It is also possible to form an additional intermediate layer (for example, a titanium or aluminum layer between the bismuth telluride layer and the nickel layer) to aid in the formation of the alloy. Then, an annealing operation (for example, rapid thermal annealing) may be performed at a temperature higher than 400 ° C to allow nickel to permeate the bismuth telluride and form nickel ruthenium. The treatment can also be carried out at a pressure below about 1 Torr and can be carried out at a pressure below or about 1 mTorr.

The method 700 can include the step of depositing a second alloy material 850 at operation 720 as shown in FIG. 8B. The alloy material can be any number of materials including alloys of titanium. Again, a second ruthenium containing material may be deposited first at operation 718 to form an alloy as described above. The second alloy material 850 can be formed by alloying titanium with a cerium-containing material (eg, cerium nitride) to form titanium cerium nitride. Additional second and third titanium-containing alloys or other metal alloys may also be formed. For example, titanium can be used as a material layer because it can also be formed over the NMOS source and drain material as shown. The deposition of the second alloy material 850 may be selectively deposited on the second semiconductor material 640 and may not be formed on any other exposed material (including the cap material 625, the gate spacer 630, or may remain exposed in the PMOS region) Any material).

In an embodiment, deposition may be performed without first blocking the PMOS region (eg, by forming a photoresist or hard mask). The alloy material can be formed in a variety of ways and can be formed by creating a first material layer and then forming an alloy material. In one example of forming titanium arsenide, a tantalum nitride layer may be formed and then a titanium layer is formed. Again, additional intermediate layers can be formed as previously described. Then, an annealing operation (for example, rapid thermal annealing) may be performed at a temperature higher than 400 ° C to allow titanium to penetrate tantalum nitride and form titanium nitride. The treatment can also be carried out at a pressure below about 1 Torr and can be carried out at a pressure below or about 1 mTorr.

Since many materials are positioned or formed in a particular region, the deposited layer can generally be different from other exposed material layers (on which no deposition occurs, or to a lesser extent). One or more of layers 635, 640, 845, and 850 can be formed using a variety of selective deposition techniques by depositing a layer of material (consisting of materials different from other exposed materials).

Selective deposition of any of the disclosed materials can be performed in a chamber capable of deposition and capable of atomic layer deposition, including chamber 400 described above. The premise of the deposition may be based on selective deposition of the metal or semiconductor material relative to the dielectric or insulating material including the capping material 625 and the gate spacer 630, as well as other exposed materials in the regions where deposition occurs. For example, the first semiconductor material 635 (which may be germanium in some embodiments) may be formed substantially on the source and drain material 610 of the p region (which may be germanium germanium) while being minimally formed on the gate Spacer 630 is either limited to gate spacer 630 (which may be germanium carbon oxide in other materials). The first semiconductor material 635 can also be formed at least or limited to nitride, carbide, or oxide cap material 625 and exposed materials in the NMOS region (eg, the source and the germanium of the n-region of the bismuth phosphide) Pole material 615). The following selective deposition can be similarly performed to deposit more material at a desired location than on any other exposed material, other exposed materials can also include a substrate 605, which can be germanium or some other semiconductor material. Selective deposition can be performed by a variety of operations, which can include forming a self-assembled monolayer to facilitate selective deposition, or can include actively inhibiting the formation of materials on other dielectric materials.

A self-assembled monolayer can be formed over the area of the structure to tune the deposition. For example, a first self-assembled monolayer can be formed on the structure and then exposed to the lithographic mask to accept deposition (eg, source and drain regions of the source and drain regions of the p-region 610 or n regions) Any area of the pole material 615) removes the single layer. Materials previously formed in these regions can also be targets for subsequent deposition. The single layer can be maintained on a dielectric or insulating material (eg, cap material 625 and gate spacer 630). The monolayer may have a capping moiety that may or may not interact with the subsequently delivered precursor. For example, in embodiments, the capping moiety can be hydrophobic and can be capped with a hydrogen containing moiety (eg, a methyl group) that can not interact with the additional precursor. A second self-assembled monolayer can be formed over the target region (eg, on the source of the p-region and the source and drain material 615 of the n-region). The self-assembled monolayer can be hydrophilic or can react with one or more precursors used to create a particular deposition material, which can be any of the foregoing materials. Because the material can be repelled from the first self-assembled monolayer, or can be selectively drawn to the target area, a second self-assembled monolayer can be selectively formed over the target area. The second self-assembled monolayer can be capped with a hydroxyl or other hydrophilic moiety, or partially capped with an additional precursor that interacts specifically with the formation of a specified deposition material (eg, a metal or dielectric material).

Atomic layer deposition can then be performed using two or more precursors to form a deposited material (which can be any of the materials previously described for layers 635, 640, 845, 850). The deposited precursor can include a metal-containing or ruthenium-containing precursor and includes a precursor configured to interact with a portion of the capped second self-assembled monolayer (rather than the first self-assembled monolayer). For example, when a hydrophilic and hydrophobic capping monolayer is used, one of the atomic layer deposition precursors can include water. In this way, deposition may not be formed on the first self-assembled monolayer which may be hydrophobic. If the deposition material includes a metal oxide, the precursor for atomic layer deposition may include a specified metal-containing precursor and water. For example, once formation is complete, the oxide can be removed to leave a metal layer. In other embodiments, a ruthenium containing precursor can be used. Then, during a half reaction with water, the water may not interact with the first self-assembled monolayer formed on the other exposed material, and thus the deposition may not be formed on the first self-assembled monolayer. In this way, a specific material can be selectively formed on the target area, or a specific material can be preferentially formed on the target area. It should be understood that this is only a single example, while other precursors may be utilized with similar operating principles to form the previously described specific materials for each deposition zone.

After the identified deposition has been formed to a suitable height, the first self-assembled monolayer may be exposed to UV light and removed from the substrate, or some other removal may be made. In this way, multiple operations used in conventional formations can be eliminated, which can significantly reduce the queue time (eg, several hours). In other embodiments, depending on the operation performed, a slight depression may be performed after selective deposition to remove residual material from other exposed regions discussed below. It should be understood that this is merely an example of utilizing a self-assembled monolayer based on a set of deposited materials.

Depending on the materials used for a particular deposition material, the self-assembled monolayer can be oriented toward the material. As previously mentioned, water can be one of the precursors, and as previously described, the self-assembled monolayer can be structured (eg, including a hydroxyl-terminated material at a target location to promote formation relative to other exposed materials). On the material). In addition, the nitrogen-containing material can serve as one of the self-assembled monolayers on the material used for deposition (eg, one of the capping portions of the monolayer), while allowing for attraction to form the previously described material. Specific precursor of one or more. Additional precursors can be used to achieve or facilitate metal to metal deposition or semiconductor deposition.

Because of the structure of some exposed metal or semiconductor materials, the exposed material may also be corroded or passivated to reduce activity relative to other materials on which deposition occurs, which may allow for increased deposition on the target material. Passivation of the material can include exposure to a ruthenium substituted or halogen substituted material, which can limit the deposition of other materials. For example, oxidation of the material can utilize oxygen-containing materials or halogen-containing materials, which can allow for preferential deposition on other surfaces. Once oxidized (e.g., by exposure to an oxygen-containing material), atomic layer deposition can be performed similar to that described, wherein one of the precursors can include an oxygen-containing material, which may not interact with the oxidic material.

Passivation can also be performed on exposed insulating and dielectric materials. For example, the cover material 625 can include an oxide, for example, can be treated to adjust the capping group to contain ruthenium, hydrogen, or halogen. This may allow preferential deposition of metallic or semiconducting materials on other exposed areas. In other embodiments, the nitrogen-containing precursor can serve as one or two precursors in the atomic layer deposition process, which can allow for preferential deposition on the metal surface relative to the oxide surface.

Embodiments may also utilize an inhibitor to selectively form one of the deposited materials on the target surface, rather than forming a deposited material on a dielectric or insulating material or other exposed surface. For example, the sprayed inhibitor can be applied across the surface of the substrate and can be applied along the top surface of the substrate and can not penetrate into the recessed portion of the substrate. The inhibitor can be any number of materials, and the material can be characterized by a siloxane backbone (e.g., a decane) or a tetrafluoroethylene backbone (e.g., PTFE), as well as other oily or surfactant materials. Material may be applied across the top surface of the substrate to cover the exposed portions of cover material 625 and gate spacers 630. By using a spray or coating application, the material may not be applied to the recessed portion of the substrate and may not contact the source and drain regions on which the deposition takes place. Additional selectivity techniques can be used in combination to form a self-assembled monolayer on the PMOS and NMOS regions, for example, as previously described to facilitate deposition at one location rather than another. The selected material can then be formed, for example, by atomic layer deposition or other vapor deposition or physical deposition mechanisms.

The inhibitor material prevents adhesion or adsorption of the deposited material that can be normally formed or deposited at the target location. After the material is formed, a remover can be applied to the substrate to remove the inhibitor material. The remover can be a wet etchant, a reactant, or a surfactant cleaner, and the residual inhibitor material that exposes the underlying dielectric to the insulating material can be removed. The use of inhibitors may allow for the formation of separate layers in defined regions without the need for patterning and/or etching definitions through subsequent blanket coatings. By removing the previous and subsequent patterning operations, the process can further reduce the queue time relative to conventional processing.

The inhibitor may also be the product of a plasma application that can neutralize the surface of the substrate or render the surface of the substrate inert. For example, the modified plasma can be formed from one or more precursors, and can include an inert precursor. The plasma may be applied to the surface of the substrate or raised above the substrate, while the top surface of the exposed material may be altered and may not penetrate into portions of the substrate or within portions of the substrate surface. For example, a nitrogen-containing precursor (which may be nitrogen) can be delivered to the plasma processing zone of the processing chamber that produces the plasma. The plasma effluent (which may include a nitrogen-containing plasma effluent) may be delivered to the substrate and may form a nitrided surface along the exposed portion of the substrate along the top surface (which may include exposure of the capping material 625 and the gate spacer 630) region).

The plasma effluent may not deliver or may not flow to the surface of the substrate, but may maintain a pure or unreacted surface along the source and the drain material. The deposition material (eg, forming a self-assembled monolayer) can then be formed using one or more deposition techniques and/or additional selectivity techniques, which can include atomic layer deposition or other vapor or physical deposition. For example, the plasma effluent can be subsequently processed using atomic layer deposition techniques to form a self-assembled monolayer on the PMOS and NMOS regions of the substrate. After each cycle of deposition, the nitrogen-containing plasma can be reapplied to the surface area of the substrate (eg, on a dielectric or insulating material). In this manner, the surface of the dielectric material can be passivated to prevent or limit the formation of deposited materials on those areas. Utilizing these plasma effluents from the raised portions of the substrate may allow deposition material to be formed in defined regions along the substrate surface without the need for patterning and/or etching definitions through subsequent blanket coatings. By removing the previous and subsequent patterning operations, the process can further reduce the queue time relative to conventional processing.

Additional selective deposition techniques can utilize temperature differences to enhance deposition on the cerium-containing material relative to the oxygen-containing material. For example, atomic layer deposition using a hafnium-containing precursor can be performed at temperatures above or about 500 ° C, and can be above or about 750 ° C, above or about 900 ° C, above or about 1000 ° C, It is performed at a temperature of up to, above, or about 1100 °C.

As the temperature increases within this range, deposition can occur on certain exposed materials at a higher rate than on an oxygen containing material (e.g., can be cap material 625). A selective etch of the formed material can then be performed to remove the first dielectric material from the oxide surface. Although the first semiconductor material can also be reduced on the target surface, since the thickness can be many times thicker than on the oxide surface, complete removal of the oxide surface can be performed while maintaining the thickness on the target surface greater than or about 1 nm, Greater than or about 2 nm, greater than or about 3 nm, greater than or about 4 nm, greater than or about 5 nm, greater than or about 6 nm, greater than or about 7 nm, greater than or about 8 nm, greater than or about 9 nm, greater or about 10 nm, or greater. This effect may be achieved in a manner that is limited by conventional techniques. During normal conformal or blanket deposition, portions of the target surface may have a thickness equal to the thickness on the cover material or may be less than the thickness on the cover material. Therefore, the etch back process may over-etch the target area or may cause perforations in the layer.

Any of these techniques may selectively deposit or form a previously specified material relative to one or more other metals, semiconductors, non-metals, dielectrics, or regions of insulation. Moreover, two or more of these techniques can be combined or iteratively performed to produce a surface having a particular area that can or can be deposited with a higher rate of deposition. The selectivity may be complete, wherein the deposition material is formed only on the target location (eg, the source of the p region and the source of the drain 610 or n region and the drain 615, or the intermediate layer), and may be completely absent A deposition material is formed on the exposed material. In other embodiments, the selectivity may not be complete, and the ratio of deposition on the target location relative to other exposed materials may be greater than or about 2:1. The selectivity may also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35. : 1. greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more. As previously mentioned, the thickness of the deposited material can be less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or less. Thus, a selectivity below 20:1 may be acceptable to completely deposit a separate layer while forming a limited amount of material or substantially no material formation on other exposed areas.

The deposition operation can be performed at any of the foregoing temperatures or pressures, and can be performed at temperatures greater than or about 300 ° C, and can be greater than or about 400 ° C, greater than or about 450 ° C, greater than or about 500 ° C, greater than or about Execution is carried out at a temperature of 600 ° C, greater than or about 700 ° C, greater than or about 800 ° C, greater than or about 900 ° C, greater than or about 1000 ° C, or higher. For example, during an atomic layer deposition operation, a temperature greater than or about 500 °C can be used to activate the precursors to interact with one another as the material layers are formed.

Depending on the type of deposition performed, certain operations may be performed in a different order than previously described. For example, if a single layer (formed to resist or prevent formation) can be used with more than one material, the layer can be maintained during subsequent operations to increase efficiency. For example, method 500 is illustrated as forming indium gallium arsenide prior to forming a nickel alloy material on the tantalum in the PMOS region of method 700. However, if a self-assembled monolayer is used to resist, reduce, or prevent the formation of a tantalum layer on other exposed materials, these layers may be maintained during subsequent operations of the alloyed metal (eg, forming an initial tantalum layer). In this manner, in some embodiments, operations 510 and 715 can be reversed, and all PMOS operations can be performed continuously, and all NMOS operations can be performed continuously.

One or more etching operations may also be performed depending on the amount formed and the selectivity of the individual deposition. The etching operation can utilize dry etch chemistry, while in embodiments the plasmonic chemicals can be utilized. For example, etchback can be performed in chamber 200, which can be on the same cluster tool as the one or more deposition chambers that performed the previous deposition. In this way, several deposition and etching operations can be performed in a single environment (eg, shared by cluster tools between chambers). For example, an additional chamber may be used with one or more etch chambers 200 and deposition chambers 400, for example, to perform UV processing, as may be used in some deposition techniques described below. Each transfer can be done under vacuum, and each of the chambers can reside on the same cluster tool to allow the transfer to occur in a controlled environment. For example, vacuum conditions can be maintained during transfer and transfer can be performed without breaking the vacuum. Method 500 can be performed on a single tool with respect to conventional techniques that can include additional masking operations, lithography, and other operations that may require transfer between many tools, where vacuum conditions are not compromised in the embodiments. Moreover, method 500 may not utilize any RIE operation, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE.

The etching operation can be performed using a plasma excited precursor and may involve additional precursors along with a particular fluorine-containing precursor. In some embodiments, nitrogen trifluoride can be used to produce a plasma effluent. Additional or alternative fluorine precursors may also be utilized. For example, the fluorine-containing precursor may flow into the distal plasma region, and the fluorine-containing precursor may include a group selected from the group consisting of atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, and six. At least one precursor of the group of sulfur fluoride, and antimony difluoride. The distal plasma zone can be in a different module than the processing chamber or in a compartment within the processing chamber. As shown in FIG. 2, both the RPS unit 201 and the first plasma region 215 can serve as a distal plasma region. The RPS can allow the plasma effluent to dissociate without damaging other chamber components, while the first plasma region 215 can provide a shorter path length to the substrate during which recombination can occur.

Additional precursors can also be delivered to the remote plasma region to enhance the fluorine-containing precursor. For example, a nitrogen and hydrogen containing precursor, an oxygenated precursor, or a hydrogen precursor can be delivered with a fluorine-containing precursor. For example, the additional precursor can be a nitrogen-containing precursor (eg, ammonia), or can be oxygen, hydrogen, or any number of precursors including one or more of these components. The additional precursor can flow into the processing chamber in an unexcited state to interact with the substrate surface. These formulations can selectively etch one of the exposed materials relative to one or more of the other exposed materials. For example, the etch chemistry can be used to recess one or more alloy materials and any epitaxially grown material relative to the exposed cap and spacer material and relative to other formed materials. The etch selectivity may be greater than or about 10:1, greater than or about 20:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 150:1, or More. In this way, all of the additional material that may have formed during deposition can be removed with minimal material loss at the desired location. This can occur because the selectivity of the deposit can produce at least twice the material at the desired location compared to other exposed materials.

In an embodiment, the etching operation can be performed below about 10 Torr, and in embodiments can be performed below or about 5 Torr. In embodiments, the treatment may also be performed at temperatures below about 100 °C and may be performed below about 50 °C. As performed in variations of the chamber 200 or such chambers, or in different chambers capable of performing similar operations, the process may be selective to remove other portions of the deposited material for other exposed materials across the substrate. By utilizing the present technology, manufacturing can be performed with more selective formation and removal than conventional techniques, and can reduce the queue time by several hours compared to conventional processing.

In the previous description, numerous details have been set forth in order to provide an understanding of various embodiments of the present invention. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

The invention has been described in terms of a number of modifications, alternative constructions, and equivalents, which can be used in the art without departing from the spirit of the embodiments. Moreover, many of the known processes and elements are not described in order to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be taken as limiting the scope of the technology.

When a range of values is provided, it is to be understood that unless the context clearly dictates otherwise, each intermediate value between the upper and lower limits of the range is specifically disclosed. Any narrower range between any stated or un recited intermediate value in the range and any other stated or intermediate value in the range. The upper and lower limits of these smaller ranges may be independently included in the range or excluded, and each of the smaller ranges including one or both of the upper and lower limits and the upper and lower limits are also included in the present technology. Depending on the limits specifically excluded from the stated range. Where the stated range includes one or two limitations, the scope of the one or both of the

The singular forms "a", "an" and "the" Thus, for example, reference to "a" or "an" or "an" or "an"

In addition, the words "including", "including", "including", "including", "including", and "including" are used in the specification and the following claims. The existence of a component, or operation, does not exclude the presence or addition of one or more other features, components, components, operations, acts, or groups.

10‧‧‧Loading lock chamber

15‧‧‧Isolation valve

20‧‧‧Processing chamber

30‧‧‧ gas distribution board

60‧‧‧Substrate

61‧‧‧ first surface

65‧‧‧Transportation shuttle

70‧‧‧ Track

90‧‧‧radiation heat source

100‧‧‧Processing system

102‧‧‧Front open wafer cassette

104‧‧‧Machine arm

106‧‧‧holding area

108a‧‧‧Processing chamber

108b‧‧‧Processing chamber

108c‧‧‧Processing chamber

108d‧‧‧Processing chamber

108e‧‧‧Processing chamber

108f‧‧‧Processing chamber

109a‧‧‧Series section

109b‧‧‧Series section

109c‧‧‧Series section

110‧‧‧Second robotic arm

200‧‧‧ chamber

201‧‧‧RPS unit

203‧‧‧Cooling plate

205‧‧‧ gas inlet assembly

210‧‧‧Fluid Supply System

214‧‧‧Upper board

215‧‧‧First plasma area

216‧‧‧ Lower board

217‧‧‧ panel

218‧‧‧ volume

219‧‧‧First fluid passage

220‧‧‧Insulation ring

221‧‧‧Second fluid channel

223‧‧‧Ion suppressor

225‧‧‧Sprinkler

233‧‧‧Substrate processing area

240‧‧‧Power supply

253‧‧‧Detailed view

255‧‧‧Substrate

258‧‧‧ gas supply area

259‧‧‧ pores

265‧‧‧ pedestal

325‧‧‧Sprinkler

365‧‧‧through hole

375‧‧‧Small holes

400‧‧‧ chamber

420‧‧‧Syringe

425‧‧‧ gas 埠

430‧‧‧Syringe

435‧‧‧ gas 埠

440‧‧‧Syringe

445‧‧‧ gas 埠

450‧‧‧ pumping system

455‧‧‧vacuum

460‧‧‧ partition

498‧‧‧ arrow

500‧‧‧ method

505‧‧‧ operation

510‧‧‧ operation

600‧‧‧Substrate

605‧‧‧Substrate

Source and bungee of the 610‧‧‧p area

Source and bungee in the 615‧‧‧n area

620‧‧‧Metal gate

625‧‧‧ Cover material

630‧‧‧gate spacer

635‧‧‧First semiconductor material

640‧‧‧second semiconductor material

700‧‧‧ method

712‧‧‧ operation

715‧‧‧ operation

718‧‧‧ operation

720‧‧‧ operation

845‧‧‧First alloy material

850‧‧‧Second alloy material

A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the description and the accompanying drawings.

FIG. 1 illustrates a top plan view of an exemplary processing system in accordance with an embodiment of the present technology.

2A illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.

2B illustrates a detailed view of an exemplary panel in accordance with an embodiment of the present technology.

FIG. 3 illustrates a bottom plan view of an exemplary showerhead in accordance with an embodiment of the present technology.

FIG. 4 illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.

FIG. 5 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

6A through 6B illustrate schematic cross-sectional views of an exemplary substrate in accordance with an embodiment of the present technology.

FIG. 7 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

8A through 8B illustrate schematic cross-sectional views of an exemplary substrate in accordance with an embodiment of the present technology.

Several of the figures are included as schematics. It is understood that the drawings are for illustrative purposes only and are not to In addition, as a schematic, the drawings are provided to aid understanding, and the drawings may not include all aspects or information as compared to the actual representation, and may include exaggerated materials for illustrative purposes.

Similar components and/or features may have the same component symbols in the accompanying drawings. Furthermore, various components of the same type may be distinguished by the use of letters after the component symbols to distinguish similar components. If only the foremost component symbol is used in the specification, the description applies to any similar component having the same topmost component symbol, regardless of the letter.

Domestic deposit information (please note according to the order of the depository, date, number)

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Claims (20)

A method of forming a semiconductor structure, the method comprising the steps of: depositing a first semiconductor material on a semiconductor substrate, wherein the first semiconductor material is selectively deposited on a first germanium relative to a second germanium containing material And depositing a second semiconductor material on the semiconductor substrate, wherein the second semiconductor material is selectively deposited on the second germanium-containing material relative to the first semiconductor material. A method of forming a semiconductor structure according to claim 1, wherein the first semiconductor material is deposited on a PMOS region of the semiconductor substrate with respect to an NMOS region of the semiconductor substrate. A method of forming a semiconductor structure according to claim 1, wherein the first semiconductor material comprises germanium, and wherein the first germanium-containing material comprises germanium germanium. A method of forming a semiconductor structure according to claim 3, wherein the second ruthenium-containing material comprises phosphorus. A method of forming a semiconductor structure as described in claim 1, wherein the method is performed without performing a reactive ion etching operation. A method of forming a semiconductor structure according to claim 1, wherein the depositing of the first semiconductor material is performed using a selectivity of the first germanium-containing material relative to the second germanium-containing material by greater than or about 2:1. A method of forming a semiconductor structure according to claim 1, wherein the depositing occurs on an NMOS region of the semiconductor substrate with respect to a PMOS region of the semiconductor substrate. A method of forming a semiconductor structure as described in claim 7, wherein the method is performed without forming a photoresist on the PMOS region. A method of forming a semiconductor structure according to claim 1, wherein the first semiconductor material comprises indium, and wherein the first germanium-containing material comprises germanium phosphide. A method of forming a semiconductor structure according to claim 9, wherein the second ruthenium-containing material comprises ruthenium. A method of forming a semiconductor structure according to claim 9, wherein the first semiconductor material is indium gallium arsenide. A method of forming a semiconductor structure, the method comprising the steps of: depositing a first alloy material on a first semiconductor material, wherein the alloy material is selectively deposited on the first material relative to a nitride material or an oxide material And a second alloy material is deposited on a second semiconductor material, wherein the second alloy material is selectively deposited on the second semiconductor material relative to the nitride material or the oxide material. The method of forming a semiconductor structure according to claim 12, wherein the first alloy material is deposited on an indium-containing material in an NMOS region of the semiconductor substrate, and wherein the second alloy material is deposited thereon A germanium-containing material in a PMOS region of the semiconductor substrate. A method of forming a semiconductor structure according to claim 12, wherein the nitride material comprises tantalum nitride, and wherein the oxide material comprises hafnium oxide, tantalum carbonoxide, or a metal oxide. . A method of forming a semiconductor structure according to claim 14, wherein the metal oxide comprises tungsten oxide or aluminum oxide. A method of forming a semiconductor structure as described in claim 12, wherein the method is performed without performing a reactive ion etching operation. A method of forming a semiconductor structure according to claim 12, wherein the second alloy material comprises a nickel-containing material. A method of forming a semiconductor structure according to claim 17, wherein the second alloy material comprises nickel ruthenium. A method of forming a semiconductor structure according to claim 12, wherein the first alloy material comprises a titanium-containing material. A method of forming a semiconductor structure according to claim 19, wherein the first alloy material comprises titanium niobium nitride.