WO2015172715A1 - 一种铁电存储器 - Google Patents

一种铁电存储器 Download PDF

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Publication number
WO2015172715A1
WO2015172715A1 PCT/CN2015/078834 CN2015078834W WO2015172715A1 WO 2015172715 A1 WO2015172715 A1 WO 2015172715A1 CN 2015078834 W CN2015078834 W CN 2015078834W WO 2015172715 A1 WO2015172715 A1 WO 2015172715A1
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Prior art keywords
storage unit
unit
bit line
data
reference unit
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PCT/CN2015/078834
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English (en)
French (fr)
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贾泽
赵俊峰
杨伟
邹重人
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华为技术有限公司
电子科技大学
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Publication of WO2015172715A1 publication Critical patent/WO2015172715A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

Definitions

  • the present invention relates to the field of storage technologies, and in particular, to a ferroelectric memory.
  • Ferroelectric memory is a new type of non-volatile memory device.
  • the ferroelectric memory utilizes the spontaneous polarization phenomenon in the ferroelectric material to realize the storage of binary data.
  • the ferroelectric memory includes a reference unit and a storage unit, wherein the reference unit provides a reference voltage signal for reading and writing data of the storage unit.
  • the reference unit provides a reference voltage signal for reading and writing data of the storage unit.
  • Embodiments of the present invention provide a ferroelectric memory for balancing read and write fatigue of two reference units in a reference unit pair.
  • a first aspect of the embodiments of the present invention provides a ferroelectric memory, which may include:
  • a first storage unit column a first reference unit, a second reference unit, and a control circuit
  • the first storage unit column includes at least one storage unit, the at least one storage unit is configured to store data, wherein each storage unit includes a ferroelectric capacitor and a transistor;
  • the control circuit is connected to the first reference unit, the second reference unit, and a storage unit in the first storage unit column;
  • the first reference unit and the second reference unit are configured to provide a reference voltage, wherein each reference unit includes a ferroelectric capacitor and a transistor, and the data stored in the first reference unit and the second reference unit Different values;
  • the control circuit is configured to obtain the first storage according to the reference voltage and an output signal of the first storage unit when reading data stored in the first storage unit in the first storage unit column Data stored in the unit; after reading the data stored in the first storage unit, writing data different from the value of the read data to the first reference unit, and Data having the same value is written to the second reference unit.
  • the control circuit includes a first voltage amplifier, a first triode, and a first enable inverter;
  • a first end of the first transistor is connected to a bit line of the first reference unit, and a second end of the first transistor is connected to a bit line of the second reference unit, wherein the first The first end and the second end of the triode are not the conduction control ends of the first triode;
  • An input end of the first enable inverter is connected to the bit line of the first reference unit, and an output end of the first enable inverter is connected to a bit line of the second reference unit;
  • the amplified signal input end of the first voltage amplifier is connected to the bit line of the first memory unit, and the reference voltage input end of the first voltage amplifier is connected to the bit line of the first reference unit.
  • the first storage unit column includes a plurality of storage units, the first storage unit The plurality of memory cells in the column share the same bit line.
  • the ferroelectric memory further includes :
  • the second storage unit column includes at least one storage unit;
  • the control circuit is coupled to the storage unit in the second storage unit column;
  • the second storage unit column includes the At least one storage unit is configured to store data, wherein each of the second storage unit columns includes a ferroelectric capacitor and a transistor;
  • the control circuit is further configured to: when reading data stored in the second storage unit in the second storage unit column, obtain the second according to the reference voltage and an output signal of the second storage unit Data stored in the storage unit; after reading the data stored in the second storage unit, writing data different from the value of the data stored in the read second storage unit to the second Referring to the unit, and writing data having the same value as the data stored in the read second storage unit to the first reference unit.
  • control circuit further includes: a second voltage amplifier and a second enable inverter;
  • An input end of the second enable inverter is coupled to a bit line of the second reference unit, and the second An output end of the inverter is connected to a bit line of the first reference unit; an amplified signal input end of the second voltage amplifier is connected to a bit line of the second memory unit, and a reference voltage input of the second voltage amplifier The terminal is connected to the bit line of the second reference unit.
  • the second storage unit column includes multiple storages a unit, the plurality of memory cells in the second memory cell column sharing the same bit line.
  • the ferroelectric memory further includes: a third storage unit column, a third reference unit, and a fourth reference unit;
  • the third storage unit column includes at least one storage unit, the at least one storage unit included in the third storage unit column is configured to store data, wherein each storage unit in the third storage unit column Including a ferroelectric capacitor and a transistor;
  • the third reference unit and the fourth reference unit are configured to provide a reference voltage, wherein each of the third reference unit and the fourth reference unit includes a ferroelectric capacitor and a transistor, The values of the data stored in the third reference unit and the fourth reference unit are different;
  • the control circuit is further configured to: when reading data stored in the third storage unit in the third storage unit column, according to an output signal of the third storage unit, and the third reference unit and a reference voltage provided by the fourth reference unit to obtain data stored in the third storage unit; after reading the data stored by the third storage unit, the third storage unit to be read and read The stored data of the same value of the data is written into the fourth reference unit, and data different from the value of the data stored in the read third storage unit is written into the third Reference unit.
  • control circuit further includes: a third voltage amplifier, a second triode, and a third enable Phaser
  • the first end of the second transistor is connected to the bit line of the third reference unit
  • the second a second end of the triode is connected to the bit line of the fourth reference unit, wherein the first end and the second end of the second triode are not the conduction control end of the second triode
  • An input end of the third enable inverter is connected to the bit line of the third reference unit, and an output end of the third enable inverter is connected to a bit line of the fourth reference unit;
  • An amplifying signal input end of the third voltage amplifier is connected to a bit line of a third memory cell in the third memory cell column, and a reference voltage input end of the third voltage amplifier is connected to the third reference cell Bit line.
  • the ferroelectric memory further includes a fourth storage unit column,
  • the fourth storage unit column includes at least one storage unit, the at least one storage unit included in the fourth storage unit column is configured to store data, wherein each storage unit in the fourth storage unit column Including a ferroelectric capacitor and a transistor;
  • the control circuit is further configured to: when reading data stored in the fourth storage unit in the fourth storage unit column, according to an output signal of the fourth storage unit, and the third reference unit and a reference voltage provided by the fourth reference unit to obtain data stored in the fourth storage unit; after reading the data stored in the fourth storage unit, stored in the fourth storage unit to be read Data having different values of data is written to the fourth reference unit, and data having the same value as the data stored in the read fourth storage unit is written to the third reference unit.
  • control circuit further includes a fourth voltage amplifier and a fourth enable inverter;
  • An input end of the fourth enable inverter is connected to a bit line of the fourth reference unit, and an output end of the fourth enable inverter is connected to a bit line of the third reference unit;
  • An amplifying signal input end of the fourth voltage amplifier is connected to a bit line of a fourth memory cell in the fourth memory cell column, and a reference voltage input end of the fourth voltage amplifier is connected to the fourth reference unit Bit line.
  • the third reference unit and the first storage unit share the same bit line;
  • the fourth reference unit shares the same bit line as the second storage unit.
  • the first reference unit and the first The three memory cells share the same bit line; and the second reference cell shares the same bit line as the fourth memory cell.
  • the ferroelectric memory architecture provided by the implementation of the present invention is advantageous for better balance and readiness and fatigue for the two reference units in the reference unit pair of the reference signal. It is beneficial to greatly improve the fatigue resistance of the reference unit.
  • FIG. 1 is a schematic structural diagram of a ferroelectric memory according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another ferroelectric memory according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another ferroelectric memory according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of another ferroelectric memory according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another ferroelectric memory according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another ferroelectric memory according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of another ferroelectric memory according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a memory cell of an ITIC type ferroelectric according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of data read and write timing of a first storage unit 111 according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of simulation of data reading and writing by the first storage unit 111 according to an embodiment of the present invention.
  • Embodiments of the present invention provide a ferroelectric memory, in order to improve data write-back efficiency of a reference unit and a storage unit, and to balance read and write fatigue of two reference units in a reference unit pair.
  • Ferroelectricity is one of the more mature new dielectric materials.
  • the storage unit whose storage unit is a ferroelectric medium is taken as an example
  • the reference unit whose reference unit is a ferroelectric medium is taken as an example.
  • FIG. 1 is a schematic structural diagram of a ferroelectric memory according to an embodiment of the present invention.
  • the ferroelectric memory shown in FIG. 1 may include: a first memory cell column 110, a first reference cell Ck1, and a second reference. Unit Ck2 and control circuit 200.
  • the first storage unit column 110 includes at least one storage unit, wherein the at least one storage unit included in the first storage unit column 110 is configured to store data, wherein each of the first storage unit columns 110
  • the storage unit may include a ferroelectric capacitor and a transistor.
  • the first memory cell column 110 is illustrated in FIG. 1 as including at least one memory cell including the first memory cell 111.
  • the first storage unit 111 may be any one of the first storage unit columns 110.
  • the control circuit 200 is connected to the first reference unit Ck1, the second reference unit Ck2, and the storage unit in the first storage unit column 110.
  • each of the first reference unit Ck1 and the second reference unit Ck2 may include a ferroelectric capacitor and a transistor.
  • the first reference unit Ck1 and the second reference unit Ck2 are used to provide a reference voltage.
  • the values of the data stored in the first reference unit Ck1 and the second reference unit Ck2 are different.
  • the control circuit 200 is configured to obtain, according to the reference voltage and an output signal of the first storage unit 111, when reading data stored in the first storage unit 111 in the column of the first storage unit 110.
  • the data stored in the first storage unit 111 after the data stored by the first storage unit 111 is read, the data stored in the read first storage unit 111
  • the data of the same value is written into the second reference unit Ck2, and data different from the value of the data stored in the read first storage unit 111 is written into the first reference unit Ck1.
  • the data with the value "1” is written after the data stored in the first storage unit 111 is read.
  • the second reference unit Ck2 is input, and data having a value of "0" is written to the first reference unit Ck1. It is assumed that the value of the data stored in the read first storage unit 111 is “0”, and after the data stored in the first storage unit 111 is read, the data with the value “0” is written.
  • the second reference unit Ck2 is input, and data having a value of "1” is written into the first reference unit Ck1. It can be understood that after reading the data stored in the other storage units in the first storage unit column 110, the data write-back mechanism of the first reference unit Ck1 and the second reference unit Ck2 can be deduced.
  • the write-back state of the first reference unit and the second reference unit depends on the value of the data stored in the storage unit that supplies the reference voltage.
  • the value of the data stored in the storage unit is regarded as random, and the write back state of the first reference unit and the second reference unit is also random, that is, whether the reference unit stores "0" or "1".
  • the data randomly read by the storage unit determines that the probability of storing "0" in each reference unit is usually equal to the probability of storing "1", and the mechanism for fixing the value of the data stored in the conventional reference unit is completely complete.
  • the data stored in the two reference units in each pair of reference units that cooperate to provide the reference signal have different values, and one of the fixed storage values is “1” data, and the other fixed storage takes The value is "0”, and each time the data is stored in the reference unit, the data read from the reference unit needs to be written back to the reference unit, for example, if the value stored in the reference unit is "1" "Data”, when the reference unit writes back, it needs to write data with the value "1" to the reference unit.
  • the reference unit stores data with the value "0"
  • the reference unit writes back
  • the data with the value “0” needs to be written to the reference unit, and the fatigue of the reference unit that causes the fixed storage “1” is relatively large, and the architecture of the present invention facilitates good equalization to provide the reference signal.
  • Write fatigue test unit of two reference cells thereby facilitating the reference cell greatly improved fatigue resistance.
  • control circuit 200 may be various.
  • the control circuit 200 shown in FIG. 2 may include a first voltage amplifier SA1, a first transistor Q12, and a first enable inverter F1.
  • the first end of the first transistor Q12 is connected to the bit line of the first reference unit Ck1, and the second end of the first transistor Q12 is connected to the bit line of the second reference unit Ck1, wherein the first three poles
  • the first end and the second end of the tube Q12 are not the conduction control terminals (e.g., gates) of the first transistor Q12.
  • the first end of the first transistor Q12 may be the source of the first transistor Q12
  • the second end of the first transistor Q12 may be the drain of the first transistor Q12
  • the first The second end of the transistor Q12 is the source of the first transistor Q12
  • the first end of the first transistor Q12 is the drain of the first transistor Q12.
  • the input terminal of the first enable inverter F1 is connected to the bit line of the first reference cell Ck1, and the output terminal of the first enable inverter F1 is connected to the bit line of the second reference cell Ck2.
  • the amplification signal input end of the first voltage amplifier SA1 is connected to the bit line BL1 of the first memory unit 111 (referred to as a first bit line), and the reference voltage input end of the first voltage amplifier SA1 is connected to the bit line of the first reference unit Ck1. .
  • the first memory cell columns 110 may share the same bit.
  • a line, for example, the first memory unit 111 may share the same bit line as the other one or more memory cells in the first memory cell column 110.
  • the above-described ferroelectric memory further includes a second memory cell column 120.
  • the control circuit 200 is connected to the storage unit in the second storage unit column 120.
  • the second storage unit column 120 includes at least one storage unit.
  • the at least one storage unit included in the second storage unit column 120 is configured to store data, wherein each of the second storage unit columns 120 may include a ferroelectric capacitor and a transistor.
  • the second memory cell column 120 is exemplarily shown in FIG. 3 to include at least one memory cell including the third memory cell 121.
  • the second storage unit 121 can be any one of the second storage unit columns 120.
  • the control circuit 200 is further configured to: when reading data stored in the second storage unit 121 in the second storage unit column 120, according to an output signal of the second storage unit 121, and the first reference unit Ck1 and the second Referring to the reference voltage provided by the unit Ck2, the data stored in the second storage unit 121 is obtained; after the data stored in the second storage unit 121 is read out, it is stored in the second storage unit 121 to be read. The data of the same value of the data is written into the first reference unit Ck1, and the data different from the value of the data stored in the read second storage unit 121 is written into the second reference unit Ck2.
  • the data with the value "1” is written after the data stored in the second storage unit 121 is read.
  • the first reference unit Ck1 is entered, and data having a value of "0" is written to the second reference unit Ck2. It is assumed that the value of the data stored in the read second storage unit 121 is “0”, and after the data stored in the second storage unit 121 is read, the data with the value “0” is written.
  • the first reference unit Ck1 data having a value of "1” is written to the second reference unit Ck2. It can be understood that after reading the data stored in the other storage units in the second storage unit column 120, the data write back mechanism of the first reference unit Ck1 and the second reference unit Ck2 can be deduced.
  • a pair of reference cells that cooperatively provide a reference signal can provide reference signals for memory cells in two columns of memory cell columns.
  • the data After reading the data stored in the second storage unit, the data will be Writing data having different values is written into the second reference unit, and writing the same data as the value of the above-mentioned data stored in the read second storage unit into the first reference unit, that is, the first reference unit and The write back state of the second reference unit still depends on the value of the data stored in the memory cell in which the reference voltage is supplied, and the data stored in each of the first memory cell column 110 or the second memory cell column 120
  • the value of the first reference unit and the second reference unit are also random, that is, whether the "0" or the "1" is stored in the reference unit is randomly read by the storage unit.
  • the data determines that the probability of storing "0" in each of a pair of reference cells that cooperate to provide the reference signal is typically approximately equal to the probability of storing "1", which is compared to the data stored in each of the conventional reference cells.
  • the mechanism of fixing the value is completely different, so the above architecture is beneficial for well-balanced read and write fatigue of the two reference units in the reference unit pair of the reference signal, which is beneficial to greatly improve the reference.
  • the fatigue resistance of the unit is beneficial for well-balanced read and write fatigue of the two reference units in the reference unit pair of the reference signal, which is beneficial to greatly improve the reference.
  • FIG. 4 shows the structure of another possible control circuit 200.
  • control circuit 200 shown in FIG. 4 further includes a second voltage amplifier SA2 and a second enable inverter F2, compared to the control circuit 200 shown in FIG.
  • the input terminal of the second enable inverter F2 is connected to the bit line of the second reference cell Ck2, and the output terminal of the second enable inverter F2 is connected to the bit line of the first reference cell Ck1.
  • the amplified signal input terminal of the second voltage amplifier SA2 is connected to the bit line BL2 of the second memory unit 121, and the reference voltage input terminal of the second voltage amplifier SA2 is connected to the bit line of the second reference unit Ck2.
  • some or all of the storage units in the second storage unit column 120 may share the same bit line.
  • the second storage unit 121 may share the same as the other one or more storage units in the second storage unit column 120. Bit line.
  • the ferroelectric memory may further include a third storage unit column 130, a third reference unit Ck3, and a fourth reference unit Ck4.
  • the third reference unit Ck3 and the fourth reference unit Ck4 are used to provide a reference voltage.
  • the third storage unit column 130 includes at least one storage unit.
  • the third memory cell column 130 is exemplified in FIG. 5 to include at least one memory cell including the third memory cell 131.
  • the third storage unit 131 may be any one of the third storage unit columns 130.
  • the at least one storage unit included in the third storage unit column 130 is configured to store data, wherein the third storage unit column
  • Each of the memory cells 130 may include a ferroelectric capacitor and a transistor.
  • control circuit 200 can also be used to read the data stored in the third storage unit 131 in the third storage unit 130, according to the output signal of the third storage unit 131, and the third reference unit Ck3 and The reference voltage provided by the fourth reference unit Ck4 obtains the data stored in the third storage unit 131; after the data stored by the third storage unit 131 is read out, it is stored in the third storage unit 131 to be read.
  • the data of the same value of the data is written into the fourth reference unit Ck4, and the data different from the value of the data stored in the read third storage unit 131 is written into the third reference unit Ck3.
  • the data with the value "1” is written after the data stored in the third storage unit 131 is read.
  • the fourth reference unit Ck4 is entered, and data having a value of "0" is written to the third reference unit Ck3. It is assumed that the value of the data stored in the read third storage unit 131 is “0”, and after the data stored in the third storage unit 131 is read, the data with the value “0” is written.
  • data having a value of "1” is written to the third reference unit Ck3. It can be understood that after reading the data stored in the other storage units in the third storage unit column 130, the data write-back mechanism of the third reference unit Ck3 and the fourth reference unit Ck4 can be deduced.
  • control circuit 200 shown in FIG. 5 further includes a third voltage amplifier SA3, a second transistor Q34, and a third enable inverter F3, compared to the control circuit 200 shown in FIG.
  • the first end of the second transistor Q34 is connected to the bit line of the third reference unit Ck3, and the second end of the second transistor Q34 is connected to the fourth reference unit Ck4, wherein the first end of the second transistor Q34 Both the terminal and the second terminal are not the conduction control terminals of the second transistor Q34.
  • the first end of the second transistor Q34 may be the source of the second transistor Q34, and the second end of the second transistor Q34 may be the drain of the second transistor Q34, or The second end of the two transistor Q34 is the source of the second transistor Q34, and the first end of the second transistor Q34 is the drain of the second transistor Q34.
  • the input terminal of the third enable inverter F3 is connected to the bit line of the third reference cell Ck3, and the output terminal of the third enable inverter F3 is connected to the bit line of the fourth reference cell Ck4.
  • the amplified signal input terminal of the third voltage amplifier SA3 is connected to the bit line BL3 of the third memory cell 131 in the third memory cell column 130, and the reference voltage input terminal of the third voltage amplifier SA3 is connected to the third reference. Bit line of cell Ck3.
  • FIG. 5 shows that the third reference unit Ck3 and the first memory unit 111 can share the same bit line; the fourth reference unit Ck4 and the second memory unit 121 share the same bit line.
  • the architecture shown in FIG. 5 may also be adjusted such that the third reference unit Ck3 does not share the same bit line with the first storage unit 111, and/or the fourth reference unit Ck4 and the second storage unit 121 do not share the same bit. line.
  • the ferroelectric memory shown in FIG. 6 further includes a fourth memory cell column 140 compared to the ferroelectric memory shown in FIG.
  • the fourth storage unit column 140 includes at least one storage unit.
  • the fourth memory cell column 140 is illustrated in FIG. 6 as including at least one memory cell including the fourth memory cell 141.
  • the fourth storage unit 141 may be any one of the fourth storage unit columns 140.
  • the at least one storage unit included in the fourth storage unit column 140 is configured to store data, wherein each of the fourth storage unit columns 140 may include a ferroelectric capacitor and a transistor.
  • control circuit 200 can also be used to read the data stored in the fourth storage unit 141 in the fourth storage unit 140, according to the output signal of the fourth storage unit 141, and the third reference unit Ck3 and The reference voltage provided by the fourth reference unit Ck4 obtains the data stored in the fourth storage unit 141; after the data stored in the fourth storage unit 141 is read out, it is stored in the read and stored fourth storage unit 141 The data of the same value of the data is written in the third reference unit Ck2, and the data different from the value of the data stored in the read fourth storage unit 141 is written into the fourth reference unit Ck4.
  • the data with the value "1” is written after the data stored in the fourth storage unit 141 is read.
  • the fourth reference unit Ck4 is entered, and data having a value of "1” is written to the third reference unit Ck3. It is assumed that the value of the data stored in the read fourth storage unit 141 is “0”, and after the data stored in the fourth storage unit 141 is read, the data with the value “1” is written.
  • data having a value of "0” is written to the third reference unit Ck3. It can be understood that after reading the data stored in the other storage units in the fourth storage unit column 140, the data write back mechanism of the third reference unit Ck3 and the fourth reference unit Ck4 can be deduced.
  • control circuit 200 shown in FIG. 6 can further be compared to the control circuit 200 shown in FIG.
  • a fourth voltage amplifier SA4 and a fourth enable inverter F4 are included.
  • the input terminal of the fourth enable inverter F4 is connected to the bit line of the fourth reference cell Ck4, and the output terminal of the fourth enable inverter F4 is connected to the bit line of the third reference cell Ck3.
  • the amplified signal input terminal of the fourth voltage amplifier SA4 is connected to the bit line BL4 of the fourth memory cell 141 in the fourth memory cell column 140, and the reference voltage input terminal of the fourth voltage amplifier SA4 is connected to the bit line of the fourth reference cell Ck4.
  • FIG. 6 shows that the first reference unit Ck1 and the third storage unit 131 can share the same bit line.
  • the second reference unit Ck2 and the fourth storage unit 141 share the same bit line.
  • the architecture shown in FIG. 6 may also be adjusted such that the first reference unit Ck1 and the third storage unit 131 do not share the same bit line, and/or the second reference unit Ck2 and the fourth storage unit 141 do not share the same bit. line.
  • the first transistor Q12 can be a P-type field effect transistor or an N-type field effect transistor.
  • the second transistor Q34 can be a P-type field effect transistor or an N-type field effect transistor.
  • the first voltage amplifier SA1 may be a cross-coupled voltage sense amplifier or other type of voltage amplifier.
  • the second voltage amplifier SA2 can be a cross-coupled voltage sense amplifier or other type of voltage amplifier.
  • the third voltage amplifier SA3 may be a cross-coupled voltage sense amplifier or other type of voltage amplifier.
  • the fourth voltage amplifier SA4 may be a cross-coupled voltage sense amplifier or other type of voltage amplifier.
  • the field effect transistor is mainly used as an N-type field effect transistor, and of course, FIG. 2, FIG. 4, FIG. 5 and FIG. Some or all of the N-type field effect transistors in the illustrated architecture are replaced with P-type field effect transistors.
  • the connection relationship between the drain and the source of each N-type field effect transistor in the architecture shown in FIG. 2, FIG. 4, FIG. 5 and FIG. 6 is also interchangeable (ie, the drain of the N-type field effect transistor is connected The device is connected by the source of the N-type field effect transistor, and the device connected to the source of the N-type field effect transistor is connected to the drain of the N-type field effect transistor.
  • connection relationship between the drain and the source of the P-type field effect transistor is also interchangeable.
  • the difference from the architecture shown in FIG. 6 is that the connection relationship between the drain and the source of the first transistor Q12 is interchanged in the architecture shown in FIG. 7, FIG. 2, FIG. 4, and FIG. 5 and the scenario where the connection relationship between the drain and the source of other field effect transistors in the architecture shown in FIG. 6 is interchangeable.
  • the element may be a storage unit of a 1T1C type ferroelectric.
  • the storage unit of the 1T1C type ferroelectric medium is a storage unit including one triode and one ferroelectric capacitor, and one storage unit can store one bit binary number, such as storing data with a value of “0” or “1”.
  • the reference unit (for example, the third reference unit Ck3, the first reference unit Ck1, the fourth reference unit Ck4, the second reference unit Ck2, etc.) among the ferroelectric memories may be a reference unit of a 1T1C type ferroelectric.
  • the reference cell of the 1T1C type ferroelectric has a similar structure to the memory cell of the 1T1C type ferroelectric.
  • One reference cell can store a 1-bit binary number, such as storing data with a value of "0" or "1".
  • the third reference unit Ck3 and the fourth reference unit Ck4 are a pair of reference units, and one of the third reference unit Ck3 and the fourth reference unit Ck4 stores “0” and the other stores “1”.
  • the first reference unit Ck1 and the second reference unit Ck2 serve as a pair of reference units, one of the first reference unit Ck1 and the second reference unit Ck2 stores a value of “0” data, and the other storage value is “1” data.
  • the architecture shown in Fig. 8 includes a voltage amplifier SA-x and a 1T1C type ferroelectric memory cell 100.
  • the bit line BL of the memory cell 100 is connected to the amplified signal input terminal of the voltage amplifier SA-x.
  • the data writing process of the storage unit 100 can be as follows:
  • the bit line BL is at a high level
  • the word line WL is also at a high level so that the N-type field effect transistor Qx is turned on.
  • the pulse line PL changes from a low level to a high level
  • the bit line BL and the pulse line PL are both at a high level, there is no voltage difference between the upper and lower electrodes of the ferroelectric capacitor Cfe, so the residual polarization direction is not
  • the high-level pulse on the pulse line PL goes low again, and the level of the word line WL also goes from high to low, and the process of writing the value of "1" is completed.
  • the bit line BL is at a low level
  • the word line WL is also at a high level, so that the N-type field effect transistor Qx is turned on, and the pulse line PL is input to a high level.
  • the pulse is pulsed
  • the ferroelectric capacitor Cfe is negatively polarized; after the pulse line PL is pulsed high, it becomes low level. At this time, the polarization direction of the ferroelectric capacitor Cfe remains unchanged, and the value of "0" is also completed.
  • the data readout process of the memory cell 100 can be as follows: the word line WL is changed from a low level to a high level so that the N-type field effect transistor Qx is turned on, and the rising edge of the pulse signal input on the pulse line PL, the parasitic bit line BL.
  • the capacitor and the ferroelectric capacitor Cfe perform charge sharing to generate different voltage values on the bit line BL, and the voltage value generated on the bit line BL is compared with the reference voltage input from the reference voltage input terminal of the voltage amplifier SA-x.
  • the output is amplified by the voltage amplifier SA-x, and the voltage of the signal outputted after being amplified by the voltage amplifier SA-x corresponds to the value of the data stored in the memory unit 100, for example, the signal output after the voltage amplifier SA-x is amplified. If the voltage is high, it means that the value of the data stored in the read memory cell 100 is "1", and the signal outputted after the voltage amplifier SA-x is amplified is a low voltage, which means that the read memory unit 100 stores The value of the data is "0".
  • the voltage signal applied to the ferroelectric capacitor Cfe may destroy the original polarization state of the ferroelectric capacitor (destructive readout), and therefore, the pulse line PL after the end of data reading
  • the upper pulse signal changes from a high level to a low level to complete the recovery of the polarization state of the ferroelectric capacitor Cfe (ie, data write back).
  • the data writeback process after the read operation can be as follows:
  • the bit line BL is pulled to the level at which the data is read, that is, the data bit having the value "1” is read after the bit line BL is at the high level, and the data value of the value "0" is read.
  • the post bit line BL is low.
  • the write back operation of the memory unit 100 is unified so that the pulse signal on the pulse line PL is changed from the high level of the original read operation to the low level.
  • the pulse line PL is at the high level during reading, and the direction of the electric field in the ferroelectric capacitor Cfe is The ferroelectric material has the same polarization direction, and the polarization state of the central atom remains unchanged.
  • the bit line BL is at a low level (the level at which the data of the value "0" is read).
  • the pulse line PL becomes a low level, and at this time, the bit line BL is also at a low level, so the potential of the ferroelectric capacitor Cfe is the same, and there is no electric field at both ends of the ferroelectric capacitor Cfe.
  • the storage state is still in the state of storing data with a value of "0".
  • the ferroelectric material in the ferroelectric capacitor Cfe is negatively polarized, and the pulse line PL is at the high level during reading.
  • the electric field in the ferroelectric capacitor Cfe The direction is opposite to the polarization direction of the ferroelectric material, then the central atom polarization state jumps to forward polarization, and the bit line BL is read high after reading (the level when reading data with a value of "1") .
  • pulse line PL It becomes a low level, and at this time, the bit line BL is at a high level, so the potential of the ferroelectric capacitor is different at both ends, and there is an electric field from the top to the bottom direction, which is a value of "1" written to the memory cell.
  • the operation of the data so the memory unit is written back with a value of "1", which completes the data write back.
  • the 1T1C type ferroelectric reference unit having a similar structure to the 1T1C type ferroelectric memory cell, the data read The writing process is similar.
  • the 1T1C type ferroelectric dielectric reference unit is a 1T1C type ferroelectric memory unit, but the two functions in the memory are different.
  • the first reference cell Ck1 and the second reference cell Ck2 operate to provide a reference for the first memory cell column 110 or the second memory cell column 120.
  • Voltage When accessing the third memory cell column 130 or the fourth memory cell column 140, the third reference cell Ck3 and the fourth reference cell Ck4 operate to provide a reference voltage for the third memory cell column 130 or the fourth memory cell column 140.
  • the first reference unit Ck1 and the second reference unit Ck2 respectively store data having values of "0" and "1".
  • the third reference unit Ck3 and the fourth reference unit Ck4 respectively store data having values of "0" and "1".
  • the data "0" stored in the first storage unit 111 in the first storage unit column 110 is read.
  • the data readout and writeback process can be divided into 5 steps, namely: t0, t1, t2, t3, and t4.
  • the specific timing relationship can be as shown in FIG.
  • the word line WL1 of the first memory unit 111 changes from a low level to a high level, so that the N-type field effect transistor Qx1 in the first memory unit 111 is turned on to open the first memory unit.
  • the pulse line PL1 of the first memory unit 111 changes from a low level to a high level, and the ferroelectric capacitor Cfe1 performs charge sharing with the parasitic capacitance C BL1 of the first bit line BL1 (wherein the ferroelectric capacitor Cfe1 is expressed in different storage states)
  • the capacitance value of the ferroelectric capacitor Cfe1 in the state where the data of the value "0" is stored is assumed to be C 0
  • the capacitance value of the ferroelectric capacitor Cfe1 in the state where the data of the value "1" is stored is respectively For C 1 ), a voltage V 0 is generated on the first bit line BL1 (ie, the amplified signal input terminal of the first amplifier SA1).
  • V 0 C 0 * C BL1 / (C 0 + C BL1 ).
  • the gate voltage of the first transistor Q12 is flipped from a high level to a low level, and the voltage on the reference voltage input terminal BL1B of the first voltage amplifier SA1 is clamped at V ref .
  • the first voltage amplifier The level of the enable signal SAE1 of SA1 is inverted from a low level to a high level, the first voltage amplifier SA1 is enabled to start operation, and after reading, the data "0" stored by the first memory unit 111 is read out, and the first The bit line BL1 voltage is pulled low.
  • the pulse line PL1 of the memory cell 111 changes from a high level to a low level, and the stored data is written back, and the enable signal Ref_wb of the first enable inverter F1 changes from a low level to a high level.
  • the first enable inverter F1 starts to work, since the voltage of the first bit line BL1 is pulled to a low level, the reference voltage input terminal BL1B of the first voltage amplifier is at a high level, and therefore, the first reference unit Ck1
  • the bit line is also at a high level, and data with a value of "1" can be written to the first reference cell Ck1, and the bit line of the second reference cell Ck2 is also caused by the action of the first enable inverter F1. Low level, so data with a value of "0" can be written to the second reference unit Ck2.
  • the enable inverter connected between the two bit lines of the reference cell pair does not work at this time, wherein the input is enabled when the inverter is not in operation.
  • the terminals and outputs are isolated from each other.
  • FIG. 10 is a schematic diagram of a simulation of reading the value of "0" stored in the first storage unit 111 in the architecture shown in FIG. 6 or FIG.
  • a first reference unit Ck1 and a second reference unit Ck2 that provide a reference voltage for a read operation.
  • the first reference unit Ck1 prestores data "1", that is, a high level
  • the second reference unit Ck2 prestores data "0", that is, a low level
  • the pulse line PL1 is high level to read out the data "0" in the memory cell 111, and a peak (i.e., low level) lower than 2V appears on the first bit line BL1.
  • the data in the first reference unit Ck1 and the second reference unit Ck2 are read, so that the third potential line BL3 and the fourth bit line BL4 appear corresponding potential changes, as shown in the figure, the second bit line BL3 appears to be greater than 2V.
  • the fourth bit line BL4 exhibits a peak lower than 2V (ie, a low level, coincident with the first bit line BL1).
  • the first transistor Q12 is turned on, and the potentials of the third bit line BL3 and the fourth bit line BL4 are jumped to the same height (ie, the potential height at the indication of the operating point of the first voltage amplifier SA1), that is, the reference potential is formed.
  • the potential of the first bit line BL1 jumps to 0V, that is, the data "0" is read.
  • the potential of the third bit line BL3 jumps to a high level VDD, and the potential of the fourth bit line BL4 jumps to 0V due to the action of the first enable inverter F1.
  • the level of the amplified signal input terminal of the first voltage amplifier SA1 and the first bit line BL1 is pulled to 0 V, and the reference voltage input of the first voltage amplifier SA1 is input.
  • the potential of the bit line directly connected to the first reference unit Ck1 (the bit line of the first reference unit Ck1 is connected to the third bit line BL3) is pulled to the high level VDD, and the bit line of the second reference unit Ck1 (the The bit line of the second reference cell Ck2 is connected to the fourth bit line BL4) is connected to the bit line of the first reference cell Ck1 through the first enable inverter F1, so the potential of the fourth bit line BL4 is also 0V.
  • the level signals on the third bit line BL3 and the fourth bit line BL4 can be directly used for data write back to the first reference unit Ck1 and the second reference unit Ck2.
  • the data "0" is read from the memory cells 111 in the first memory cell column 110.
  • the amplified signal input terminal of the first voltage amplifier SA1 is pulled to a low level, which is consistent with the level corresponding to the read data.
  • the reference voltage input of the first voltage amplifier SA1 is pulled high, opposite the level corresponding to the read data.
  • the first voltage amplifier SA1 is referenced to the voltage input terminal directly to the first reference unit Ck1
  • the bit lines are connected, and the first voltage amplifier SA1 reference voltage input is connected to the bit line of the second reference unit Ck2 through the first enable inverter F1.
  • the data write-back signal on the bit line of the first reference unit Ck1 is at a high level, so that data with a value of "1" is written back thereto; the data write-back signal on the bit line of the second reference unit Ck2 is Low level, so write back the data with the value "0". If the memory unit 111 reads out the data "1", the data write back situation for a reference unit Ck1 and the second reference unit Ck2 is reversed, and the first reference unit Ck1 will be written back with data having a value of "0"; The second reference unit Ck2 is written back with data having a value of "1".
  • the first reference unit Ck2 and the second reference unit Ck4 are written back, depending on the value of the data stored in the storage unit that supplies the reference voltage, and the value of the data stored in the storage unit is regarded as random. Then, the write-back state of the first reference unit Ck1 and the second reference unit Ck2 is also random, and this is completely different from the mechanism in which the value of the data stored in the conventional reference unit is always fixed.
  • the data write back mechanism of the third reference unit Ck3 and the fourth reference unit Ck4 is similar. Therefore, the architecture of the present invention greatly improves the disadvantages of uneven ferroelectric capacitance inversion fatigue in the reference unit, and is advantageous for improving overall performance.
  • the ferroelectric memory provided by the embodiment of the present invention includes a first storage unit column, a first reference unit, a second reference unit, and a control circuit; wherein the first storage unit column includes at least one storage unit; the first reference unit And the second reference unit is configured to provide a reference voltage; wherein the control circuit is configured to, when reading the data stored in the first storage unit in the first storage unit column, according to the reference voltage and the output signal of the first storage unit, Obtaining data stored in the first storage unit; after reading the data stored by the first storage unit, writing data different from the value of the foregoing data into the first reference unit, and The data of the same value of the above-mentioned data stored in a storage unit is written into the second reference unit.
  • the data stored in the first storage unit After the data stored in the first storage unit is read, data different from the value of the data is written into the first reference unit, and the data stored in the first storage unit is read.
  • the data of the same value is written into the second reference unit, that is, the write-back state of the first reference unit and the second reference unit is stored according to the value of the data stored in the storage unit that supplies the reference voltage.
  • the value of the data stored in the unit is regarded as random, and the write-back status of the first reference unit and the second reference unit is also random, that is, whether the reference unit stores "0" or "1" is
  • the data randomly read by the storage unit determines that the probability of storing "0" in each reference unit is usually equal to the probability of storing "1", and this is consistent with the mechanism of the value of the data stored in the conventional reference unit. It is completely different, and the architecture of the present invention is advantageous for well-balanced read and write fatigue of two reference units in a reference unit pair providing reference signals, which is advantageous for greatly improving the fatigue resistance of the reference unit.
  • the timing limitation between the reference unit and the write back of the storage unit is released, so that the reference unit and the storage unit can simultaneously perform a data write-back operation, which is beneficial to improving the data write-back efficiency of the reference unit and the storage unit, thereby facilitating comparison Greatly shorten the read and write cycles of the memory.
  • one storage unit column (for example, the first storage unit column, the second storage unit column, the third storage unit column, or the fourth storage unit column) mentioned in each embodiment of the present invention may refer to a physics.
  • the storage unit on the same column is processed in a location, and may also include a storage unit set formed by a plurality of storage units sharing the same bit line, or may also be a plurality of storage units having certain common features divided based on other attributes. A set of storage units formed.
  • the disclosed apparatus may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical or otherwise.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold as a standalone product Or when used, it can be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk, and the like. .

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Abstract

一种铁电存储器，可包括：第一存储单元列（110）、第一参考单元（Ck1）、第二参考单元（Ck2）和控制电路（200）；第一参考单元（Ck1）和第二参考单元（Ck2）用于提供参考电压；控制电路（200），用于在读取第一存储单元列（110）中的第一存储单元（111）中所存储数据时，根据参考电压与第一存储单元（111）的输出信号，获得第一存储单元（111）中所存储的数据；在读取出了第一存储单元（111）所存储的数据之后，将与数据的取值不同的数据写入第一参考单元（Ck1），并将与读取的第一存储单元（111）中所存储的数据的取值相同的数据写入第二参考单元（Ck2）。提供的铁电存储器有利于提高参考单元与存储单元的数据回写效率，均衡参考单元对中的两个参考单元的读写疲劳度。

Description

一种铁电存储器 技术领域
本发明涉及存储技术领域，具体涉及一种铁电存储器。
背景技术
铁电存储器是一种新型非挥发存储器件。铁电存储器利用铁电材料中的自发极化现象实现二值数据的存储。
铁电存储器中包含参考单元和存储单元，其中，参考单元为存储单元的数据读写提供参考电压信号。现有铁电存储器中，每对参考单元中的两个参考单元的读写疲劳度差异很大，严重影响参考单元整体寿命。
发明内容
本发明实施例提供一种铁电存储器，以期均衡参考单元对中的两个参考单元的读写疲劳度。
本发明实施例第一方面提供一种铁电存储器，可包括：
第一存储单元列、第一参考单元、第二参考单元和控制电路；
所述第一存储单元列包括至少一个存储单元，所述至少一个存储单元用于存储数据，其中，每个存储单元中包括一个铁电电容以及一个晶体管；
所述控制电路与所述第一参考单元、所述第二参考单元以及所述第一存储单元列中的存储单元连接；
所述第一参考单元和第二参考单元用于提供参考电压，其中，每个参考单元中包括一个铁电电容以及一个晶体管，所述第一参考单元与所述第二参考单元中存储的数据的取值不同；
所述控制电路，用于在读取所述第一存储单元列中的第一存储单元中存储的数据时，根据所述参考电压与所述第一存储单元的输出信号获得所述第一存储单元中存储的数据；在读取所述第一存储单元中存储的数据之后，将与读取的数据的取值不同的数据写入所述第一参考单元，并将与读取的数据的取值相同的数据写入所述第二参考单元。
结合第一方面，在第一方面的第一种可能的实施方式中，所述控制电路包括第一电压放大器、第一三极管和第一使能反相器；
所述第一三极管的第一端连接所述第一参考单元的位线，所述第一三极管的第二端连接所述第二参考单元的位线，其中，所述第一三极管的第一端和第二端均不是所述第一三极管的导通控制端；
所述第一使能反相器的输入端连接所述第一参考单元的所述位线，所述第一使能反相器的输出端连接所述第二参考单元的位线；
所述第一电压放大器的放大信号输入端连接所述第一存储单元的位线，所述第一电压放大器的参考电压输入端连接所述第一参考单元的所述位线。
结合第一方面或第一方面的第一种可能的实施方式，在第一方面的第二种可能的实施方式中，所述第一存储单元列包含多个存储单元，所述第一存储单元列中的所述多个存储单元共用相同的位线。
结合第一方面或第一方面的第一种可能的实施方式或第一方面的第二种可能的实施方式，在第一方面的第三种可能的实施方式中，所述铁电存储器还包括：
第二存储单元列，其中，所述第二存储单元列包括至少一个存储单元；所述控制电路与所述第二存储单元列中的存储单元连接；所述第二存储单元列包括的所述至少一个存储单元用于存储数据，其中，所述第二存储单元列中的每个存储单元中包括一个铁电电容以及一个晶体管；
所述控制电路，还用于在读取所述第二存储单元列中的第二存储单元中存储的数据时，根据所述参考电压与所述第二存储单元的输出信号获得所述第二存储单元中所存储的数据；在读取所述第二存储单元中存储的数据之后，将与读取的所述第二存储单元中存储的数据的取值不同的数据写入所述第二参考单元，并将与读取的所述第二存储单元中存储的数据的取值相同的数据写入所述第一参考单元。
结合第一方面的第三种可能的实施方式，在第一方面的第四种可能的实施方式中，所述控制电路还包括：第二电压放大器和第二使能反相器；
所述第二使能反相器的输入端连接所述第二参考单元的位线，所述第二使 能反相器的输出端连接所述第一参考单元的位线；所述第二电压放大器的放大信号输入端连接所述第二存储单元的位线，所述第二电压放大器的参考电压输入端连接所述第二参考单元的所述位线。
结合第一方面的第三种可能的实施方式或第一方面的第四种可能的实施方式，在第一方面的第五种可能的实施方式中，所述第二存储单元列包含多个存储单元，所述第二存储单元列中的所述多个存储单元共用相同的位线。
结合第一方面的第一种可能的实施方式或者第一方面的第二种可能的实施方式或者第一方面的第三种可能的实施方式或者第一方面的第四种可能的实施方式或者第一方面的第五种可能的实施方式，在第一方面的第六种可能的实施方式中，所述铁电存储器还包括：第三存储单元列、第三参考单元和第四参考单元；
其中，所述第三存储单元列包括至少一个存储单元，所述第三存储单元列包括的所述至少一个存储单元用于存储数据，其中，所述第三存储单元列中的每个存储单元中包括一个铁电电容以及一个晶体管；
所述第三参考单元和所述第四参考单元用于提供参考电压，其中，所述第三参考单元和所述第四参考单元中的每个参考单元中包括一个铁电电容以及一个晶体管，所述第三参考单元与所述第四参考单元中存储的数据的取值不同；
所述控制电路还可用于，在读取所述第三存储单元列中的第三存储单元中所存储的数据时，根据所述第三存储单元的输出信号，以及所述第三参考单元和第四参考单元提供的参考电压，获得所述第三存储单元中所存储的数据；在读取所述第三存储单元所存储的数据后，将与读取的所述第三存储单元中所存储的所述数据的取值相同的数据写入所述第四参考单元，将与读取的所述第三存储单元中所存储的所述数据的取值不同的数据写入所述第三参考单元。
结合第一方面的第六种可能的实施方式，在第一方面的第七种可能的实施方式中，所述控制电路还包括：第三电压放大器、第二三极管和第三使能反相器；
其中，所述第二三极管的第一端连接所述第三参考单元的位线，所述第二 三极管的第二端连接所述第四参考单元的位线，其中，所述第二三极管的第一端和第二端均不是所述第二三极管的导通控制端；
所述第三使能反相器的输入端连接所述第三参考单元的所述位线，所述第三使能反相器的输出端连接所述第四参考单元的位线；
所述第三电压放大器的放大信号输入端连接所述第三存储单元列中的第三存储单元的位线，所述第三电压放大器的参考电压输入端连接所述第三参考单元的所述位线。
结合第一方面的第六种可能的实施方式或第一方面的第七种可能的实施方式，在第一方面的第八种可能的实施方式中，
所述铁电存储器还包括第四存储单元列，
其中，所述第四存储单元列包括至少一个存储单元，所述第四存储单元列包括的所述至少一个存储单元用于存储数据，其中，所述第四存储单元列中的每个存储单元中包括一个铁电电容以及一个晶体管；
所述控制电路，还用于在读取所述第四存储单元列中的第四存储单元中存储的数据时，根据所述第四存储单元的输出信号，以及所述第三参考单元和第四参考单元提供的参考电压，获得所述第四存储单元中所存储的数据；在读取所述第四存储单元中存储的数据之后，将与读取的所述第四存储单元中存储的数据的取值不同的数据写入所述第四参考单元，并将与读取的所述第四存储单元中存储的数据的取值相同的数据写入所述第三参考单元。
结合第一方面的第八种可能的实施方式，在第一方面的第九种可能的实施方式中，所述控制电路还包括第四电压放大器和第四使能反相器；
所述第四使能反相器的输入端连接所述第四参考单元的位线，所述第四使能反相器的输出端连接所述第三参考单元的位线；
所述第四电压放大器的放大信号输入端连接所述第四存储单元列中的第四存储单元的位线，所述第四电压放大器的参考电压输入端连接所述第四参考单元的所述位线。
结合第一方面的第九种可能的实施方式，在第一方面的第十种可能的实施方式中，所述第三参考单元与所述第一存储单元共用相同的位线；并且，所述 第四参考单元与所述第二存储单元共用相同的位线。
结合第一方面的第九种可能的实施方式或第一方面的第十种可能的实施方式，在第一方面的第十一种可能的实施方式中，所述第一参考单元与所述第三存储单元共用相同位线；并且所述第二参考单元与所述第四存储单元共用相同的位线。
可以看出，本发明实施例提供的技术方案中，由于在读取出第一存储单元所存储的数据后，将与该数据的取值不同的数据写入第一参考单元，并将与读取的第一存储单元中所存储的上述数据的取值相同的数据写入第二参考单元，也就是说，第一参考单元和第二参考单元的回写状态，取决于其提供参考电压的存储单元中所存储数据的取值，而存储单元中所存储数据的取值看成是随机的，那么第一参考单元和第二参考单元的回写状态也是随机的，这与传统的参考单元中所存数据的取值一直固定的机制完全不同，可见本发明实施提供的铁电存储器架构有利于较好的均衡提协同供参考信号的参考单元对中的两个参考单元的读写疲劳度，有利于极大提高参考单元的抗疲劳特性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种铁电存储器的架构示意图；
图2是本发明实施例提供的另一种铁电存储器的架构示意图；
图3是本发明实施例提供的另一种铁电存储器的架构示意图；
图4是本发明实施例提供的另一种铁电存储器的架构示意图；
图5是本发明实施例提供的另一种铁电存储器的架构示意图；
图6是本发明实施例提供的另一种铁电存储器的架构示意图；
图7是本发明实施例提供的另一种铁电存储器的架构示意图；
图8是本发明实施例提供的一种ITIC型的铁电介质的存储单元的示意图；
图9是本发明实施例提供的一种第一存储单元111的数据读写时序示意图；
图10是本发明实施例提供的一种第一存储单元111的数据读写的仿真示意图。
具体实施方式
本发明实施例提供一种铁电存储器，以期提高参考单元与存储单元的数据回写效率，均衡参考单元对中的两个参考单元的读写疲劳度。
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
以下分别进行详细说明。
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”“第四”等是用于区别不同的对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
目前，市场上对存储器的高密度、高速度、低功耗、长寿命等方面的要求日益苛刻，传统的半导体存储器已无法满足完全满足要求，基于新介质的非挥发性存储器，是解决上述问题的重要途径之一。铁电介质便是其中较为成熟的新介质材料之一。其中，本发明实施例的举例方案中主要以存储单元为铁电介质的存储单元为例，以参考单元为铁电介质的参考单元为例。
参见图1，图1是本发明实施例提供的一种铁电存储器的结构示意图，如图1所示的铁电存储器可包括：第一存储单元列110、第一参考单元Ck1、第二参考单元Ck2和控制电路200。
其中，所述第一存储单元列110包括至少一个存储单元，其中，第一存储单元列110包括的上述至少一个存储单元用于存储数据，其中，所述第一存储单元列110中的每个存储单元中可包括一个铁电电容以及一个晶体管。
图1中举例示出第一存储单元列110包括包含第一存储单元111在内的至少一个存储单元。其中，第一存储单元111可为第一存储单元列110中的任意一个存储单元。
控制电路200与第一参考单元Ck1、第二参考单元Ck2以及第一存储单元列110中的存储单元连接。其中，第一参考单元Ck1和第二参考单元Ck2中每个参考单元中可包括一个铁电电容以及一个晶体管。
其中，第一参考单元Ck1和第二参考单元Ck2用于提供参考电压。
其中，第一参考单元Ck1与第二参考单元Ck2中所存储数据的取值不同。
其中，控制电路200，用于在读取所述第一存储单元110列中的第一存储单元111中所存储数据时，根据所述参考电压与所述第一存储单元111的输出信号，获得所述第一存储单元111中所存储的数据；在读取出了所述第一存储单元111所存储的数据之后，将与读取的所述第一存储单元111中所存储的所述数据的取值相同的数据写入第二参考单元Ck2，并将与读取的第一存储单元111中所存储的所述数据的取值不同的数据写入第一参考单元Ck1。
例如假设读取的第一存储单元111中所存储的数据的取值为“1”，则在读取出了第一存储单元111所存储的数据之后，将取值为“1”的数据写入第二参考单元Ck2，并将取值为“0”的数据写入第一参考单元Ck1。假设，读取的第一存储单元111中所存储的数据的取值为“0”，则在读取出了第一存储单元111所存储的数据之后，将取值为“0”的数据写入第二参考单元Ck2，将取值为“1”的数据写入第一参考单元Ck1。可以理解，读取第一存储单元列110中的其它存储单元中所存储数据之后，第一参考单元Ck1和第二参考单元Ck2的数据回写机制可以此类推。
可以看出，由于在读取出第一存储单元所存储的数据之后，将与该数据的取值不同的数据写入第一参考单元，并将与读取的第一存储单元中所存储的上述数据的取值相同的数据写入第二参考单元，也就是说，第一参考单元和第二参考单元的回写状态，取决于其提供参考电压的存储单元中所存储数据的取值，而存储单元中所存储数据的取值看成是随机的，那么第一参考单元和第二参考单元的回写状态也是随机的，即是说，参考单元中存“0”还是存“1”是 由存储单元随机读出的数据决定，每个参考单元中存“0”的概率通常约等于存“1”的概率，而这与传统的参考单元中所存数据的取值一直固定的机制是完全不同的，在传统机制中，协同提供参考信号的每对参考单元中的两个参考单元中存储的数据取值不同，且其中一个固定存储取值为“1”的数据，另一个固定存储取值为“0”的数据，而每次读取完参考单元中存储数据之后，需要向该参考单元回写从该参考单元所读取的数据，例如若参考单元中存储了取值为“1”的数据，在该参考单元回写时需向该参考单元写入取值为“1”的数据，若参考单元中存储了取值为“0”的数据，则在该参考单元回写时需向该参考单元写入取值为“0”的数据，而这就造成了固定存储“1”的那个参考单元的疲劳度会相对较大，本发明架构有利于很好的均衡提供参考信号的参考单元对中的两个参考单元的读写疲劳度，进而有利于极大的提高参考单元的抗疲劳特性。
其中，控制电路200的结构可能是多种多样的。
例如参见图2，图2举例示出了一种可能的控制电路200的结构。
其中，图2所示的控制电路200可包括第一电压放大器SA1、第一三极管Q12和第一使能反相器F1。
其中，第一三极管Q12的第一端连接第一参考单元Ck1的位线，第一三极管Q12的第二端连接所述第二参考单元Ck1的位线，其中，第一三极管Q12的第一端和第二端均不是第一三极管Q12的导通控制端(例如栅极)。例如，第一三极管Q12的第一端可为第一三极管Q12的源极，并且第一三极管Q12的第二端可为第一三极管Q12的漏极，或第一三极管Q12的第二端为第一三极管Q12的源极，并且第一三极管Q12的第一端为第一三极管Q12的漏极。
第一使能反相器F1的输入端连接第一参考单元Ck1的所述位线，第一使能反相器F1的输出端连接第二参考单元Ck2的位线。
其中，第一电压放大器SA1的放大信号输入端连接第一存储单元111的位线BL1(可称第一位线)，第一电压放大器SA1的参考电压输入端连接第一参考单元Ck1的位线。
可选的，第一存储单元列110中的部分或者全部存储单元可共用相同的位 线，例如第一存储单元111可以与第一存储单元列110中的其它一个或者多个存储单元共用相同的位线。
参见图3，在本发明的一些实施例中，上述铁电存储器还包括第二存储单元列120。
其中，控制电路200与第二存储单元列120中的存储单元连接。
其中，第二存储单元列120包括至少一个存储单元。其中，第二存储单元列120包括的上述至少一个存储单元用于存储数据，其中，所述第二存储单元列120中的每个存储单元中可包括一个铁电电容以及一个晶体管。
图3中举例示出第二存储单元列120中包括包含第三存储单元121在内的至少一个存储单元。其中，第二存储单元121可为第二存储单元列120中的任意一个存储单元。
其中，控制电路200还可用于，在读取第二存储单元列120中的第二存储单元121中所存储数据时，根据第二存储单元121的输出信号，以及第一参考单元Ck1和第二参考单元Ck2所提供的参考电压，获得第二存储单元121中所存储的数据；在读取出了第二存储单元121所存储的数据之后，将与读取的第二存储单元121中所存储的数据的取值相同的数据写入第一参考单元Ck1，并将与读取的第二存储单元121中所存储的数据的取值不同的数据写入第二参考单元Ck2。
例如假设读取的第二存储单元121中所存储的数据的取值为“1”，则在读取出了第二存储单元121所存储的数据之后，将取值为“1”的数据写入第一参考单元Ck1，并将取值为“0”的数据写入第二参考单元Ck2。假设，读取的第二存储单元121中所存储的数据的取值为“0”，则在读取出了第二存储单元121所存储的数据之后，将取值为“0”的数据写入第一参考单元Ck1，将取值为“1”的数据写入第二参考单元Ck2。可以理解，读取第二存储单元列120中的其它存储单元中所存储数据之后，第一参考单元Ck1和第二参考单元Ck2的数据回写机制可以此类推。
可以看出，协同提供参考信号的一对参考单元可为两列存储单元列中的存储单元提供参考信号。在读取出第二存储单元所存储的数据后，将与该数据的 取值不同的数据写入第二参考单元，并将与读取的第二存储单元中所存储的上述数据的取值相同的数据写入第一参考单元，也就是说，第一参考单元和第二参考单元的回写状态，仍然取决于其提供参考电压的存储单元中所存储数据的取值，而第一存储单元列110或第二存储单元列120中的各存储单元中所存储数据的取值看成是随机的，那么第一参考单元和第二参考单元的回写状态也是随机的，即是说，参考单元中存“0”还是存“1”是由存储单元随机读出的数据决定，协同提供参考信号的一对参考单元中的每个参考单元中存“0”的概率通常约等于存“1”的概率，而这与传统的每个参考单元中所存储数据的取值一直固定的机制是完全不同的，因此上述架构有利于很好的均衡提供参考信号的参考单元对中的两个参考单元的读写疲劳度，有利于极大提高参考单元的抗疲劳特性。
进一步的，参见图4，图4示出了另一种可能的控制电路200的结构。
其中，相比于图2所示的控制电路200，图4所示的控制电路200还进一步包括第二电压放大器SA2和第二使能反相器F2。
第二使能反相器F2的输入端连接第二参考单元Ck2的位线，第二使能反相器F2的输出端连接第一参考单元Ck1的位线。第二电压放大器SA2的放大信号输入端连接第二存储单元121的位线BL2，第二电压放大器SA2的参考电压输入端连接所述第二参考单元Ck2的位线。
可选的，第二存储单元列120中的部分或者全部存储单元可共用相同的位线，例如第二存储单元121可以与第二存储单元列120中的其它一个或者多个存储单元共用相同的位线。
参见图5，可选的，所述铁电存储器还可包括第三存储单元列130、第三参考单元Ck3和第四参考单元Ck4。其中，第三参考单元Ck3和第四参考单元Ck4用于提供参考电压。
其中，第三存储单元列130包括至少一个存储单元。图5中举例示出第三存储单元列130包括包含第三存储单元131在内的至少1个存储单元。第三存储单元131可为第三存储单元列130中的任意一个存储单元。其中，第三存储单元列130包括的上述至少一个存储单元用于存储数据，其中，所述第三存储单元列 130中的每个存储单元中可包括一个铁电电容以及一个晶体管。
类似的，控制电路200还可用于，在读取第三存储单元130列中的第三存储单元131中所存储数据时，根据第三存储单元131的输出信号，以及第三参考单元Ck3和第四参考单元Ck4提供的参考电压，获得第三存储单元131中所存储的数据；在读取出了第三存储单元131所存储的数据后，将与读取的第三存储单元131中所存储的所述数据的取值相同的数据写入第四参考单元Ck4，将与读取的第三存储单元131中所存储的所述数据的取值不同的数据写入第三参考单元Ck3。
例如假设读取的第三存储单元131中所存储的数据的取值为“1”，则在读取出了第三存储单元131所存储的数据之后，将取值为“1”的数据写入第四参考单元Ck4，并将取值为“0”的数据写入第三参考单元Ck3。假设，读取的第三存储单元131中所存储的数据的取值为“0”，则在读取出了第三存储单元131所存储的数据之后，将取值为“0”的数据写入第四参考单元Ck4，将取值为“1”的数据写入第三参考单元Ck3。可以理解，读取第三存储单元列130中的其它存储单元中所存储数据之后，第三参考单元Ck3和第四参考单元Ck4的数据回写机制可以此类推。
其中，相比于图4所示的控制电路200，图5所示的控制电路200还进一步包括第三电压放大器SA3、第二三极管Q34和第三使能反相器F3。
其中，第二三极管Q34的第一端连接第三参考单元Ck3的位线，第二三极管Q34的第二端连接第四参考单元Ck4，其中，第二三极管Q34的第一端和第二端均不是第二三极管Q34的导通控制端。例如，第二三极管Q34的第一端可为第二三极管Q34的源极，并且第二三极管Q34的第二端可为第二三极管Q34的漏极，或，第二三极管Q34的第二端为第二三极管Q34的源极，并且第二三极管Q34的第一端为第二三极管Q34的漏极。
第三使能反相器F3的输入端连接第三参考单元Ck3的位线，第三使能反相器F3的输出端连接第四参考单元Ck4的位线。
第三电压放大器SA3的放大信号输入端连接第三存储单元列130中的第三存储单元131的位线BL3，第三电压放大器SA3的参考电压输入端连接第三参考 单元Ck3的位线。
其中，图5示出第三参考单元Ck3与第一存储单元111可共用相同的位线；第四参考单元Ck4与第二存储单元121共用相同的位线。当然，也可调整图5所示架构，使得第三参考单元Ck3与第一存储单元111不共用相同的位线，和/或，第四参考单元Ck4与第二存储单元121不共用相同的位线。
进一步的，参见图6，相比于图5所示的铁电存储器，图6所示的铁电存储器还进一步包括第四存储单元列140。
其中，所述第四存储单元列140包括至少一个存储单元。图6中举例示出第四存储单元列140包括包含第四存储单元141在内的至少1个存储单元。第四存储单元141可为第四存储单元列140中的任意一个存储单元。其中，第四存储单元列140包括的上述至少一个存储单元用于存储数据，其中，第四存储单元列140中的每个存储单元中可包括一个铁电电容以及一个晶体管。
类似的，控制电路200还可用于，在读取第四存储单元140列中的第四存储单元141中所存储数据时，根据第四存储单元141的输出信号，以及第三参考单元Ck3和第四参考单元Ck4提供的参考电压，获得第四存储单元141中所存储的数据；在读取出了第四存储单元141所存储的数据后，将与读取的第四存储单元141中所存储的所述数据的取值相同的数据写入第三参考单元Ck2，将与读取的第四存储单元141中所存储的所述数据的取值不同的数据写入第四参考单元Ck4。
例如假设读取的第四存储单元141中所存储的数据的取值为“1”，则在读取出了第四存储单元141所存储的数据之后，将取值为“1”的数据写入第四参考单元Ck4，并将取值为“1”的数据写入第三参考单元Ck3。假设，读取的第四存储单元141中所存储的数据的取值为“0”，则在读取出了第四存储单元141所存储的数据之后，将取值为“1”的数据写入第四参考单元Ck4，将取值为“0”的数据写入第三参考单元Ck3。可以理解，读取第四存储单元列140中的其它存储单元中所存储数据之后，第三参考单元Ck3和第四参考单元Ck4的数据回写机制可以此类推。
其中，相比于图5所示的控制电路200，图6所示的控制电路200还可进一步 包括第四电压放大器SA4和第四使能反相器F4。
第四使能反相器F4的输入端连接所述第四参考单元Ck4的位线，第四使能反相器F4的输出端连接第三参考单元Ck3的位线。第四电压放大器SA4的放大信号输入端连接第四存储单元列140中的第四存储单元141的位线BL4，第四电压放大器SA4的参考电压输入端连接第四参考单元Ck4的位线。
其中，图6示出第一参考单元Ck1与第三存储单元131可共用相同的位线。第二参考单元Ck2与第四存储单元141共用相同的位线。当然，也可调整图6所示架构，使得第一参考单元Ck1与第三存储单元131不共用相同的位线，和/或，第二参考单元Ck2与第四存储单元141不共用相同的位线。
其中，第一三极管Q12可为P型场效应三极管或N型场效应三极管。
其中，第二三极管Q34可为P型场效应三极管或N型场效应三极管。
可选的，第一电压放大器SA1可为交叉耦合型电压灵敏放大器或其它类型的电压放大器。第二电压放大器SA2可为交叉耦合型电压灵敏放大器或其它类型的电压放大器。第三电压放大器SA3可为交叉耦合型电压灵敏放大器或其它类型的电压放大器。第四电压放大器SA4可为交叉耦合型电压灵敏放大器或其它类型的电压放大器。
需要说明的是，图2、图4、图5和图6所示架构中主要以各场效应三极管为N型场效应三极管为例，当然亦可将图2、图4、图5和图6所示架构中的部分或全部N型场效应三极管替换为P型场效应三极管。图2、图4、图5和图6所示架构中的各N型场效应三极管的漏极和源极的连接关系也可互换(即可将N型场效应三极管的漏极所连接的器件改由N型场效应三极管的源极连接，将N型场效应三极管的源极所连接的器件改由N型场效应三极管的漏极连接)，若将N型场效应三极管替换为P型场效应三极管，则P型场效应三极管的漏极和源极的连接关系也可互换。例如图7所示，与图6所示架构的区别在于，图7所示架构中将第一三极管Q12的漏极和源极的连接关系进行了互换，图2、图4、图5和图6所示架构中的其它场效应三极管的漏极和源极的连接关系互换的场景可以此类推。
其中，上述铁电存储器中的部分或全部存储单元列中的部分或全部存储单 元可为1T1C型的铁电介质的存储单元。其中，1T1C型的铁电介质的存储单元为包含1个三极管和一个铁电介质电容的存储单元，一个存储单元可存储一位二进制数，如存储取值为“0”或“1”的数据。
其中，铁电存储器之中的参考单元(例如第三参考单元Ck3、第一参考单元Ck1、第四参考单元Ck4、第二参考单元Ck2等)可为1T1C型的铁电介质的参考单元。1T1C型的铁电介质的参考单元与1T1C型的铁电介质的存储单元具有类似结构，一个参考单元可存储1位二进制数，如存储取值为“0”或“1”的数据。
其中，第三参考单元Ck3和第四参考单元Ck4作为一对参考单元，第三参考单元Ck3和第四参考单元Ck4中的其中1个存储“0”，另一个存储“1”。第一参考单元Ck1和第二参考单元Ck2作为一对参考单元，第一参考单元Ck1和第二参考单元Ck2中的其中一个存储取值为“0”数据，另一个存储取值为“1”数据。
为便于更好理解1T1C型铁电介质的存储单元的工作原理，下面对1T1C型铁电介质的存储单元的数据读写机制进行简单介绍。参见图8，图8所示架构包括1个电压放大器SA-x和1个1T1C型的铁电介质的存储单元100，存储单元100的位线BL连接到电压放大器SA-x的放大信号输入端。
其中，存储单元100的数据写入过程可以如下：
例如图8所示，当需向存储单元100写入取值为“1”数据时，位线BL为高电平，字线WL也为高电平使得N型场效应三极管Qx导通，此时，脉冲线PL由低电平变为高电平，由于位线BL和脉冲线PL均为高电平，因此，铁电电容Cfe上下电极之间没有电压差，因此其剩余极化方向不变；脉冲线PL上的高电平脉冲过后又变为低电平，字线WL的电平也由高变低，写入取值为“1”数据的过程完毕。
当需要向存储单元100写入取值为“0”数据时，位线BL为低电平，字线WL也为高电平使得N型场效应三极管Qx导通，脉冲线PL输入高电平脉冲时对铁电电容Cfe进行负向极化；脉冲线PL高电平脉冲过后变为低电平，此时铁电电容Cfe极化方向保持不变，同样可完成取值为“0”数据的写入。
存储单元100的数据读出过程可如下：字线WL由低电平变为高电平使得N型场效应三极管Qx导通，在脉冲线PL输入的脉冲信号的上升沿，位线BL的寄生电容和铁电电容Cfe进行电荷分享，以在位线BL上产生不同电压值，而位线BL上产生的该电压值将与电压放大器SA-x的参考电压输入端输入的参考电压进行比较后，经电压放大器SA-x进行放大后输出，经电压放大器SA-x放大之后输出的信号的电压大小与存储单元100所存储数据的取值对应，例如，电压放大器SA-x放大之后输出的信号为高电压，则可表示读出的存储单元100所存储数据的取值为“1”，经电压放大器SA-x放大之后输出的信号为低电压，则可表示读出的存储单元100所存储数据的取值为“0”。
在读出存储单元100中所存数据过程中，加在铁电电容Cfe上的电压信号可能会破坏铁电电容原来的极化状态(破坏性读出)，因此，数据读出结束后脉冲线PL上的脉冲信号由高电平变为低电平，以完成对铁电电容Cfe的极化状态的恢复(即数据回写)。
读操作后的数据回写过程可如下：
在数据读取完后，位线BL被拉到读出数据时的电平，即取值为“1”的数据读出后位线BL为高电平，取值为“0”的数据读出后位线BL为低电平。存储单元100回写操作统一为，脉冲线PL上的脉冲信号由原来读操作的高电平跳变为低电平。
由于在存储取值为“0”的数据的状态下，铁电电容Cfe中的铁电材料正向极化，读取时脉冲线PL为高电平，此时铁电电容Cfe中电场方向与铁电材料极化方向一致，那么中心原子极化状态不变，数据读出后，位线BL为低电平(读出取值为“0”的数据时的电平)。读出之后再进行回写时，脉冲线PL变为低电平，而此时位线BL也为低电平，因此铁电电容Cfe两端电势相同，铁电电容Cfe两端无电场，因此存储状态仍处于存储取值为“0”的数据的状态。
而在存储取值为“1”的数据的状态之下，铁电电容Cfe中的铁电材料负向极化，读取时脉冲线PL为高电平，此时，铁电电容Cfe中电场方向与铁电材料极化方向相反，那么中心原子极化状态跳变为正向极化，读出后位线BL为高电平(读出取值为“1”的数据时的电平)。读出之后再进行回写，脉冲线PL 变为低电平，而此时，位线BL为高电平，因此铁电电容两端电势不同，存在由上到下方向的电场，这是对存储单元写入取值为“1”的数据的操作，因此存储单元被回写了取值为“1”数据，这就完成了数据回写。
以上是结合图8对1T1C型的铁电介质的存储单元的读写工作原理进行了举例介绍，对于与1T1C型的铁电介质的存储单元具有类似结构的1T1C型的铁电介质的参考单元，其数据读写过程与之类似，从本质上讲，1T1C型的铁电介质的参考单元就是一种1T1C型的铁电介质的存储单元，只是两者在存储器中所发挥的作用不同而已。
下面介绍一下图2、图4、图5、图6和图7所示的架构的铁电存储器的工作原理。
其中，由于同一时刻只对某列存储单元列进行访问，因此在访问某列存储单元列中的存储单元时，其它存储单元列中的存储单元处于非访问状态(存储单元在非访问状态下的字线和脉冲线处于无效状态)。
举例来说，当访问第一存储单元列110或第二存储单元列120时，第一参考单元Ck1和第二参考单元Ck2工作，以为第一存储单元列110或第二存储单元列120提供参考电压。当访问第三存储单元列130或第四存储单元列140时，第三参考单元Ck3和第四参考单元Ck4工作，以为第三存储单元列130或第四存储单元列140提供参考电压。其中，第一参考单元Ck1和第二参考单元Ck2分别存储取值为“0”和“1”的数据。第三参考单元Ck3和第四参考单元Ck4分别存储取值为“0”和“1”的数据。
以读出第一存储单元列110中的第一存储单元111所存数据“0”为例。数据读出及回写过程分可为5个阶，即：t0、t1、t2、t3、t4，具体时序关系可如图9所示。
其中，t0阶段，第一存储单元111的字线WL1由低电平变为高电平，使得第一存储单元111中的N型场效应三极管Qx1导通，以打开第一存储单元。第一存储单元111的脉冲线PL1由低电平变为高电平，铁电电容Cfe1与第一位线BL1的寄生电容CBL1进行电荷分享(其中，铁电电容Cfe1在不同存储状态下表现出不同电容值，假设存储取值为“0”的数据的状态下的铁电电容Cfe1的电容值 为C0，存储取值为“1”的数据的状态下铁电电容Cfe1的电容值分别为C1)，在第一位线BL1上(即第一放大器SA1的放大信号输入端)产生电压V0。
其中，V0＝C0*CBL1/(C0+CBL1)。
同时，第一参考单元Ck1和第二参考单元Ck2的参考字线RWL和参考脉冲线RPL的电平也由低电平翻转到高电平，第一参考单元Ck1和第二参考单元Ck2的其中一个可在其位线上产生电压V0＝C0*CRBL/(C0+CRBL)，另一个可在其位线上产生电压V1＝C1*CRBL/(C1+CRBL)。
而在t1阶段，第一三极管Q12的栅极电压由低电平翻转到高电平，第一三极管Q12，第一参考单元Ck1和第二参考单元Ck2的位线短路连通，于是在第一参考单元Ck1和第二参考单元Ck2的位线上发生电荷分享，电荷分享稳定后在第一电压放大器SA1的参考电压输入端BL1B上产生的参考电压Vref＝(V0+V1)/2。
在t2阶段，第一三极管Q12的栅极电压由高电平翻转到低电平，第一电压放大器SA1的参考电压输入端BL1B上电压钳位在Vref，此时，第一电压放大器SA1的使能信号SAE1的电平由低电平翻转到高电平，第一电压放大器SA1被使能开始工作，稳定后读出第一存储单元111存储的数据“0”，并将第一位线BL1电压拉到低电平。
在t3阶段，存储单元111的脉冲线PL1由高电平变为低电平，进行存储数据回写，而第一使能反相器F1的使能信号Ref_wb由低电平变为高电平，使得第一使能反相器F1开始工作，由于第一位线BL1电压拉到低电平，因此，第一电压放大器的参考电压输入端BL1B为高电平，因此，第一参考单元Ck1的位线也为高电平，可向第一参考单元Ck1写入取值为“1”的数据，而由于第一使能反相器F1的作用，使得第二参考单元Ck2的位线也低电平，故而可向第二参考单元Ck2中写入取值为“0”的数据。
在t4阶段，各信号的电位全部变为低电平，数据读出及回写操作结束。
其中，当参考电压读出的时候，提供参考电压的参考单元对中的各自位线上的电压不能被改变，否则会影响到参考电压的产生。因此，此时连在参考单元对的两条位线间的使能反相器不工作，其中，使能反相器不工作时，其输入 端和输出端是相互隔离的。
请参见图10，其中，图10是对图6或图7所示架构中的第一存储单元111所存储的取值为“0”数据进行读取的一种仿真示意图，
为读操作提供参考电压的第一参考单元Ck1和第二参考单元Ck2。
例如第一参考单元Ck1预存数据“1”，即高电平，第二参考单元Ck2中预存数据“0”，即低电平。
读操作开始，脉冲线PL1高电平以将存储单元111中数据“0”读出，此时第一位线BL1上出现一个低于2V的峰值(即低电平)。同时，对第一参考单元Ck1和第二参考单元Ck2中的数据进行读取，使第三位线BL3和第四位线BL4出现相应电位变化，如图中第二位线BL3出现大于2V的峰值(即高电平)，第四位线BL4出现低于2V的峰值(即低电平，与第一位线BL1重合)。接着，第一三极管Q12导通，第三位线BL3和第四位线BL4的电位跳变到同一高度(即第一电压放大器SA1工作点指示处的电位高度)，即形成参考电位。第一电压放大器SA1工作后，第一位线BL1的电位跳变到0V，即将数据“0”读出。而第三位线BL3的电位则跳变到高电平VDD，由于第一使能反相器F1的作用，第四位线BL4的电位跳变到0V。因为第一存储单元111的数据“0”被读出后，第一电压放大器SA1的放大信号输入端与第一位线BL1的电平被拉到0V，而第一电压放大器SA1的参考电压输入端直接连接第一参考单元Ck1的位线(第一参考单元Ck1的位线与第三位线BL3连接)的电位会被拉到高电平VDD，而第二参考单元Ck1的位线(第二参考单元Ck2的位线与第四位线BL4连接)通过第一使能反相器F1与第一参考单元Ck1的位线相连的，所以，第四位线BL4的电位也是0V。此时，第三位线BL3和第四位线BL4上的电平信号可直接用于对第一参考单元Ck1和第二参考单元Ck2进行数据回写。
例如，在图2、图4、图5、图6和图7所示架构中，当存储单元的数据读出完成后，假设从第一存储单元列110中的存储单元111读出数据“0”，那么第一电压放大器SA1的放大信号输入端会被拉到低电平，与读出数据对应的电平相一致。第一电压放大器SA1的参考电压输入端会被拉到高电平，与读出数据对应的电平相反。第一电压放大器SA1参考电压输入端直接与第一参考单元Ck1 的位线连接，并且第一电压放大器SA1参考电压输入端通过第一使能反相器F1与第二参考单元Ck2的位线连接。即，第一参考单元Ck1的位线上的数据回写信号为高电平，故而对其回写取值为“1”的数据；第二参考单元Ck2的位线上的数据回写信号为低电平，故而对其回写取值为“0”的数据。如果存储单元111读出数据“1”，那么对一参考单元Ck1和第二参考单元Ck2的数据回写情况刚好相反，第一参考单元Ck1将被回写取值为“0”的数据；第二参考单元Ck2被回写取值为“1”的数据。从上可知，第一参考单元Ck2和第二参考单元Ck4回写状态，取决于其提供参考电压的存储单元中所存储数据的取值，而存储单元中所存储数据的取值看成是随机的，那么第一参考单元Ck1和第二参考单元Ck2的回写状态也是随机的，而这与传统的参考单元中所存数据的取值一直固定的机制是完全不同。第三参考单元Ck3和第四参考单元Ck4的数据回写机制类似。因此，本发明架构极大改善了参考单元中的铁电电容翻转疲劳度不均的弊病，有利于提高整体性能。
可以看出，本发明实施例提供的铁电存储器包括第一存储单元列、第一参考单元、第二参考单元和控制电路；其中，第一存储单元列包括至少一个存储单元；第一参考单元和第二参考单元用于提供参考电压；其中，控制电路用于在读取第一存储单元列中的第一存储单元中所存储数据时，根据上述参考电压与第一存储单元的输出信号，获得第一存储单元中所存储的数据；在读取出了第一存储单元所存储的数据之后，将与上述数据的取值不同的数据写入第一参考单元，并将与读取的第一存储单元中所存储的上述数据的取值相同的数据写入第二参考单元。其中，由于在读取出第一存储单元所存储的数据后，将与该数据的取值不同的数据写入第一参考单元，并将与读取的第一存储单元中所存储的上述数据的取值相同的数据写入第二参考单元，也就是说，第一参考单元和第二参考单元的回写状态，取决于其提供参考电压的存储单元中所存储数据的取值，而存储单元中所存储数据的取值看成是随机的，那么第一参考单元和第二参考单元的回写状态也是随机的，即是说，参考单元中存“0”还是存“1”是由存储单元随机读出的数据决定，每个参考单元中存“0”的概率通常约等于存“1”的概率，而这与传统的参考单元中所存数据的取值一直固定的机制 是完全不同，本发明架构有利于很好的均衡提供参考信号的参考单元对中的两个参考单元的读写疲劳度，有利于极大提高参考单元的抗疲劳特性。
进一步的，解除参考单元和存储单元的回写之间的时序限定，因此参考单元和存储单元可以同时进行数据回写操作，有利于提高参考单元与存储单元的数据回写效率，进而有利于较大缩短存储器的读写周期。
需要说明的是，本发明的各实施例中提及的一个存储单元列(例如第一存储单元列、第二存储单元列、第三存储单元列或第四存储单元列)，可以是指物理位置上处理同一列上的存储单元，也可以包括共用相同位线的若干个存储单元所形成的存储单元集合，或者也可能是基于其它属性划分出的具有某种共同特征的若干个存储单元所形成的存储单元集合。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售 或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (12)

  1. 一种铁电存储器，其特征在于，包括：
    第一存储单元列、第一参考单元、第二参考单元和控制电路；
    所述第一存储单元列包括至少一个存储单元，所述至少一个存储单元用于存储数据，其中，每个存储单元中包括一个铁电电容以及一个晶体管；
    所述控制电路与所述第一参考单元、所述第二参考单元以及所述第一存储单元列中的存储单元连接；
    所述第一参考单元和第二参考单元用于提供参考电压，其中，每个参考单元中包括一个铁电电容以及一个晶体管，所述第一参考单元与所述第二参考单元中存储的数据的取值不同；
    所述控制电路，用于在读取所述第一存储单元列中的第一存储单元中存储的数据时，根据所述参考电压与所述第一存储单元的输出信号获得所述第一存储单元中存储的数据；在读取所述第一存储单元中存储的数据之后，将与读取的数据的取值不同的数据写入所述第一参考单元，并将与读取的数据的取值相同的数据写入所述第二参考单元。
  2. 根据权利要求1所述的铁电存储器，其特征在于，所述控制电路包括第一电压放大器、第一三极管和第一使能反相器；
    所述第一三极管的第一端连接所述第一参考单元的位线，所述第一三极管的第二端连接所述第二参考单元的位线，其中，所述第一三极管的第一端和第二端均不是所述第一三极管的导通控制端；
    所述第一使能反相器的输入端连接所述第一参考单元的所述位线，所述第一使能反相器的输出端连接所述第二参考单元的位线；
    所述第一电压放大器的放大信号输入端连接所述第一存储单元的位线，所述第一电压放大器的参考电压输入端连接所述第一参考单元的所述位线。
  3. 根据权利要求1或2所述的铁电存储器，其特征在于，所述第一存储单元列包含多个存储单元，所述第一存储单元列中的所述多个存储单元共用相同的位线。
  4. 根据权利要求1至3任一项所述的铁电存储器，其特征在于，还包括：
    第二存储单元列，其中，所述第二存储单元列包括至少一个存储单元；所述控制电路与所述第二存储单元列中的存储单元连接；所述第二存储单元列包括的所述至少一个存储单元用于存储数据，其中，所述第二存储单元列中的每个存储单元中包括一个铁电电容以及一个晶体管；
    所述控制电路，还用于在读取所述第二存储单元列中的第二存储单元中存储的数据时，根据所述参考电压与所述第二存储单元的输出信号获得所述第二存储单元中所存储的数据；在读取所述第二存储单元中存储的数据之后，将与读取的所述第二存储单元中存储的数据的取值不同的数据写入所述第二参考单元，并将与读取的所述第二存储单元中存储的数据的取值相同的数据写入所述第一参考单元。
  5. 根据权利要求4所述的铁电存储器，其特征在于，所述控制电路还包括：第二电压放大器和第二使能反相器；
    所述第二使能反相器的输入端连接所述第二参考单元的位线，所述第二使能反相器的输出端连接所述第一参考单元的位线；所述第二电压放大器的放大信号输入端连接所述第二存储单元的位线，所述第二电压放大器的参考电压输入端连接所述第二参考单元的所述位线。
  6. 根据权利要求4或5所述的铁电存储器，其特征在于，所述第二存储单元列包含多个存储单元，所述第二存储单元列中的所述多个存储单元共用相同的位线。
  7. 根据权利要求2至6任一项所述的铁电存储器，其特征在于，
    还包括：第三存储单元列、第三参考单元和第四参考单元；
    其中，所述第三存储单元列包括至少一个存储单元，所述第三存储单元列包括的所述至少一个存储单元用于存储数据，其中，所述第三存储单元列中的每个存储单元中包括一个铁电电容以及一个晶体管；
    所述第三参考单元和所述第四参考单元用于提供参考电压，其中，所述第三参考单元和所述第四参考单元中的每个参考单元中包括一个铁电电容以及一个晶体管，所述第三参考单元与所述第四参考单元中存储的数据的取值不同；
    所述控制电路还可用于，在读取所述第三存储单元列中的第三存储单元中所存储的数据时，根据所述第三存储单元的输出信号，以及所述第三参考单元和第四参考单元提供的参考电压，获得所述第三存储单元中所存储的数据；在读取所述第三存储单元所存储的数据后，将与读取的所述第三存储单元中所存储的所述数据的取值相同的数据写入所述第四参考单元，将与读取的所述第三存储单元中所存储的所述数据的取值不同的数据写入所述第三参考单元。
  8. 根据权利要求7所述的铁电存储器，其特征在于，
    所述控制电路还包括第三电压放大器、第二三极管和第三使能反相器；
    其中，所述第二三极管的第一端连接所述第三参考单元的位线，所述第二三极管的第二端连接所述第四参考单元的位线，其中，所述第二三极管的第一端和第二端均不是所述第二三极管的导通控制端；
    所述第三使能反相器的输入端连接所述第三参考单元的所述位线，所述第三使能反相器的输出端连接所述第四参考单元的位线；
    所述第三电压放大器的放大信号输入端连接所述第三存储单元列中的第三存储单元的位线，所述第三电压放大器的参考电压输入端连接所述第三参考单元的所述位线。
  9. 根据权利要求7或8所述的铁电存储器，其特征在于，
    所述铁电存储器还包括第四存储单元列，
    其中，所述第四存储单元列包括至少一个存储单元，所述第四存储单元列包括的所述至少一个存储单元用于存储数据，其中，所述第四存储单元列中的每个存储单元中包括一个铁电电容以及一个晶体管；
    所述控制电路，还用于在读取所述第四存储单元列中的第四存储单元中存储的数据时，根据所述第四存储单元的输出信号，以及所述第三参考单元和第四参考单元提供的参考电压，获得所述第四存储单元中所存储的数据；在读取所述第四存储单元中存储的数据之后，将与读取的所述第四存储单元中存储的数据的取值不同的数据写入所述第四参考单元，并将与读取的所述第四存储单元中存储的数据的取值相同的数据写入所述第三参考单元。
  10. 根据权利要求9所述的铁电存储器，其特征在于，
    所述控制电路还包括第四电压放大器和第四使能反相器；
    所述第四使能反相器的输入端连接所述第四参考单元的位线，所述第四使能反相器的输出端连接所述第三参考单元的位线；
    所述第四电压放大器的放大信号输入端连接所述第四存储单元列中的第四存储单元的位线，所述第四电压放大器的参考电压输入端连接所述第四参考单元的所述位线。
  11. 根据权利要求10所述的铁电存储器，其特征在于，所述第三参考单元与所述第一存储单元共用相同的位线；并且，所述第四参考单元与所述第二存储单元共用相同的位线。
  12. 根据权利要求10或11所述的铁电存储器，其特征在于，所述第一参考单元与所述第三存储单元共用相同位线；并且所述第二参考单元与所述第四存储单元共用相同的位线。
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