WO2015136699A1 - Appareil de surveillance d'appareil de conversion de courant - Google Patents

Appareil de surveillance d'appareil de conversion de courant Download PDF

Info

Publication number
WO2015136699A1
WO2015136699A1 PCT/JP2014/056967 JP2014056967W WO2015136699A1 WO 2015136699 A1 WO2015136699 A1 WO 2015136699A1 JP 2014056967 W JP2014056967 W JP 2014056967W WO 2015136699 A1 WO2015136699 A1 WO 2015136699A1
Authority
WO
WIPO (PCT)
Prior art keywords
monitoring
output
power converter
frequency
abnormality
Prior art date
Application number
PCT/JP2014/056967
Other languages
English (en)
Japanese (ja)
Inventor
高村　晴久
信明 土井
川上　和人
Original Assignee
東芝三菱電機産業システム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東芝三菱電機産業システム株式会社 filed Critical 東芝三菱電機産業システム株式会社
Priority to JP2016507235A priority Critical patent/JP6270987B2/ja
Priority to PCT/JP2014/056967 priority patent/WO2015136699A1/fr
Publication of WO2015136699A1 publication Critical patent/WO2015136699A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

Definitions

  • the present invention relates to a monitoring device for a power conversion device that monitors the power conversion device.
  • a power conversion device such as an inverter has a failure detection function for detecting a failure.
  • a monitoring device receives a failure signal and a history data recording signal input in time series from a control circuit of an electric motor control device, and creates display trend data (see Patent Document 1).
  • each power converter stores its own trend data with its own fault signal, and when the process controller receives the fault signal, it receives the trend data of the power converter that sent the fault signal, and The trend data of the peripheral power converters is received and the collected trend data is edited (see Patent Document 2).
  • An object of the present invention is to provide a monitoring device for a power conversion device with an increased detection rate of a failure occurring in the power conversion device.
  • a monitoring device for a power conversion device is a monitoring device for a power conversion device configured by hardware independent of a control system of the power conversion device and monitoring the power conversion device, wherein the power conversion For output monitoring means for detecting the output of the apparatus, output monitoring means for monitoring the output of the power conversion apparatus based on the output of the power conversion apparatus detected by the output detection means, and monitoring by the output monitoring means Based on output abnormality detection means for detecting an output abnormality of the power converter, monitoring signal receiving means for receiving a monitoring signal indicating whether or not the power converter is in a state of being monitored, and the output monitoring means And monitoring abnormality detecting means for detecting a monitoring abnormality based on the monitoring signal received from the monitoring signal and the monitoring signal received from the monitoring signal receiving means.
  • FIG. 1 is a configuration diagram showing the configuration of the drive system according to the first embodiment of the present invention.
  • FIG. 2 is a schematic diagram illustrating functions of the filter circuit according to the first embodiment.
  • FIG. 3 is a configuration diagram showing the configuration of the drive system according to the second embodiment of the present invention.
  • FIG. 4 is a configuration diagram showing the configuration of the drive system according to the third embodiment of the present invention.
  • FIG. 5 is a configuration diagram showing the configuration of the drive system according to the fourth embodiment of the present invention.
  • FIG. 6 is a configuration diagram showing the configuration of the drive system according to the fifth embodiment of the present invention.
  • FIG. 7 is a configuration diagram showing the configuration of the drive system according to the sixth embodiment of the present invention.
  • FIG. 8 is a configuration diagram showing the configuration of the drive system according to the seventh embodiment of the present invention.
  • FIG. 1 is a configuration diagram showing the configuration of a drive system 10 according to the first embodiment of the present invention.
  • symbol is attached
  • the drive system 10 includes a monitoring device 1, an inverter device 2, an electric motor 3, and a DC power supply 4.
  • the drive system 10 is a speed sensorless drive system to which a speed sensor cannot be attached.
  • the DC power supply 4 is connected to the inverter device 2.
  • the DC power supply 4 supplies DC power to the inverter device 2.
  • the DC power supply 4 may be anything as long as it outputs DC power, such as a generator, a battery, or a power converter.
  • the inverter device 2 is a power conversion device that converts DC power supplied from the DC power supply 4 into three-phase AC power.
  • An electric motor 3 is connected to the AC side of the inverter device 2.
  • the inverter device 2 controls the drive of the electric motor 3 by outputting the converted AC power to the electric motor 3.
  • the inverter device 2 performs VVVF (variable voltage variable frequency) control that keeps the V / F (voltage / frequency) ratio of the electric motor 3 constant.
  • the V / F ratio is a ratio of voltage and frequency for making the magnetic flux of the electric motor 3 constant.
  • the monitoring device 1 is a device composed of hardware independent from the inverter device 2 and the electric motor 3.
  • the monitoring device 1 is a wiring that takes in the interphase voltage of the three-phase AC voltage output from the inverter device 2, and is connected to an electrical path through which AC power is supplied from the inverter device 2 to the motor 3.
  • the monitoring device 1 is a transmission path for transmitting information and is connected to the control device 8 of the inverter device 2.
  • the monitoring device 1 monitors the state of the inverter device 2 by detecting the interphase voltage output from the inverter device 2 and transmitting / receiving information to / from the control device 8.
  • the inverter device 2 includes an inverter circuit 7 and a control device 8.
  • the inverter circuit 7 is an electric circuit that converts DC power supplied from the DC power supply 4 into three-phase AC power.
  • the inverter circuit 7 includes a switching element that is a semiconductor element.
  • the inverter circuit 7 performs power conversion by PWM (pulse width modulation) control.
  • the control device 8 is a device built in the inverter device 2.
  • the control device 8 receives various information and controls the drive system 10.
  • the control device 8 mainly drives the electric motor 3 by controlling the AC power output from the inverter circuit 7.
  • the control device 8 controls the AC power output from the inverter circuit 7 by outputting a gate signal and driving a switching element of the inverter circuit 7. Thereby, the electric motor 3 is driven.
  • the control device 8 includes an operation sequence execution unit 31, an electric motor control unit 32, a monitoring command unit 33, and a gate block command unit 34.
  • the operation sequence execution unit 31 receives information for grasping the states of the electric motor 3 and the inverter circuit 7 from the electric motor control unit 32 and the failure signal NG detected by the monitoring device 1.
  • the operation sequence execution unit 31 determines control to be performed on the inverter circuit 7 and the electric motor 3 in accordance with a predetermined operation sequence based on the received information.
  • the operation sequence execution unit 31 outputs various types of information to the electric motor control unit 32 or the monitoring command unit 33 in order to execute the control determined by the operation sequence.
  • the operation sequence execution unit 31 When receiving the failure signal NG from the monitoring device 1, the operation sequence execution unit 31 performs control to limit or stop the operations of the inverter circuit 7 and the electric motor 3 according to the operation sequence.
  • the electric motor control unit 32 receives information such as voltage or current from various sensors provided in the inverter circuit 7 or the electric motor 3 and determines the state of the inverter circuit 7 or the electric motor 3.
  • the motor control unit 32 controls the output power of the inverter circuit 7 based on the determined state to drive the motor 3 in order to execute the control determined by the operation sequence execution unit 31.
  • the electric motor control unit 32 outputs information necessary for the operation sequence of the operation sequence execution unit 31 to the operation sequence execution unit 31.
  • the monitoring command unit 33 determines whether the monitoring condition is satisfied based on the information input from the operation sequence execution unit 31. Whether or not the monitoring condition is satisfied is determined by whether or not the inverter device 2 is in a state of being monitored. If there is no factor on the inverter device 2 side that prevents monitoring by the monitoring device 1 from being performed normally, the monitoring condition is satisfied. For example, when the inverter circuit 7 is not operating normally (when the output of the inverter circuit 7 is not normal), the monitoring condition is not satisfied. If the monitoring condition is satisfied, the monitoring command unit 33 outputs a monitoring command to the monitoring device 1. When the monitoring condition is not satisfied, the monitoring command unit 33 does not output a monitoring command to the monitoring device 1.
  • the monitoring command may be output when the inverter device 2 operates normally by self-diagnosis.
  • the monitoring command unit 33 transmits the monitoring command signal C1 to ‘1’ when outputting the monitoring command, and transmits the monitoring command signal C1 to ‘0’ when not outputting the monitoring command.
  • the gate block command unit 34 gate-blocks the switching element of the inverter circuit 7 when receiving the failure signal NG detected by the monitoring device 1. Thereby, the conversion operation of the inverter circuit 7 is stopped.
  • the monitoring device 1 includes a voltage detector 5 and a monitoring circuit 6.
  • the voltage detector 5 detects a voltage (phase voltage) between two phases among the three phases of the AC voltage output from the inverter device 2 and outputs the voltage to the monitoring circuit 6.
  • the voltage detector 5 includes a filter circuit 11 and an insulation circuit 12.
  • FIG. 2 is a schematic diagram showing the function of the filter circuit 11.
  • the filter circuit 11 shapes the rectangular wave voltage into a sine wave voltage.
  • the voltage waveform output from the PWM-controlled inverter circuit 7 is a one-pulse or multi-pulse rectangular wave.
  • the waveform input to the filter circuit 11 is shaped from a rectangular wave to a sine wave.
  • the sine wave voltage output from the filter circuit 11 is output to the monitoring circuit 6 via the insulation circuit 12.
  • the monitoring circuit 6 is insulated from the main circuit of the drive system 10.
  • the monitoring circuit 6 monitors the drive system 10 based on the output voltage detected by the voltage detector 5 and the signal received from the inverter device 2.
  • the monitoring circuit 6 includes a frequency detection unit 13, a voltage detection unit 14, a voltage drop detection setting unit 15, a frequency drop detection setting unit 16, an overfrequency detection setting unit 17, a voltage comparison unit 18, a frequency comparison unit 19, and a frequency comparison unit 20. , NOT operation circuit 21, NOT operation circuit 22, AND operation circuit 23, XOR operation circuit 24, and failure detection unit 25.
  • the frequency detector 13 calculates the frequency f based on the voltage waveform detected by the voltage detector 5. Specifically, as shown in FIG. 2, the time T between the zero cross points of the sine wave is measured. The frequency detection unit 13 obtains the frequency f from the measured time T using the following equation. The frequency detection unit 13 outputs the calculated frequency f to the frequency comparison unit 19 and the frequency comparison unit 20.
  • the voltage detector 14 calculates the voltage V according to the following equation.
  • the voltage detection unit 14 outputs the calculated voltage V to the voltage comparison unit 18.
  • m is the number of samplings
  • i is the number of samplings
  • Vi is the instantaneous value of the sampled voltage.
  • the voltage drop detection setting unit 15 is set with a voltage drop set value Vs that serves as a threshold for detecting that the output voltage V of the inverter device 2 is greatly reduced.
  • the voltage drop detection setting unit 15 outputs the voltage drop setting value Vs to the voltage comparison unit 18.
  • a frequency decrease set value fs1 is set as a threshold for detecting that the output frequency f of the inverter device 2 is largely decreased.
  • the frequency decrease detection setting unit 16 outputs the frequency decrease setting value fs1 to the frequency comparison unit 19.
  • an over-frequency setting value fs2 that is a threshold value for detecting an excessive increase in the output frequency f of the inverter device 2 is set.
  • the overfrequency detection setting unit 17 outputs the overfrequency setting value fs2 to the frequency comparison unit 20.
  • the voltage comparison unit 18 compares the voltage V detected by the voltage detection unit 14 with the voltage decrease setting value Vs set in the voltage decrease detection setting unit 15, and determines whether or not the voltage V is lower than the voltage decrease setting value Vs. Determine whether.
  • the voltage comparison unit 18 outputs a signal to the NOT operation circuit 21 and the AND operation circuit 23 based on the determination result. When the voltage V is lower than the voltage drop setting value Vs, the voltage comparison unit 18 outputs a signal indicating “0” as a voltage drop abnormality. When the voltage V is equal to or higher than the voltage drop set value Vs, the voltage comparison unit 18 outputs a signal indicating “1” as normal.
  • the NOT operation circuit 21 inverts the input signal (logical negation) and outputs it to the failure detection unit 25. Therefore, “1” is input to the failure detection unit 25 when the voltage drop is abnormal, and “0” is input when the voltage is normal.
  • the frequency comparison unit 19 compares the frequency f detected by the frequency detection unit 13 with the frequency reduction setting value fs1 set in the frequency reduction detection setting unit 16, and determines whether the frequency f is lower than the frequency reduction setting value fs1. Determine whether.
  • the frequency comparison unit 19 outputs a signal to the NOT operation circuit 22 and the AND operation circuit 23 based on the determination result. When the frequency f is lower than the frequency reduction setting value fs1, the frequency comparison unit 19 outputs a signal indicating “0” as the frequency reduction abnormality. When the frequency f is equal to or higher than the frequency reduction setting value fs1, the frequency comparison unit 19 outputs a signal indicating “1” as normal.
  • NOT operation circuit 22 inverts the input signal (logical negation) and outputs it to failure detection unit 25. Therefore, ‘1’ is input to the failure detection unit 25 when the frequency drop is abnormal, and ‘0’ is input when the frequency is normal.
  • the frequency comparison unit 20 compares the frequency f detected by the frequency detection unit 13 with the overfrequency setting value fs2 set in the overfrequency detection setting unit 17, and determines whether the frequency f is higher than the overfrequency setting value fs2. Determine whether.
  • the frequency comparison unit 20 outputs a signal to the failure detection unit 25 based on the determination result.
  • the frequency comparison unit 20 When the frequency f is higher than the overfrequency setting value fs2, the frequency comparison unit 20 outputs a signal indicating “1” as an overfrequency abnormality.
  • the frequency comparison unit 20 outputs a signal indicating “0” as normal.
  • Signals are input to the AND operation circuit 23 from the voltage comparison unit 18 and the frequency comparison unit 19, respectively.
  • the AND operation circuit 23 outputs the logical product of the two input signals to the XOR operation circuit 24. Accordingly, when both of the two input signals are “1” (when both of the two input signals indicate “normal”), the AND operation circuit 23 outputs a signal indicating “1”. Otherwise (when at least one of the two input signals indicates “abnormal”), a signal indicating “0” is output.
  • the XOR operation circuit 24 receives the signal output from the AND operation circuit 23 and the signal transmitted from the monitoring command unit 33 of the inverter device 2.
  • the XOR operation circuit 24 outputs an exclusive OR of the two signals to the failure detection unit 25.
  • the XOR operation circuit 24 outputs a signal indicating “1” as a monitoring abnormality when the two input signals do not match, and outputs a signal indicating “0” as normal when they match.
  • the XOR operation circuit 24 determines that a monitoring abnormality has occurred and '1 A signal indicating 'is output.
  • This abnormality means that although the monitoring device 1 is normally monitoring, the monitoring condition is not satisfied on the inverter device 2 side.
  • the XOR operation circuit 24 determines that there is an abnormality and indicates a signal indicating “1”. Is output. This abnormality means that the monitoring condition is established on the inverter device 2 side, and the monitoring device 1 is in a state of detecting the abnormality.
  • the failure detection unit 25 detects a failure based on signals received from the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, and the XOR operation circuit 24.
  • the failure detection unit 25 determines that a failure occurs if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality).
  • the failure detection unit 25 outputs a failure signal NG to the inverter device 2.
  • the inverter device 2 by configuring the monitoring device 1 with hardware independent of the control system of the inverter device 2, even if an abnormality occurs in the inverter device 2, the inverter device 2
  • the monitoring device 1 can monitor the inverter device 2 without being affected by the abnormality. For example, when a failure is detected inside the inverter device 2, it is difficult to detect a failure such as a failure in the failure detection circuit itself or a rise in the system clock. However, if the monitoring device 1 is independent from the inverter device 2. It can be easily detected. Therefore, the drive system 10 can be a highly reliable system.
  • the monitoring apparatus 1 is provided with the monitoring command unit 33, and when the monitoring condition is satisfied, the monitoring apparatus 1 can perform monitoring with higher reliability by transmitting the monitoring command to the monitoring apparatus 1. .
  • the monitoring command transmitted from the inverter device 2 with the monitoring status detected by the monitoring device 1, it is possible to detect an abnormality that cannot be detected from outside the inverter device 2.
  • the monitoring device 1 can detect an abnormality that does not cause a change in the output voltage V of the inverter device 2.
  • FIG. 3 is a configuration diagram showing the configuration of the drive system 10A according to the second embodiment of the present invention.
  • the drive system 10A is obtained by replacing the monitoring device 1 with the monitoring device 1A in the drive system 10 according to the first embodiment shown in FIG.
  • the monitoring device 1A replaces the monitoring circuit 6 of the monitoring device 1 according to the first embodiment from the failure detection unit 25 to the failure detection unit 25A, and replaces the frequency change setting unit 26, the frequency change comparison unit 27, and the previous value memory. 28 and a monitoring circuit 6A to which a subtractor 29 is added. Other points are the same as in the first embodiment.
  • a frequency change set value fs3 is set as a threshold value for detecting a significant change in the output frequency of the inverter device 2.
  • the frequency change setting unit 26 outputs the frequency change set value fs3 to the frequency change comparison unit 27.
  • the frequency f detected by the frequency detector 13 is input to the previous value memory 28.
  • the previous value memory 28 outputs the previously stored previous frequency fp to the subtractor 29, and newly stores the input frequency f as the previous frequency fp.
  • the subtracter 29 receives the frequency f detected by the frequency detector 13 and the previous frequency fp stored in the previous value memory 28.
  • the subtractor 29 outputs a frequency change fd obtained by subtracting the frequency f from the previous frequency fp to the frequency change comparison unit 27.
  • the frequency change comparison unit 27 calculates the absolute value of the frequency change fd calculated by the subtractor 29.
  • the frequency change comparison unit 27 compares the calculated absolute value of the frequency change fd with the frequency change set value fs3 set in the frequency change setting unit 26, and the absolute value of the frequency change fd is the frequency change. It is determined whether or not it is larger than the set value fs3.
  • the frequency change comparison unit 27 outputs a signal to the failure detection unit 25A based on the determination result.
  • the absolute value of the frequency change fd is larger than the frequency change set value fs3
  • the frequency change comparison unit 27 outputs a signal indicating ‘1’ as the frequency change abnormality.
  • the absolute value of the frequency change fd is equal to or less than the frequency change set value fs3, the frequency change comparison unit 27 outputs a signal indicating “0” as normal.
  • the failure detection unit 25A detects a failure based on signals received from the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, and the frequency change comparison unit 27.
  • the failure detection unit 25A determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality).
  • the failure detection unit 25A outputs a failure signal NG to the inverter device 2 when detecting a failure.
  • the present embodiment in addition to the operational effects of the first embodiment, by monitoring the change in the output frequency of the inverter device 2, it is possible to detect an abnormality such as a significant change in the output frequency.
  • FIG. 4 is a configuration diagram showing the configuration of a drive system 10B according to the third embodiment of the present invention.
  • the drive system 10B is obtained by replacing the monitoring device 1 with the monitoring device 1B and replacing the inverter device 2 with the inverter device 2B in the drive system 10 according to the first embodiment shown in FIG.
  • the monitoring device 1B replaces the monitoring circuit 6 of the monitoring device 1 according to the first embodiment with the failure detection unit 25B from the failure detection unit 25, and includes a voltage reference difference setting unit 41, a frequency reference difference setting unit 42, and a voltage reference comparison.
  • This is a monitoring circuit 6B in which a unit 43, a voltage reference calculation unit 44, a frequency reference comparison unit 45, and two subtractors 46 and 47 are added.
  • the inverter device 2B is obtained by replacing the control device 8 of the inverter device 2 according to the first embodiment with a control device 8B to which a frequency reference output unit 35 is added. Other points are the same as in the first embodiment.
  • the current frequency reference fr controlling the inverter circuit 7 is input from the operation sequence execution unit 31 to the frequency reference output unit 35.
  • the frequency reference fr is used for control by the control device 8B and is a reference for controlling the output frequency of the inverter circuit 7.
  • the frequency reference output unit 35 outputs the frequency reference fr to the monitoring device 1B.
  • the frequency reference fr is input to the voltage reference calculation unit 44 from the frequency reference output unit 35 of the inverter device 2B.
  • the voltage reference calculation unit 44 calculates the voltage reference Vr by multiplying the input frequency reference fr by a preset V / F ratio.
  • the voltage reference calculation unit 44 outputs the calculated voltage reference Vr to the subtractor 46.
  • the voltage reference difference setting unit 41 is set with a voltage reference difference setting value Vsr that serves as a threshold for detecting that the difference between the output voltage V of the inverter 2B and the voltage reference Vr calculated by the voltage reference calculation unit 44 is large. ing.
  • the voltage reference difference setting unit 41 outputs the voltage reference difference setting value Vsr to the voltage reference comparison unit 43.
  • the frequency reference difference setting unit 42 is set with a frequency reference difference setting value fsr that is a threshold value for detecting that the difference between the output frequency f of the inverter device 2B and the frequency reference fr input from the inverter device 2B is large. .
  • the frequency reference difference setting unit 42 outputs the frequency reference difference setting value fsr to the frequency reference comparison unit 45.
  • the subtracter 46 receives the voltage V detected by the voltage detector 14 and the voltage reference Vr calculated by the voltage reference calculator 44.
  • the subtractor 46 calculates a voltage error Ve obtained by subtracting the voltage V from the voltage reference Vr.
  • the subtractor 46 outputs the calculated voltage error Ve to the voltage reference comparison unit 43.
  • the frequency reference fr output from the inverter device 2B and the frequency f detected by the frequency detector 13 are input to the subtractor 47.
  • the subtractor 47 calculates a frequency error fe obtained by subtracting the frequency f from the frequency reference fr.
  • the subtractor 47 outputs the calculated frequency error fe to the frequency reference comparison unit 45.
  • the voltage reference comparison unit 43 calculates the absolute value of the voltage error Ve calculated by the subtractor 46.
  • the voltage reference comparison unit 43 compares the calculated absolute value of the voltage error Ve with the voltage reference difference setting value Vsr set in the voltage reference difference setting unit 41, and the absolute value of the voltage error Ve is the voltage reference difference setting value Vsr. It is judged whether it is larger than.
  • the voltage reference comparison unit 43 outputs a signal to the failure detection unit 25B based on the determination result.
  • the voltage reference comparison unit 43 When the absolute value of the voltage error Ve is larger than the voltage reference difference setting value Vsr, the voltage reference comparison unit 43 outputs a signal indicating “1” as a voltage reference abnormality.
  • the voltage reference comparison unit 43 When the absolute value of the voltage error Ve is equal to or smaller than the voltage reference difference setting value Vsr, the voltage reference comparison unit 43 outputs a signal indicating “0” as normal.
  • the frequency reference comparison unit 45 calculates the absolute value of the frequency error fe calculated by the subtractor 47.
  • the frequency reference comparison unit 45 compares the calculated absolute value of the frequency error fe with the frequency reference difference setting value fsr set in the frequency reference difference setting unit 42, and the absolute value of the frequency error fe is the frequency reference difference setting value fsr. It is judged whether it is larger than.
  • the frequency reference comparison unit 45 outputs a signal to the failure detection unit 25B based on the determination result.
  • the frequency reference comparison unit 45 When the absolute value of the frequency error fe is larger than the frequency reference difference set value fsr, the frequency reference comparison unit 45 outputs a signal indicating “1” as a frequency reference abnormality.
  • the absolute value of the frequency error fe is equal to or less than the frequency reference difference set value fsr, the frequency reference comparison unit 45 outputs a signal indicating “0” as normal.
  • the failure detection unit 25B detects a failure based on signals received from the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, the voltage reference comparison unit 43, and the frequency reference comparison unit 45. To detect.
  • the failure detection unit 25B determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality).
  • the failure detection unit 25B outputs a failure signal NG to the inverter device 2B.
  • the frequency reference fr is multiplied by the V / F ratio to obtain the voltage reference Vr, and the output voltage V of the inverter device 2B is compared with the voltage reference Vr, thereby detecting the output abnormality of the inverter device 2B by the VVVF control. it can.
  • FIG. 5 is a configuration diagram showing the configuration of a drive system 10C according to the fourth embodiment of the present invention.
  • the drive system 10C is obtained by replacing the monitoring device 1 with the monitoring device 1C in the drive system 10 according to the first embodiment shown in FIG.
  • the monitoring device 1C includes a voltage detector 5C and a monitoring circuit 6C.
  • the monitoring circuit 6C includes a voltage comparison unit 18, a frequency comparison unit 19, a frequency comparison unit 20, and a failure detection unit 25.
  • the voltage comparison unit 18C, the frequency comparison unit 19C, instead of the comparison unit 20C and the failure detection unit 25C, a phase sequence setting unit 51, a phase sequence comparison unit 52, and three majority decision circuits 53, 54, and 55 are added. Other points are the same as in the first embodiment.
  • the voltage detector 5C is the same as the voltage detector 5 according to the first embodiment, except that the three interphase voltages output from the inverter device 2 are detected. In addition, although the voltage detector 5C demonstrates the structure which detects an interphase voltage here, the structure which detects a phase voltage may be sufficient.
  • the voltage detector 5C includes a filter circuit 11C and an insulation circuit 12C.
  • the filter circuit 11C shapes the three interphase voltages from a rectangular wave to a sine wave. Other points are the same as those of the filter circuit 11 according to the first embodiment.
  • the insulation circuit 12 insulates the monitoring circuit 6C from the main circuit of the drive system 10C for the three interphase voltages. Other points are the same as those of the insulating circuit 12 according to the first embodiment.
  • the frequency detector 13C detects the frequencies fuv, fvw, and fwu based on the waveform of the voltage between the phases detected by the voltage detector 5C.
  • the frequency fuv is the frequency of the voltage between the U phase and the V phase
  • the frequency fvw is the frequency of the voltage between the V phase and the W phase
  • the frequency fwu is the voltage between the W phase and the U phase. It is assumed that each frequency is represented.
  • the frequency detection unit 13C outputs the calculated frequencies fuv, fvw, fwu of the respective interphase voltages to the frequency comparison unit 19C and the frequency comparison unit 20C, and zero-crosses the detected interphase voltages to calculate the frequencies fuv, fvw, fwu. Information about the points is output to the phase sequence comparison unit 52.
  • the voltage detection unit 14C calculates the interphase voltages Vuv, Vvw, Vwu based on the instantaneous value of the voltage detected by the voltage detector 5C.
  • the interphase voltage Vuv is the voltage between the U phase and the V phase
  • the interphase voltage Vvw is the voltage between the V phase and the W phase
  • the interphase voltage Vwu is the voltage between the W phase and the U phase.
  • the voltage detection unit 14C outputs the calculated interphase voltages Vuv, Vvw, Vwu to the voltage comparison unit 18C.
  • phase order setting unit 51 a phase order set value Sqs is set.
  • the phase order is a phase order in which a zero cross point occurs at the output voltage V of the inverter device 2.
  • the phase sequence setting unit 51 outputs the phase sequence to the phase sequence comparison unit 52.
  • the phase order is the order of the U phase, the V phase, and the W phase, and the phase order set value Sqs is also set in the same order.
  • the phase order comparison unit 52 receives the information about the zero-cross point of each interphase voltage output from the frequency detection unit 13 ⁇ / b> C and the phase sequence setting value Sqs set in the phase sequence setting unit 51.
  • the phase sequence comparison unit 52 determines whether or not the phase sequence Sq determined based on the zero cross point of each interphase voltage matches the phase sequence setting value Sqs. If they match, the phase sequence comparison unit 52 outputs a signal indicating “0” as normal to the failure detection unit 25C. If they do not match, the phase sequence comparison unit 52 outputs a signal indicating '1' as a phase sequence abnormality to the failure detection unit 25C.
  • the calculation for determining the phase sequence Sq from the zero cross point of each interphase voltage may be performed by the frequency detector 13C.
  • the voltage comparison unit 18C uses the interphase voltages Vuv, Vvw, Vwu detected by the voltage detection unit 14C and the voltage drop setting value Vs set in the voltage drop detection setting unit 15 in the same manner as in the first embodiment. Compare. The voltage comparison unit 18C outputs the comparison results for the interphase voltages Vuv, Vvw, and Vwu to the majority decision circuit 53.
  • Majority determination circuits 53 to 55 are circuits that output more than a majority of information among a plurality of input information. For example, when three signals indicating a binary variable that takes “0” or “1” are input, the majority decision circuits 53 to 55 are “1” if two or more signals indicate “1”. 'Is output, otherwise' 0 'is output.
  • the majority decision determination circuit 53 determines whether or not the voltage drop is abnormal based on the comparison result input from the voltage comparison unit 18C.
  • the majority decision circuit 53 determines that the voltage drop is abnormal if at least two of the three interphase voltages Vuv, Vvw, and Vwu are lower than the voltage drop set value Vs. That is, if two or more of the following three inequalities hold, it is determined that the voltage drop is abnormal, and otherwise, it is determined normal.
  • the majority decision circuit 53 outputs a signal indicating “0” to the NOT operation circuit 21 and the AND operation circuit 23 when determining that the voltage drop abnormality is normal, and when determining that it is normal, the majority determination circuit 53 outputs a signal indicating “1”. .
  • the frequency comparison unit 19C sets the frequency fuv, fvw, fwu of each inter-phase voltage detected by the frequency detection unit 13C and the frequency decrease setting value fs1 set in the frequency decrease detection setting unit 16 as in the first embodiment. Compare in the same way.
  • the frequency comparison unit 19 ⁇ / b> C outputs the comparison results for the frequencies fuv, fvw, and fwu to the majority decision circuit 54.
  • the majority decision determination circuit 54 determines whether or not it is a frequency drop abnormality based on the comparison result input from the frequency comparison unit 19C.
  • the majority decision circuit 54 determines that the frequency decrease is abnormal if at least two of the three frequencies fuv, fvw, and fwu are lower than the frequency decrease setting value fs1, and otherwise determines that the frequency is normal. That is, if two or more of the following three inequalities hold, it is determined that the frequency drop is abnormal, otherwise it is determined normal.
  • the majority decision circuit 54 outputs a signal indicating “0” to the NOT operation circuit 22 and the AND operation circuit 23 when it is determined that the frequency decrease is abnormal, and when it is determined that the majority determination circuit 54 is normal. .
  • the frequency comparison unit 20C uses the frequencies fuv, fvw, fwu of the voltages between the phases detected by the frequency detection unit 13C and the overfrequency setting value fs2 set in the overfrequency detection setting unit 17 as in the first embodiment. Compare in the same way.
  • the frequency comparison unit 20 ⁇ / b> C outputs the comparison results for the frequencies fuv, fvw, and fwu to the majority decision circuit 55.
  • the majority decision determination circuit 55 determines whether or not there is an overfrequency abnormality based on the comparison result input from the frequency comparison unit 20C.
  • the majority decision circuit 55 determines that the frequency is abnormal when at least two of the three frequencies fuv, fvw, and fwu are higher than the overfrequency setting value fs2, and determines that the frequency is normal otherwise. That is, if two or more of the following three inequalities hold, it is determined that there is an overfrequency abnormality, and otherwise, it is determined that it is normal.
  • the majority decision circuit 55 outputs a signal indicating ‘1’ to the failure detection unit 25 if it is determined to be abnormal, and a signal indicating ‘0’ to the failure detection unit 25 if it is determined to be normal.
  • the failure detection unit 25C detects a failure based on signals received from the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, the phase sequence comparison unit 52, and the majority decision determination circuit 55.
  • the failure detection unit 25C determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality).
  • the failure detection unit 25C outputs a failure signal NG to the inverter device 2 when detecting a failure.
  • FIG. 6 is a configuration diagram showing the configuration of a drive system 10D according to the fifth embodiment of the present invention.
  • the drive system 10D is obtained by replacing the monitoring device 1 with the monitoring device 1D in the drive system 10 according to the first embodiment shown in FIG.
  • the monitoring device 1D includes three monitoring devices 1, 101, and 102, and a majority circuit 56 is added. Other points are the same as in the first embodiment.
  • the monitoring devices 101 and 102 are the same devices as the monitoring device 1.
  • the majority circuit 56 is the same as the majority circuits 53 to 55 according to the fourth embodiment.
  • the three monitoring devices 1, 101, 102 input different line voltages to the voltage detector 5 and perform monitoring separately.
  • the failure output signals NG 1 to NG 3 of the failure detection unit 25 of each of the monitoring devices 1, 101, 102 are input to the majority decision circuit 56.
  • the majority decision circuit 56 determines that a failure has occurred if at least two or more of the outputs of the three failure detectors 25 are signals indicating ‘1’ (that is, signals indicating abnormality).
  • the majority decision circuit 26 outputs a failure signal NG to the inverter device 2.
  • the monitoring devices 1, 101, 102 By arranging the monitoring devices 1, 101, 102 separately for each detected interphase voltage and using the majority decision circuit 56 to determine an abnormality, erroneous detection of the abnormality can be suppressed. Thus, the reliability of abnormality detection by the monitoring device 1D can be improved.
  • FIG. 7 is a configuration diagram showing the configuration of a drive system 10E according to the sixth embodiment of the present invention.
  • the drive system 10E is obtained by replacing the monitoring device 1 with the monitoring device 1E in the drive system 10 according to the first embodiment shown in FIG.
  • the monitoring device 1E includes a voltage detector 5C and a monitoring circuit 6E according to the fourth embodiment.
  • the monitoring circuit 6E replaces the failure detection unit 25 with the failure detection unit 25E, and replaces the frequency detection unit 13 and the voltage detection unit 14 with the frequency detection unit 13C according to the fourth embodiment.
  • the voltage comparison unit 18, the frequency comparison unit 19, and the frequency comparison unit 20 are replaced with the voltage comparison unit 18E, the frequency comparison unit 19E, and the frequency comparison unit 20E, respectively.
  • a phase sequence setting unit 51 and a phase sequence comparison unit 52, a voltage variation detection setting unit 61, a frequency variation detection setting unit 62, a voltage difference comparison unit 63, and a frequency difference comparison unit 64 are added. Other points are the same as in the first embodiment.
  • the voltage comparison unit 18E compares the interphase voltages Vuv, Vvw, Vwu detected by the voltage detection unit 14C with the voltage decrease setting value Vs set in the voltage decrease detection setting unit 15, respectively, and at least one interphase voltage If Vuv, Vvw, Vwu are lower than the voltage drop set value Vs, it is determined that the voltage drop is abnormal.
  • the other points are the same as those of the voltage comparison unit 18 according to the first embodiment.
  • the frequency comparison unit 19E compares each frequency fuv, fvw, fwu detected by the frequency detection unit 13C with the frequency decrease setting value fs1 set in the frequency decrease detection setting unit 16, and thereby compares at least one frequency fuv, If fvw and fwu are lower than the frequency drop set value fs1, it is determined that the frequency drop is abnormal. Other points are the same as those of the frequency comparison unit 19 according to the first embodiment.
  • the frequency comparison unit 20E compares at least one frequency fuv, fvw, fwu detected by the frequency detection unit 13C with the overfrequency setting value fs2 set in the overfrequency detection setting unit 17, respectively. If fvw and fwu are higher than the overfrequency set value fs2, it is determined that the overfrequency is abnormal. Other points are the same as those of the frequency comparison unit 20 according to the first embodiment.
  • phase sequence setting unit 51 and the phase sequence comparison unit 52 The method of detecting the phase sequence abnormality by the phase sequence setting unit 51 and the phase sequence comparison unit 52 is the same as in the fourth embodiment.
  • a voltage fluctuation setting value Vsv serving as a threshold for detecting large fluctuations among the output phase voltages Vuv, Vvw, Vwu of the inverter device 2 is set.
  • the voltage fluctuation detection setting unit 61 outputs the voltage fluctuation setting value Vsv to the voltage difference comparison unit 63.
  • a frequency fluctuation setting value fsv serving as a threshold for detecting large fluctuations among the frequencies fuv, fvw, and fwu of the output phase voltage of the inverter device 2 is set.
  • the frequency fluctuation detection setting unit 62 outputs the frequency fluctuation setting value fsv to the frequency difference comparison unit 64.
  • the voltage difference comparison unit 63 calculates the absolute value of the voltage difference between the interphase voltages Vuv, Vvw, and Vwu detected by the voltage detection unit 14C.
  • the voltage difference comparison unit 63 compares the calculated three voltage difference absolute values with the voltage variation setting value Vsv set in the voltage variation detection setting unit 61 to determine whether or not the voltage variation is abnormal. If at least one of the absolute values of these voltage differences is larger than the voltage fluctuation set value Vsv, it is determined that the voltage fluctuation is abnormal. That is, if at least one of the following three inequalities holds, it is determined that the voltage fluctuation is abnormal, and otherwise, it is determined normal.
  • the voltage difference comparison unit 63 When it is determined that the voltage fluctuation is abnormal, the voltage difference comparison unit 63 outputs a signal indicating “1” to the failure detection unit 25E. When it is determined that the voltage is normal, the voltage difference comparison unit 63 outputs a signal indicating “0” to the failure detection unit 25E.
  • the frequency difference comparison unit 64 calculates the absolute value of the frequency difference between the frequencies fuv, fvw, and fwu of the interphase voltage detected by the frequency detection unit 13C.
  • the frequency difference comparison unit 64 compares the calculated absolute values of the three frequency differences with the frequency variation setting value fsv set in the frequency variation detection setting unit 62 to determine whether or not the frequency variation is abnormal. If at least one of the absolute values of these frequency differences is larger than the frequency fluctuation set value fsv, it is determined that the frequency fluctuation is abnormal.
  • the frequency difference comparison unit 64 outputs a signal indicating “1” to the failure detection unit 25E. If it is determined that the frequency is normal, the frequency difference comparison unit 64 outputs a signal indicating “0” to the failure detection unit 25E.
  • the failure detection unit 25E receives signals from the frequency comparison unit 20E, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, the phase sequence comparison unit 52, the voltage difference comparison unit 63, and the frequency difference comparison unit 64. Based on the above, a failure is detected.
  • the failure detection unit 25E determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality).
  • the failure detection unit 25E outputs a failure signal NG to the inverter device 2 when detecting a failure.
  • FIG. 8 is a configuration diagram showing a configuration of a drive system 10F according to the seventh embodiment of the present invention.
  • the drive system 10F is obtained by replacing the monitoring device 1 with the monitoring device 1F and adding a host system 9.
  • the monitoring device 1F replaces the monitoring circuit 6 of the monitoring device 1 according to the first embodiment with a monitoring circuit 6F in which an OR operation circuit 71 and an XOR operation circuit 72 are added instead of the failure detection unit 25 to the failure detection unit 25F. It is a thing. Other points are the same as in the first embodiment.
  • the host system 9 is a host control system of the control device 8 of the inverter device 2.
  • the host system 9 includes an operation command unit 91 and a monitoring command unit 92.
  • the operation command unit 91 transmits an operation command including the control content of the drive system 10F to the control device 8 of the inverter device 2.
  • the operation command unit 91 grasps the current operation state of the drive system 10 ⁇ / b> F by transmitting and receiving information to and from the operation sequence execution unit 31 of the control device 8.
  • the operation command unit 91 determines the content of the operation command based on the operation state of the drive system 10F.
  • the control device 8 controls the drive system 10F in accordance with the operation command received from the operation command unit 91.
  • the monitoring command unit 92 outputs a monitoring command to the monitoring device 1F when the monitoring condition is satisfied. Whether or not the monitoring condition is satisfied is determined by whether or not the inverter device 2 is in a state of being monitored, similarly to the monitoring command unit 33 of the inverter device 2. The monitoring condition is satisfied if there is no factor that prevents the monitoring by the monitoring device 1F from being performed normally. For example, the monitoring command unit 92 determines whether or not the monitoring condition is satisfied based on the operation state of the inverter device 2 and the electric motor 3 received from the operation command unit 91. If the monitoring condition is satisfied, the monitoring command unit 92 outputs a monitoring command to the monitoring device 1F.
  • the monitoring command unit 92 When the monitoring condition is not satisfied, the monitoring command unit 92 does not output a monitoring command to the monitoring device 1F.
  • the monitoring command unit 92 transmits the monitoring command signal C2 to “1” when outputting the monitoring command, and transmits the monitoring command signal C2 to “0” when not outputting the monitoring command. .
  • the OR operation circuit 71 receives the monitoring command signal C1 received from the inverter device 2 and the monitoring command signal C2 received from the host system 9.
  • the OR operation circuit 71 outputs the logical sum of the two input monitoring command signals C1 and C2 to the XOR operation circuit 24. Therefore, when at least one of the two input monitoring command signals C1 and C2 is '1' (when at least one of the host system 9 or the inverter device 2 outputs a monitoring command), the XOR operation circuit “1” is input to 24, otherwise “0” is input to the XOR operation circuit 24.
  • the monitor command signal C1 received from the inverter device 2 and the monitor command signal C2 received from the host system 9 are input to the XOR operation circuit 72.
  • the XOR operation circuit 72 outputs the exclusive OR of the two input monitoring command signals C1 and C2 to the failure detection unit 25F.
  • the XOR operation circuit 72 outputs a signal indicating “1” as a mismatch error, and is not so. In this case, a signal indicating “0” is output as normal. In this abnormality detection, this abnormality can be detected when either the inverter device 2 or the host system 9 has an abnormality.
  • the failure detection unit 25F detects a failure based on signals received from each of the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, and the XOR operation circuit 72.
  • the failure detection unit 25F determines that there is a failure if any of the received signals is a signal indicating '1' (that is, a signal indicating abnormality).
  • the failure detection unit 25F outputs a failure signal NG to the inverter device 2 when detecting a failure.
  • the monitoring device 1 which is an external device, matches the consistency between the control by the control device 8 built in the inverter device 2 and the control of the host system 9. Can be monitored. Thereby, the reliability of control of the drive system 10F can be improved.
  • the abnormality detection method may be arbitrarily combined. An appropriate abnormality detection method can be selected according to the operating environment of the monitoring device.
  • a majority decision circuit is used. However, in other embodiments, a majority decision circuit may be used for arbitrary abnormality detection.
  • the host system 9 according to the seventh embodiment may be applied to other embodiments.
  • the configuration using the voltage detectors 5 and 5C that detect (measure) the voltage has been described.
  • the output current or the output power Any output amount may be detected, such as the amount of electricity (such as magnitude or frequency), or the amount of operation such as the rotational speed or torque of an electric motor that operates with the output of the power converter.
  • the inverter circuit 7 when the inverter devices 2 and 2B receive the failure signal NG detected by the monitoring devices 1 to 1F, the inverter circuit 7 is gate-blocked, but the protection operation other than the gate block is performed. Also good. For example, when a failure is detected by the monitoring devices 1 to 1F, the circuit breaker provided on the DC side or the AC side may be tripped so as to stop the output of the inverter devices 2 and 2B.
  • the majority decision determination circuits 53 to 56 are circuits that output more than a majority of the input information, but may output an abnormality only when the total number is abnormal.
  • a system for controlling an electric motor using an inverter has been described.
  • any monitoring target system and monitoring device may be used as long as the system controls the output of a power conversion device (including an inverter).
  • the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage.
  • various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment.
  • constituent elements over different embodiments may be appropriately combined.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

L'invention porte sur un appareil de surveillance (1), qui est configuré à partir d'un matériel indépendant d'un système de commande d'un appareil onduleur (2), et qui surveille l'appareil onduleur (2). L'appareil de surveillance détecte une tension de sortie (V) de l'appareil onduleur (2), surveille la tension de sortie (V) sur la base de la tension de sortie détectée (V), détecte une anomalie de sortie de l'appareil onduleur (2) sur la base de la surveillance de la tension de sortie (V), reçoit des signaux d'instruction de surveillance (C1) qui indiquent si l'appareil onduleur (2) est ou non dans un état qui est à surveiller, et détecte une anomalie de surveillance sur la base de la surveillance de la tension de sortie (V) et des signaux d'instruction de surveillance (C1).
PCT/JP2014/056967 2014-03-14 2014-03-14 Appareil de surveillance d'appareil de conversion de courant WO2015136699A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016507235A JP6270987B2 (ja) 2014-03-14 2014-03-14 電力変換装置の監視装置
PCT/JP2014/056967 WO2015136699A1 (fr) 2014-03-14 2014-03-14 Appareil de surveillance d'appareil de conversion de courant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/056967 WO2015136699A1 (fr) 2014-03-14 2014-03-14 Appareil de surveillance d'appareil de conversion de courant

Publications (1)

Publication Number Publication Date
WO2015136699A1 true WO2015136699A1 (fr) 2015-09-17

Family

ID=54071176

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/056967 WO2015136699A1 (fr) 2014-03-14 2014-03-14 Appareil de surveillance d'appareil de conversion de courant

Country Status (2)

Country Link
JP (1) JP6270987B2 (fr)
WO (1) WO2015136699A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018198191A1 (fr) * 2017-04-25 2018-11-01 東芝三菱電機産業システム株式会社 Dispositif de conversion de puissance et système de conversion de puissance

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3089597B1 (fr) 2018-12-06 2020-11-20 Gaztransport Et Technigaz Cuve étanche et thermiquement isolante
CN109945396B (zh) * 2019-03-25 2021-10-26 广东美的制冷设备有限公司 空调器、驱动电路故障的检测方法和检测装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02254923A (ja) * 1989-03-24 1990-10-15 Fuji Electric Co Ltd インバータ異常の外部検出回路
JPH08223937A (ja) * 1995-02-16 1996-08-30 Toyo Densan Kk インバータ監視装置
JP2001037242A (ja) * 1999-07-22 2001-02-09 Toshiba Corp インバータ装置の過電流保護装置
JP2005175741A (ja) * 2003-12-10 2005-06-30 Mitsubishi Electric Corp スイッチングデバイスの制御装置およびモーターの駆動回路の制御装置
JP2010115094A (ja) * 2008-11-10 2010-05-20 Toshiba Corp インバータの単独運転検出装置および単独運転検出方法
JP2012005229A (ja) * 2010-06-16 2012-01-05 Hitachi Automotive Systems Ltd 電力変換装置
JP2013132135A (ja) * 2011-12-21 2013-07-04 Aisin Aw Co Ltd 回転電機制御装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02254923A (ja) * 1989-03-24 1990-10-15 Fuji Electric Co Ltd インバータ異常の外部検出回路
JPH08223937A (ja) * 1995-02-16 1996-08-30 Toyo Densan Kk インバータ監視装置
JP2001037242A (ja) * 1999-07-22 2001-02-09 Toshiba Corp インバータ装置の過電流保護装置
JP2005175741A (ja) * 2003-12-10 2005-06-30 Mitsubishi Electric Corp スイッチングデバイスの制御装置およびモーターの駆動回路の制御装置
JP2010115094A (ja) * 2008-11-10 2010-05-20 Toshiba Corp インバータの単独運転検出装置および単独運転検出方法
JP2012005229A (ja) * 2010-06-16 2012-01-05 Hitachi Automotive Systems Ltd 電力変換装置
JP2013132135A (ja) * 2011-12-21 2013-07-04 Aisin Aw Co Ltd 回転電機制御装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018198191A1 (fr) * 2017-04-25 2018-11-01 東芝三菱電機産業システム株式会社 Dispositif de conversion de puissance et système de conversion de puissance
JPWO2018198191A1 (ja) * 2017-04-25 2019-11-07 東芝三菱電機産業システム株式会社 電力変換装置及び電力変換システム
US10965226B2 (en) 2017-04-25 2021-03-30 Toshiba Mitsubishi-Electric Industrial Systems Corporation Power conversion apparatus and power conversion system

Also Published As

Publication number Publication date
JP6270987B2 (ja) 2018-01-31
JPWO2015136699A1 (ja) 2017-04-06

Similar Documents

Publication Publication Date Title
US8471507B2 (en) Electric power conversion system and electric power conversion device
EP2705599B1 (fr) Onduleur et procédé de commande d'une machine électrique
JP5266687B2 (ja) 異常検出装置
WO2017199643A1 (fr) Dispositif de commande d'onduleur et dispositif de conversion de puissance
US9991785B2 (en) Electric power converting device
WO2018117058A1 (fr) Dispositif de conversion de puissance à fonction de décharge
JP5491210B2 (ja) 交流電動機の監視装置
JP6270987B2 (ja) 電力変換装置の監視装置
US20180013375A1 (en) Slip-Dependent Motor Model
JP4737093B2 (ja) 多相回転電機の制御装置
JP5972638B2 (ja) 保護制御装置
JP5707761B2 (ja) 欠相診断装置及び欠相診断方法
JP6093555B2 (ja) 制御システム及び二重化制御方法
EP3012953B1 (fr) Procédé de commande d'onduleur
JP2006304456A (ja) 電力変換装置
JP3800391B2 (ja) 電圧形インバータ装置の欠相検出方法とその回路
JP5481055B2 (ja) 電力変換装置
JP6281117B2 (ja) 電力変換装置
JP7172509B2 (ja) 異常検出装置および電力変換装置
US10879832B2 (en) Method for detection of e-motor open-phase problem in electrified powertrain
CN110663168A (zh) 旋转角度检测装置及交流旋转电机控制装置
EP1668768B1 (fr) Commande d'un convertisseur
JP2024025753A (ja) 双方向交流電力変換装置
KR20220080580A (ko) 인버터 고장 검출 방법 및 그 장치
JP2001251866A (ja) 電圧型インバータ装置の欠相検出方法とその回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14885795

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2016507235

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14885795

Country of ref document: EP

Kind code of ref document: A1