WO2015136699A1 - Power conversion apparatus monitoring apparatus - Google Patents

Power conversion apparatus monitoring apparatus Download PDF

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Publication number
WO2015136699A1
WO2015136699A1 PCT/JP2014/056967 JP2014056967W WO2015136699A1 WO 2015136699 A1 WO2015136699 A1 WO 2015136699A1 JP 2014056967 W JP2014056967 W JP 2014056967W WO 2015136699 A1 WO2015136699 A1 WO 2015136699A1
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WO
WIPO (PCT)
Prior art keywords
monitoring
output
power converter
frequency
abnormality
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Application number
PCT/JP2014/056967
Other languages
French (fr)
Japanese (ja)
Inventor
高村　晴久
信明 土井
川上　和人
Original Assignee
東芝三菱電機産業システム株式会社
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Application filed by 東芝三菱電機産業システム株式会社 filed Critical 東芝三菱電機産業システム株式会社
Priority to PCT/JP2014/056967 priority Critical patent/WO2015136699A1/en
Priority to JP2016507235A priority patent/JP6270987B2/en
Publication of WO2015136699A1 publication Critical patent/WO2015136699A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

Definitions

  • the present invention relates to a monitoring device for a power conversion device that monitors the power conversion device.
  • a power conversion device such as an inverter has a failure detection function for detecting a failure.
  • a monitoring device receives a failure signal and a history data recording signal input in time series from a control circuit of an electric motor control device, and creates display trend data (see Patent Document 1).
  • each power converter stores its own trend data with its own fault signal, and when the process controller receives the fault signal, it receives the trend data of the power converter that sent the fault signal, and The trend data of the peripheral power converters is received and the collected trend data is edited (see Patent Document 2).
  • An object of the present invention is to provide a monitoring device for a power conversion device with an increased detection rate of a failure occurring in the power conversion device.
  • a monitoring device for a power conversion device is a monitoring device for a power conversion device configured by hardware independent of a control system of the power conversion device and monitoring the power conversion device, wherein the power conversion For output monitoring means for detecting the output of the apparatus, output monitoring means for monitoring the output of the power conversion apparatus based on the output of the power conversion apparatus detected by the output detection means, and monitoring by the output monitoring means Based on output abnormality detection means for detecting an output abnormality of the power converter, monitoring signal receiving means for receiving a monitoring signal indicating whether or not the power converter is in a state of being monitored, and the output monitoring means And monitoring abnormality detecting means for detecting a monitoring abnormality based on the monitoring signal received from the monitoring signal and the monitoring signal received from the monitoring signal receiving means.
  • FIG. 1 is a configuration diagram showing the configuration of the drive system according to the first embodiment of the present invention.
  • FIG. 2 is a schematic diagram illustrating functions of the filter circuit according to the first embodiment.
  • FIG. 3 is a configuration diagram showing the configuration of the drive system according to the second embodiment of the present invention.
  • FIG. 4 is a configuration diagram showing the configuration of the drive system according to the third embodiment of the present invention.
  • FIG. 5 is a configuration diagram showing the configuration of the drive system according to the fourth embodiment of the present invention.
  • FIG. 6 is a configuration diagram showing the configuration of the drive system according to the fifth embodiment of the present invention.
  • FIG. 7 is a configuration diagram showing the configuration of the drive system according to the sixth embodiment of the present invention.
  • FIG. 8 is a configuration diagram showing the configuration of the drive system according to the seventh embodiment of the present invention.
  • FIG. 1 is a configuration diagram showing the configuration of a drive system 10 according to the first embodiment of the present invention.
  • symbol is attached
  • the drive system 10 includes a monitoring device 1, an inverter device 2, an electric motor 3, and a DC power supply 4.
  • the drive system 10 is a speed sensorless drive system to which a speed sensor cannot be attached.
  • the DC power supply 4 is connected to the inverter device 2.
  • the DC power supply 4 supplies DC power to the inverter device 2.
  • the DC power supply 4 may be anything as long as it outputs DC power, such as a generator, a battery, or a power converter.
  • the inverter device 2 is a power conversion device that converts DC power supplied from the DC power supply 4 into three-phase AC power.
  • An electric motor 3 is connected to the AC side of the inverter device 2.
  • the inverter device 2 controls the drive of the electric motor 3 by outputting the converted AC power to the electric motor 3.
  • the inverter device 2 performs VVVF (variable voltage variable frequency) control that keeps the V / F (voltage / frequency) ratio of the electric motor 3 constant.
  • the V / F ratio is a ratio of voltage and frequency for making the magnetic flux of the electric motor 3 constant.
  • the monitoring device 1 is a device composed of hardware independent from the inverter device 2 and the electric motor 3.
  • the monitoring device 1 is a wiring that takes in the interphase voltage of the three-phase AC voltage output from the inverter device 2, and is connected to an electrical path through which AC power is supplied from the inverter device 2 to the motor 3.
  • the monitoring device 1 is a transmission path for transmitting information and is connected to the control device 8 of the inverter device 2.
  • the monitoring device 1 monitors the state of the inverter device 2 by detecting the interphase voltage output from the inverter device 2 and transmitting / receiving information to / from the control device 8.
  • the inverter device 2 includes an inverter circuit 7 and a control device 8.
  • the inverter circuit 7 is an electric circuit that converts DC power supplied from the DC power supply 4 into three-phase AC power.
  • the inverter circuit 7 includes a switching element that is a semiconductor element.
  • the inverter circuit 7 performs power conversion by PWM (pulse width modulation) control.
  • the control device 8 is a device built in the inverter device 2.
  • the control device 8 receives various information and controls the drive system 10.
  • the control device 8 mainly drives the electric motor 3 by controlling the AC power output from the inverter circuit 7.
  • the control device 8 controls the AC power output from the inverter circuit 7 by outputting a gate signal and driving a switching element of the inverter circuit 7. Thereby, the electric motor 3 is driven.
  • the control device 8 includes an operation sequence execution unit 31, an electric motor control unit 32, a monitoring command unit 33, and a gate block command unit 34.
  • the operation sequence execution unit 31 receives information for grasping the states of the electric motor 3 and the inverter circuit 7 from the electric motor control unit 32 and the failure signal NG detected by the monitoring device 1.
  • the operation sequence execution unit 31 determines control to be performed on the inverter circuit 7 and the electric motor 3 in accordance with a predetermined operation sequence based on the received information.
  • the operation sequence execution unit 31 outputs various types of information to the electric motor control unit 32 or the monitoring command unit 33 in order to execute the control determined by the operation sequence.
  • the operation sequence execution unit 31 When receiving the failure signal NG from the monitoring device 1, the operation sequence execution unit 31 performs control to limit or stop the operations of the inverter circuit 7 and the electric motor 3 according to the operation sequence.
  • the electric motor control unit 32 receives information such as voltage or current from various sensors provided in the inverter circuit 7 or the electric motor 3 and determines the state of the inverter circuit 7 or the electric motor 3.
  • the motor control unit 32 controls the output power of the inverter circuit 7 based on the determined state to drive the motor 3 in order to execute the control determined by the operation sequence execution unit 31.
  • the electric motor control unit 32 outputs information necessary for the operation sequence of the operation sequence execution unit 31 to the operation sequence execution unit 31.
  • the monitoring command unit 33 determines whether the monitoring condition is satisfied based on the information input from the operation sequence execution unit 31. Whether or not the monitoring condition is satisfied is determined by whether or not the inverter device 2 is in a state of being monitored. If there is no factor on the inverter device 2 side that prevents monitoring by the monitoring device 1 from being performed normally, the monitoring condition is satisfied. For example, when the inverter circuit 7 is not operating normally (when the output of the inverter circuit 7 is not normal), the monitoring condition is not satisfied. If the monitoring condition is satisfied, the monitoring command unit 33 outputs a monitoring command to the monitoring device 1. When the monitoring condition is not satisfied, the monitoring command unit 33 does not output a monitoring command to the monitoring device 1.
  • the monitoring command may be output when the inverter device 2 operates normally by self-diagnosis.
  • the monitoring command unit 33 transmits the monitoring command signal C1 to ‘1’ when outputting the monitoring command, and transmits the monitoring command signal C1 to ‘0’ when not outputting the monitoring command.
  • the gate block command unit 34 gate-blocks the switching element of the inverter circuit 7 when receiving the failure signal NG detected by the monitoring device 1. Thereby, the conversion operation of the inverter circuit 7 is stopped.
  • the monitoring device 1 includes a voltage detector 5 and a monitoring circuit 6.
  • the voltage detector 5 detects a voltage (phase voltage) between two phases among the three phases of the AC voltage output from the inverter device 2 and outputs the voltage to the monitoring circuit 6.
  • the voltage detector 5 includes a filter circuit 11 and an insulation circuit 12.
  • FIG. 2 is a schematic diagram showing the function of the filter circuit 11.
  • the filter circuit 11 shapes the rectangular wave voltage into a sine wave voltage.
  • the voltage waveform output from the PWM-controlled inverter circuit 7 is a one-pulse or multi-pulse rectangular wave.
  • the waveform input to the filter circuit 11 is shaped from a rectangular wave to a sine wave.
  • the sine wave voltage output from the filter circuit 11 is output to the monitoring circuit 6 via the insulation circuit 12.
  • the monitoring circuit 6 is insulated from the main circuit of the drive system 10.
  • the monitoring circuit 6 monitors the drive system 10 based on the output voltage detected by the voltage detector 5 and the signal received from the inverter device 2.
  • the monitoring circuit 6 includes a frequency detection unit 13, a voltage detection unit 14, a voltage drop detection setting unit 15, a frequency drop detection setting unit 16, an overfrequency detection setting unit 17, a voltage comparison unit 18, a frequency comparison unit 19, and a frequency comparison unit 20. , NOT operation circuit 21, NOT operation circuit 22, AND operation circuit 23, XOR operation circuit 24, and failure detection unit 25.
  • the frequency detector 13 calculates the frequency f based on the voltage waveform detected by the voltage detector 5. Specifically, as shown in FIG. 2, the time T between the zero cross points of the sine wave is measured. The frequency detection unit 13 obtains the frequency f from the measured time T using the following equation. The frequency detection unit 13 outputs the calculated frequency f to the frequency comparison unit 19 and the frequency comparison unit 20.
  • the voltage detector 14 calculates the voltage V according to the following equation.
  • the voltage detection unit 14 outputs the calculated voltage V to the voltage comparison unit 18.
  • m is the number of samplings
  • i is the number of samplings
  • Vi is the instantaneous value of the sampled voltage.
  • the voltage drop detection setting unit 15 is set with a voltage drop set value Vs that serves as a threshold for detecting that the output voltage V of the inverter device 2 is greatly reduced.
  • the voltage drop detection setting unit 15 outputs the voltage drop setting value Vs to the voltage comparison unit 18.
  • a frequency decrease set value fs1 is set as a threshold for detecting that the output frequency f of the inverter device 2 is largely decreased.
  • the frequency decrease detection setting unit 16 outputs the frequency decrease setting value fs1 to the frequency comparison unit 19.
  • an over-frequency setting value fs2 that is a threshold value for detecting an excessive increase in the output frequency f of the inverter device 2 is set.
  • the overfrequency detection setting unit 17 outputs the overfrequency setting value fs2 to the frequency comparison unit 20.
  • the voltage comparison unit 18 compares the voltage V detected by the voltage detection unit 14 with the voltage decrease setting value Vs set in the voltage decrease detection setting unit 15, and determines whether or not the voltage V is lower than the voltage decrease setting value Vs. Determine whether.
  • the voltage comparison unit 18 outputs a signal to the NOT operation circuit 21 and the AND operation circuit 23 based on the determination result. When the voltage V is lower than the voltage drop setting value Vs, the voltage comparison unit 18 outputs a signal indicating “0” as a voltage drop abnormality. When the voltage V is equal to or higher than the voltage drop set value Vs, the voltage comparison unit 18 outputs a signal indicating “1” as normal.
  • the NOT operation circuit 21 inverts the input signal (logical negation) and outputs it to the failure detection unit 25. Therefore, “1” is input to the failure detection unit 25 when the voltage drop is abnormal, and “0” is input when the voltage is normal.
  • the frequency comparison unit 19 compares the frequency f detected by the frequency detection unit 13 with the frequency reduction setting value fs1 set in the frequency reduction detection setting unit 16, and determines whether the frequency f is lower than the frequency reduction setting value fs1. Determine whether.
  • the frequency comparison unit 19 outputs a signal to the NOT operation circuit 22 and the AND operation circuit 23 based on the determination result. When the frequency f is lower than the frequency reduction setting value fs1, the frequency comparison unit 19 outputs a signal indicating “0” as the frequency reduction abnormality. When the frequency f is equal to or higher than the frequency reduction setting value fs1, the frequency comparison unit 19 outputs a signal indicating “1” as normal.
  • NOT operation circuit 22 inverts the input signal (logical negation) and outputs it to failure detection unit 25. Therefore, ‘1’ is input to the failure detection unit 25 when the frequency drop is abnormal, and ‘0’ is input when the frequency is normal.
  • the frequency comparison unit 20 compares the frequency f detected by the frequency detection unit 13 with the overfrequency setting value fs2 set in the overfrequency detection setting unit 17, and determines whether the frequency f is higher than the overfrequency setting value fs2. Determine whether.
  • the frequency comparison unit 20 outputs a signal to the failure detection unit 25 based on the determination result.
  • the frequency comparison unit 20 When the frequency f is higher than the overfrequency setting value fs2, the frequency comparison unit 20 outputs a signal indicating “1” as an overfrequency abnormality.
  • the frequency comparison unit 20 outputs a signal indicating “0” as normal.
  • Signals are input to the AND operation circuit 23 from the voltage comparison unit 18 and the frequency comparison unit 19, respectively.
  • the AND operation circuit 23 outputs the logical product of the two input signals to the XOR operation circuit 24. Accordingly, when both of the two input signals are “1” (when both of the two input signals indicate “normal”), the AND operation circuit 23 outputs a signal indicating “1”. Otherwise (when at least one of the two input signals indicates “abnormal”), a signal indicating “0” is output.
  • the XOR operation circuit 24 receives the signal output from the AND operation circuit 23 and the signal transmitted from the monitoring command unit 33 of the inverter device 2.
  • the XOR operation circuit 24 outputs an exclusive OR of the two signals to the failure detection unit 25.
  • the XOR operation circuit 24 outputs a signal indicating “1” as a monitoring abnormality when the two input signals do not match, and outputs a signal indicating “0” as normal when they match.
  • the XOR operation circuit 24 determines that a monitoring abnormality has occurred and '1 A signal indicating 'is output.
  • This abnormality means that although the monitoring device 1 is normally monitoring, the monitoring condition is not satisfied on the inverter device 2 side.
  • the XOR operation circuit 24 determines that there is an abnormality and indicates a signal indicating “1”. Is output. This abnormality means that the monitoring condition is established on the inverter device 2 side, and the monitoring device 1 is in a state of detecting the abnormality.
  • the failure detection unit 25 detects a failure based on signals received from the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, and the XOR operation circuit 24.
  • the failure detection unit 25 determines that a failure occurs if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality).
  • the failure detection unit 25 outputs a failure signal NG to the inverter device 2.
  • the inverter device 2 by configuring the monitoring device 1 with hardware independent of the control system of the inverter device 2, even if an abnormality occurs in the inverter device 2, the inverter device 2
  • the monitoring device 1 can monitor the inverter device 2 without being affected by the abnormality. For example, when a failure is detected inside the inverter device 2, it is difficult to detect a failure such as a failure in the failure detection circuit itself or a rise in the system clock. However, if the monitoring device 1 is independent from the inverter device 2. It can be easily detected. Therefore, the drive system 10 can be a highly reliable system.
  • the monitoring apparatus 1 is provided with the monitoring command unit 33, and when the monitoring condition is satisfied, the monitoring apparatus 1 can perform monitoring with higher reliability by transmitting the monitoring command to the monitoring apparatus 1. .
  • the monitoring command transmitted from the inverter device 2 with the monitoring status detected by the monitoring device 1, it is possible to detect an abnormality that cannot be detected from outside the inverter device 2.
  • the monitoring device 1 can detect an abnormality that does not cause a change in the output voltage V of the inverter device 2.
  • FIG. 3 is a configuration diagram showing the configuration of the drive system 10A according to the second embodiment of the present invention.
  • the drive system 10A is obtained by replacing the monitoring device 1 with the monitoring device 1A in the drive system 10 according to the first embodiment shown in FIG.
  • the monitoring device 1A replaces the monitoring circuit 6 of the monitoring device 1 according to the first embodiment from the failure detection unit 25 to the failure detection unit 25A, and replaces the frequency change setting unit 26, the frequency change comparison unit 27, and the previous value memory. 28 and a monitoring circuit 6A to which a subtractor 29 is added. Other points are the same as in the first embodiment.
  • a frequency change set value fs3 is set as a threshold value for detecting a significant change in the output frequency of the inverter device 2.
  • the frequency change setting unit 26 outputs the frequency change set value fs3 to the frequency change comparison unit 27.
  • the frequency f detected by the frequency detector 13 is input to the previous value memory 28.
  • the previous value memory 28 outputs the previously stored previous frequency fp to the subtractor 29, and newly stores the input frequency f as the previous frequency fp.
  • the subtracter 29 receives the frequency f detected by the frequency detector 13 and the previous frequency fp stored in the previous value memory 28.
  • the subtractor 29 outputs a frequency change fd obtained by subtracting the frequency f from the previous frequency fp to the frequency change comparison unit 27.
  • the frequency change comparison unit 27 calculates the absolute value of the frequency change fd calculated by the subtractor 29.
  • the frequency change comparison unit 27 compares the calculated absolute value of the frequency change fd with the frequency change set value fs3 set in the frequency change setting unit 26, and the absolute value of the frequency change fd is the frequency change. It is determined whether or not it is larger than the set value fs3.
  • the frequency change comparison unit 27 outputs a signal to the failure detection unit 25A based on the determination result.
  • the absolute value of the frequency change fd is larger than the frequency change set value fs3
  • the frequency change comparison unit 27 outputs a signal indicating ‘1’ as the frequency change abnormality.
  • the absolute value of the frequency change fd is equal to or less than the frequency change set value fs3, the frequency change comparison unit 27 outputs a signal indicating “0” as normal.
  • the failure detection unit 25A detects a failure based on signals received from the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, and the frequency change comparison unit 27.
  • the failure detection unit 25A determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality).
  • the failure detection unit 25A outputs a failure signal NG to the inverter device 2 when detecting a failure.
  • the present embodiment in addition to the operational effects of the first embodiment, by monitoring the change in the output frequency of the inverter device 2, it is possible to detect an abnormality such as a significant change in the output frequency.
  • FIG. 4 is a configuration diagram showing the configuration of a drive system 10B according to the third embodiment of the present invention.
  • the drive system 10B is obtained by replacing the monitoring device 1 with the monitoring device 1B and replacing the inverter device 2 with the inverter device 2B in the drive system 10 according to the first embodiment shown in FIG.
  • the monitoring device 1B replaces the monitoring circuit 6 of the monitoring device 1 according to the first embodiment with the failure detection unit 25B from the failure detection unit 25, and includes a voltage reference difference setting unit 41, a frequency reference difference setting unit 42, and a voltage reference comparison.
  • This is a monitoring circuit 6B in which a unit 43, a voltage reference calculation unit 44, a frequency reference comparison unit 45, and two subtractors 46 and 47 are added.
  • the inverter device 2B is obtained by replacing the control device 8 of the inverter device 2 according to the first embodiment with a control device 8B to which a frequency reference output unit 35 is added. Other points are the same as in the first embodiment.
  • the current frequency reference fr controlling the inverter circuit 7 is input from the operation sequence execution unit 31 to the frequency reference output unit 35.
  • the frequency reference fr is used for control by the control device 8B and is a reference for controlling the output frequency of the inverter circuit 7.
  • the frequency reference output unit 35 outputs the frequency reference fr to the monitoring device 1B.
  • the frequency reference fr is input to the voltage reference calculation unit 44 from the frequency reference output unit 35 of the inverter device 2B.
  • the voltage reference calculation unit 44 calculates the voltage reference Vr by multiplying the input frequency reference fr by a preset V / F ratio.
  • the voltage reference calculation unit 44 outputs the calculated voltage reference Vr to the subtractor 46.
  • the voltage reference difference setting unit 41 is set with a voltage reference difference setting value Vsr that serves as a threshold for detecting that the difference between the output voltage V of the inverter 2B and the voltage reference Vr calculated by the voltage reference calculation unit 44 is large. ing.
  • the voltage reference difference setting unit 41 outputs the voltage reference difference setting value Vsr to the voltage reference comparison unit 43.
  • the frequency reference difference setting unit 42 is set with a frequency reference difference setting value fsr that is a threshold value for detecting that the difference between the output frequency f of the inverter device 2B and the frequency reference fr input from the inverter device 2B is large. .
  • the frequency reference difference setting unit 42 outputs the frequency reference difference setting value fsr to the frequency reference comparison unit 45.
  • the subtracter 46 receives the voltage V detected by the voltage detector 14 and the voltage reference Vr calculated by the voltage reference calculator 44.
  • the subtractor 46 calculates a voltage error Ve obtained by subtracting the voltage V from the voltage reference Vr.
  • the subtractor 46 outputs the calculated voltage error Ve to the voltage reference comparison unit 43.
  • the frequency reference fr output from the inverter device 2B and the frequency f detected by the frequency detector 13 are input to the subtractor 47.
  • the subtractor 47 calculates a frequency error fe obtained by subtracting the frequency f from the frequency reference fr.
  • the subtractor 47 outputs the calculated frequency error fe to the frequency reference comparison unit 45.
  • the voltage reference comparison unit 43 calculates the absolute value of the voltage error Ve calculated by the subtractor 46.
  • the voltage reference comparison unit 43 compares the calculated absolute value of the voltage error Ve with the voltage reference difference setting value Vsr set in the voltage reference difference setting unit 41, and the absolute value of the voltage error Ve is the voltage reference difference setting value Vsr. It is judged whether it is larger than.
  • the voltage reference comparison unit 43 outputs a signal to the failure detection unit 25B based on the determination result.
  • the voltage reference comparison unit 43 When the absolute value of the voltage error Ve is larger than the voltage reference difference setting value Vsr, the voltage reference comparison unit 43 outputs a signal indicating “1” as a voltage reference abnormality.
  • the voltage reference comparison unit 43 When the absolute value of the voltage error Ve is equal to or smaller than the voltage reference difference setting value Vsr, the voltage reference comparison unit 43 outputs a signal indicating “0” as normal.
  • the frequency reference comparison unit 45 calculates the absolute value of the frequency error fe calculated by the subtractor 47.
  • the frequency reference comparison unit 45 compares the calculated absolute value of the frequency error fe with the frequency reference difference setting value fsr set in the frequency reference difference setting unit 42, and the absolute value of the frequency error fe is the frequency reference difference setting value fsr. It is judged whether it is larger than.
  • the frequency reference comparison unit 45 outputs a signal to the failure detection unit 25B based on the determination result.
  • the frequency reference comparison unit 45 When the absolute value of the frequency error fe is larger than the frequency reference difference set value fsr, the frequency reference comparison unit 45 outputs a signal indicating “1” as a frequency reference abnormality.
  • the absolute value of the frequency error fe is equal to or less than the frequency reference difference set value fsr, the frequency reference comparison unit 45 outputs a signal indicating “0” as normal.
  • the failure detection unit 25B detects a failure based on signals received from the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, the voltage reference comparison unit 43, and the frequency reference comparison unit 45. To detect.
  • the failure detection unit 25B determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality).
  • the failure detection unit 25B outputs a failure signal NG to the inverter device 2B.
  • the frequency reference fr is multiplied by the V / F ratio to obtain the voltage reference Vr, and the output voltage V of the inverter device 2B is compared with the voltage reference Vr, thereby detecting the output abnormality of the inverter device 2B by the VVVF control. it can.
  • FIG. 5 is a configuration diagram showing the configuration of a drive system 10C according to the fourth embodiment of the present invention.
  • the drive system 10C is obtained by replacing the monitoring device 1 with the monitoring device 1C in the drive system 10 according to the first embodiment shown in FIG.
  • the monitoring device 1C includes a voltage detector 5C and a monitoring circuit 6C.
  • the monitoring circuit 6C includes a voltage comparison unit 18, a frequency comparison unit 19, a frequency comparison unit 20, and a failure detection unit 25.
  • the voltage comparison unit 18C, the frequency comparison unit 19C, instead of the comparison unit 20C and the failure detection unit 25C, a phase sequence setting unit 51, a phase sequence comparison unit 52, and three majority decision circuits 53, 54, and 55 are added. Other points are the same as in the first embodiment.
  • the voltage detector 5C is the same as the voltage detector 5 according to the first embodiment, except that the three interphase voltages output from the inverter device 2 are detected. In addition, although the voltage detector 5C demonstrates the structure which detects an interphase voltage here, the structure which detects a phase voltage may be sufficient.
  • the voltage detector 5C includes a filter circuit 11C and an insulation circuit 12C.
  • the filter circuit 11C shapes the three interphase voltages from a rectangular wave to a sine wave. Other points are the same as those of the filter circuit 11 according to the first embodiment.
  • the insulation circuit 12 insulates the monitoring circuit 6C from the main circuit of the drive system 10C for the three interphase voltages. Other points are the same as those of the insulating circuit 12 according to the first embodiment.
  • the frequency detector 13C detects the frequencies fuv, fvw, and fwu based on the waveform of the voltage between the phases detected by the voltage detector 5C.
  • the frequency fuv is the frequency of the voltage between the U phase and the V phase
  • the frequency fvw is the frequency of the voltage between the V phase and the W phase
  • the frequency fwu is the voltage between the W phase and the U phase. It is assumed that each frequency is represented.
  • the frequency detection unit 13C outputs the calculated frequencies fuv, fvw, fwu of the respective interphase voltages to the frequency comparison unit 19C and the frequency comparison unit 20C, and zero-crosses the detected interphase voltages to calculate the frequencies fuv, fvw, fwu. Information about the points is output to the phase sequence comparison unit 52.
  • the voltage detection unit 14C calculates the interphase voltages Vuv, Vvw, Vwu based on the instantaneous value of the voltage detected by the voltage detector 5C.
  • the interphase voltage Vuv is the voltage between the U phase and the V phase
  • the interphase voltage Vvw is the voltage between the V phase and the W phase
  • the interphase voltage Vwu is the voltage between the W phase and the U phase.
  • the voltage detection unit 14C outputs the calculated interphase voltages Vuv, Vvw, Vwu to the voltage comparison unit 18C.
  • phase order setting unit 51 a phase order set value Sqs is set.
  • the phase order is a phase order in which a zero cross point occurs at the output voltage V of the inverter device 2.
  • the phase sequence setting unit 51 outputs the phase sequence to the phase sequence comparison unit 52.
  • the phase order is the order of the U phase, the V phase, and the W phase, and the phase order set value Sqs is also set in the same order.
  • the phase order comparison unit 52 receives the information about the zero-cross point of each interphase voltage output from the frequency detection unit 13 ⁇ / b> C and the phase sequence setting value Sqs set in the phase sequence setting unit 51.
  • the phase sequence comparison unit 52 determines whether or not the phase sequence Sq determined based on the zero cross point of each interphase voltage matches the phase sequence setting value Sqs. If they match, the phase sequence comparison unit 52 outputs a signal indicating “0” as normal to the failure detection unit 25C. If they do not match, the phase sequence comparison unit 52 outputs a signal indicating '1' as a phase sequence abnormality to the failure detection unit 25C.
  • the calculation for determining the phase sequence Sq from the zero cross point of each interphase voltage may be performed by the frequency detector 13C.
  • the voltage comparison unit 18C uses the interphase voltages Vuv, Vvw, Vwu detected by the voltage detection unit 14C and the voltage drop setting value Vs set in the voltage drop detection setting unit 15 in the same manner as in the first embodiment. Compare. The voltage comparison unit 18C outputs the comparison results for the interphase voltages Vuv, Vvw, and Vwu to the majority decision circuit 53.
  • Majority determination circuits 53 to 55 are circuits that output more than a majority of information among a plurality of input information. For example, when three signals indicating a binary variable that takes “0” or “1” are input, the majority decision circuits 53 to 55 are “1” if two or more signals indicate “1”. 'Is output, otherwise' 0 'is output.
  • the majority decision determination circuit 53 determines whether or not the voltage drop is abnormal based on the comparison result input from the voltage comparison unit 18C.
  • the majority decision circuit 53 determines that the voltage drop is abnormal if at least two of the three interphase voltages Vuv, Vvw, and Vwu are lower than the voltage drop set value Vs. That is, if two or more of the following three inequalities hold, it is determined that the voltage drop is abnormal, and otherwise, it is determined normal.
  • the majority decision circuit 53 outputs a signal indicating “0” to the NOT operation circuit 21 and the AND operation circuit 23 when determining that the voltage drop abnormality is normal, and when determining that it is normal, the majority determination circuit 53 outputs a signal indicating “1”. .
  • the frequency comparison unit 19C sets the frequency fuv, fvw, fwu of each inter-phase voltage detected by the frequency detection unit 13C and the frequency decrease setting value fs1 set in the frequency decrease detection setting unit 16 as in the first embodiment. Compare in the same way.
  • the frequency comparison unit 19 ⁇ / b> C outputs the comparison results for the frequencies fuv, fvw, and fwu to the majority decision circuit 54.
  • the majority decision determination circuit 54 determines whether or not it is a frequency drop abnormality based on the comparison result input from the frequency comparison unit 19C.
  • the majority decision circuit 54 determines that the frequency decrease is abnormal if at least two of the three frequencies fuv, fvw, and fwu are lower than the frequency decrease setting value fs1, and otherwise determines that the frequency is normal. That is, if two or more of the following three inequalities hold, it is determined that the frequency drop is abnormal, otherwise it is determined normal.
  • the majority decision circuit 54 outputs a signal indicating “0” to the NOT operation circuit 22 and the AND operation circuit 23 when it is determined that the frequency decrease is abnormal, and when it is determined that the majority determination circuit 54 is normal. .
  • the frequency comparison unit 20C uses the frequencies fuv, fvw, fwu of the voltages between the phases detected by the frequency detection unit 13C and the overfrequency setting value fs2 set in the overfrequency detection setting unit 17 as in the first embodiment. Compare in the same way.
  • the frequency comparison unit 20 ⁇ / b> C outputs the comparison results for the frequencies fuv, fvw, and fwu to the majority decision circuit 55.
  • the majority decision determination circuit 55 determines whether or not there is an overfrequency abnormality based on the comparison result input from the frequency comparison unit 20C.
  • the majority decision circuit 55 determines that the frequency is abnormal when at least two of the three frequencies fuv, fvw, and fwu are higher than the overfrequency setting value fs2, and determines that the frequency is normal otherwise. That is, if two or more of the following three inequalities hold, it is determined that there is an overfrequency abnormality, and otherwise, it is determined that it is normal.
  • the majority decision circuit 55 outputs a signal indicating ‘1’ to the failure detection unit 25 if it is determined to be abnormal, and a signal indicating ‘0’ to the failure detection unit 25 if it is determined to be normal.
  • the failure detection unit 25C detects a failure based on signals received from the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, the phase sequence comparison unit 52, and the majority decision determination circuit 55.
  • the failure detection unit 25C determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality).
  • the failure detection unit 25C outputs a failure signal NG to the inverter device 2 when detecting a failure.
  • FIG. 6 is a configuration diagram showing the configuration of a drive system 10D according to the fifth embodiment of the present invention.
  • the drive system 10D is obtained by replacing the monitoring device 1 with the monitoring device 1D in the drive system 10 according to the first embodiment shown in FIG.
  • the monitoring device 1D includes three monitoring devices 1, 101, and 102, and a majority circuit 56 is added. Other points are the same as in the first embodiment.
  • the monitoring devices 101 and 102 are the same devices as the monitoring device 1.
  • the majority circuit 56 is the same as the majority circuits 53 to 55 according to the fourth embodiment.
  • the three monitoring devices 1, 101, 102 input different line voltages to the voltage detector 5 and perform monitoring separately.
  • the failure output signals NG 1 to NG 3 of the failure detection unit 25 of each of the monitoring devices 1, 101, 102 are input to the majority decision circuit 56.
  • the majority decision circuit 56 determines that a failure has occurred if at least two or more of the outputs of the three failure detectors 25 are signals indicating ‘1’ (that is, signals indicating abnormality).
  • the majority decision circuit 26 outputs a failure signal NG to the inverter device 2.
  • the monitoring devices 1, 101, 102 By arranging the monitoring devices 1, 101, 102 separately for each detected interphase voltage and using the majority decision circuit 56 to determine an abnormality, erroneous detection of the abnormality can be suppressed. Thus, the reliability of abnormality detection by the monitoring device 1D can be improved.
  • FIG. 7 is a configuration diagram showing the configuration of a drive system 10E according to the sixth embodiment of the present invention.
  • the drive system 10E is obtained by replacing the monitoring device 1 with the monitoring device 1E in the drive system 10 according to the first embodiment shown in FIG.
  • the monitoring device 1E includes a voltage detector 5C and a monitoring circuit 6E according to the fourth embodiment.
  • the monitoring circuit 6E replaces the failure detection unit 25 with the failure detection unit 25E, and replaces the frequency detection unit 13 and the voltage detection unit 14 with the frequency detection unit 13C according to the fourth embodiment.
  • the voltage comparison unit 18, the frequency comparison unit 19, and the frequency comparison unit 20 are replaced with the voltage comparison unit 18E, the frequency comparison unit 19E, and the frequency comparison unit 20E, respectively.
  • a phase sequence setting unit 51 and a phase sequence comparison unit 52, a voltage variation detection setting unit 61, a frequency variation detection setting unit 62, a voltage difference comparison unit 63, and a frequency difference comparison unit 64 are added. Other points are the same as in the first embodiment.
  • the voltage comparison unit 18E compares the interphase voltages Vuv, Vvw, Vwu detected by the voltage detection unit 14C with the voltage decrease setting value Vs set in the voltage decrease detection setting unit 15, respectively, and at least one interphase voltage If Vuv, Vvw, Vwu are lower than the voltage drop set value Vs, it is determined that the voltage drop is abnormal.
  • the other points are the same as those of the voltage comparison unit 18 according to the first embodiment.
  • the frequency comparison unit 19E compares each frequency fuv, fvw, fwu detected by the frequency detection unit 13C with the frequency decrease setting value fs1 set in the frequency decrease detection setting unit 16, and thereby compares at least one frequency fuv, If fvw and fwu are lower than the frequency drop set value fs1, it is determined that the frequency drop is abnormal. Other points are the same as those of the frequency comparison unit 19 according to the first embodiment.
  • the frequency comparison unit 20E compares at least one frequency fuv, fvw, fwu detected by the frequency detection unit 13C with the overfrequency setting value fs2 set in the overfrequency detection setting unit 17, respectively. If fvw and fwu are higher than the overfrequency set value fs2, it is determined that the overfrequency is abnormal. Other points are the same as those of the frequency comparison unit 20 according to the first embodiment.
  • phase sequence setting unit 51 and the phase sequence comparison unit 52 The method of detecting the phase sequence abnormality by the phase sequence setting unit 51 and the phase sequence comparison unit 52 is the same as in the fourth embodiment.
  • a voltage fluctuation setting value Vsv serving as a threshold for detecting large fluctuations among the output phase voltages Vuv, Vvw, Vwu of the inverter device 2 is set.
  • the voltage fluctuation detection setting unit 61 outputs the voltage fluctuation setting value Vsv to the voltage difference comparison unit 63.
  • a frequency fluctuation setting value fsv serving as a threshold for detecting large fluctuations among the frequencies fuv, fvw, and fwu of the output phase voltage of the inverter device 2 is set.
  • the frequency fluctuation detection setting unit 62 outputs the frequency fluctuation setting value fsv to the frequency difference comparison unit 64.
  • the voltage difference comparison unit 63 calculates the absolute value of the voltage difference between the interphase voltages Vuv, Vvw, and Vwu detected by the voltage detection unit 14C.
  • the voltage difference comparison unit 63 compares the calculated three voltage difference absolute values with the voltage variation setting value Vsv set in the voltage variation detection setting unit 61 to determine whether or not the voltage variation is abnormal. If at least one of the absolute values of these voltage differences is larger than the voltage fluctuation set value Vsv, it is determined that the voltage fluctuation is abnormal. That is, if at least one of the following three inequalities holds, it is determined that the voltage fluctuation is abnormal, and otherwise, it is determined normal.
  • the voltage difference comparison unit 63 When it is determined that the voltage fluctuation is abnormal, the voltage difference comparison unit 63 outputs a signal indicating “1” to the failure detection unit 25E. When it is determined that the voltage is normal, the voltage difference comparison unit 63 outputs a signal indicating “0” to the failure detection unit 25E.
  • the frequency difference comparison unit 64 calculates the absolute value of the frequency difference between the frequencies fuv, fvw, and fwu of the interphase voltage detected by the frequency detection unit 13C.
  • the frequency difference comparison unit 64 compares the calculated absolute values of the three frequency differences with the frequency variation setting value fsv set in the frequency variation detection setting unit 62 to determine whether or not the frequency variation is abnormal. If at least one of the absolute values of these frequency differences is larger than the frequency fluctuation set value fsv, it is determined that the frequency fluctuation is abnormal.
  • the frequency difference comparison unit 64 outputs a signal indicating “1” to the failure detection unit 25E. If it is determined that the frequency is normal, the frequency difference comparison unit 64 outputs a signal indicating “0” to the failure detection unit 25E.
  • the failure detection unit 25E receives signals from the frequency comparison unit 20E, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, the phase sequence comparison unit 52, the voltage difference comparison unit 63, and the frequency difference comparison unit 64. Based on the above, a failure is detected.
  • the failure detection unit 25E determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality).
  • the failure detection unit 25E outputs a failure signal NG to the inverter device 2 when detecting a failure.
  • FIG. 8 is a configuration diagram showing a configuration of a drive system 10F according to the seventh embodiment of the present invention.
  • the drive system 10F is obtained by replacing the monitoring device 1 with the monitoring device 1F and adding a host system 9.
  • the monitoring device 1F replaces the monitoring circuit 6 of the monitoring device 1 according to the first embodiment with a monitoring circuit 6F in which an OR operation circuit 71 and an XOR operation circuit 72 are added instead of the failure detection unit 25 to the failure detection unit 25F. It is a thing. Other points are the same as in the first embodiment.
  • the host system 9 is a host control system of the control device 8 of the inverter device 2.
  • the host system 9 includes an operation command unit 91 and a monitoring command unit 92.
  • the operation command unit 91 transmits an operation command including the control content of the drive system 10F to the control device 8 of the inverter device 2.
  • the operation command unit 91 grasps the current operation state of the drive system 10 ⁇ / b> F by transmitting and receiving information to and from the operation sequence execution unit 31 of the control device 8.
  • the operation command unit 91 determines the content of the operation command based on the operation state of the drive system 10F.
  • the control device 8 controls the drive system 10F in accordance with the operation command received from the operation command unit 91.
  • the monitoring command unit 92 outputs a monitoring command to the monitoring device 1F when the monitoring condition is satisfied. Whether or not the monitoring condition is satisfied is determined by whether or not the inverter device 2 is in a state of being monitored, similarly to the monitoring command unit 33 of the inverter device 2. The monitoring condition is satisfied if there is no factor that prevents the monitoring by the monitoring device 1F from being performed normally. For example, the monitoring command unit 92 determines whether or not the monitoring condition is satisfied based on the operation state of the inverter device 2 and the electric motor 3 received from the operation command unit 91. If the monitoring condition is satisfied, the monitoring command unit 92 outputs a monitoring command to the monitoring device 1F.
  • the monitoring command unit 92 When the monitoring condition is not satisfied, the monitoring command unit 92 does not output a monitoring command to the monitoring device 1F.
  • the monitoring command unit 92 transmits the monitoring command signal C2 to “1” when outputting the monitoring command, and transmits the monitoring command signal C2 to “0” when not outputting the monitoring command. .
  • the OR operation circuit 71 receives the monitoring command signal C1 received from the inverter device 2 and the monitoring command signal C2 received from the host system 9.
  • the OR operation circuit 71 outputs the logical sum of the two input monitoring command signals C1 and C2 to the XOR operation circuit 24. Therefore, when at least one of the two input monitoring command signals C1 and C2 is '1' (when at least one of the host system 9 or the inverter device 2 outputs a monitoring command), the XOR operation circuit “1” is input to 24, otherwise “0” is input to the XOR operation circuit 24.
  • the monitor command signal C1 received from the inverter device 2 and the monitor command signal C2 received from the host system 9 are input to the XOR operation circuit 72.
  • the XOR operation circuit 72 outputs the exclusive OR of the two input monitoring command signals C1 and C2 to the failure detection unit 25F.
  • the XOR operation circuit 72 outputs a signal indicating “1” as a mismatch error, and is not so. In this case, a signal indicating “0” is output as normal. In this abnormality detection, this abnormality can be detected when either the inverter device 2 or the host system 9 has an abnormality.
  • the failure detection unit 25F detects a failure based on signals received from each of the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, and the XOR operation circuit 72.
  • the failure detection unit 25F determines that there is a failure if any of the received signals is a signal indicating '1' (that is, a signal indicating abnormality).
  • the failure detection unit 25F outputs a failure signal NG to the inverter device 2 when detecting a failure.
  • the monitoring device 1 which is an external device, matches the consistency between the control by the control device 8 built in the inverter device 2 and the control of the host system 9. Can be monitored. Thereby, the reliability of control of the drive system 10F can be improved.
  • the abnormality detection method may be arbitrarily combined. An appropriate abnormality detection method can be selected according to the operating environment of the monitoring device.
  • a majority decision circuit is used. However, in other embodiments, a majority decision circuit may be used for arbitrary abnormality detection.
  • the host system 9 according to the seventh embodiment may be applied to other embodiments.
  • the configuration using the voltage detectors 5 and 5C that detect (measure) the voltage has been described.
  • the output current or the output power Any output amount may be detected, such as the amount of electricity (such as magnitude or frequency), or the amount of operation such as the rotational speed or torque of an electric motor that operates with the output of the power converter.
  • the inverter circuit 7 when the inverter devices 2 and 2B receive the failure signal NG detected by the monitoring devices 1 to 1F, the inverter circuit 7 is gate-blocked, but the protection operation other than the gate block is performed. Also good. For example, when a failure is detected by the monitoring devices 1 to 1F, the circuit breaker provided on the DC side or the AC side may be tripped so as to stop the output of the inverter devices 2 and 2B.
  • the majority decision determination circuits 53 to 56 are circuits that output more than a majority of the input information, but may output an abnormality only when the total number is abnormal.
  • a system for controlling an electric motor using an inverter has been described.
  • any monitoring target system and monitoring device may be used as long as the system controls the output of a power conversion device (including an inverter).
  • the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage.
  • various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment.
  • constituent elements over different embodiments may be appropriately combined.

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  • Inverter Devices (AREA)

Abstract

Disclosed is a monitoring apparatus (1), which is configured from a hardware independent from a control system of an inverter apparatus (2), and which monitors the inverter apparatus (2). The monitoring apparatus detects an output voltage (V) of the inverter apparatus (2), monitors the output voltage (V) on the basis of the detected output voltage (V), detects an output abnormality of the inverter apparatus (2) on the basis of the monitoring of the output voltage (V), receives monitor command signals (C1) that indicate whether the inverter apparatus (2) is in a state of being to be monitored or not, and detects a monitor abnormality on the basis of the monitoring of the output voltage (V) and the monitor command signals (C1).

Description

電力変換装置の監視装置Monitoring device for power converter
　本発明は、電力変換装置を監視する電力変換装置の監視装置に関する。 The present invention relates to a monitoring device for a power conversion device that monitors the power conversion device.
　一般に、インバータなどの電力変換装置には、故障を検出する故障検出機能を備えている。 Generally, a power conversion device such as an inverter has a failure detection function for detecting a failure.
　例えば、電動機制御装置の制御回路から時系列に入力される故障信号及び履歴データ記録用信号を受信して、表示用トレンドデータを作成する監視装置が開示されている（特許文献１参照）。 For example, a monitoring device is disclosed that receives a failure signal and a history data recording signal input in time series from a control circuit of an electric motor control device, and creates display trend data (see Patent Document 1).
　また、複数の電力変換装置を関連付けて故障解析を行うプラントドライブの監視システムが開示されている。この監視システムでは、電力変換装置は、それぞれ自らの故障信号で自らのトレンドデータを保存し、プロセスコントローラは、故障信号を受信すると、故障信号を送信した電力変換装置のトレンドデータを受信し、さらに周辺の電力変換装置のトレンドデータを受信して、収集したトレンドデータを編集する（特許文献２参照）。 Also, a plant drive monitoring system that performs failure analysis by associating a plurality of power conversion devices is disclosed. In this monitoring system, each power converter stores its own trend data with its own fault signal, and when the process controller receives the fault signal, it receives the trend data of the power converter that sent the fault signal, and The trend data of the peripheral power converters is received and the collected trend data is edited (see Patent Document 2).
　しかしながら、自身の故障を検出する電力変換装置では、故障検出回路自体の異常又はシステムクロックの上昇などのように電力変換装置自体に異常の原因がある場合、故障を検出できない可能性がある。 However, in the power conversion device that detects its own failure, there is a possibility that the failure cannot be detected when there is a cause of the abnormality in the power conversion device itself, such as an abnormality in the failure detection circuit itself or an increase in the system clock.
特開２００４－２８０６９９号公報JP 2004-280699 A 特開２００６－１４１０８８号公報JP 2006-141088 A
　本発明の目的は、電力変換装置に生じる故障の検出率を高めた電力変換装置の監視装置を提供することにある。 An object of the present invention is to provide a monitoring device for a power conversion device with an increased detection rate of a failure occurring in the power conversion device.
　本発明の観点に従った電力変換装置の監視装置は、電力変換装置の制御系から独立したハードウェアで構成され、前記電力変換装置を監視する電力変換装置の監視装置であって、前記電力変換装置の出力を検出する出力検出手段と、前記出力検出手段により検出された前記電力変換装置の出力に基づいて、前記電力変換装置の出力を監視する出力監視手段と、前記出力監視手段による監視に基づいて、前記電力変換装置の出力異常を検出する出力異常検出手段と、前記電力変換装置が監視される状態にあるか否かを示す監視信号を受信する監視信号受信手段と、前記出力監視手段による監視及び前記監視信号受信手段から受信した前記監視信号に基づいて、監視異常を検出する監視異常検出手段とを備える。 A monitoring device for a power conversion device according to an aspect of the present invention is a monitoring device for a power conversion device configured by hardware independent of a control system of the power conversion device and monitoring the power conversion device, wherein the power conversion For output monitoring means for detecting the output of the apparatus, output monitoring means for monitoring the output of the power conversion apparatus based on the output of the power conversion apparatus detected by the output detection means, and monitoring by the output monitoring means Based on output abnormality detection means for detecting an output abnormality of the power converter, monitoring signal receiving means for receiving a monitoring signal indicating whether or not the power converter is in a state of being monitored, and the output monitoring means And monitoring abnormality detecting means for detecting a monitoring abnormality based on the monitoring signal received from the monitoring signal and the monitoring signal received from the monitoring signal receiving means.
図１は、本発明の第１の実施形態に係るドライブシステムの構成を示す構成図である。FIG. 1 is a configuration diagram showing the configuration of the drive system according to the first embodiment of the present invention. 図２は、第１の実施形態に係るフィルタ回路の機能を示す概略図である。FIG. 2 is a schematic diagram illustrating functions of the filter circuit according to the first embodiment. 図３は、本発明の第２の実施形態に係るドライブシステムの構成を示す構成図である。FIG. 3 is a configuration diagram showing the configuration of the drive system according to the second embodiment of the present invention. 図４は、本発明の第３の実施形態に係るドライブシステムの構成を示す構成図である。FIG. 4 is a configuration diagram showing the configuration of the drive system according to the third embodiment of the present invention. 図５は、本発明の第４の実施形態に係るドライブシステムの構成を示す構成図である。FIG. 5 is a configuration diagram showing the configuration of the drive system according to the fourth embodiment of the present invention. 図６は、本発明の第５の実施形態に係るドライブシステムの構成を示す構成図である。FIG. 6 is a configuration diagram showing the configuration of the drive system according to the fifth embodiment of the present invention. 図７は、本発明の第６の実施形態に係るドライブシステムの構成を示す構成図である。FIG. 7 is a configuration diagram showing the configuration of the drive system according to the sixth embodiment of the present invention. 図８は、本発明の第７の実施形態に係るドライブシステムの構成を示す構成図である。FIG. 8 is a configuration diagram showing the configuration of the drive system according to the seventh embodiment of the present invention.
（第１の実施形態）
　図１は、本発明の第１の実施形態に係るドライブシステム１０の構成を示す構成図である。なお、図面における同一部分には同一符号を付して重複する説明を適宜省略し、異なる部分について主に述べる。 (First embodiment)
FIG. 1 is a configuration diagram showing the configuration of a drive system 10 according to the first embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same part in drawing, the overlapping description is abbreviate | omitted suitably, and a different part is mainly described.
　ドライブシステム１０は、監視装置１、インバータ装置２、電動機３、及び直流電源４を備える。例えば、ドライブシステム１０は、速度センサを取り付けることができない速度センサレスドライブシステムである。 The drive system 10 includes a monitoring device 1, an inverter device 2, an electric motor 3, and a DC power supply 4. For example, the drive system 10 is a speed sensorless drive system to which a speed sensor cannot be attached.
　直流電源４は、インバータ装置２に接続されている。直流電源４は、インバータ装置２に直流電力を供給する。直流電源４は、発電機、電池、又は電力変換装置など直流電力を出力するものであれば何でもよい。 The DC power supply 4 is connected to the inverter device 2. The DC power supply 4 supplies DC power to the inverter device 2. The DC power supply 4 may be anything as long as it outputs DC power, such as a generator, a battery, or a power converter.
　インバータ装置２は、直流電源４から供給された直流電力を三相交流電力に変換する電力変換装置である。インバータ装置２の交流側には、電動機３が接続されている。インバータ装置２は、変換した交流電力を電動機３に出力することで、電動機３の駆動を制御する。インバータ装置２は、電動機３のＶ／Ｆ（電圧／周波数）比を一定に維持するＶＶＶＦ(variable voltage variable frequency)制御をする。Ｖ／Ｆ比は、電動機３の磁束を一定にするための電圧と周波数の比率である。 The inverter device 2 is a power conversion device that converts DC power supplied from the DC power supply 4 into three-phase AC power. An electric motor 3 is connected to the AC side of the inverter device 2. The inverter device 2 controls the drive of the electric motor 3 by outputting the converted AC power to the electric motor 3. The inverter device 2 performs VVVF (variable voltage variable frequency) control that keeps the V / F (voltage / frequency) ratio of the electric motor 3 constant. The V / F ratio is a ratio of voltage and frequency for making the magnetic flux of the electric motor 3 constant.
　監視装置１は、インバータ装置２及び電動機３から独立したハードウェアで構成される装置である。監視装置１は、インバータ装置２から出力される三相交流電圧の相間電圧を取り込む配線で、インバータ装置２から電動機３に交流電力が供給される電気経路に接続されている。監視装置１は、情報を伝送する伝送路で、インバータ装置２の制御装置８と接続されている。監視装置１は、インバータ装置２から出力される相間電圧を検出し、制御装置８と情報の送受信をすることで、インバータ装置２の状態を監視する。 The monitoring device 1 is a device composed of hardware independent from the inverter device 2 and the electric motor 3. The monitoring device 1 is a wiring that takes in the interphase voltage of the three-phase AC voltage output from the inverter device 2, and is connected to an electrical path through which AC power is supplied from the inverter device 2 to the motor 3. The monitoring device 1 is a transmission path for transmitting information and is connected to the control device 8 of the inverter device 2. The monitoring device 1 monitors the state of the inverter device 2 by detecting the interphase voltage output from the inverter device 2 and transmitting / receiving information to / from the control device 8.
　インバータ装置２は、インバータ回路７及び制御装置８を備える。 The inverter device 2 includes an inverter circuit 7 and a control device 8.
　インバータ回路７は、直流電源４から供給された直流電力を三相交流電力に変換する電気回路である。インバータ回路７は、半導体素子であるスイッチング素子などにより構成されている。インバータ回路７は、ＰＷＭ(pulse width modulation)制御されることにより、電力変換を行う。 The inverter circuit 7 is an electric circuit that converts DC power supplied from the DC power supply 4 into three-phase AC power. The inverter circuit 7 includes a switching element that is a semiconductor element. The inverter circuit 7 performs power conversion by PWM (pulse width modulation) control.
　制御装置８は、インバータ装置２に内蔵された装置である。制御装置８は、各種情報を受信して、ドライブシステム１０を制御する。主に、制御装置８は、インバータ回路７から出力される交流電力を制御することで、電動機３を駆動する。具体的には、制御装置８は、ゲート信号を出力して、インバータ回路７のスイッチング素子を駆動することで、インバータ回路７から出力される交流電力を制御する。これにより、電動機３を駆動する。 The control device 8 is a device built in the inverter device 2. The control device 8 receives various information and controls the drive system 10. The control device 8 mainly drives the electric motor 3 by controlling the AC power output from the inverter circuit 7. Specifically, the control device 8 controls the AC power output from the inverter circuit 7 by outputting a gate signal and driving a switching element of the inverter circuit 7. Thereby, the electric motor 3 is driven.
　制御装置８は、運転シーケンス実行部３１、電動機制御部３２、監視指令部３３、及びゲートブロック指令部３４を備える。 The control device 8 includes an operation sequence execution unit 31, an electric motor control unit 32, a monitoring command unit 33, and a gate block command unit 34.
　運転シーケンス実行部３１は、電動機制御部３２から電動機３及びインバータ回路７の状態などを把握する情報、及び監視装置１により検出された故障信号ＮＧを受信する。運転シーケンス実行部３１は、これらの受信した情報に基づいて、予め決められた運転シーケンスに従って、インバータ回路７及び電動機３に対して行う制御を決定する。運転シーケンス実行部３１は、運転シーケンスにより決定された制御を実行するために、電動機制御部３２又は監視指令部３３に各種の情報を出力する。運転シーケンス実行部３１は、監視装置１から故障信号ＮＧを受信すると、運転シーケンスに従って、インバータ回路７及び電動機３の動作を制限又は停止するような制御を行う。 The operation sequence execution unit 31 receives information for grasping the states of the electric motor 3 and the inverter circuit 7 from the electric motor control unit 32 and the failure signal NG detected by the monitoring device 1. The operation sequence execution unit 31 determines control to be performed on the inverter circuit 7 and the electric motor 3 in accordance with a predetermined operation sequence based on the received information. The operation sequence execution unit 31 outputs various types of information to the electric motor control unit 32 or the monitoring command unit 33 in order to execute the control determined by the operation sequence. When receiving the failure signal NG from the monitoring device 1, the operation sequence execution unit 31 performs control to limit or stop the operations of the inverter circuit 7 and the electric motor 3 according to the operation sequence.
　電動機制御部３２は、インバータ回路７又は電動機３などに設けられた各種センサから電圧又は電流などの情報を受信し、インバータ回路７又は電動機３の状態を判断する。電動機制御部３２は、運転シーケンス実行部３１により決定された制御を実行するために、判断した状態に基づいて、インバータ回路７の出力電力を制御して、電動機３を駆動する。電動機制御部３２は、運転シーケンス実行部３１の運転シーケンスで必要な情報を運転シーケンス実行部３１に出力する。 The electric motor control unit 32 receives information such as voltage or current from various sensors provided in the inverter circuit 7 or the electric motor 3 and determines the state of the inverter circuit 7 or the electric motor 3. The motor control unit 32 controls the output power of the inverter circuit 7 based on the determined state to drive the motor 3 in order to execute the control determined by the operation sequence execution unit 31. The electric motor control unit 32 outputs information necessary for the operation sequence of the operation sequence execution unit 31 to the operation sequence execution unit 31.
　監視指令部３３は、運転シーケンス実行部３１から入力された情報に基づいて、監視条件が成立しているか否かを判断する。監視条件が成立するか否かは、インバータ装置２が監視される状態にあるか否かで決定される。監視装置１による監視が正常に行えないような要因がインバータ装置２側に無ければ、監視条件は成立する。例えば、インバータ回路７が正常に動作していない場合（インバータ回路７の出力が正常でない場合）は、監視条件は不成立となる。監視条件が成立している場合は、監視指令部３３は、監視装置１に監視指令を出力する。監視条件が成立していない場合は、監視指令部３３は、監視装置１に監視指令を出力しない。例えば、監視指令は、インバータ装置２が自己診断により動作が正常の場合に出力するようにしてもよい。監視指令部３３は、監視指令を出力する場合は、監視指令信号Ｃ１を‘１’にして送信し、監視指令を出力しない場合は、監視指令信号Ｃ１を‘０’にして送信する。 The monitoring command unit 33 determines whether the monitoring condition is satisfied based on the information input from the operation sequence execution unit 31. Whether or not the monitoring condition is satisfied is determined by whether or not the inverter device 2 is in a state of being monitored. If there is no factor on the inverter device 2 side that prevents monitoring by the monitoring device 1 from being performed normally, the monitoring condition is satisfied. For example, when the inverter circuit 7 is not operating normally (when the output of the inverter circuit 7 is not normal), the monitoring condition is not satisfied. If the monitoring condition is satisfied, the monitoring command unit 33 outputs a monitoring command to the monitoring device 1. When the monitoring condition is not satisfied, the monitoring command unit 33 does not output a monitoring command to the monitoring device 1. For example, the monitoring command may be output when the inverter device 2 operates normally by self-diagnosis. The monitoring command unit 33 transmits the monitoring command signal C1 to ‘1’ when outputting the monitoring command, and transmits the monitoring command signal C1 to ‘0’ when not outputting the monitoring command.
　ゲートブロック指令部３４は、監視装置１により検出された故障信号ＮＧを受信すると、インバータ回路７のスイッチング素子をゲートブロックする。これにより、インバータ回路７の変換動作は停止する。 The gate block command unit 34 gate-blocks the switching element of the inverter circuit 7 when receiving the failure signal NG detected by the monitoring device 1. Thereby, the conversion operation of the inverter circuit 7 is stopped.
　監視装置１は、電圧検出器５及び監視回路６を備える。 The monitoring device 1 includes a voltage detector 5 and a monitoring circuit 6.
　電圧検出器５は、インバータ装置２から出力される交流電圧の３相のうち２つの相の間の電圧（相間電圧）を検出して、監視回路６に出力する。電圧検出器５は、フィルタ回路１１及び絶縁回路１２を備える。 The voltage detector 5 detects a voltage (phase voltage) between two phases among the three phases of the AC voltage output from the inverter device 2 and outputs the voltage to the monitoring circuit 6. The voltage detector 5 includes a filter circuit 11 and an insulation circuit 12.
　図２は、フィルタ回路１１の機能を示す概略図である。フィルタ回路１１は、矩形波の電圧を正弦波の電圧に成形する。ＰＷＭ制御されるインバータ回路７から出力される電圧波形は、１パルス又はマルチパルスの矩形波である。フィルタ回路１１にインバータ回路７の出力電圧を通すことで、フィルタ回路１１に入力された波形は、矩形波から正弦波に成形される。フィルタ回路１１から出力される正弦波の電圧は、絶縁回路１２を介して監視回路６に出力される。絶縁回路１２を用いることにより、監視回路６は、ドライブシステム１０の主回路と絶縁される。 FIG. 2 is a schematic diagram showing the function of the filter circuit 11. The filter circuit 11 shapes the rectangular wave voltage into a sine wave voltage. The voltage waveform output from the PWM-controlled inverter circuit 7 is a one-pulse or multi-pulse rectangular wave. By passing the output voltage of the inverter circuit 7 through the filter circuit 11, the waveform input to the filter circuit 11 is shaped from a rectangular wave to a sine wave. The sine wave voltage output from the filter circuit 11 is output to the monitoring circuit 6 via the insulation circuit 12. By using the insulating circuit 12, the monitoring circuit 6 is insulated from the main circuit of the drive system 10.
　監視回路６は、電圧検出器５により検出された出力電圧及びインバータ装置２から受信する信号に基づいて、ドライブシステム１０を監視する。 The monitoring circuit 6 monitors the drive system 10 based on the output voltage detected by the voltage detector 5 and the signal received from the inverter device 2.
　監視回路６は、周波数検出部１３、電圧検出部１４、電圧低下検出設定部１５、周波数低下検出設定部１６、過周波数検出設定部１７、電圧比較部１８、周波数比較部１９、周波数比較部２０、ＮＯＴ演算回路２１、ＮＯＴ演算回路２２、ＡＮＤ演算回路２３、ＸＯＲ演算回路２４、及び故障検出部２５を備える。 The monitoring circuit 6 includes a frequency detection unit 13, a voltage detection unit 14, a voltage drop detection setting unit 15, a frequency drop detection setting unit 16, an overfrequency detection setting unit 17, a voltage comparison unit 18, a frequency comparison unit 19, and a frequency comparison unit 20. , NOT operation circuit 21, NOT operation circuit 22, AND operation circuit 23, XOR operation circuit 24, and failure detection unit 25.
　周波数検出部１３は、電圧検出器５により検出された電圧波形に基づいて、周波数ｆを演算する。具体的には、図２に示すように、正弦波のゼロクロス点間の時間Ｔを計測する。周波数検出部１３は、次式を用いて、計測した時間Ｔから周波数ｆを求める。周波数検出部１３は、演算した周波数ｆを周波数比較部１９及び周波数比較部２０に出力する。 The frequency detector 13 calculates the frequency f based on the voltage waveform detected by the voltage detector 5. Specifically, as shown in FIG. 2, the time T between the zero cross points of the sine wave is measured. The frequency detection unit 13 obtains the frequency f from the measured time T using the following equation. The frequency detection unit 13 outputs the calculated frequency f to the frequency comparison unit 19 and the frequency comparison unit 20.
　　　ｆ＝１／２Ｔ　[Hz]
　電圧検出部１４は、電圧検出器５により検出された電圧の瞬時値（サンプリング値）に基づいて、次式により、電圧Ｖを演算する。電圧検出部１４は、演算した電圧Ｖを電圧比較部１８に出力する。
Figure JPOXMLDOC01-appb-M000001
 f = 1 / 2T [Hz]
Based on the instantaneous voltage value (sampling value) detected by the voltage detector 5, the voltage detector 14 calculates the voltage V according to the following equation. The voltage detection unit 14 outputs the calculated voltage V to the voltage comparison unit 18.
Figure JPOXMLDOC01-appb-M000001
　ここで、ｍはサンプリング数、ｉはサンプリング回数、Ｖｉはサンプリングした電圧の瞬時値を示している。 Here, m is the number of samplings, i is the number of samplings, and Vi is the instantaneous value of the sampled voltage.
　電圧低下検出設定部１５には、インバータ装置２の出力電圧Ｖの低下が大きいことを検出する閾値となる電圧低下設定値Ｖｓが設定されている。電圧低下検出設定部１５は、電圧低下設定値Ｖｓを電圧比較部１８に出力する。 The voltage drop detection setting unit 15 is set with a voltage drop set value Vs that serves as a threshold for detecting that the output voltage V of the inverter device 2 is greatly reduced. The voltage drop detection setting unit 15 outputs the voltage drop setting value Vs to the voltage comparison unit 18.
　周波数低下検出設定部１６には、インバータ装置２の出力周波数ｆの低下が大きいことを検出する閾値となる周波数低下設定値ｆｓ１が設定されている。周波数低下検出設定部１６は、周波数低下設定値ｆｓ１を周波数比較部１９に出力する。 In the frequency decrease detection setting unit 16, a frequency decrease set value fs1 is set as a threshold for detecting that the output frequency f of the inverter device 2 is largely decreased. The frequency decrease detection setting unit 16 outputs the frequency decrease setting value fs1 to the frequency comparison unit 19.
　過周波数検出設定部１７には、インバータ装置２の出力周波数ｆの過度な上昇を検出する閾値となる過周波数設定値ｆｓ２が設定されている。過周波数検出設定部１７は、過周波数設定値ｆｓ２を周波数比較部２０に出力する。 In the over-frequency detection setting unit 17, an over-frequency setting value fs2 that is a threshold value for detecting an excessive increase in the output frequency f of the inverter device 2 is set. The overfrequency detection setting unit 17 outputs the overfrequency setting value fs2 to the frequency comparison unit 20.
　電圧比較部１８は、電圧検出部１４により検出された電圧Ｖと電圧低下検出設定部１５に設定されている電圧低下設定値Ｖｓを比較し、電圧Ｖが電圧低下設定値Ｖｓよりも低いか否かを判断する。電圧比較部１８は、判断結果に基づいて、ＮＯＴ演算回路２１及びＡＮＤ演算回路２３に信号を出力する。電圧Ｖが電圧低下設定値Ｖｓよりも低い場合、電圧比較部１８は、電圧低下異常として‘０’を示す信号を出力する。電圧Ｖが電圧低下設定値Ｖｓ以上の場合、電圧比較部１８は、正常として‘１’を示す信号を出力する。 The voltage comparison unit 18 compares the voltage V detected by the voltage detection unit 14 with the voltage decrease setting value Vs set in the voltage decrease detection setting unit 15, and determines whether or not the voltage V is lower than the voltage decrease setting value Vs. Determine whether. The voltage comparison unit 18 outputs a signal to the NOT operation circuit 21 and the AND operation circuit 23 based on the determination result. When the voltage V is lower than the voltage drop setting value Vs, the voltage comparison unit 18 outputs a signal indicating “0” as a voltage drop abnormality. When the voltage V is equal to or higher than the voltage drop set value Vs, the voltage comparison unit 18 outputs a signal indicating “1” as normal.
　ＮＯＴ演算回路２１は、入力された信号を反転（論理否定）して、故障検出部２５に出力する。従って、故障検出部２５には、電圧低下異常の場合は‘１’が入力され、正常の場合は‘０’が入力される。 The NOT operation circuit 21 inverts the input signal (logical negation) and outputs it to the failure detection unit 25. Therefore, “1” is input to the failure detection unit 25 when the voltage drop is abnormal, and “0” is input when the voltage is normal.
　周波数比較部１９は、周波数検出部１３により検出された周波数ｆと周波数低下検出設定部１６に設定されている周波数低下設定値ｆｓ１を比較し、周波数ｆが周波数低下設定値ｆｓ１よりも低いか否かを判断する。周波数比較部１９は、判断結果に基づいて、ＮＯＴ演算回路２２及びＡＮＤ演算回路２３に信号を出力する。周波数ｆが周波数低下設定値ｆｓ１よりも低い場合、周波数比較部１９は、周波数低下異常として‘０’を示す信号を出力する。周波数ｆが周波数低下設定値ｆｓ１以上の場合、周波数比較部１９は、正常として‘１’を示す信号を出力する。 The frequency comparison unit 19 compares the frequency f detected by the frequency detection unit 13 with the frequency reduction setting value fs1 set in the frequency reduction detection setting unit 16, and determines whether the frequency f is lower than the frequency reduction setting value fs1. Determine whether. The frequency comparison unit 19 outputs a signal to the NOT operation circuit 22 and the AND operation circuit 23 based on the determination result. When the frequency f is lower than the frequency reduction setting value fs1, the frequency comparison unit 19 outputs a signal indicating “0” as the frequency reduction abnormality. When the frequency f is equal to or higher than the frequency reduction setting value fs1, the frequency comparison unit 19 outputs a signal indicating “1” as normal.
　ＮＯＴ演算回路２２は、入力された信号を反転（論理否定）して、故障検出部２５に出力する。従って、故障検出部２５には、周波数低下異常の場合は‘１’が入力され、正常の場合は‘０’が入力される。 NOT operation circuit 22 inverts the input signal (logical negation) and outputs it to failure detection unit 25. Therefore, ‘1’ is input to the failure detection unit 25 when the frequency drop is abnormal, and ‘0’ is input when the frequency is normal.
　周波数比較部２０は、周波数検出部１３により検出された周波数ｆと過周波数検出設定部１７に設定されている過周波数設定値ｆｓ２を比較し、周波数ｆが過周波数設定値ｆｓ２よりも高いか否かを判断する。周波数比較部２０は、判断結果に基づいて、故障検出部２５に信号を出力する。周波数ｆが過周波数設定値ｆｓ２よりも高い場合、周波数比較部２０は、過周波数異常として‘１’を示す信号を出力する。周波数ｆが過周波数設定値ｆｓ２以下の場合、周波数比較部２０は、正常として‘０’を示す信号を出力する。 The frequency comparison unit 20 compares the frequency f detected by the frequency detection unit 13 with the overfrequency setting value fs2 set in the overfrequency detection setting unit 17, and determines whether the frequency f is higher than the overfrequency setting value fs2. Determine whether. The frequency comparison unit 20 outputs a signal to the failure detection unit 25 based on the determination result. When the frequency f is higher than the overfrequency setting value fs2, the frequency comparison unit 20 outputs a signal indicating “1” as an overfrequency abnormality. When the frequency f is equal to or lower than the overfrequency setting value fs2, the frequency comparison unit 20 outputs a signal indicating “0” as normal.
　ＡＮＤ演算回路２３には、電圧比較部１８及び周波数比較部１９からそれぞれ信号が入力される。ＡＮＤ演算回路２３は、入力された２つの信号の論理積をＸＯＲ演算回路２４に出力する。従って、入力された２つの信号がいずれも‘１’の場合（入力された２つの信号がいずれも‘正常’を示す場合）、ＡＮＤ演算回路２３は、‘１’を示す信号を出力する。そうでない場合（入力された２つの信号のうち少なくとも１つが‘異常’を示す場合）、‘０’を示す信号を出力する。 Signals are input to the AND operation circuit 23 from the voltage comparison unit 18 and the frequency comparison unit 19, respectively. The AND operation circuit 23 outputs the logical product of the two input signals to the XOR operation circuit 24. Accordingly, when both of the two input signals are “1” (when both of the two input signals indicate “normal”), the AND operation circuit 23 outputs a signal indicating “1”. Otherwise (when at least one of the two input signals indicates “abnormal”), a signal indicating “0” is output.
　ＸＯＲ演算回路２４には、ＡＮＤ演算回路２３から出力された信号及びインバータ装置２の監視指令部３３から送信された信号が入力される。ＸＯＲ演算回路２４は、２つの信号の排他的論理和を故障検出部２５に出力する。ＸＯＲ演算回路２４は、入力された２つの信号が一致しない場合、監視異常として‘１’を示す信号を出力し、一致する場合、正常として‘０’を示す信号を出力する。 The XOR operation circuit 24 receives the signal output from the AND operation circuit 23 and the signal transmitted from the monitoring command unit 33 of the inverter device 2. The XOR operation circuit 24 outputs an exclusive OR of the two signals to the failure detection unit 25. The XOR operation circuit 24 outputs a signal indicating “1” as a monitoring abnormality when the two input signals do not match, and outputs a signal indicating “0” as normal when they match.
　具体的には、電圧低下異常及び周波数低下異常のいずれも発生しておらず、かつインバータ装置２から監視指令を受信していない場合、ＸＯＲ演算回路２４は、監視異常と判断して、‘１’を示す信号を出力する。この異常は、監視装置１では正常に監視できている状態なのに、インバータ装置２側では監視条件が成立していないことを意味する。また、電圧低下異常又は周波数低下異常のいずれかが発生しており、かつインバータ装置２から監視指令を受信している場合、ＸＯＲ演算回路２４は、異常と判断して、‘１’を示す信号を出力する。この異常は、インバータ装置２側では監視条件が成立しており、監視装置１では異常を検出している状態であることを意味する。 Specifically, when neither a voltage drop abnormality nor a frequency drop abnormality has occurred and a monitoring command has not been received from the inverter device 2, the XOR operation circuit 24 determines that a monitoring abnormality has occurred and '1 A signal indicating 'is output. This abnormality means that although the monitoring device 1 is normally monitoring, the monitoring condition is not satisfied on the inverter device 2 side. When either a voltage drop abnormality or a frequency drop abnormality has occurred and a monitoring command has been received from the inverter device 2, the XOR operation circuit 24 determines that there is an abnormality and indicates a signal indicating “1”. Is output. This abnormality means that the monitoring condition is established on the inverter device 2 side, and the monitoring device 1 is in a state of detecting the abnormality.
　故障検出部２５は、周波数比較部２０、ＮＯＴ演算回路２１、ＮＯＴ演算回路２２、及びＸＯＲ演算回路２４のそれぞれから受信する信号に基づいて、故障を検出する。故障検出部２５は、受信した信号のうちいずれかが‘１’を示す信号（即ち、異常を示す信号）であれば故障と判断する。故障検出部２５は、故障を検出すると、故障信号ＮＧをインバータ装置２に出力する。 The failure detection unit 25 detects a failure based on signals received from the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, and the XOR operation circuit 24. The failure detection unit 25 determines that a failure occurs if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality). When the failure detection unit 25 detects a failure, the failure detection unit 25 outputs a failure signal NG to the inverter device 2.
　本実施形態によれば、ドライブシステム１０において、インバータ装置２の制御系から独立したハードウェアで監視装置１を構成することで、インバータ装置２の内部で異常が生じた場合でも、インバータ装置２の異常による影響を受けずに、監視装置１は、インバータ装置２を監視することができる。例えば、インバータ装置２の内部で故障検出をする場合、故障検出回路自体の故障又はシステムクロックの上昇などの故障を検出するのは困難であるが、インバータ装置２から独立した監視装置１であれば容易に検出することができる。従って、ドライブシステム１０を信頼性の高いシステムにすることができる。 According to the present embodiment, in the drive system 10, by configuring the monitoring device 1 with hardware independent of the control system of the inverter device 2, even if an abnormality occurs in the inverter device 2, the inverter device 2 The monitoring device 1 can monitor the inverter device 2 without being affected by the abnormality. For example, when a failure is detected inside the inverter device 2, it is difficult to detect a failure such as a failure in the failure detection circuit itself or a rise in the system clock. However, if the monitoring device 1 is independent from the inverter device 2. It can be easily detected. Therefore, the drive system 10 can be a highly reliable system.
　また、インバータ装置２に監視指令部３３を設け、監視条件が成立すると、監視指令を監視装置１に送信するようにすることで、監視装置１は、より信頼性の高い監視をすることができる。例えば、インバータ装置２から送信された監視指令と監視装置１で検出している監視状況を比較することで、インバータ装置２の外部からでは検出することができない異常でも検出することができる。例えば、監視装置１は、インバータ装置２の出力電圧Ｖに変化が現れないような異常でも検出することができる。 Moreover, the monitoring apparatus 1 is provided with the monitoring command unit 33, and when the monitoring condition is satisfied, the monitoring apparatus 1 can perform monitoring with higher reliability by transmitting the monitoring command to the monitoring apparatus 1. . For example, by comparing the monitoring command transmitted from the inverter device 2 with the monitoring status detected by the monitoring device 1, it is possible to detect an abnormality that cannot be detected from outside the inverter device 2. For example, the monitoring device 1 can detect an abnormality that does not cause a change in the output voltage V of the inverter device 2.
　さらに、インバータ装置２の出力電圧及び出力周波数を監視することで、ドライブシステム１０の運転に直接的に影響を及ぼすインバータ装置２の出力異常を検出することができる。 Furthermore, by monitoring the output voltage and output frequency of the inverter device 2, it is possible to detect an output abnormality of the inverter device 2 that directly affects the operation of the drive system 10.
（第２の実施形態）
　図３は、本発明の第２の実施形態に係るドライブシステム１０Ａの構成を示す構成図である。 (Second Embodiment)
FIG. 3 is a configuration diagram showing the configuration of the drive system 10A according to the second embodiment of the present invention.
　ドライブシステム１０Ａは、図１に示す第１の実施形態に係るドライブシステム１０において、監視装置１を監視装置１Ａに代えたものである。監視装置１Ａは、第１の実施形態に係る監視装置１の監視回路６を、故障検出部２５から故障検出部２５Ａに代え、周波数変化分設定部２６、周波数変化分比較部２７、前回値メモリ２８、及び減算器２９を追加した監視回路６Ａに代えたものである。その他の点は、第１の実施形態と同様である。 The drive system 10A is obtained by replacing the monitoring device 1 with the monitoring device 1A in the drive system 10 according to the first embodiment shown in FIG. The monitoring device 1A replaces the monitoring circuit 6 of the monitoring device 1 according to the first embodiment from the failure detection unit 25 to the failure detection unit 25A, and replaces the frequency change setting unit 26, the frequency change comparison unit 27, and the previous value memory. 28 and a monitoring circuit 6A to which a subtractor 29 is added. Other points are the same as in the first embodiment.
　周波数変化分設定部２６には、インバータ装置２の出力周波数の大幅な変化を検出する閾値となる周波数変化分設定値ｆｓ３が設定されている。周波数変化分設定部２６は、周波数変化分設定値ｆｓ３を周波数変化分比較部２７に出力する。 In the frequency change setting unit 26, a frequency change set value fs3 is set as a threshold value for detecting a significant change in the output frequency of the inverter device 2. The frequency change setting unit 26 outputs the frequency change set value fs3 to the frequency change comparison unit 27.
　前回値メモリ２８には、周波数検出部１３により検出された周波数ｆが入力される。前回値メモリ２８は、周波数ｆが入力されると、前回記憶された前回周波数ｆｐを減算器２９に出力し、入力された周波数ｆを新たに前回周波数ｆｐとして記憶する。 The frequency f detected by the frequency detector 13 is input to the previous value memory 28. When the frequency f is input, the previous value memory 28 outputs the previously stored previous frequency fp to the subtractor 29, and newly stores the input frequency f as the previous frequency fp.
　減算器２９には、周波数検出部１３により検出された周波数ｆ及び前回値メモリ２８に記憶された前回周波数ｆｐが入力される。減算器２９は、前回周波数ｆｐから周波数ｆを引いた周波数変化分ｆｄを周波数変化分比較部２７に出力する。 The subtracter 29 receives the frequency f detected by the frequency detector 13 and the previous frequency fp stored in the previous value memory 28. The subtractor 29 outputs a frequency change fd obtained by subtracting the frequency f from the previous frequency fp to the frequency change comparison unit 27.
　周波数変化分比較部２７は、減算器２９により演算された周波数変化分ｆｄの絶対値を演算する。周波数変化分比較部２７は、演算した周波数変化分ｆｄの絶対値と周波数変化分設定部２６に設定されている周波数変化分設定値ｆｓ３を比較し、周波数変化分ｆｄの絶対値が周波数変化分設定値ｆｓ３よりも大きいか否かを判断する。周波数変化分比較部２７は、判断結果に基づいて、故障検出部２５Ａに信号を出力する。周波数変化分ｆｄの絶対値が周波数変化分設定値ｆｓ３よりも大きい場合、周波数変化分比較部２７は、周波数変化異常として、‘１’を示す信号を出力する。周波数変化分ｆｄの絶対値が周波数変化分設定値ｆｓ３以下の場合、周波数変化分比較部２７は、正常として‘０’を示す信号を出力する。 The frequency change comparison unit 27 calculates the absolute value of the frequency change fd calculated by the subtractor 29. The frequency change comparison unit 27 compares the calculated absolute value of the frequency change fd with the frequency change set value fs3 set in the frequency change setting unit 26, and the absolute value of the frequency change fd is the frequency change. It is determined whether or not it is larger than the set value fs3. The frequency change comparison unit 27 outputs a signal to the failure detection unit 25A based on the determination result. When the absolute value of the frequency change fd is larger than the frequency change set value fs3, the frequency change comparison unit 27 outputs a signal indicating ‘1’ as the frequency change abnormality. When the absolute value of the frequency change fd is equal to or less than the frequency change set value fs3, the frequency change comparison unit 27 outputs a signal indicating “0” as normal.
　故障検出部２５Ａは、周波数比較部２０、ＮＯＴ演算回路２１、ＮＯＴ演算回路２２、ＸＯＲ演算回路２４、及び周波数変化分比較部２７のそれぞれから受信する信号に基づいて、故障を検出する。故障検出部２５Ａは、受信した信号のうちいずれかが‘１’を示す信号（即ち、異常を示す信号）であれば故障と判断する。故障検出部２５Ａは、故障を検出すると、故障信号ＮＧをインバータ装置２に出力する。 The failure detection unit 25A detects a failure based on signals received from the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, and the frequency change comparison unit 27. The failure detection unit 25A determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality). The failure detection unit 25A outputs a failure signal NG to the inverter device 2 when detecting a failure.
　本実施形態によれば、第１の実施形態による作用効果に加え、インバータ装置２の出力周波数の変化を監視することで、出力周波数の大幅な変化などの異常を検出することができる。 According to the present embodiment, in addition to the operational effects of the first embodiment, by monitoring the change in the output frequency of the inverter device 2, it is possible to detect an abnormality such as a significant change in the output frequency.
（第３の実施形態）
　図４は、本発明の第３の実施形態に係るドライブシステム１０Ｂの構成を示す構成図である。 (Third embodiment)
FIG. 4 is a configuration diagram showing the configuration of a drive system 10B according to the third embodiment of the present invention.
　ドライブシステム１０Ｂは、図１に示す第１の実施形態に係るドライブシステム１０において、監視装置１を監視装置１Ｂに代え、インバータ装置２をインバータ装置２Ｂに代えたものである。監視装置１Ｂは、第１の実施形態に係る監視装置１の監視回路６を、故障検出部２５から故障検出部２５Ｂに代え、電圧基準差設定部４１、周波数基準差設定部４２、電圧基準比較部４３、電圧基準演算部４４、周波数基準比較部４５、及び２つの減算器４６，４７を追加した監視回路６Ｂに代えたものである。インバータ装置２Ｂは、第１の実施形態に係るインバータ装置２の制御装置８を、周波数基準出力部３５を加えた制御装置８Ｂに代えたものである。その他の点は、第１の実施形態と同様である。 The drive system 10B is obtained by replacing the monitoring device 1 with the monitoring device 1B and replacing the inverter device 2 with the inverter device 2B in the drive system 10 according to the first embodiment shown in FIG. The monitoring device 1B replaces the monitoring circuit 6 of the monitoring device 1 according to the first embodiment with the failure detection unit 25B from the failure detection unit 25, and includes a voltage reference difference setting unit 41, a frequency reference difference setting unit 42, and a voltage reference comparison. This is a monitoring circuit 6B in which a unit 43, a voltage reference calculation unit 44, a frequency reference comparison unit 45, and two subtractors 46 and 47 are added. The inverter device 2B is obtained by replacing the control device 8 of the inverter device 2 according to the first embodiment with a control device 8B to which a frequency reference output unit 35 is added. Other points are the same as in the first embodiment.
　周波数基準出力部３５には、インバータ回路７を制御している現在の周波数基準ｆｒが運転シーケンス実行部３１から入力される。周波数基準ｆｒは、制御装置８Ｂによる制御で用いられ、インバータ回路７の出力周波数を制御する基準である。周波数基準出力部３５は、周波数基準ｆｒを監視装置１Ｂに出力する。 The current frequency reference fr controlling the inverter circuit 7 is input from the operation sequence execution unit 31 to the frequency reference output unit 35. The frequency reference fr is used for control by the control device 8B and is a reference for controlling the output frequency of the inverter circuit 7. The frequency reference output unit 35 outputs the frequency reference fr to the monitoring device 1B.
　電圧基準演算部４４には、インバータ装置２Ｂの周波数基準出力部３５から周波数基準ｆｒが入力される。電圧基準演算部４４は、入力された周波数基準ｆｒに、予め設定されているＶ／Ｆ比を掛けて、電圧基準Ｖｒを演算する。電圧基準演算部４４は、演算した電圧基準Ｖｒを減算器４６に出力する。 The frequency reference fr is input to the voltage reference calculation unit 44 from the frequency reference output unit 35 of the inverter device 2B. The voltage reference calculation unit 44 calculates the voltage reference Vr by multiplying the input frequency reference fr by a preset V / F ratio. The voltage reference calculation unit 44 outputs the calculated voltage reference Vr to the subtractor 46.
　電圧基準差設定部４１には、インバータ装置２Ｂの出力電圧Ｖと電圧基準演算部４４により演算された電圧基準Ｖｒとの差が大きいことを検出する閾値となる電圧基準差設定値Ｖｓｒが設定されている。電圧基準差設定部４１は、電圧基準差設定値Ｖｓｒを電圧基準比較部４３に出力する。 The voltage reference difference setting unit 41 is set with a voltage reference difference setting value Vsr that serves as a threshold for detecting that the difference between the output voltage V of the inverter 2B and the voltage reference Vr calculated by the voltage reference calculation unit 44 is large. ing. The voltage reference difference setting unit 41 outputs the voltage reference difference setting value Vsr to the voltage reference comparison unit 43.
　周波数基準差設定部４２には、インバータ装置２Ｂの出力周波数ｆとインバータ装置２Ｂから入力された周波数基準ｆｒとの差が大きいことを検出する閾値となる周波数基準差設定値ｆｓｒが設定されている。周波数基準差設定部４２は、周波数基準差設定値ｆｓｒを周波数基準比較部４５に出力する。 The frequency reference difference setting unit 42 is set with a frequency reference difference setting value fsr that is a threshold value for detecting that the difference between the output frequency f of the inverter device 2B and the frequency reference fr input from the inverter device 2B is large. . The frequency reference difference setting unit 42 outputs the frequency reference difference setting value fsr to the frequency reference comparison unit 45.
　減算器４６には、電圧検出部１４により検出された電圧Ｖ及び電圧基準演算部４４により演算された電圧基準Ｖｒが入力される。減算器４６は、電圧基準Ｖｒから電圧Ｖを引いた電圧誤差Ｖｅを演算する。減算器４６は、演算した電圧誤差Ｖｅを電圧基準比較部４３に出力する。 The subtracter 46 receives the voltage V detected by the voltage detector 14 and the voltage reference Vr calculated by the voltage reference calculator 44. The subtractor 46 calculates a voltage error Ve obtained by subtracting the voltage V from the voltage reference Vr. The subtractor 46 outputs the calculated voltage error Ve to the voltage reference comparison unit 43.
　減算器４７には、インバータ装置２Ｂから出力された周波数基準ｆｒ及び周波数検出部１３により検出された周波数ｆが入力される。減算器４７は、周波数基準ｆｒから周波数ｆを引いた周波数誤差ｆｅを演算する。減算器４７は、演算した周波数誤差ｆｅを周波数基準比較部４５に出力する。 The frequency reference fr output from the inverter device 2B and the frequency f detected by the frequency detector 13 are input to the subtractor 47. The subtractor 47 calculates a frequency error fe obtained by subtracting the frequency f from the frequency reference fr. The subtractor 47 outputs the calculated frequency error fe to the frequency reference comparison unit 45.
　電圧基準比較部４３は、減算器４６により演算された電圧誤差Ｖｅの絶対値を演算する。電圧基準比較部４３は、演算した電圧誤差Ｖｅの絶対値と電圧基準差設定部４１に設定されている電圧基準差設定値Ｖｓｒを比較し、電圧誤差Ｖｅの絶対値が電圧基準差設定値Ｖｓｒよりも大きいか否かを判断する。電圧基準比較部４３は、判断結果に基づいて、故障検出部２５Ｂに信号を出力する。電圧誤差Ｖｅの絶対値が電圧基準差設定値Ｖｓｒよりも大きい場合、電圧基準比較部４３は、電圧基準異常として、‘１’を示す信号を出力する。電圧誤差Ｖｅの絶対値が電圧基準差設定値Ｖｓｒ以下の場合、電圧基準比較部４３は、正常として‘０’を示す信号を出力する。 The voltage reference comparison unit 43 calculates the absolute value of the voltage error Ve calculated by the subtractor 46. The voltage reference comparison unit 43 compares the calculated absolute value of the voltage error Ve with the voltage reference difference setting value Vsr set in the voltage reference difference setting unit 41, and the absolute value of the voltage error Ve is the voltage reference difference setting value Vsr. It is judged whether it is larger than. The voltage reference comparison unit 43 outputs a signal to the failure detection unit 25B based on the determination result. When the absolute value of the voltage error Ve is larger than the voltage reference difference setting value Vsr, the voltage reference comparison unit 43 outputs a signal indicating “1” as a voltage reference abnormality. When the absolute value of the voltage error Ve is equal to or smaller than the voltage reference difference setting value Vsr, the voltage reference comparison unit 43 outputs a signal indicating “0” as normal.
　周波数基準比較部４５は、減算器４７により演算された周波数誤差ｆｅの絶対値を演算する。周波数基準比較部４５は、演算した周波数誤差ｆｅの絶対値と周波数基準差設定部４２に設定されている周波数基準差設定値ｆｓｒを比較し、周波数誤差ｆｅの絶対値が周波数基準差設定値ｆｓｒよりも大きいか否かを判断する。周波数基準比較部４５は、判断結果に基づいて、故障検出部２５Ｂに信号を出力する。周波数誤差ｆｅの絶対値が周波数基準差設定値ｆｓｒよりも大きい場合、周波数基準比較部４５は、周波数基準異常として、‘１’を示す信号を出力する。周波数誤差ｆｅの絶対値が周波数基準差設定値ｆｓｒ以下の場合、周波数基準比較部４５は、正常として‘０’を示す信号を出力する。 The frequency reference comparison unit 45 calculates the absolute value of the frequency error fe calculated by the subtractor 47. The frequency reference comparison unit 45 compares the calculated absolute value of the frequency error fe with the frequency reference difference setting value fsr set in the frequency reference difference setting unit 42, and the absolute value of the frequency error fe is the frequency reference difference setting value fsr. It is judged whether it is larger than. The frequency reference comparison unit 45 outputs a signal to the failure detection unit 25B based on the determination result. When the absolute value of the frequency error fe is larger than the frequency reference difference set value fsr, the frequency reference comparison unit 45 outputs a signal indicating “1” as a frequency reference abnormality. When the absolute value of the frequency error fe is equal to or less than the frequency reference difference set value fsr, the frequency reference comparison unit 45 outputs a signal indicating “0” as normal.
　故障検出部２５Ｂは、周波数比較部２０、ＮＯＴ演算回路２１、ＮＯＴ演算回路２２、ＸＯＲ演算回路２４、電圧基準比較部４３、及び周波数基準比較部４５のそれぞれから受信する信号に基づいて、故障を検出する。故障検出部２５Ｂは、受信した信号のうちいずれかが‘１’を示す信号（即ち、異常を示す信号）であれば故障と判断する。故障検出部２５Ｂは、故障を検出すると、故障信号ＮＧをインバータ装置２Ｂに出力する。 The failure detection unit 25B detects a failure based on signals received from the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, the voltage reference comparison unit 43, and the frequency reference comparison unit 45. To detect. The failure detection unit 25B determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality). When the failure detection unit 25B detects a failure, the failure detection unit 25B outputs a failure signal NG to the inverter device 2B.
　本実施形態によれば、第１の実施形態に係る作用効果に加え、以下の作用効果を得ることができる。 According to the present embodiment, in addition to the functions and effects according to the first embodiment, the following functions and effects can be obtained.
　インバータ装置２Ｂから受信する周波数基準ｆｒと、監視装置１Ｂで検出するインバータ装置２Ｂの出力周波数ｆを比較することで、インバータ装置２Ｂの出力周波数の制御の異常を検出することができる。 By comparing the frequency reference fr received from the inverter device 2B with the output frequency f of the inverter device 2B detected by the monitoring device 1B, an abnormality in the control of the output frequency of the inverter device 2B can be detected.
　また、周波数基準ｆｒにＶ／Ｆ比を掛けて電圧基準Ｖｒを求め、電圧基準Ｖｒとインバータ装置２Ｂの出力電圧Ｖを比較することで、ＶＶＶＦ制御によるインバータ装置２Ｂの出力異常を検出することができる。 In addition, the frequency reference fr is multiplied by the V / F ratio to obtain the voltage reference Vr, and the output voltage V of the inverter device 2B is compared with the voltage reference Vr, thereby detecting the output abnormality of the inverter device 2B by the VVVF control. it can.
（第４の実施形態）
　図５は、本発明の第４の実施形態に係るドライブシステム１０Ｃの構成を示す構成図である。 (Fourth embodiment)
FIG. 5 is a configuration diagram showing the configuration of a drive system 10C according to the fourth embodiment of the present invention.
　ドライブシステム１０Ｃは、図１に示す第１の実施形態に係るドライブシステム１０において、監視装置１を監視装置１Ｃに代えたものである。監視装置１Ｃは、電圧検出器５Ｃ及び監視回路６Ｃを備える。監視回路６Ｃは、第１の実施形態に係る監視回路６において、電圧比較部１８、周波数比較部１９、周波数比較部２０、及び故障検出部２５を、電圧比較部１８Ｃ、周波数比較部１９Ｃ、周波数比較部２０Ｃ、及び故障検出部２５Ｃにそれぞれ代え、相順設定部５１、相順比較部５２、及び３つの多数決判定回路５３，５４，５５を追加したものである。その他の点は、第１の実施形態と同様である。 The drive system 10C is obtained by replacing the monitoring device 1 with the monitoring device 1C in the drive system 10 according to the first embodiment shown in FIG. The monitoring device 1C includes a voltage detector 5C and a monitoring circuit 6C. In the monitoring circuit 6 according to the first embodiment, the monitoring circuit 6C includes a voltage comparison unit 18, a frequency comparison unit 19, a frequency comparison unit 20, and a failure detection unit 25. The voltage comparison unit 18C, the frequency comparison unit 19C, Instead of the comparison unit 20C and the failure detection unit 25C, a phase sequence setting unit 51, a phase sequence comparison unit 52, and three majority decision circuits 53, 54, and 55 are added. Other points are the same as in the first embodiment.
　電圧検出器５Ｃは、インバータ装置２から出力される３つの相間電圧を検出する点以外は、第１の実施形態に係る電圧検出器５と同様である。なお、ここでは、電圧検出器５Ｃは、相間電圧を検出する構成について説明するが、相電圧を検出する構成でもよい。電圧検出器５Ｃは、フィルタ回路１１Ｃ及び絶縁回路１２Ｃを備える。フィルタ回路１１Ｃは、３つの相間電圧について、矩形波から正弦波に成形する。その他の点は、第１の実施形態に係るフィルタ回路１１と同様である。絶縁回路１２は、３つの相間電圧について、監視回路６Ｃをドライブシステム１０Ｃの主回路から絶縁する。その他の点は、第１の実施形態に係る絶縁回路１２と同様である。 The voltage detector 5C is the same as the voltage detector 5 according to the first embodiment, except that the three interphase voltages output from the inverter device 2 are detected. In addition, although the voltage detector 5C demonstrates the structure which detects an interphase voltage here, the structure which detects a phase voltage may be sufficient. The voltage detector 5C includes a filter circuit 11C and an insulation circuit 12C. The filter circuit 11C shapes the three interphase voltages from a rectangular wave to a sine wave. Other points are the same as those of the filter circuit 11 according to the first embodiment. The insulation circuit 12 insulates the monitoring circuit 6C from the main circuit of the drive system 10C for the three interphase voltages. Other points are the same as those of the insulating circuit 12 according to the first embodiment.
　周波数検出部１３Ｃは、第１の実施形態に係る周波数検出部１３と同様に、電圧検出器５Ｃにより検出された各相間電圧の波形に基づいて、各周波数ｆｕｖ，ｆｖｗ，ｆｗｕを検出する。ここで、周波数ｆｕｖは、Ｕ相とＶ相の間の電圧の周波数を、周波数ｆｖｗは、Ｖ相とＷ相の間の電圧の周波数を、周波数ｆｗｕは、Ｗ相とＵ相の間の電圧の周波数をそれぞれ表しているものとする。周波数検出部１３Ｃは、演算した各相間電圧の周波数ｆｕｖ，ｆｖｗ，ｆｗｕを周波数比較部１９Ｃ及び周波数比較部２０Ｃに出力し、周波数ｆｕｖ，ｆｖｗ，ｆｗｕを演算するために検出した各相間電圧のゼロクロス点に関する情報を相順比較部５２に出力する。 Similarly to the frequency detector 13 according to the first embodiment, the frequency detector 13C detects the frequencies fuv, fvw, and fwu based on the waveform of the voltage between the phases detected by the voltage detector 5C. Here, the frequency fuv is the frequency of the voltage between the U phase and the V phase, the frequency fvw is the frequency of the voltage between the V phase and the W phase, and the frequency fwu is the voltage between the W phase and the U phase. It is assumed that each frequency is represented. The frequency detection unit 13C outputs the calculated frequencies fuv, fvw, fwu of the respective interphase voltages to the frequency comparison unit 19C and the frequency comparison unit 20C, and zero-crosses the detected interphase voltages to calculate the frequencies fuv, fvw, fwu. Information about the points is output to the phase sequence comparison unit 52.
　電圧検出部１４Ｃは、第１の実施形態に係る電圧検出部１４と同様に、電圧検出器５Ｃにより検出された電圧の瞬時値に基づいて、各相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕを演算する。ここで、相間電圧Ｖｕｖは、Ｕ相とＶ相の間の電圧を、相間電圧Ｖｖｗは、Ｖ相とＷ相の間の電圧を、相間電圧Ｖｗｕは、Ｗ相とＵ相の間の電圧をそれぞれ表しているものとする。電圧検出部１４Ｃは、演算した相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕを電圧比較部１８Ｃに出力する。 Similarly to the voltage detection unit 14 according to the first embodiment, the voltage detection unit 14C calculates the interphase voltages Vuv, Vvw, Vwu based on the instantaneous value of the voltage detected by the voltage detector 5C. Here, the interphase voltage Vuv is the voltage between the U phase and the V phase, the interphase voltage Vvw is the voltage between the V phase and the W phase, and the interphase voltage Vwu is the voltage between the W phase and the U phase. Each shall be represented. The voltage detection unit 14C outputs the calculated interphase voltages Vuv, Vvw, Vwu to the voltage comparison unit 18C.
　相順設定部５１には、相順設定値Ｓｑｓが設定されている。相順とは、インバータ装置２の出力電圧Ｖでゼロクロス点が発生する相の順番である。相順設定部５１は、相順を相順比較部５２に出力する。ここでは、相順は、Ｕ相、Ｖ相、Ｗ相の順番とし、相順設定値Ｓｑｓも同じ順番で設定されているものとする。 In the phase order setting unit 51, a phase order set value Sqs is set. The phase order is a phase order in which a zero cross point occurs at the output voltage V of the inverter device 2. The phase sequence setting unit 51 outputs the phase sequence to the phase sequence comparison unit 52. Here, the phase order is the order of the U phase, the V phase, and the W phase, and the phase order set value Sqs is also set in the same order.
　相順比較部５２には、周波数検出部１３Ｃから出力された各相間電圧のゼロクロス点に関する情報及び相順設定部５１に設定されている相順設定値Ｓｑｓが入力される。相順比較部５２は、各相間電圧のゼロクロス点に基づいて決定された相順Ｓｑが相順設定値Ｓｑｓと一致しているか否かを判断する。一致している場合は、相順比較部５２は、故障検出部２５Ｃに正常として‘０’を示す信号を出力する。一致していない場合は、相順比較部５２は、故障検出部２５Ｃに相順異常として‘１’を示す信号を出力する。なお、各相間電圧のゼロクロス点から相順Ｓｑを決定する演算は、周波数検出部１３Ｃで行ってもよい。 The phase order comparison unit 52 receives the information about the zero-cross point of each interphase voltage output from the frequency detection unit 13 </ b> C and the phase sequence setting value Sqs set in the phase sequence setting unit 51. The phase sequence comparison unit 52 determines whether or not the phase sequence Sq determined based on the zero cross point of each interphase voltage matches the phase sequence setting value Sqs. If they match, the phase sequence comparison unit 52 outputs a signal indicating “0” as normal to the failure detection unit 25C. If they do not match, the phase sequence comparison unit 52 outputs a signal indicating '1' as a phase sequence abnormality to the failure detection unit 25C. The calculation for determining the phase sequence Sq from the zero cross point of each interphase voltage may be performed by the frequency detector 13C.
　電圧比較部１８Ｃは、電圧検出部１４Ｃにより検出された各相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕと電圧低下検出設定部１５に設定されている電圧低下設定値Ｖｓを、それぞれ第１の実施形態と同様に比較する。電圧比較部１８Ｃは、各相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕについての比較結果を多数決判定回路５３に出力する。 The voltage comparison unit 18C uses the interphase voltages Vuv, Vvw, Vwu detected by the voltage detection unit 14C and the voltage drop setting value Vs set in the voltage drop detection setting unit 15 in the same manner as in the first embodiment. Compare. The voltage comparison unit 18C outputs the comparison results for the interphase voltages Vuv, Vvw, and Vwu to the majority decision circuit 53.
　多数決判定回路５３～５５は、入力された複数の情報のうち過半数以上の情報を出力する回路である。例えば、多数決判定回路５３～５５は、‘０’か‘１’をとる二値変数を示す３つの信号が入力される場合、２つ以上の信号が‘１’を示していれば、‘１’を出力し、そうでない場合、‘０’を出力する。 Majority determination circuits 53 to 55 are circuits that output more than a majority of information among a plurality of input information. For example, when three signals indicating a binary variable that takes “0” or “1” are input, the majority decision circuits 53 to 55 are “1” if two or more signals indicate “1”. 'Is output, otherwise' 0 'is output.
　多数決判定回路５３は、電圧比較部１８Ｃから入力された比較結果に基づいて、電圧低下異常か否かについて判断する。多数決判定回路５３は、３つの相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕのうち少なくとも２以上が電圧低下設定値Ｖｓよりも低ければ、電圧低下異常と判断する。即ち、下記の３つの不等式のうち２つ以上が成り立てば、電圧低下異常と判断し、そうでなければ、正常と判断する。多数決判定回路５３は、電圧低下異常と判断した場合は、‘０’を示す信号を、正常と判断した場合は、‘１’を示す信号を、ＮＯＴ演算回路２１及びＡＮＤ演算回路２３に出力する。 The majority decision determination circuit 53 determines whether or not the voltage drop is abnormal based on the comparison result input from the voltage comparison unit 18C. The majority decision circuit 53 determines that the voltage drop is abnormal if at least two of the three interphase voltages Vuv, Vvw, and Vwu are lower than the voltage drop set value Vs. That is, if two or more of the following three inequalities hold, it is determined that the voltage drop is abnormal, and otherwise, it is determined normal. The majority decision circuit 53 outputs a signal indicating “0” to the NOT operation circuit 21 and the AND operation circuit 23 when determining that the voltage drop abnormality is normal, and when determining that it is normal, the majority determination circuit 53 outputs a signal indicating “1”. .
　Ｖｕｖ　＜　Ｖｓ、　Ｖｖｗ　＜　Ｖｓ、　Ｖｗｕ　＜　Ｖｓ
　周波数比較部１９Ｃは、周波数検出部１３Ｃにより検出された各相間電圧の周波数ｆｕｖ，ｆｖｗ，ｆｗｕと周波数低下検出設定部１６に設定されている周波数低下設定値ｆｓ１を、それぞれ第１の実施形態と同様に比較する。周波数比較部１９Ｃは、各周波数ｆｕｖ，ｆｖｗ，ｆｗｕについての比較結果を多数決判定回路５４に出力する。 Vuv <Vs, Vvw <Vs, Vwu <Vs
The frequency comparison unit 19C sets the frequency fuv, fvw, fwu of each inter-phase voltage detected by the frequency detection unit 13C and the frequency decrease setting value fs1 set in the frequency decrease detection setting unit 16 as in the first embodiment. Compare in the same way. The frequency comparison unit 19 </ b> C outputs the comparison results for the frequencies fuv, fvw, and fwu to the majority decision circuit 54.
　多数決判定回路５４は、周波数比較部１９Ｃから入力された比較結果に基づいて、周波数低下異常であるか否かについて判断する。多数決判定回路５４は、３つの周波数ｆｕｖ，ｆｖｗ，ｆｗｕのうち少なくとも２以上が周波数低下設定値ｆｓ１よりも低ければ、周波数低下異常と判断し、そうでなければ、正常と判断する。即ち、下記の３つの不等式のうち２つ以上が成り立てば、周波数低下異常と判断し、そうでなければ、正常と判断する。多数決判定回路５４は、周波数低下異常と判断した場合は、‘０’を示す信号を、正常と判断した場合は、‘１’を示す信号を、ＮＯＴ演算回路２２及びＡＮＤ演算回路２３に出力する。 The majority decision determination circuit 54 determines whether or not it is a frequency drop abnormality based on the comparison result input from the frequency comparison unit 19C. The majority decision circuit 54 determines that the frequency decrease is abnormal if at least two of the three frequencies fuv, fvw, and fwu are lower than the frequency decrease setting value fs1, and otherwise determines that the frequency is normal. That is, if two or more of the following three inequalities hold, it is determined that the frequency drop is abnormal, otherwise it is determined normal. The majority decision circuit 54 outputs a signal indicating “0” to the NOT operation circuit 22 and the AND operation circuit 23 when it is determined that the frequency decrease is abnormal, and when it is determined that the majority determination circuit 54 is normal. .
　ｆｕｖ　＜　ｆｓ１、　ｆｖｗ　＜　ｆｓ１、　ｆｗｕ　＜　ｆｓ１
　周波数比較部２０Ｃは、周波数検出部１３Ｃにより検出された各相間電圧の周波数ｆｕｖ，ｆｖｗ，ｆｗｕと過周波数検出設定部１７に設定されている過周波数設定値ｆｓ２を、それぞれ第１の実施形態と同様に比較する。周波数比較部２０Ｃは、各周波数ｆｕｖ，ｆｖｗ，ｆｗｕについての比較結果を多数決判定回路５５に出力する。 fuv <fs1, fvw <fs1, ffu <fs1
The frequency comparison unit 20C uses the frequencies fuv, fvw, fwu of the voltages between the phases detected by the frequency detection unit 13C and the overfrequency setting value fs2 set in the overfrequency detection setting unit 17 as in the first embodiment. Compare in the same way. The frequency comparison unit 20 </ b> C outputs the comparison results for the frequencies fuv, fvw, and fwu to the majority decision circuit 55.
　多数決判定回路５５は、周波数比較部２０Ｃから入力された比較結果に基づいて、過周波数異常であるか否かについて判断する。多数決判定回路５５は、３つの周波数ｆｕｖ，ｆｖｗ，ｆｗｕのうち少なくとも２以上が過周波数設定値ｆｓ２よりも高ければ、過周波数異常と判断し、そうでなければ、正常と判断する。即ち、下記の３つの不等式のうち２つ以上が成り立てば、過周波数異常と判断し、そうでなければ、正常と判断する。多数決判定回路５５は、過周波数異常と判断した場合は、‘１’を示す信号を、正常と判断した場合は、‘０’を示す信号を、故障検出部２５に出力する。 The majority decision determination circuit 55 determines whether or not there is an overfrequency abnormality based on the comparison result input from the frequency comparison unit 20C. The majority decision circuit 55 determines that the frequency is abnormal when at least two of the three frequencies fuv, fvw, and fwu are higher than the overfrequency setting value fs2, and determines that the frequency is normal otherwise. That is, if two or more of the following three inequalities hold, it is determined that there is an overfrequency abnormality, and otherwise, it is determined that it is normal. The majority decision circuit 55 outputs a signal indicating ‘1’ to the failure detection unit 25 if it is determined to be abnormal, and a signal indicating ‘0’ to the failure detection unit 25 if it is determined to be normal.
　ｆｕｖ　＞　ｆｓ２、　ｆｖｗ　＞　ｆｓ２、　ｆｗｕ　＞　ｆｓ２
　故障検出部２５Ｃは、ＮＯＴ演算回路２１、ＮＯＴ演算回路２２、ＸＯＲ演算回路２４、相順比較部５２、及び多数決判定回路５５のそれぞれから受信する信号に基づいて、故障を検出する。故障検出部２５Ｃは、受信した信号のうちいずれかが‘１’を示す信号（即ち、異常を示す信号）であれば故障と判断する。故障検出部２５Ｃは、故障を検出すると、故障信号ＮＧをインバータ装置２に出力する。 fuv> fs2, fvw> fs2, fwu> fs2
The failure detection unit 25C detects a failure based on signals received from the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, the phase sequence comparison unit 52, and the majority decision determination circuit 55. The failure detection unit 25C determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality). The failure detection unit 25C outputs a failure signal NG to the inverter device 2 when detecting a failure.
　本実施形態によれば、第１の実施形態に係る作用効果に加え、以下の作用効果を得ることができる。 According to the present embodiment, in addition to the functions and effects according to the first embodiment, the following functions and effects can be obtained.
　検出した各相のゼロクロス点に基づいて決定される相順Ｓｑが予め設定されている相順設定値Ｓｑｓと一致しているか否かを監視することで、インバータ装置２の異常を検出することができる。また、多数決判定回路５３～５５を用いて、異常を判断することで、異常の誤検出を抑えることができる。これらにより、監視装置１Ｃによる異常検出の信頼性を高めることができる。 It is possible to detect an abnormality in the inverter device 2 by monitoring whether or not the phase sequence Sq determined based on the detected zero-cross point of each phase matches a preset phase sequence setting value Sqs. it can. In addition, by using the majority decision determination circuits 53 to 55 to determine an abnormality, erroneous detection of the abnormality can be suppressed. Accordingly, the reliability of abnormality detection by the monitoring device 1C can be improved.
（第５の実施形態）
　図６は、本発明の第５の実施形態に係るドライブシステム１０Ｄの構成を示す構成図である。 (Fifth embodiment)
FIG. 6 is a configuration diagram showing the configuration of a drive system 10D according to the fifth embodiment of the present invention.
　ドライブシステム１０Ｄは、図１に示す第１の実施形態に係るドライブシステム１０において、監視装置１を監視装置１Ｄに代えたものである。監視装置１Ｄは、３台の監視装置１，１０１，１０２を配置し、多数決回路５６を追加したものである。その他の点は、第１の実施形態と同様である。監視装置１０１，１０２は監視装置１と同じ装置である。多数決回路５６は、第４の実施形態に係る多数決回路５３～５５と同じものである。 The drive system 10D is obtained by replacing the monitoring device 1 with the monitoring device 1D in the drive system 10 according to the first embodiment shown in FIG. The monitoring device 1D includes three monitoring devices 1, 101, and 102, and a majority circuit 56 is added. Other points are the same as in the first embodiment. The monitoring devices 101 and 102 are the same devices as the monitoring device 1. The majority circuit 56 is the same as the majority circuits 53 to 55 according to the fourth embodiment.
　３台の監視装置１，１０１，１０２は、電圧検出器５に、異なる線間電圧を入力し、別々に監視を行う。各監視装置１，１０１，１０２の故障検出部２５の故障出力信号ＮＧ１～ＮＧ３を多数決判定回路５６に入力する。多数決判定回路５６は、３つの故障検出部２５の出力のうち少なくとも２以上が‘１’を示す信号（即ち、異常を示す信号）であれば故障と判断する。多数決判定回路２６は故障信号ＮＧをインバータ装置２に出力する。 The three monitoring devices 1, 101, 102 input different line voltages to the voltage detector 5 and perform monitoring separately. The failure output signals NG 1 to NG 3 of the failure detection unit 25 of each of the monitoring devices 1, 101, 102 are input to the majority decision circuit 56. The majority decision circuit 56 determines that a failure has occurred if at least two or more of the outputs of the three failure detectors 25 are signals indicating ‘1’ (that is, signals indicating abnormality). The majority decision circuit 26 outputs a failure signal NG to the inverter device 2.
　本実施形態によれば、第１の実施形態に係る作用効果に加え、以下の作用効果を得ることができる。 According to the present embodiment, in addition to the functions and effects according to the first embodiment, the following functions and effects can be obtained.
　検出した相間電圧ごとに監視装置１，１０１，１０２を別々に配置し、多数決判定回路５６を用いて、異常を判断することで、異常の誤検出を抑えることができる。これらにより、監視装置１Ｄによる異常検出の信頼性を高めることができる。 By arranging the monitoring devices 1, 101, 102 separately for each detected interphase voltage and using the majority decision circuit 56 to determine an abnormality, erroneous detection of the abnormality can be suppressed. Thus, the reliability of abnormality detection by the monitoring device 1D can be improved.
（第６の実施形態）
　図７は、本発明の第６の実施形態に係るドライブシステム１０Ｅの構成を示す構成図である。 (Sixth embodiment)
FIG. 7 is a configuration diagram showing the configuration of a drive system 10E according to the sixth embodiment of the present invention.
　ドライブシステム１０Ｅは、図１に示す第１の実施形態に係るドライブシステム１０において、監視装置１を監視装置１Ｅに代えたものである。監視装置１Ｅは、第４の実施形態に係る電圧検出器５Ｃ、及び監視回路６Ｅを備える。監視回路６Ｅは、第１の実施形態に係る監視回路６において、故障検出部２５を故障検出部２５Ｅに代え、周波数検出部１３及び電圧検出部１４を第４の実施形態に係る周波数検出部１３Ｃ及び電圧検出部１４Ｃにそれぞれ代え、電圧比較部１８、周波数比較部１９、及び周波数比較部２０を、電圧比較部１８Ｅ、周波数比較部１９Ｅ、及び周波数比較部２０Ｅにそれぞれ代え、第４の実施形態に係る相順設定部５１及び相順比較部５２、電圧変動検出設定部６１、周波数変動検出設定部６２、電圧差比較部６３、及び周波数差比較部６４を追加したものである。その他の点は、第１の実施形態と同様である。 The drive system 10E is obtained by replacing the monitoring device 1 with the monitoring device 1E in the drive system 10 according to the first embodiment shown in FIG. The monitoring device 1E includes a voltage detector 5C and a monitoring circuit 6E according to the fourth embodiment. In the monitoring circuit 6 according to the first embodiment, the monitoring circuit 6E replaces the failure detection unit 25 with the failure detection unit 25E, and replaces the frequency detection unit 13 and the voltage detection unit 14 with the frequency detection unit 13C according to the fourth embodiment. In the fourth embodiment, the voltage comparison unit 18, the frequency comparison unit 19, and the frequency comparison unit 20 are replaced with the voltage comparison unit 18E, the frequency comparison unit 19E, and the frequency comparison unit 20E, respectively. A phase sequence setting unit 51 and a phase sequence comparison unit 52, a voltage variation detection setting unit 61, a frequency variation detection setting unit 62, a voltage difference comparison unit 63, and a frequency difference comparison unit 64 are added. Other points are the same as in the first embodiment.
　電圧比較部１８Ｅは、電圧検出部１４Ｃにより検出された各相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕと電圧低下検出設定部１５に設定されている電圧低下設定値Ｖｓをそれぞれ比較して、少なくとも１つの相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕが電圧低下設定値Ｖｓよりも低ければ、電圧低下異常と判断する。その他の点は、第１の実施形態に係る電圧比較部１８と同様である。 The voltage comparison unit 18E compares the interphase voltages Vuv, Vvw, Vwu detected by the voltage detection unit 14C with the voltage decrease setting value Vs set in the voltage decrease detection setting unit 15, respectively, and at least one interphase voltage If Vuv, Vvw, Vwu are lower than the voltage drop set value Vs, it is determined that the voltage drop is abnormal. The other points are the same as those of the voltage comparison unit 18 according to the first embodiment.
　周波数比較部１９Ｅは、周波数検出部１３Ｃにより検出された各周波数ｆｕｖ，ｆｖｗ，ｆｗｕと周波数低下検出設定部１６に設定されている周波数低下設定値ｆｓ１をそれぞれ比較して、少なくとも１つの周波数ｆｕｖ，ｆｖｗ，ｆｗｕが周波数低下設定値ｆｓ１よりも低ければ、周波数低下異常と判断する。その他の点は、第１の実施形態に係る周波数比較部１９と同様である。 The frequency comparison unit 19E compares each frequency fuv, fvw, fwu detected by the frequency detection unit 13C with the frequency decrease setting value fs1 set in the frequency decrease detection setting unit 16, and thereby compares at least one frequency fuv, If fvw and fwu are lower than the frequency drop set value fs1, it is determined that the frequency drop is abnormal. Other points are the same as those of the frequency comparison unit 19 according to the first embodiment.
　周波数比較部２０Ｅは、周波数検出部１３Ｃにより検出された各周波数ｆｕｖ，ｆｖｗ，ｆｗｕと過周波数検出設定部１７に設定されている過周波数設定値ｆｓ２をそれぞれ比較して、少なくとも１つの周波数ｆｕｖ，ｆｖｗ，ｆｗｕが過周波数設定値ｆｓ２よりも高ければ、過周波数異常と判断する。その他の点は、第１の実施形態に係る周波数比較部２０と同様である。 The frequency comparison unit 20E compares at least one frequency fuv, fvw, fwu detected by the frequency detection unit 13C with the overfrequency setting value fs2 set in the overfrequency detection setting unit 17, respectively. If fvw and fwu are higher than the overfrequency set value fs2, it is determined that the overfrequency is abnormal. Other points are the same as those of the frequency comparison unit 20 according to the first embodiment.
　相順設定部５１及び相順比較部５２による相順異常の検出方法は、第４の実施形態と同様である。 The method of detecting the phase sequence abnormality by the phase sequence setting unit 51 and the phase sequence comparison unit 52 is the same as in the fourth embodiment.
　電圧変動検出設定部６１には、インバータ装置２の出力相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕの相互間の大きな変動を検出する閾値となる電圧変動設定値Ｖｓｖが設定されている。電圧変動検出設定部６１は、電圧変動設定値Ｖｓｖを電圧差比較部６３に出力する。 In the voltage fluctuation detection setting unit 61, a voltage fluctuation setting value Vsv serving as a threshold for detecting large fluctuations among the output phase voltages Vuv, Vvw, Vwu of the inverter device 2 is set. The voltage fluctuation detection setting unit 61 outputs the voltage fluctuation setting value Vsv to the voltage difference comparison unit 63.
　周波数変動検出設定部６２には、インバータ装置２の出力相間電圧の周波数ｆｕｖ，ｆｖｗ，ｆｗｕの相互間の大きな変動を検出する閾値となる周波数変動設定値ｆｓｖが設定されている。周波数変動検出設定部６２は、周波数変動設定値ｆｓｖを周波数差比較部６４に出力する。 In the frequency fluctuation detection setting unit 62, a frequency fluctuation setting value fsv serving as a threshold for detecting large fluctuations among the frequencies fuv, fvw, and fwu of the output phase voltage of the inverter device 2 is set. The frequency fluctuation detection setting unit 62 outputs the frequency fluctuation setting value fsv to the frequency difference comparison unit 64.
　電圧差比較部６３は、電圧検出部１４Ｃにより検出された相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕの相互間の電圧差の絶対値を演算する。電圧差比較部６３は、演算した３つの電圧差の絶対値と電圧変動検出設定部６１に設定されている電圧変動設定値Ｖｓｖを比較して、電圧変動異常か否かについて判断する。これらの電圧差の絶対値のうち少なくとも１つが電圧変動設定値Ｖｓｖよりも大きければ、電圧変動異常と判断する。即ち、下記の３つの不等式のうち少なくとも１つが成り立てば、電圧変動異常と判断し、そうでなければ、正常と判断する。電圧変動異常と判断した場合、電圧差比較部６３は、‘１’を示す信号を故障検出部２５Ｅに出力する。正常と判断した場合、電圧差比較部６３は、‘０’を示す信号を故障検出部２５Ｅに出力する。 The voltage difference comparison unit 63 calculates the absolute value of the voltage difference between the interphase voltages Vuv, Vvw, and Vwu detected by the voltage detection unit 14C. The voltage difference comparison unit 63 compares the calculated three voltage difference absolute values with the voltage variation setting value Vsv set in the voltage variation detection setting unit 61 to determine whether or not the voltage variation is abnormal. If at least one of the absolute values of these voltage differences is larger than the voltage fluctuation set value Vsv, it is determined that the voltage fluctuation is abnormal. That is, if at least one of the following three inequalities holds, it is determined that the voltage fluctuation is abnormal, and otherwise, it is determined normal. When it is determined that the voltage fluctuation is abnormal, the voltage difference comparison unit 63 outputs a signal indicating “1” to the failure detection unit 25E. When it is determined that the voltage is normal, the voltage difference comparison unit 63 outputs a signal indicating “0” to the failure detection unit 25E.
　｜Ｖｕｖ－Ｖｖｗ｜　＞　Ｖｓｖ、　｜Ｖｖｗ－Ｖｗｕ｜　＞　Ｖｓｖ、　｜Ｖｗｕ－Ｖｕｖ｜　＞　Ｖｓｖ
　周波数差比較部６４は、周波数検出部１３Ｃにより検出された相間電圧の周波数ｆｕｖ，ｆｖｗ，ｆｗｕの相互間の周波数差の絶対値を演算する。周波数差比較部６４は、演算した３つの周波数差の絶対値と周波数変動検出設定部６２に設定されている周波数変動設定値ｆｓｖを比較して、周波数変動異常か否かについて判断する。これらの周波数差の絶対値のうち少なくとも１つが周波数変動設定値ｆｓｖよりも大きければ、周波数変動異常と判断する。即ち、下記の３つの不等式のうち少なくとも１つが成り立てば、周波数変動異常と判断し、そうでなければ、正常と判断する。周波数変動異常と判断した場合、周波数差比較部６４は、‘１’を示す信号を故障検出部２５Ｅに出力する。正常と判断した場合、周波数差比較部６４は、‘０’を示す信号を故障検出部２５Ｅに出力する。 | Vuv-Vvw |> Vsv, | Vvw-Vwu |> Vsv, | Vwu-Vuv |> Vsv
The frequency difference comparison unit 64 calculates the absolute value of the frequency difference between the frequencies fuv, fvw, and fwu of the interphase voltage detected by the frequency detection unit 13C. The frequency difference comparison unit 64 compares the calculated absolute values of the three frequency differences with the frequency variation setting value fsv set in the frequency variation detection setting unit 62 to determine whether or not the frequency variation is abnormal. If at least one of the absolute values of these frequency differences is larger than the frequency fluctuation set value fsv, it is determined that the frequency fluctuation is abnormal. That is, if at least one of the following three inequalities holds, it is determined that the frequency fluctuation is abnormal, and otherwise, it is determined normal. When it is determined that the frequency fluctuation is abnormal, the frequency difference comparison unit 64 outputs a signal indicating “1” to the failure detection unit 25E. If it is determined that the frequency is normal, the frequency difference comparison unit 64 outputs a signal indicating “0” to the failure detection unit 25E.
　｜ｆｕｖ－ｆｖｗ｜　＞　ｆｓｖ、　｜ｆｖｗ－ｆｗｕ｜　＞　ｆｓｖ、　｜ｆｗｕ－ｆｕｖ｜　＞ｆＶｓｖ
　故障検出部２５Ｅは、周波数比較部２０Ｅ、ＮＯＴ演算回路２１、ＮＯＴ演算回路２２、ＸＯＲ演算回路２４、相順比較部５２、電圧差比較部６３、及び周波数差比較部６４のそれぞれから受信する信号に基づいて、故障を検出する。故障検出部２５Ｅは、受信した信号のうちいずれかが‘１’を示す信号（即ち、異常を示す信号）であれば故障と判断する。故障検出部２５Ｅは、故障を検出すると、故障信号ＮＧをインバータ装置２に出力する。 | Fuv-fvw |> fsv, | fvw-fwu |> fsv, | fwu-fuv |> fVsv
The failure detection unit 25E receives signals from the frequency comparison unit 20E, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, the phase sequence comparison unit 52, the voltage difference comparison unit 63, and the frequency difference comparison unit 64. Based on the above, a failure is detected. The failure detection unit 25E determines that a failure has occurred if any of the received signals is a signal indicating “1” (that is, a signal indicating abnormality). The failure detection unit 25E outputs a failure signal NG to the inverter device 2 when detecting a failure.
　本実施形態によれば、第１の実施形態による作用効果に加え、以下の作用効果を得ることができる。 According to the present embodiment, in addition to the functions and effects of the first embodiment, the following functions and effects can be obtained.
　相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕの相互間の電圧差及び相間電圧の周波数ｆｕｖ，ｆｖｗ，ｆｗｕの相互間の周波数差を監視することで、相間電圧Ｖｕｖ，Ｖｖｗ，Ｖｗｕを別々に監視しても検出することのできない異常を検出することができる。 Even if the interphase voltages Vuv, Vvw, and Vwu are separately monitored by monitoring the voltage difference between the interphase voltages Vuv, Vvw, and Vwu and the frequency difference between the interphase voltages fuv, fvw, and fwu. Abnormalities that cannot be detected can be detected.
（第７の実施形態）
　図８は、本発明の第７の実施形態に係るドライブシステム１０Ｆの構成を示す構成図である。 (Seventh embodiment)
FIG. 8 is a configuration diagram showing a configuration of a drive system 10F according to the seventh embodiment of the present invention.
　ドライブシステム１０Ｆは、図１に示す第１の実施形態に係るドライブシステム１０において、監視装置１を監視装置１Ｆに代え、上位システム９を追加したものである。監視装置１Ｆは、第１の実施形態に係る監視装置１の監視回路６を、故障検出部２５から故障検出部２５Ｆに代え、ＯＲ演算回路７１及びＸＯＲ演算回路７２を追加した監視回路６Ｆに代えたものである。その他の点は、第１の実施形態と同様である。 In the drive system 10 according to the first embodiment shown in FIG. 1, the drive system 10F is obtained by replacing the monitoring device 1 with the monitoring device 1F and adding a host system 9. The monitoring device 1F replaces the monitoring circuit 6 of the monitoring device 1 according to the first embodiment with a monitoring circuit 6F in which an OR operation circuit 71 and an XOR operation circuit 72 are added instead of the failure detection unit 25 to the failure detection unit 25F. It is a thing. Other points are the same as in the first embodiment.
　上位システム９は、インバータ装置２の制御装置８の上位制御系のシステムである。上位システム９は、運転指令部９１及び監視指令部９２を備える。 The host system 9 is a host control system of the control device 8 of the inverter device 2. The host system 9 includes an operation command unit 91 and a monitoring command unit 92.
　運転指令部９１は、インバータ装置２の制御装置８にドライブシステム１０Ｆの制御内容などを含む運転指令を送信する。運転指令部９１は、制御装置８の運転シーケンス実行部３１と情報の送受信することで、ドライブシステム１０Ｆの現在の運転状態を把握する。運転指令部９１は、ドライブシステム１０Ｆの運転状態に基づいて、運転指令の内容を決定する。制御装置８は、運転指令部９１から受信した運転指令に従って、ドライブシステム１０Ｆを制御する。 The operation command unit 91 transmits an operation command including the control content of the drive system 10F to the control device 8 of the inverter device 2. The operation command unit 91 grasps the current operation state of the drive system 10 </ b> F by transmitting and receiving information to and from the operation sequence execution unit 31 of the control device 8. The operation command unit 91 determines the content of the operation command based on the operation state of the drive system 10F. The control device 8 controls the drive system 10F in accordance with the operation command received from the operation command unit 91.
　監視指令部９２は、監視条件が成立している場合に、監視装置１Ｆに監視指令を出力する。監視条件が成立しているかどうかは、インバータ装置２の監視指令部３３と同様に、インバータ装置２が監視される状態にあるか否かで決定される。監視条件は、監視装置１Ｆによる監視が正常に行えないような要因が無ければ成立する。例えば、監視指令部９２は、運転指令部９１から受信するインバータ装置２及び電動機３の運転状態に基づいて、監視条件が成立しているか否かを判断する。監視条件が成立している場合は、監視指令部９２は、監視装置１Ｆに監視指令を出力する。監視条件が成立していない場合は、監視指令部９２は、監視装置１Ｆに監視指令を出力しない。ここで、監視指令部９２は、監視指令を出力する場合は、監視指令信号Ｃ２を‘１’にして送信し、監視指令を出力しない場合は、監視指令信号Ｃ２を‘０’にして送信する。 The monitoring command unit 92 outputs a monitoring command to the monitoring device 1F when the monitoring condition is satisfied. Whether or not the monitoring condition is satisfied is determined by whether or not the inverter device 2 is in a state of being monitored, similarly to the monitoring command unit 33 of the inverter device 2. The monitoring condition is satisfied if there is no factor that prevents the monitoring by the monitoring device 1F from being performed normally. For example, the monitoring command unit 92 determines whether or not the monitoring condition is satisfied based on the operation state of the inverter device 2 and the electric motor 3 received from the operation command unit 91. If the monitoring condition is satisfied, the monitoring command unit 92 outputs a monitoring command to the monitoring device 1F. When the monitoring condition is not satisfied, the monitoring command unit 92 does not output a monitoring command to the monitoring device 1F. Here, the monitoring command unit 92 transmits the monitoring command signal C2 to “1” when outputting the monitoring command, and transmits the monitoring command signal C2 to “0” when not outputting the monitoring command. .
　ＯＲ演算回路７１には、インバータ装置２から受信した監視指令信号Ｃ１及び上位システム９から受信した監視指令信号Ｃ２が入力される。ＯＲ演算回路７１は、入力された２つの監視指令信号Ｃ１，Ｃ２の論理和をＸＯＲ演算回路２４に出力する。従って、入力された２つの監視指令信号Ｃ１，Ｃ２のうち少なくとも１つが‘１’の場合（上位システム９又はインバータ装置２のうち少なくとも一方が監視指令を出力している場合）は、ＸＯＲ演算回路２４に‘１’が入力され、そうでない場合は、ＸＯＲ演算回路２４に‘０’が入力される。 The OR operation circuit 71 receives the monitoring command signal C1 received from the inverter device 2 and the monitoring command signal C2 received from the host system 9. The OR operation circuit 71 outputs the logical sum of the two input monitoring command signals C1 and C2 to the XOR operation circuit 24. Therefore, when at least one of the two input monitoring command signals C1 and C2 is '1' (when at least one of the host system 9 or the inverter device 2 outputs a monitoring command), the XOR operation circuit “1” is input to 24, otherwise “0” is input to the XOR operation circuit 24.
　ＸＯＲ演算回路７２には、インバータ装置２から受信した監視指令信号Ｃ１及び上位システム９から受信した監視指令信号Ｃ２が入力される。ＸＯＲ演算回路７２は、入力された２つの監視指令信号Ｃ１，Ｃ２の排他的論理和を故障検出部２５Ｆに出力する。これにより、インバータ装置２から受信した監視指令信号Ｃ１と上位システム９から受信した監視指令信号Ｃ２が一致しない場合、ＸＯＲ演算回路７２は、不一致異常として‘１’を示す信号を出力し、そうでない場合、正常として‘０’を示す信号を出力する。この異常検出では、インバータ装置２又は上位システム９のいずれか一方に異常があるような場合に、この異常を検出できる。 The monitor command signal C1 received from the inverter device 2 and the monitor command signal C2 received from the host system 9 are input to the XOR operation circuit 72. The XOR operation circuit 72 outputs the exclusive OR of the two input monitoring command signals C1 and C2 to the failure detection unit 25F. As a result, when the monitoring command signal C1 received from the inverter device 2 and the monitoring command signal C2 received from the host system 9 do not match, the XOR operation circuit 72 outputs a signal indicating “1” as a mismatch error, and is not so. In this case, a signal indicating “0” is output as normal. In this abnormality detection, this abnormality can be detected when either the inverter device 2 or the host system 9 has an abnormality.
　故障検出部２５Ｆは、周波数比較部２０、ＮＯＴ演算回路２１、ＮＯＴ演算回路２２、ＸＯＲ演算回路２４、及びＸＯＲ演算回路７２のそれぞれから受信する信号に基づいて、故障を検出する。故障検出部２５Ｆは、受信した信号のうちいずれかが‘１’を示す信号（即ち、異常を示す信号）であれば故障と判断する。故障検出部２５Ｆは、故障を検出すると、故障信号ＮＧをインバータ装置２に出力する。 The failure detection unit 25F detects a failure based on signals received from each of the frequency comparison unit 20, the NOT operation circuit 21, the NOT operation circuit 22, the XOR operation circuit 24, and the XOR operation circuit 72. The failure detection unit 25F determines that there is a failure if any of the received signals is a signal indicating '1' (that is, a signal indicating abnormality). The failure detection unit 25F outputs a failure signal NG to the inverter device 2 when detecting a failure.
　本実施形態によれば、第１の実施形態による作用効果に加え、以下の作用効果を得ることができる。 According to the present embodiment, in addition to the functions and effects of the first embodiment, the following functions and effects can be obtained.
　インバータ装置２に、上位システム９のような上位制御系の装置がある場合、インバータ装置２に内蔵する制御装置８による制御と上位システム９の制御との整合性を外部装置である監視装置１で監視することができる。これにより、ドライブシステム１０Ｆの制御の信頼性を高めることができる。 When the inverter device 2 has a host control system device such as the host system 9, the monitoring device 1, which is an external device, matches the consistency between the control by the control device 8 built in the inverter device 2 and the control of the host system 9. Can be monitored. Thereby, the reliability of control of the drive system 10F can be improved.
　なお、各実施形態において、異常の検出方法については、任意に組み合わせてもよい。監視装置の運用環境に応じて適切な異常検出方法を選択することができる。また、第４の実施形態では、多数決判定回路を用いたが、その他の実施形態でも、任意の異常検出で多数決判定回路を用いてもよい。さらに、第７の実施形態に係る上位システム９は、他の実施形態に適用してもよい。 In each embodiment, the abnormality detection method may be arbitrarily combined. An appropriate abnormality detection method can be selected according to the operating environment of the monitoring device. In the fourth embodiment, a majority decision circuit is used. However, in other embodiments, a majority decision circuit may be used for arbitrary abnormality detection. Furthermore, the host system 9 according to the seventh embodiment may be applied to other embodiments.
　各実施形態では、電圧を検出（測定）する電圧検出器５，５Ｃを用いた構成で説明したが、監視対象から出力される電力変換装置の出力を検出するのであれば、出力電流若しくは出力電力などの電気量（大きさ又は周波数など）、又は電力変換装置の出力で動作する電動機の回転数若しくはトルクなどの動作量など、どのような出力量を検出してもよい。 In each embodiment, the configuration using the voltage detectors 5 and 5C that detect (measure) the voltage has been described. However, if the output of the power converter output from the monitoring target is detected, the output current or the output power Any output amount may be detected, such as the amount of electricity (such as magnitude or frequency), or the amount of operation such as the rotational speed or torque of an electric motor that operates with the output of the power converter.
　各実施形態では、インバータ装置２，２Ｂは、監視装置１～１Ｆにより検出された故障信号ＮＧを受信した場合、インバータ回路７をゲートブロックしたが、ゲートブロック以外の他の保護動作を実行してもよい。例えば、監視装置１～１Ｆにより故障が検出された場合、インバータ装置２，２Ｂの出力を止めるように、直流側又は交流側に設けられた遮断器をトリップするようにしてもよい。 In each embodiment, when the inverter devices 2 and 2B receive the failure signal NG detected by the monitoring devices 1 to 1F, the inverter circuit 7 is gate-blocked, but the protection operation other than the gate block is performed. Also good. For example, when a failure is detected by the monitoring devices 1 to 1F, the circuit breaker provided on the DC side or the AC side may be tripped so as to stop the output of the inverter devices 2 and 2B.
　多数決判定回路５３～５６は、入力された複数の情報のうち過半数以上の情報を出力する回路としたが、全数が異常の場合のみ異常を出力するようにしてもよい。　各実施形態では、インバータを用いて電動機を制御するシステムについて説明したが、電力変換装置（インバータを含む）の出力を制御するシステムであれば、どのような監視対象のシステム及び監視装置でもよい。 The majority decision determination circuits 53 to 56 are circuits that output more than a majority of the input information, but may output an abnormality only when the total number is abnormal. In each embodiment, a system for controlling an electric motor using an inverter has been described. However, any monitoring target system and monitoring device may be used as long as the system controls the output of a power conversion device (including an inverter).
　なお、本発明は上記実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより、種々の発明を形成できる。例えば、実施形態に示される全構成要素から幾つかの構成要素を削除してもよい。さらに、異なる実施形態にわたる構成要素を適宜組み合わせてもよい。 Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

Claims (11)

  1. 　電力変換装置の制御系から独立したハードウェアで構成され、前記電力変換装置を監視する電力変換装置の監視装置であって、
    　前記電力変換装置の出力を検出する出力検出手段と、
    　前記出力検出手段により検出された前記電力変換装置の出力に基づいて、前記電力変換装置の出力を監視する出力監視手段と、
    　前記出力監視手段による監視に基づいて、前記電力変換装置の出力異常を検出する出力異常検出手段と、
    　前記電力変換装置が監視される状態にあるか否かを示す監視信号を受信する監視信号受信手段と、
    　前記出力監視手段による監視及び前記監視信号受信手段から受信した前記監視信号に基づいて、監視異常を検出する監視異常検出手段と
    を備えることを特徴とする電力変換装置の監視装置。     A power conversion device monitoring device configured by hardware independent from a control system of the power conversion device and monitoring the power conversion device,
    Output detection means for detecting the output of the power converter;
    Output monitoring means for monitoring the output of the power converter based on the output of the power converter detected by the output detector;
    Based on monitoring by the output monitoring means, output abnormality detection means for detecting an output abnormality of the power converter,
    Monitoring signal receiving means for receiving a monitoring signal indicating whether or not the power converter is in a state of being monitored;
    A monitoring apparatus for a power converter, comprising: monitoring abnormality detecting means for detecting monitoring abnormality based on monitoring by the output monitoring means and the monitoring signal received from the monitoring signal receiving means.
  2. 　前記出力検出手段は、前記電力変換装置から出力される電気量を検出し、
    　前記出力異常検出手段は、前記出力検出手段により検出された電気量の大きさ及び周波数の異常を検出すること
    を特徴とする請求項１に記載の電力変換装置の監視装置。     The output detection means detects the amount of electricity output from the power converter,
    The monitoring apparatus for a power converter according to claim 1, wherein the output abnormality detection means detects an abnormality in magnitude and frequency of electricity detected by the output detection means.
  3. 　前記出力異常検出手段は、前記周波数の変化が所定値よりも大きい場合、周波数変化異常を検出すること
    を特徴とする請求項２に記載の電力変換装置の監視装置。     The monitoring apparatus for a power converter according to claim 2, wherein the output abnormality detecting means detects a frequency change abnormality when the change in the frequency is greater than a predetermined value.
  4. 　前記出力異常検出手段は、前記電気量の前記大きさと前記周波数の比が異常であることを検出すること
    を特徴とする請求項２に記載の電力変換装置の監視装置。     The monitoring apparatus for a power converter according to claim 2, wherein the output abnormality detecting means detects that the ratio of the magnitude of the quantity of electricity and the frequency is abnormal.
  5. 　前記出力検出手段は、前記電力変換装置から出力される少なくとも３つの電気量を検出し、
    　前記出力異常検出手段は、前記出力検出手段により検出された前記少なくとも３つの電気量のうち過半数、または全数の電気量が異常である場合、前記出力異常を検出すること
    を特徴とする請求項２に記載の電力変換装置の監視装置。     The output detection means detects at least three electric quantities output from the power converter,
    3. The output abnormality detection unit detects the output abnormality when a majority or all of the at least three electric quantities detected by the output detection unit are abnormal. The monitoring apparatus of the power converter device of description.
  6. 　前記出力検出手段は、前記電力変換装置から出力される少なくとも３つの電気量を検出し、
    　前記出力異常検出手段は、前記電気量ごとの前記出力異常の過半数、または全数が異常である場合、前記出力異常を検出すること
    を特徴とする請求項２に記載の電力変換装置の監視装置。     The output detection means detects at least three electric quantities output from the power converter,
    The power output monitoring device according to claim 2, wherein the output abnormality detection unit detects the output abnormality when a majority or all of the output abnormalities for each electric quantity are abnormal.
  7. 　前記出力検出手段は、前記電力変換装置から出力される３つの電気量を検出し、
    　前記出力異常検出手段は、前記出力検出手段により検出された前記３つの電気量の相互間の差に基づいて、前記出力異常を検出すること
    を特徴とする請求項２に記載の電力変換装置の監視装置。     The output detection means detects three electric quantities output from the power converter,
    3. The power converter according to claim 2, wherein the output abnormality detection unit detects the output abnormality based on a difference between the three electric quantities detected by the output detection unit. Monitoring device.
  8. 　前記電力変換装置の上位制御系から前記電力変換装置が監視される状態にあるか否かを示す上位制御系信号を受信する上位制御系信号受信手段と、
    　前記監視信号受信手段により受信した前記監視信号の内容と前記上位制御系信号受信手段により受信した前記上位制御系信号の内容が一致しない場合、不一致異常を検出する不一致異常検出手段と
    を備えることを特徴とする請求項１に記載の電力変換装置の監視装置。     Upper control system signal receiving means for receiving an upper control system signal indicating whether or not the power converter is in a state of being monitored from the upper control system of the power converter;
    A mismatch abnormality detecting means for detecting a mismatch abnormality when the contents of the monitoring signal received by the monitoring signal receiving means and the contents of the higher control system signal received by the higher control system signal receiving means do not match. The monitoring apparatus for a power conversion apparatus according to claim 1, wherein the monitoring apparatus is a power conversion apparatus.
  9. 　電力変換装置の制御系から独立したハードウェアで構成され、前記電力変換装置を監視する電力変換装置の監視方法であって、
    　前記電力変換装置の出力を検出し、
    　検出した前記電力変換装置の出力に基づいて、前記電力変換装置の出力を監視し、
    　前記監視に基づいて、前記電力変換装置の出力異常を検出し、
    　前記電力変換装置が監視される状態にあるか否かを示す監視信号を受信し、
    　前記監視及び受信した前記監視信号に基づいて、監視異常を検出すること
    を含むことを特徴とする電力変換装置の監視方法。     A method for monitoring a power converter, which is configured by hardware independent of a control system of the power converter, and monitors the power converter,
    Detecting the output of the power converter,
    Based on the detected output of the power converter, the output of the power converter is monitored,
    Based on the monitoring, detecting an output abnormality of the power converter,
    Receiving a monitoring signal indicating whether the power converter is in a state of being monitored;
    A monitoring method for a power converter, comprising: detecting a monitoring abnormality based on the monitoring and the received monitoring signal.
  10. 　監視対象の電力変換装置と、
    　前記電力変換装置の制御系から独立したハードウェアで構成され、前記電力変換装置を監視する監視装置とを備え、
    　前記監視装置は、
    　前記電力変換装置の出力を検出する出力検出手段と、
    　前記出力検出手段により検出された前記電力変換装置の出力に基づいて、前記電力変換装置の出力を監視する出力監視手段と、
    　前記出力監視手段による監視に基づいて、前記電力変換装置の出力異常を検出する出力異常検出手段と、
    　前記電力変換装置が監視される状態にあるか否かを示す監視信号を受信する監視信号受信手段と、
    　前記出力監視手段による監視及び前記監視信号受信手段から受信した前記監視信号に基づいて、監視異常を検出する監視異常検出手段とを備えること
    を特徴とする監視システム。     A power conversion device to be monitored;
    It is composed of hardware independent from the control system of the power converter, and includes a monitoring device that monitors the power converter,
    The monitoring device
    Output detection means for detecting the output of the power converter;
    Output monitoring means for monitoring the output of the power converter based on the output of the power converter detected by the output detector;
    Based on monitoring by the output monitoring means, output abnormality detection means for detecting an output abnormality of the power converter,
    Monitoring signal receiving means for receiving a monitoring signal indicating whether or not the power converter is in a state of being monitored;
    A monitoring abnormality detecting means for detecting a monitoring abnormality based on the monitoring by the output monitoring means and the monitoring signal received from the monitoring signal receiving means.
  11. 　前記電力変換装置から出力される交流電力により駆動する電動機
    を備えることを特徴とする請求項１０に記載の監視システム。     The monitoring system according to claim 10, further comprising an electric motor driven by AC power output from the power converter.
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JPWO2018198191A1 (en) * 2017-04-25 2019-11-07 東芝三菱電機産業システム株式会社 Power conversion device and power conversion system
US10965226B2 (en) 2017-04-25 2021-03-30 Toshiba Mitsubishi-Electric Industrial Systems Corporation Power conversion apparatus and power conversion system

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