JPWO2018198191A1 - Power conversion device and power conversion system - Google Patents

Abstract

Provided are a power conversion device and a power conversion system that ensure safety capable of reliably performing an emergency stop and have a failure monitoring function. The power conversion apparatus includes a control circuit unit that transmits a PWM signal to the main circuit unit, and includes an operation command signal for operating / stopping the electric motor and a first emergency stop command signal for performing an emergency stop, and the control The circuit unit includes a PWM signal generation circuit, a test signal generation and monitoring circuit unit that controls the timing at which the PWM signal is output and monitors the operation, the operation command signal is in an operating state, and the first emergency An on-delay 3 output signal that outputs a predetermined time T3 and L level when the stop command signal is not in an emergency stop state, and during that output, a test pulse generation command signal is output to turn on / off the PWM signal. When the first emergency stop command signal is received or when the first test lock signal is output, the first answer signal is transmitted as a response signal to the host monitoring device.

Description

  Embodiments described herein relate generally to a power conversion device and a power conversion system.

  In order to reliably stop the power conversion device, the reliability of the emergency stop circuit becomes an issue. Although it is necessary to self-diagnose that the emergency stop circuit is healthy, there is a problem that the reliability of the entire apparatus is impaired when the diagnostic circuit becomes complicated.

  In a drive device that is a power conversion device that drives a motor, the drive device is interposed between a gate drive circuit that drives the inverter unit and a PWM generation circuit that generates a pulse width modulation (PWM) signal to be given to the gate drive circuit. The safety stop circuit is configured with an external power cutoff terminal and a PWM signal cutoff circuit that shuts off any of the PWM signals in conjunction with the external power cutoff terminal. A technique for blocking a PWM signal to a gate drive circuit by blocking a PWM signal blocking circuit is disclosed (see Patent Document 1).

WO2008-132975

  However, the invention described in Patent Document 1 functions normally when the safety stop circuit (or emergency stop circuit) is healthy, but safely when reliability of soundness is not obtained. There was a problem that there was a possibility that it could not be stopped.

  The present invention has been made in order to solve the above-described problems. The emergency stop command signal for emergency stop of the drive device between the host supervisory control device and the drive device is a dual system, and the host monitor Power conversion that can make an emergency stop reliably by delaying the start of operation for a predetermined time after the operation command signal is output from the control device and checking the emergency stop circuit in the drive device with a monitoring circuit An object is to provide an apparatus and a power conversion system.

In order to achieve the above object, a power conversion system according to claim 1 of the present invention provides:
A power conversion system configured to have a power conversion device that receives power supply to drive an electric motor, and a host supervisory control device that is communicably connected to the power conversion device,
The upper monitoring device is at least:
An operation command signal to be transmitted to the control circuit unit to operate and stop the converter;
A first emergency stop command signal and a second emergency stop command signal transmitted to the control circuit unit to perform an emergency stop of the converter,
The power converter is
A main circuit section having a power conversion section for supplying AC power to the motor;
A control circuit unit that transmits a gate pulse for driving a semiconductor element constituting the power conversion unit of the main circuit unit to the main circuit unit by a light emitting element, and
The control circuit unit is
A first logic unit that is established on the condition that the first emergency stop command is not established, the second emergency stop command is not established, and the operation command signal;
A first on-delay that outputs a completion signal after a predetermined first predetermined time from the establishment of the output of the first logic unit;
A PWM signal generating circuit for generating the PWM signal when the output of the first on-delay is established;
The light emitting element that converts the output of the logical product of the output of the PWM signal generation circuit and the first lock signal into the gate pulse and transmits the gate pulse to the main circuit unit;
A test signal generating circuit for generating a first test signal and a second test signal;
A lock signal generation function for generating the first lock signal by the logical product of the failure of the first emergency stop command and the first test signal;
A circuit in which power is supplied to the light emitting element only when an output of the logical product of the failure of the second emergency stop command and the second test signal is satisfied;
A function of monitoring the first lock signal;
And a circuit for detecting a decrease in power supply voltage supplied to the light emitting element.

  According to the present invention, the emergency stop command signal for causing the drive device to perform an emergency stop between the host supervisory control device and the drive device is a dual system. It is possible to provide a power conversion device and a power conversion system capable of surely performing an emergency stop by delaying time and operation start and checking the emergency stop circuit in the drive device by the monitoring circuit. .

1 is a schematic configuration diagram of a power conversion system using a power conversion device (drive device) according to Embodiment 1. FIG. The block diagram which shows the flow of the signal between the high-order monitoring control apparatus and drive apparatus which comprise the power conversion system shown in FIG. FIG. 3 is a circuit diagram for explaining functions and operations of portions according to an embodiment of a control circuit unit constituting the drive device shown in FIG. 2. The circuit diagram explaining the function and operation | movement of the part which concerns on the Example of the test signal generation | occurrence | production and monitoring circuit part shown in FIG. FIG. 4 is a timing chart for explaining functions and operations of a control circuit unit and a test signal generation and monitoring circuit unit shown in FIG. 3.

  Embodiments of the present invention will be described below with reference to the drawings.

  Here, the power converter may be referred to as a drive device.

  FIG. 1 is a schematic configuration diagram of a power conversion system 100 using the power conversion device (drive device) 2 according to the first embodiment. The power conversion system 100 includes a drive device 2 and a host supervisory control device 3 that are driven by a three-phase AC power source (hereinafter referred to as an AC power source unless otherwise distinguished) 1 to drive an electric motor 4. Composed.

  The AC power supply 1 supplies AC power to the drive device 2.

  The drive device 2 includes a main circuit unit 20 and a control circuit unit 21, is connected to the AC power source 1 and the motor 4, receives AC power from the AC power source 1, and drives the motor 4. Electric power is generated and supplied to the electric motor 4.

  The main circuit unit 20 includes a power conversion unit (not shown) that converts AC power into AC power necessary for driving the electric motor 4. For example, a converter that converts AC power into DC power, an inverter that converts DC power into AC power, and the like are included, but the description thereof is omitted here because it is not the gist of the present invention.

  The host supervisory control device 3 is communicably connected to the drive device 2 and is provided with an emergency stop command 1 signal and an emergency stop command 2 signal to ensure the reliability of the emergency stop circuit of the drive device 2, and outputs an emergency stop command signal. A double system is used. Further, when the emergency stop command signal is transmitted to the drive device 2, it is confirmed that the answer signal as a response signal from the drive device 2 responds in synchronization. Reference numeral 30a is a control signal from the host supervisory control device 3 to the drive device 20, and an electric motor speed command, an operation command, and an emergency stop command signal (especially an emergency stop command when there is no need to distinguish between signals) The symbol 30b is a response signal (an answer signal) from the drive device 20 to the host supervisory control device 3. When there is no need to distinguish between signals, Is sometimes synonymous with an answer). There are a plurality of emergency stop commands and answers, and details will be described later.

  FIG. 2 is a block diagram showing a signal flow between the host monitoring device 3 and the drive device 2 constituting the power conversion system 100 shown in FIG.

  The host supervisory control device 3 is provided with a command for controlling the drive of the drive device 2 and an abnormality notification means when an abnormality of the drive device 2 is detected.

  As command signals for controlling the drive of the drive device 2, the motor speed command signal 31, the DEB / GB command signal 32, the emergency stop command 1 signal (first emergency stop signal) 33, and the emergency stop command 2 signal (first signal) 2 emergency stop signal) 34 is provided.

  The motor speed command signal 31 is a command for setting the speed reference of the motor 4, and is output from the host monitoring control device 3 to the control circuit unit 21 of the drive device 2.

  The DEB / GB command signal 32 is a so-called operation command signal, and is output from the host monitoring control device 3 to the control circuit unit 21 of the drive device 2.

DEB means to release the gate block, and is a command that permits a switching operation of a switching element (not shown) constituting the drive device 2.

  The GB command is a command for blocking (prohibiting) a switching operation of a switching element (not shown) constituting the drive device 2. That is, here, DEB and GB are two sides. Here, the DEB / GB command 32 is transmitted to the drive device 2 at the time of an operation command, and an H (high) level is transmitted to the drive device 2, and the DEB / GB command 32 is transmitted to the drive device 2 at an L (low) level.

  The emergency stop command 1 signal 33 is a command for emergency stop of the drive device 2, and is output from the host monitoring control device 3 to the control circuit unit 21 of the drive device 2.

The emergency stop command 1 signal 33 is used when an emergency stop button (not shown) provided outside is pressed, or when an emergency stop command signal generated in a sequence by protection interlocking is output. Command 1 signal 33 is transmitted. Here, the emergency stop command 1 signal 33 is transmitted at the L level when the emergency stop command is transmitted.

  The emergency stop command 2 signal 34 is provided for a dual system of command signals for stopping the device as described in the above-mentioned “Problem to be Solved by the Invention”. To the control circuit unit 21 of the drive device 2.

The emergency stop command 2 signal 34 has the same function as the emergency stop command 1 signal 33. The emergency stop command 2 signal 34 is transmitted at the L level when the emergency stop command is transmitted.

  The answer 1 signal 35 is a signal transmitted from the control circuit unit 21 to the host monitoring device 3 and is a response signal of the emergency stop command 1 signal 33.

  The answer 2 signal 36 is a signal transmitted from the control circuit unit 21 to the host monitoring device 3 and is a response signal of the emergency stop command 2 signal 34.

  The emergency stop 1 anomaly 37a is calculated by calculating the emergency stop command 1 signal 33 and the answer 1 signal 35 with the exclusive OR EXOR 37, and the obtained output signal is timed by the on-delay OND1 when the input signal changes from L level to H level. This signal is obtained by delaying by T1. (Hereinafter, the exclusive OR EXOR37 is simply referred to as EXOR37, and the on-delay OND1 is simply referred to as OND1.) The emergency stop command 1 signal 33 is transmitted to the control circuit unit 21 of the drive device 2 at the L level, and the control circuit unit When the answer 1 signal 35 is output at L level from 21, the output signal of the EXOR 37 becomes L level and is determined to be in a normal state, but some abnormality occurs in the control circuit unit 21, and the answer 1 signal 35 is When the signal is not output at the L level, the output signal of the EXOR 37 becomes the H level, and after the delay time T1 has elapsed, the emergency stop 1 abnormality 37a is output (notified) from the OND 1 at the H level. Note that the on-delay is delayed for a predetermined time when the input changes from L level to H level, but there is no output delay when the input changes from H level to L level.

  The emergency stop 2 abnormality 38a is obtained by calculating the emergency stop command 2 signal 34 and the answer 2 signal 36 by the exclusive OR EXOR 38 based on the provision of the emergency stop command 2 signal 34 for the double system of command signals. This is a signal obtained by delaying the obtained output signal by time T1 by the on-delay OND2. (Hereinafter, the exclusive OR EXOR38 is simply referred to as EXOR38, and the on-delay OND2 is simply referred to as OND2.) The emergency stop command 2 signal 34 is transmitted to the control circuit unit 21 of the drive device 2 at the L level, and the control circuit unit 21, when the answer 2 signal 36 is output at the L level, the output signal of the EXOR 38 becomes the L level and is determined to be in a normal state, but some abnormality occurs in the control circuit unit 21, and the answer 2 signal 36 is When the signal is not output at the L level, the output signal of the EXOR 38 becomes the H level, and after the delay time T1 has elapsed, the emergency stop 1 abnormality 38a is output (notified) from the OND 2 at the H level.

  The delay time T1 of OND1 and OND2 is a value that takes into account the processing delay of the circuit and the signal transmission time, and is usually a delay of about several hundred ms. Further, when the emergency stop 1 abnormality 37a or the emergency stop 2 abnormality 38a is established, the host supervisory control device 3 performs necessary protection interlocking processing, but the description thereof is omitted.

  FIG. 3 is a circuit diagram illustrating functions and operations of portions according to the embodiment of the control circuit unit 21 constituting the drive device 2 shown in FIG. FIG. 5 is a timing chart for explaining the functions and functions of the control circuit unit 21 and the test signal generation and monitoring circuit unit shown in FIG. Hereinafter, description will be given with reference to these drawings.

  The control circuit unit 21 is connected to the host monitoring device 3 via the interface unit 210. In addition, a gate pulse based on an optical signal is transmitted to the main circuit unit 20 via the optical communication cable 211. Although the optical communication cable 211 is used here, a gate pulse may be transmitted from the control circuit unit 21 to the main circuit unit 20 using a photocoupler.

  The interface unit 210 with the host monitoring device 3 includes a DEB / GB command 32, an emergency stop command 1 signal 33, an emergency stop command 2 signal 34, an answer 1 signal 35, an answer 2 signal 36, etc., as shown in FIG. This is as described in the host monitoring device 3.

The DEB / GB command 32, the emergency stop command 1 signal 33, and the emergency stop command 2 signal 34 transmitted from the host monitoring device 3 are converted into appropriate signal levels by the interface unit 210, and the DEB / GB command 32a and the emergency stop command are respectively transmitted. 1 signal 33a and emergency stop command 2 signal 34a.

The emergency stop command 1 signal 33a and the emergency stop command 2 signal 34a are input to the logical product AND4 (hereinafter, the logical product AND4 is simply referred to as AND4).

  The DEB / GB command 32a is input to the test signal generation and monitoring unit 214 and the logical product AND5. (Hereinafter, the logical product AND5 is simply referred to as AND5.) The emergency stop command 1 signal 33a is input to the test signal generation and monitoring unit 214 and the logical product AND1 (hereinafter, the logical product AND1 is simply referred to as AND1.) .

  The test lock 1 signal 46 is input from the test signal generation and monitoring unit 214 to the other of AND1. The test lock 1 signal 46 corresponds to a forced operation signal of the emergency stop command 1 signal 33a.

The emergency stop command 2 signal 34a is input to the test signal generation and monitoring unit 214 and the logical product AND2 (hereinafter, the logical product 2 is simply referred to as AND2).

  The test lock 2 signal 47 is input from the test signal generation and monitoring unit 214 to the other of the AND2. The test lock 2 signal 47 corresponds to the forced operation signal of the emergency stop command 2 signal 34a.

  Other operation permission condition signal 40 from a circuit (not shown) is input to the other input terminal of AND5.

  The other operation permission conditions are, for example, a state signal of the cooling device, a state of the AC power supply 1, and the like. When the operation permission is established, the other operation permission condition signal 40 becomes H level.

  The output of AND4 and the output of AND5 are input to the logical product AND6 (hereinafter, the logical product AND6 is simply referred to as AND6).

  The gate generation permission signal 41 that is the output of the AND 6 is input to the on-delay OND 3 (hereinafter, the on-delay OND 3 is simply referred to as OND 3).

  OND3 is an on-delay in which when the input signal changes from L level to H level, the output signal is delayed by a predetermined time T3 to become H level.

  The output signal 42 of the OND 3 is input to the logical OR 21 and also to the test signal generation and monitoring unit 214. A test pulse generation command signal 48 is input from the test signal generation and monitoring unit 214 to the other input of the logical OR 21.

  The output signal 44 of the logical sum OR1 is input to the PWM signal generation circuit 215.

When the output signal 44 of the logical OR 1 becomes H level, the PWM signal generation circuit 215 switches the PWM signal 44 for switching the semiconductor elements of the main circuit unit 20 in accordance with a motor speed command (not shown), an output current feedback signal of the drive device 2, and the like. Is generated.

  The answer 1 signal 35a, which is the output of AND1, is input to the logical product AND3 and the test signal generation and monitoring unit 214 (hereinafter, the logical product AND3 is simply referred to as AND3). Further, the answer 1 signal 35a, which is the output of AND1, is input to the interface unit 210, is desensitized to an appropriate signal level, and is output as the answer 1 signal 35 to the host monitoring device 3.

  The PWM signal 44 that is the output of the PWM signal generation circuit 215 is input to the AND 3, and the output 45 of the AND 3 is connected to the light emitting element 212 and the test signal generation and monitoring unit 214.

  Further, the PWM signal 44 that is the output of the PWM signal generation circuit 215 is connected to the test signal generation and monitoring unit 214.

  The power source of the light emitting element 212 is connected from the power source for the light emitting element to the emitter of the transistor Tr1, and further connected to the power supply terminal of the light emitting element 212 via the collector of Tr1. The output of the AND2 is connected to the base of the transistor Tr1 through the amplifier AMP1 (hereinafter, the amplifier AMP1 is simply referred to as AMP1).

  When power is supplied to the light emitting element 212, the output 45 of the AND3 is converted into an optical signal by the light emitting element 212 and transmitted to the main circuit unit 20 as a gate pulse via the optical communication cable 211.

  The collector of the transistor Tr <b> 1 is connected to the power supply terminal of the light emitting element 212 and to the power supply drop detection unit 213. The output of the power drop detection unit 213 is input to the test signal generation and monitoring unit 214 as the answer 2 signal 36 a and also input to the interface unit 210, and is output to the higher-level monitoring device 3 as the answer 2 signal 36 after being perceived by an appropriate signal level. Is done.

(Operation at startup)
The operation at the time of start-up refers to an operation in a state where the emergency stop state is canceled and the operation stop state returns to the state (1) below.

(1) The DEB / GB command signal is in the DEB state (H level), the emergency stop command 1 signal 33 and the emergency stop command 2 signal 34 are not in a state where the emergency stop command is output (H level), and The other driving permission condition signal 40 is in a driving permission state (H level). That is, the emergency stop command 1 signal 33 changes from the L level to the H level (timing t1 in FIG. 5), the emergency stop command 2 signal 34 changes from the L level to the H level (timing t2 in FIG. 5), and other operation permission condition signals 40 Is from the L level to the H level (timing t3 in FIG. 5), and the DEB / GB command signal 32 is at the H level (timing t4 in FIG. 5).

  In this case, the gate generation permission signal 41 output from AND4, AND5, and AND6 is in a permission state (H level).

  The output signal 41 of the AND 6 is input to the OND 3.

  The OND 3 is delayed for a predetermined time (hereinafter referred to as a delay time) set when the input signal changes from L level to H level. In this case, the output signal 41 of the on-delay 3 is maintained at the L level during the delay time (T3) of the signal (L level) input from the AND 6, and becomes the H level after the delay time has elapsed. The output signal 42 of the OND 3 is input to one terminal of the logical sum OR1.

  The output signal 43 of the logical sum OR1 is input to the PWM signal generation circuit 215.

  The PWM signal generation circuit 215 does not output a PWM signal while the input output signal 43 of the logical sum OR1 is at the L level, and when the predetermined delay time elapses (timing t9 in FIG. 5), the PWM signal is generated. 44 is output ((m) in FIG. 5).

  The output signal 44 of the PWM signal generation circuit 215 is input to one input terminal of the AND3, and the output signal 35a of the AND1 is input to the other input terminal of the AND3.

  Here, since the output signal 35a of AND1 is at the H level (t6 in FIG. 5 (n)), the PWM signal 44 input to one input terminal of AND3 is output from the output terminal of AND3.

  The output signal of AND2 is input to AMP1. The output signal of AMP1 is input to the base of the transistor Tr1, and the transistor Tr1 is turned on / off. Here, since the output signal of AND2 is at the H level (timing t8 in FIG. 5), the transistor Tr1 is turned on, and the power supply for the light emitting element connected to the collector C of the transistor Tr1 is supplied to the light emitting element 212. Supplied.

  The light emitting element 212 is a communication device for performing optical communication by converting the output signal 45 of the AND3 into an optical signal, and the optical signal of the light emitting element 212 is transmitted to the main circuit unit 20 connected via an optical communication cable. Sent. In the present embodiment, an optical signal is used for communication between the control circuit unit 21 and the main circuit unit 20. However, the present invention provides a communication means between the control circuit unit 21 and the main circuit unit 20. However, the present invention is not limited to this.

  The output signal 35a (FIG. 5 (n)) of the AND1 is not in the state where the emergency stop command is output (H level) in the normal operation, the emergency stop command 1 signal 33a input to one terminal of the AND1. Therefore, the test lock 1 signal 46 (first test lock signal) input to the other terminal of AND1 is excluded during the lock state (L level), that is, excluding the period from timing t4 to t6 in FIG. Thus, the H level is maintained ((i) and (n) in FIG. 5). The operation when the test lock 1 signal 46 is in the locked state (L level) will be described later.

  The AND1 output signal 35 a is transmitted as an answer 1 signal 35 to the host supervisory control device 3 via the interface unit 210 and also input to the test signal generation and monitoring circuit unit 214.

  The output signal of AND2 (FIG. 5 (o) is input to the base B of the transistor Tr1 via the AMP1, the transistor Tr1 is turned on, and the power supply for the light emitting element is supplied to the power supply terminal of the light emitting element 212. The voltage at the power supply terminal of the light emitting element 212 is detected by the voltage drop detection unit 213, and when the voltage is less than the set value, the voltage drop is detected. When the signal is equal to or higher than the set value, the H level is output, and when the set value is not less than the set value, the L level is output, and the output signal 36a of the voltage drop detection unit 213 is output as the answer 2 signal 36 via the interface unit 210. In addition to the above, the output signal 36a of the voltage drop detection unit 213 is also input to the test signal generation and monitoring circuit unit 214.

  The output signal 36a of the voltage drop detection unit 213 is a period (T5) in which the test lock 2 signal 47 input to the other terminal of AND2 is in the locked state (L level), that is, the L level from timing t4 to t8 in FIG. The H level is maintained except for () (s) in FIG. That is, when the DEB / GB command 32a, the emergency stop command 1 signal 33a, and the emergency stop command 2 signal 33b all become H level at the timing t4, the test signal generation and monitoring circuit unit 214 outputs the test lock 1 signal 46 until the timing t6. During the predetermined period T4.

  The test signal generation and monitoring circuit unit 214 monitors that the states of the emergency stop command 1 signal 32a and the answer 1 signal 35a coincide with each other until the timing t4, and performs an emergency stop with the test lock 1 signal 46 from the timing t4 to the timing t6. The forced operation is monitored in the state of the answer 1 signal 35a. Further, after timing t6, the test signal generation and monitoring circuit unit 214 monitors whether the states of the emergency stop command 1 signal 32a and the answer 1 signal 35a match. Furthermore, when the DEB / GB command 32a, the emergency stop command 1 signal 33a, and the emergency stop command 2 signal 33b all become H level at the timing t4, the test signal generation and monitoring circuit unit 214 sends the test lock 2 signal 47 until the timing t8. It is set to L level for a predetermined period T5.

  The test signal generation and monitoring circuit unit 214 monitors that the states of the emergency stop command 2 signal 33a and the answer 2 signal 36a coincide with each other until timing t4, and performs an emergency stop with the test lock 2 signal 47 from timing t4 to timing t8. Is monitored in the state of the answer 2 signal 36a. Further, after timing t8, the test signal generation and monitoring circuit unit 214 monitors whether the states of the emergency stop command 2 signal 33a and the answer 2 signal 36a match.

  The test lock 1 signal 46 monitors the range until the PWM signal is input to the input terminal of the AND 3, whereas the test lock 2 signal 47 is input to the base of the transistor Tr 1, and the power supply for the light emitting element is used as the light emitting element. In order to monitor the range until the voltage drop is detected, the lock time of the test lock 2 signal 47 is shorter than the time T3 of the on-delay 3 output signal but is shorter than the lock time T4 of the test lock 1 signal 46 T5 is set to be long.

(Operation when stopped)
The operation at the time of stop means an operation in a state satisfying any of the following (1) to (2).

(1) A state in which the DEB / GB command signal 32 outputs a GB command (L level).

(2) A state in which one or both of the emergency stop command 1 signal 33 and the emergency stop command 2 signal 34 output (L level) an emergency stop command (generic name of the emergency stop command 1 signal and 2).

  In the case of (1), the DEB / GB signal 32 a (L level) is input to one terminal of the AND 5 and also input to the test signal generation and monitoring circuit unit 214.

  The output signal (L level) of AND5 is input to one terminal of AND6. The output signal 41 (L level) of the AND 6 is input to the OND 3.

  The OND 3 delays the timing at which the input signal becomes H level for a predetermined time after the input signal becomes H level. However, in an emergency, the output signal of the AND 6 becomes L level and does not become H level until the emergency recovers. Therefore, the output 42 of the on-delay 3 is maintained at the L level and is input to one input terminal of the OR 1.

  A test pulse generation command signal 48 is input from the test signal generation and monitoring circuit unit 214 to the other input terminal of OR1. However, the test pulse generation command signal 48 is used for the operation at the time of start-up, and is not output at the time of stop and maintains the L level. As a result, the output signal 43 of OR1 is maintained at the L level, and the PWM signal 44 is not output from the PWM signal generation circuit 215.

  In the case of (2) above, either one or both of the emergency stop command 1 signal 33 and the emergency stop command 2 signal 34 output (L level) an emergency stop command (generic name for the emergency stop command 1 signal and 2). And similar to (1) above. Since the OR1 output signal 43 is maintained at the L level and the PWM signal generation circuit 215 stops operating, the PWM signal 44 is not output.

  However, the emergency stop command 1 signal 33a (L level) is input to one terminal of AND1, and when the test lock 1 signal 46 input to the other terminal is not output (H level), the AND1 The output signal 35a becomes the L level and is transmitted to the upper supervisory control device 3 as the answer 1 signal 35.

  Similarly, the emergency stop command 2 signal 34a (L level) is input to one terminal of AND2, and the test lock 2 signal 47 input to the other terminal is not output (H level). The output signal of AND2 becomes L level and is input to the base of the transistor Tr1 via the AMP1, the transistor Tr1 is turned off, and the light emitting element power supply to the light emitting element 212 is cut off.

  As described above, the emergency stop command 1 signal 33 and the emergency stop command 2 signal 34 are provided with two emergency stop commands independently, and a double system of emergency stop commands is configured. Even if there is some trouble in the system that outputs the emergency stop command 1 signal and the emergency stop command 1 signal 33 is not output, if the emergency stop command 2 signal 34 is output, the PWM signal is transmitted via the optical communication cable. Are not transmitted to the connected main circuit 20.

  FIG. 4 is a circuit diagram for explaining the functions and operations of the parts according to the embodiment of the test signal generation and monitoring circuit unit 214 shown in FIG. FIG. 5 is a timing chart for explaining the functions and operations of the control circuit unit 21 and the test signal generation and monitoring circuit unit 214 shown in FIG. This will be described below with reference to these.

(One-shot OST4, OST5, OND6 operation)
In FIG. 4, a DEB / GB command signal 32a, an emergency stop command 1 signal 33a and an emergency stop command 2 signal 34a transmitted from the host supervisory control device 3 via the interface unit 210 are input to the logical product AND11, and the logical product AND11. Are output to the one-shot OST4, the one-shot OST5, the on-delay ONDT6, and the inversion INV13. (Hereinafter, AND AND11 is simply referred to as AND11, one-shot OST4 is simply referred to as OST4, one-shot OST5 is simply referred to as OST5, on-delay OND6 is simply referred to as OND6, and inverted INV13 is simply referred to as INV13.)
When the DEB / GB command signal 32a, the emergency stop command 1 signal 33a, and the emergency stop command 2 signal 34a input to the input terminal of the AND 11 all become H level, the output signal of the AND 11 also becomes H level (timing) t4). At this time, the OST 4 keeps the output signal at the H level for a predetermined time indicated by a period T4 (timing t4 to t6). The output of the OST4 is connected to the inversion INV11, and the inversion INV11 outputs an inverted signal of the input. (Hereinafter, the inverted INV11 is simply referred to as INV11.) The output of the OST4 is the test lock 1 signal 46 (see FIG. 5 (i)).

When the output signal of AND11 becomes H level, OST5 sets the output signal to H level for a predetermined time indicated by a period T5 (timing t4 to t8). The output of the OST5 is connected to the inversion INV12 and outputs an inverted signal of the input. The output of OST5 is a test lock 2 signal 47 (FIG. 5 (j)).

  The output of the OND 6 is connected to the one-shot OST 7. When the output signal of the AND 11 changes from the L level to the H level, the output of the OND 6 is delayed by a predetermined time T6 and becomes the H level (timing t5). When the output of the OND 6 becomes H level, the one-shot OST 7 sets the output signal to H level for a predetermined time indicated by a period T7 (timing t5 to t7). This signal becomes a test pulse generation command signal (FIG. 5 (k)).

(Monitoring the coincidence of the emergency stop command 1 signal 33a and the answer 1 signal 35a)
As described with reference to FIG. 3, the answer 1 signal 35 a is an output of the AND 1 as a response signal to the emergency stop command 1 signal 33 a, and is also input to the test signal generation and monitoring circuit unit 214, and further via the interface unit 210. The signal 35 is input to the host monitoring device 3.

  The test signal generation and monitoring circuit unit 214 monitors whether the answer 1 signal 35a is responding to the input emergency stop command 1 signal 33a. Therefore, the emergency stop command 1 signal 33a is an exclusive logical sum EXOR11. The answer 1 signal 35a is input to one terminal and the other terminal of the exclusive OR EXOR11 (hereinafter, the exclusive OR EXOR11 is simply referred to as EXOR11).

  The output signal of the EXOR 11 is at the H level when the two input signals do not match, and at the L level when they match. The output signal of the EXOR 11 is input to one input terminal of the logical product AND12, and the test lock 1 signal 46 is input to the other input terminal of the logical product AND12 (hereinafter, the logical product AND12 is simply referred to as AND12). An output signal of the AND 12 is input to the failure latch circuit 411.

  In this manner, a signal for monitoring the coincidence between the emergency stop command 1 signal 33a and the answer 1 signal 35a is output from the output terminal of the AND 12. As a result of the above monitoring, if they do not match, an H level is output, which is regarded as a failure state, and is latched (saved) by the failure latch circuit 411. In the case of coincidence, the L level is output, and the failure state is not latched by the failure latch circuit 411. Note that the failure latch circuit 411 is related to the processing at the time of failure and, unlike the spirit of the present invention, can be configured with existing technology, and therefore the description thereof is omitted. The same applies to other failure latch circuits described later.

Further, as described above, the test lock 1 signal 46 input to the other input terminal of the AND 12 is output at the L level for a predetermined time indicated by the period T4 (timing t4 to t6), and is output at the other time H level. Therefore, the coincidence between the emergency stop command 1 signal 33a and the answer 1 signal 35a is monitored during the time when the H level is output, and if it does not coincide, it is regarded as a failure state and is latched by the failure latch circuit 411. (Monitoring the coincidence between the test lock 1 signal 46 and the answer 1 signal 35a)
The test lock 1 signal 46 is input to one terminal of the exclusive OR EXOR13, the answer 1 signal 35a is input to the other terminal of the exclusive OR EXOR13, and the test lock 1 signal 46 and the answer 1 signal 35a Monitor for matches. (Hereinafter, exclusive OR EXOR13 is simply referred to as EXOR13.)
As a result of this monitoring, if the output signals of the EXOR 13 do not match, an H level is output and is input to one input terminal of the logical product AND13. (Hereinafter, the logical product AND13 is simply referred to as AND13.) The output of the above-mentioned OST4 is input to the other input terminal of the AND13 (here, the test lock 1 signal 46 is at the L level when the output of the OST4 is at the H level). . The output signal of the AND 13 is input to the failure latch circuit 412.

  As described above, the test lock 1 signal 46 is at the L level for the predetermined time indicated by the period T4 (timing t4 to t6), and the H level is output for the other time, so the time during which the L level is output. The test lock 1 and the answer 1 signal 35a are monitored for coincidence. If they do not coincide with each other, the failure is regarded as a failure state and is latched by the failure latch circuit 412.

(Monitoring the coincidence of the emergency stop command 2 signal 34a and the answer 2 signal 36a)
As described with reference to FIG. 3, the emergency stop command 2 signal 34a is input to one terminal of AND2, and when the emergency stop command 2 signal 34a is at L level, the output signal of the AND2 becomes L level, and AMP1 is Is input to the base of the transistor Tr1 and the transistor Tr1 is turned off, and the light-emitting element power supply to the light-emitting element 212 is prohibited. As a result, the voltage drop detection unit 213 detects a voltage drop, and the answer 2 signal 36a, which is the output of the power supply drop detection unit 213, becomes L level. Further, the answer 2 signal 36 a is transmitted to the host monitoring apparatus 3 as a response signal to the emergency stop command 2 signal 34 via the interface unit 210.

  In order to monitor whether the answer 2 signal 36a is responding as a response signal to the emergency stop command 2 signal 34, the emergency stop command 2 signal 34a is input to one terminal of the exclusive OR EXOR 12, and the answer 2 signal 36a is This is input to the other terminal of the exclusive OR EXOR12 (hereinafter, the exclusive OR EXOR12 is simply referred to as EXOR12).

  The output signal of the EXOR 12 is at the H level when the two input signals do not match, and at the L level when they match. The output signal of the EXOR 12 is input to one input terminal of the logical product AND14, and the output signal (L level) of the logical product AND14 is input to the failure latch circuit 413 (hereinafter, the logical product AND14 is simply referred to as AND14). .

  In this way, a signal for monitoring the coincidence of the emergency stop command 2 signal 34a and the answer 2 signal 36a is output from the output terminal of the AND 14. As a result of the above monitoring, if they do not match, an H level is output, which is regarded as a failure state, and is latched by the failure latch circuit 413. In the case of coincidence, the L level is output, and the failure state is not latched by the failure latch circuit 413.

  Further, as described above, the test lock 2 signal 47 input to the other input terminal of the AND 14 is output at the L level for a predetermined time indicated by the period T5 (timing t4 to t8), and at other times the H level is output. Therefore, the coincidence between the emergency stop command 2 signal 34a and the answer 2 signal 36a is monitored during the time when the H level is being outputted, and if it does not coincide, it is regarded as a failure state and is latched by the failure latch circuit 413. Is done.

(Monitoring the coincidence between the test lock 2 signal 47 and the answer 2 signal 36a)
The test lock 2 signal 47 is input to one terminal of the exclusive OR EXOR14, the answer 2 signal is input to the other terminal of the exclusive OR EXOR14, and the match between the test lock 2 signal 47 and the answer 2 signal is monitored. (Hereinafter, the exclusive OR EXOR14 is simply referred to as EXOR14.)

  As a result of this monitoring, if the output signal of the EXOR 14 does not match, an H level is output and is input to one input terminal of the AND AND 15 (hereinafter, the AND AND 15 is simply referred to as AND 15). The output signal 53 of the OST 5 described above is input to the other input terminal of the AND 15. The output signal (L level) of the AND 15 is input to the failure latch circuit 414.

  As described above, the test lock 2 signal 47 is at the L level for a predetermined time indicated by the period T5 (timing t4 to t8), and the H level is output for the other time, so the time during which the L level is output. The test lock 2 signal 47 and the answer 2 signal 36a are monitored for coincidence. If they do not coincide with each other, the failure is regarded as a failure state and is latched by the failure latch circuit 414.

(Monitor that AND3 output signal 45 is at L level)
The output signal 45 of AND3 shown in FIG. 3 becomes operable when the DEB / GB command signal 32a, the emergency stop command 1 signal 33a, and the emergency stop command 2 signal 34a are all at the H level, and the inversion shown in FIG. A test lock 1 signal 46 is output from INV11 (hereinafter, the output signal of AND3 is simply referred to as AND3 output 45).

  As shown in FIG. 5 (9), the test lock 1 signal 46 is output at the L level for a predetermined time indicated by a period T4 (timing t4 to t6) after the operation becomes possible. The test lock 1 signal 46 (L level) is input to one input terminal of AND1, and the answer 1 signal 35a (L level) which is the output of AND1 is input to one input terminal of AND3.

  As a result, the AND3 output 45 is output at the L level while the test lock 1 signal 46 is output (L level) (see FIGS. 5I and 5P).

  The AND3 output signal 45 is a state immediately before the PWM signal is output to the issuing element 212, and confirming that this signal is at the L level monitors that the PWM signal is not output from the AND3 output terminal. It is important to confirm the emergency stop circuit.

  In FIG. 4, the test lock 1 signal 46, which is the output of INV11, and the output of INV13 are input to the OR circuit OR11. (Hereinafter, the OR circuit OR11 is simply referred to as OR11.) The output of the OR11 is input to one input terminal of the logical product AND16.

  The AND3 output 45 is input to the other input terminal of the logical product AND16, and the output signal is input to the failure latch circuit 415. If the AND3 output signal 45 is H level or a pulse signal is output when the output of the OR11 is H level, the output of the AND AND16 is also considered to be in the fault state because the H level or pulse signal is also output, and the fault latch circuit Latched at 415.

(Monitors the coincidence of PWM signal 44 and AND3 output 45)
The PWM signal 44 output from the PWM signal generation circuit 215 is input to one input terminal of the exclusive OR EXOR15, and the AND3 output 45 is input to the other input terminal of the exclusive OR EXOR15. And the AND3 output 45 are monitored for coincidence (hereinafter, the exclusive OR EXOR15 is simply referred to as EXOR15).

  In this monitoring, the timing for monitoring the coincidence of the output signals is (1) the OR1 output signal is at the H level, and (2) the output 35a of the AND1 is at the H level, and is after the timing t6.

  This monitoring makes it possible to confirm that the system of the DEB / GB command signal 32a, the emergency stop command 1 signal 33a, the emergency stop command 2 signal 34a, and the test lock 1 signal 46 is operating normally. Therefore, the output of OR11 is inverted by inversion INV14, and the signal is used as one input of logical product AND17 (hereinafter, logical product AND17 is simply referred to as AND17). The output of EXOR15 is connected to the other input of AND17. A failure latch circuit 416 is connected to the output of the AND 17.

  As a result, when the output of OR11 is at the L level, the coincidence between the PWM signal 44 and the AND3 output 45 is monitored, and when there is no coincidence, the output of the AND17 is regarded as a failure state due to the H level or pulse signal being output. Is latched on.

(Monitoring that the PWM signal is at L level)
The PWM signal 44 is input to one input terminal of the logical product AND18. (Hereinafter, the logical product AND18 is simply referred to as AND18.) The test pulse generation command signal 48 is input to one input terminal of the logical sum OR12 (hereinafter, the logical sum OR12 is simply referred to as OR12).

  The output signal 42 of the OND 3 is input to the other input terminal of the OR 12, and the output signal is input to the inversion INV 15 (hereinafter, the inversion INV 15 is simply referred to as INV 15).

  The output signal of INV15 is input to the other input terminal of the logical product AND18. As a result, the test pulse generation command signal 48 is at a predetermined time L level indicated by a period T6 (timing t4 to t5), and thereafter is at a predetermined time H level indicated by a period T7 (timing t5 to t7). The output signal 42 of time OR1 from the elapse of the period T7 to the rear end (timing t9) of the on-delay 3 output signal becomes L level, and the PWM signal 44 output from the PWM signal generation circuit 215 becomes L level. In this way, it can be monitored that the PWM signal is at the L level. If an H level or a pulse is output as a result of this monitoring, it is regarded as a failure state and is latched by the failure latch circuit 417.

(Monitoring that the PWM signal 44 is a pulse)
The test pulse generation command signal 48 and the on-delay 3 output signal 42 are input to the input terminal of the OR 12, and the output signals are input to one terminal of the logical product AND19 (hereinafter, the logical product AND19 is simply referred to as AND19). ).

As a result, one input terminal of the AND 19 has a predetermined time H level indicated by a test pulse generation command signal period T7 (timing t5 to t7) and an on-delay 3 output signal period T3 (timing t4 to t9). The L level is maintained for a predetermined time, and the H level after the lapse of the period T3 is input.

  The PWM signal 44 is input to the retriggerable one-shot ROS. Retriggerable one-shot ROS Generates and outputs a signal having a predetermined pulse width T10 set with a rising signal of a PWM signal 44 composed of a plurality of pulses as a trigger. The predetermined pulse width T10 set here is set longer than the period of the carrier frequency of the PWM signal. With this setting, when the PWM signal 44 is outputting a normal PWM pulse, the output of the retriggerable one-shot ROS is continuously at the H level.

  The output signal of the retriggerable one-shot ROS is input to the inversion INV16, and the output signal is input to the other input terminal of the AND19.

  As a result, if the circuit is normal, the output of the retriggerable one-shot OST is performed at the predetermined H level indicated by the period T7 of the test pulse generation command signal and the H level after the lapse of the period T3 of the on-delay 3 output signal. Becomes H level.

  Further, during the period when the PWM signal 44 is not output, the output of the retriggerable one-shot OST is at the H level. Therefore, by inverting the output of the retriggerable one-shot OST with the inversion INV16, the output of the inversion INV16 becomes the L level when the PWM signal 44 is generated, and becomes the H level when the PWM signal 44 is not generated. (FIG. 5 (h), (k), (m)). The output of the AND 19 is connected to the failure latch circuit 418.

  The output of the AND 19 is a monitoring signal that the PWM signal 44 is a pulse. As a result of this monitoring, when the output of the AND 19 is at the H level, it is regarded as a failure state and is latched by the failure latch circuit 418.

  If necessary, a filter may be provided at the input of the failure latch circuits 411 to 418 in order to eliminate a malfunction caused by a pulse-like abnormal signal due to a subtle signal delay or timing difference.

  Also, some or all of the logic circuit, test signal generation circuit, and monitoring circuit shown in FIG. 3 may be realized by software.

  As described above, the command signal for stopping the power conversion device is a dual system, and the test lock signal is output in the power conversion device at a predetermined time after the operation command signal is output until the operation is started. Is output, and the answer signal is transmitted to the host supervisory control device, and the emergency stop is surely performed by monitoring the coincidence between the test lock signal and the answer signal and performing the monitoring that the PWM signal is a pulse or L level. Therefore, it is possible to provide a power conversion device and a power conversion system that can ensure safety and can have a failure monitoring function.

DESCRIPTION OF SYMBOLS 100 Power conversion system 1 Three-phase alternating current power supply 2 Drive apparatus 20 Main circuit part 21 Control circuit part 210 Interface part 211 Optical communication cable 212 Light emitting element 213 Voltage drop detection part 214 Test signal generation and monitoring circuit part 215 PWM signal generation circuit 3 Monitoring control device 30a Control signal 30b Response signal 31 Motor speed command signal 32 DEB / GB command signal 33 Emergency stop command 1 signal 34 Emergency stop command 2 signal 35 Answer 1 signal 36 Answer 2 signal 37a Emergency stop 1 error 38a Emergency stop 2 error 4 Motors EXOR37, EXOR38 Exclusive logical sums OND1, OND2, OND3, OND6 On-delay AND1, AND2, AND3, AND4, AND5, AND6 Logical products AND11, AND12, AND13, AND14, AND15 Logical products AND 6, AND17, AND18 AND AMP1 Amplifier Tr1 Transistors OR1, OR11, OR12 Logical sums INV11, INV12, INV13, INV14, INV15, INV16 Inverted EXOR11, EXOR12, EXOR13, EXOR14 Exclusive logical sum EXOR15 Exclusive logical sum OST4, OST5 OST7 one shot ROST retriggerable one shot

Claims (6)

A power conversion system configured to have a power conversion device that receives power supply to drive an electric motor, and a host supervisory control device that is communicably connected to the power conversion device,
The upper supervisory control device is at least
An operation command signal to be transmitted to the power converter to operate and stop the power converter;
A first emergency stop command signal and a second emergency stop command signal transmitted to the power conversion device to perform an emergency stop of the power conversion device;
The power converter is
A main circuit section having a power conversion section for supplying AC power to the motor;
A control circuit unit that transmits to the main circuit unit a PWM signal that drives a semiconductor element that constitutes a power conversion unit of the main circuit unit,
The control circuit unit is
Means for generating the PWM signal and gate pulse transmitting means for transmitting the PWM signal to the main circuit unit;
Emergency stop means for stopping transmission of the PWM signal to the main circuit section when receiving either the first emergency stop command signal or the second emergency stop command signal;
In a state where neither the first emergency stop command signal or the second emergency stop command signal is received from the upper supervisory control device, and when an operation command signal is received from the upper supervisory control device, Means for starting the operation of the means for generating the PWM signal delayed by a predetermined first delay period;
When the first emergency stop command signal and the second emergency stop command signal are not received from the host supervisory control device, and when the operation command signal is received from the host supervisory control device,
Generating means for generating a first test operation signal for generating a forced operation signal for the first emergency stop command signal in the first delay period;
Generating means for generating a second test operation signal for generating a forced operation signal of the second emergency stop command signal in the first delay period;
Monitoring means for confirming the operation of the emergency stop means;
A power conversion system comprising: A power conversion device of a power conversion system configured to include a power conversion device that receives a supply of power to drive an electric motor, and a host supervisory control device that is communicably connected to the power conversion device,
The power converter is
Means for receiving at least an operation command signal transmitted from the host supervisory control device for operating and stopping the power converter;
Means for receiving a first emergency stop command signal and a second emergency stop command signal transmitted from the host supervisory control device to perform an emergency stop of the power converter;
A main circuit section having a power conversion section for supplying AC power to the motor;
A control circuit unit that transmits to the main circuit unit a PWM signal that drives a semiconductor element that constitutes a power conversion unit of the main circuit unit,
The control circuit unit is
Either the first emergency stop command signal or the second emergency stop command signal is received from the means for generating the PWM signal, the gate pulse transmitting means for transmitting the PWM signal to the main circuit unit, and the host supervisory control device. Emergency stop means for stopping transmission of the PWM signal to the main circuit unit when
In a state where neither the first emergency stop command signal or the second emergency stop command signal is received from the upper supervisory control device, and when an operation command signal is received from the upper supervisory control device, Means for starting the operation of the means for generating the PWM signal delayed by a predetermined first delay period;
When the first emergency stop command signal and the second emergency stop command signal are not received from the host supervisory control device and when the operation command signal is received from the host supervisory control device, A first test operation signal generating means for generating a forced operation signal of the first emergency stop command signal in one delay period;
Generating means for generating a second test operation signal for generating a forced operation signal of the second emergency stop command signal in the first delay period;
Monitoring means for confirming the operation of the emergency stop means;
A power conversion device for a power conversion system, comprising: The control circuit unit uses a light emitting element as part of the means for transmitting the gate pulse,
When the first emergency stop command signal is received, the signal transmitted from the means for generating the PWM signal to the light emitting element is cut off,
3. The power conversion system according to claim 2, wherein when the second emergency stop command signal is received, the power conversion device performs an emergency stop by shutting off power supply to the light emitting element. 4. Power converter. The monitoring means includes
Means for comparing a composite signal of the first emergency stop command signal, the first test operation signal, and an input signal of the light emitting element;
Means for comparing the combined signal of the second emergency stop command signal, the second test operation signal, and the output signal of the monitoring means for the voltage of the power supply terminal of the light emitting element;
The power conversion device of the power conversion system according to claim 3, comprising: The control circuit unit is
In the state where the second test operation signal is generated in the first delay period,
Generating a test signal for operating the means for generating the PWM signal;
Means for comparing the output signal of the means for generating the PWM signal with the input signal of the light emitting element, and monitoring means for monitoring the result of the comparison;
The power conversion device of the power conversion system according to claim 3, comprising: The control circuit unit further includes:
The first delay period is:
A time limit for detecting a mismatch between the first emergency stop signal of the upper supervisory control panel and the response signal of the first emergency stop signal, and the second emergency stop signal of the upper supervisory control board and the second 4. The power conversion device for a power conversion system according to claim 3, wherein the power conversion device is shorter than a time limit for detecting a mismatch with the response signal of the emergency stop signal.

Images