WO2015110032A1 - 显示面板线路结构 - Google Patents

显示面板线路结构 Download PDF

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Publication number
WO2015110032A1
WO2015110032A1 PCT/CN2015/071299 CN2015071299W WO2015110032A1 WO 2015110032 A1 WO2015110032 A1 WO 2015110032A1 CN 2015071299 W CN2015071299 W CN 2015071299W WO 2015110032 A1 WO2015110032 A1 WO 2015110032A1
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Prior art keywords
display panel
line
discharge circuit
discharge
drain
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PCT/CN2015/071299
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English (en)
French (fr)
Inventor
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/777,170 priority Critical patent/US9940894B2/en
Publication of WO2015110032A1 publication Critical patent/WO2015110032A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present invention relates to a line structure of a display panel.
  • the peripheral routing area of the conventional display panel is sequentially set from the inside to the outside as a virtual pixel area, a common electrode routing area, an electrostatic protection line area, a line fan-out area (Fan-out), and a bonding pad area (Bonding Pad).
  • the virtual pixels are used to keep the parameters such as the parasitic capacitance and the impedance of the pixels around the display panel and the pixels inside the display surface to prevent the display effect of the pixels around the display panel from being different from the display fruits of the pixels in the display panel.
  • the ESD protection circuit connects the signal line (scanning line or data line) to the common electrode line through a special circuit to prevent static electricity in the process from damaging the line inside the display panel. Since the above line areas all need a large amount of space occupying the peripheral area of the display panel, it is disadvantageous for the narrow bezel design of the display panel.
  • an embodiment of the present invention provides a display panel line structure including a signal line extending in a first direction, a common electrode line extending in a second direction, a pixel electrode, a first discharge circuit, and a second Discharge circuit.
  • Each of the signal lines is connected to the common electrode line through the first discharge circuit and the second discharge circuit which are connected in series.
  • the pixel electrode is coupled to an intersection between the first discharge loop and the second discharge loop.
  • first direction and the second direction are perpendicular to each other.
  • intersection of two adjacent parallel signal lines and two adjacent common electrode lines defines a plurality of the pixel units arranged in a matrix.
  • One of the pixel electrodes is disposed correspondingly in each of the pixel units.
  • the pixel unit is a virtual pixel unit.
  • the first discharge circuit and the second discharge circuit respectively comprise two thin film transistors.
  • Each of the thin film transistors includes a gate, a source, and a drain.
  • the gate of each thin film transistor is connected to the drain.
  • the source and the drain of one of the first discharge circuit and the second discharge circuit are respectively connected to the drain and the source of the other thin film transistor to form a closed loop.
  • connection point of one of the drain and the source in the first discharge circuit and the second discharge One of the drains in the electrical circuit is connected to the source connection point.
  • connection point of the other drain and source of the second discharge circuit opposite to the first discharge circuit is connected to the common electrode line.
  • connection point of the other drain and source of the second discharge circuit opposite to the first discharge circuit is connected to the common electrode line.
  • the signal line is selected from one of a scan line for transmitting a selected signal and a data line for transmitting a display signal.
  • the pixel electrode is a vertical alignment type pixel electrode having a plurality of slits.
  • the display panel circuit structure provided by the present invention forms a discharge path through a discharge loop composed of thin film transistors in a virtual pixel to function as an electrostatic shield, and the pixel electrode in the dummy pixel can maintain the load of the pixel unit around the display panel and the display panel.
  • the load of the pixel unit is the same. Therefore, the peripheral of the display panel does not need to be provided with a separate electrostatic protection circuit, which is advantageous for the frame space of the display panel to realize a narrow bezel design.
  • FIG. 1 is a schematic structural diagram of a circuit structure of a display panel according to an embodiment of the present invention.
  • the display panel line structure 1 provided by the embodiment of the present invention includes a signal line 10 extending in a first direction, a common electrode line 12 extending in a second direction, a pixel electrode 14 , a first discharge circuit 16 , and Second discharge circuit 18.
  • Each of the signal lines 10 is connected to the common electrode line 12 through the first discharge circuit 16 and the second discharge circuit 18 which are connected in series.
  • the pixel electrode 14 is connected to an intersection between the first discharge circuit 16 and the second discharge circuit 18.
  • the first direction and the second direction are perpendicular to each other, that is, the signal line 10 and the common electrode line 12 intersect perpendicularly.
  • the intersection of two adjacent parallel signal lines 10 and two adjacent common electrode lines 12 defines a plurality of said pixel units 20 arranged in a matrix.
  • One of the pixel electrodes 14 is disposed correspondingly in each of the pixel units 20.
  • One of the signal lines 10 constituting the pixel unit 20 is connected to one of the common electrode lines 12 constituting the corresponding pixel unit 20 through the first discharge circuit 16 and the second discharge circuit 18 which are connected in series.
  • the signal line 10 may be a scan line that transmits a selected signal in the display panel, or may be a data line for transmitting a display signal.
  • the pixel unit 20 is a dummy pixel unit (Dummy Pixel).
  • the first discharge circuit 16 and the second discharge circuit 18 respectively include two thin film transistors 15 (Thin Film Transistors, TFTs).
  • TFTs 15 includes a gate 150, a source 152, and a drain 154.
  • the gate 150 of each of the TFTs 15 is connected to the drain 154.
  • the source 152 and the drain 154 of one of the first discharge circuit 16 and the second discharge circuit 18 are respectively connected to the drain 154 and the source 152 of the other TFT 15 to form a closed loop.
  • a gate 150 of one of the TFTs 15 in the first discharge circuit 16 is connected to the signal line 10.
  • a connection point A of one of the drains 154 and the source 152 in the first discharge circuit 16 is connected to a connection point B of the source 152 of the second discharge circuit 18.
  • connection point of the other drain 154 and the source 152 of the second discharge circuit 18 opposite to the first discharge circuit 16 is connected to the common electrode line 12.
  • the pixel electrode 14 is connected to a connection point between the first discharge circuit 16 and the second discharge circuit 18 interconnection line.
  • the pixel electrode 14 is a vertical alignment type pixel electrode 14 having a plurality of slits.
  • the display panel circuit structure 1 provided by the present invention forms a discharge path through a discharge loop composed of the TFTs 15 in the dummy pixels to function as an electrostatic shield, and the pixel electrodes 14 in the dummy pixels can maintain the load of the pixel unit 20 around the display panel.
  • the load of the pixel unit 20 in the display panel is uniform. Therefore, the peripheral of the display panel does not need to be provided with a separate electrostatic protection circuit, which is advantageous for the frame space of the display panel to realize a narrow bezel design.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示面板线路结构（1），其包括沿第一方向延伸的信号线（10）、沿第二方向延伸的公共电极线（12）、像素电极（14）、第一放电回路（16）及第二放电回路（18）。每个信号线（10）通过相互串接的所述第一放电回路（16）及第二放电回路（18）与公共电极线（12）连接。所述像素电极（14）连接至所述第一放电回路（16）与第二放电回路（18）之间的相交点。

Description

显示面板线路结构 技术领域
本发明涉及一种显示面板的线路结构。
背景技术
传统显示面板的外围走线区由内到外依次设置为虚拟像素区、公共电极走线区，静电防护线路区，线路扇出区(Fan-out)和连接焊垫区(Bonding Pad)。其中所述虚拟像素是为了使显示面板周围的像素的寄生电容、阻抗等参数和显示面本内部的像素保持一致，以防止显示面板周围像素的显示效果与显示面板内像素的显示鲜果存在差异。静电防护线路是通过特殊的电路将信号线(扫描线或数据线)与公共电极线连接起来，以防止制程中的静电对显示面板内部的线路造成损害。由于上述线路区域都需要占用显示面板外围区域的大量空间，不利于显示面板的窄边框设计。
因此，需要提供能够改善上述问题的显示面板线路结构。
发明内容
为了解决上述技术问题，本发明实施例提供了一种显示面板线路结构，其包括沿第一方向延伸的信号线、沿第二方向延伸的公共电极线、像素电极、第一放电回路及第二放电回路。每个信号线通过相互串接的所述第一放电回路及第二放电回路与公共电极线连接。所述像素电极连接至所述第一放电回路与第二放电回路之间的相交点。
其中，所述第一方向与第二方向相互垂直。
其中，相邻的两条平行的信号线与相邻的两条公共电极线相交定义出多个呈矩阵排列的所述像素单元。所述每个像素单元内对应设置有一个所述像素电极。
其中，所述像素单元为虚拟像素单元。
其中，所述第一放电回路及第二放电回路分别包括两个薄膜晶体管。所述每一个所述薄膜晶体管包括栅极、源极及漏极。每一个薄膜晶体管的栅极与漏极相连接。所述第一放电回路及第二放电回路中的其中一个薄膜晶体管的源极及漏极分别与另一个薄膜晶体管的漏极及源极相连接以构成一个闭合回路。
其中，所述第一放电回路中的其中一个漏极与源极的连接点与所述第二放 电回路中的其中一个漏极与源极连接点相连接。
其中，所述第二放电回路与第一放电回路相对的另一个漏极与源极的连接点与公共电极线相连接。
其中，所述第二放电回路与第一放电回路相对的另一个漏极与源极的连接点与公共电极线相连接。
其中，所述信号线选自用于传递选中信号的扫描线及用于传递显示信号的数据线中的一种。
其中，所述像素电极为开设有多条狭缝的垂直配向型像素电极。
本发明所提供的显示面板线路结构通过虚拟像素中薄膜晶体管组成的放电回路形成放电途径以起到静电防护的作用，同时虚拟像素中的像素电极可以保持显示面板周边像素单元的负载与显示面板内的像素单元的负载一致。所以，显示面板的外围不需要再设置独立的静电防护电路，有利于显示面板的边框空间以实现窄边框设计。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例所提供的显示面板线路结构的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示，本发明实施方式所提供的显示面板线路结构1包括沿第一方向延伸的信号线10、沿第二方向延伸的公共电极线12、像素电极14、第一放电回路16及第二放电回路18。每个信号线10通过相互串接的所述第一放电回路16及第二放电回路18与公共电极线12连接。所述像素电极14连接至所述第一放电回路16与第二放电回路18之间的相交点。在本实施例中，所述第一方向与第二方向相互垂直，即所述信号线10与所述公共电极线12垂直相交。
相邻的两条平行的信号线10与相邻的两条公共电极线12相交定义出多个呈矩阵排列的所述像素单元20。所述每个像素单元20内对应设置有一个所述像素电极14。构成所述像素单元20的其中一条信号线10通过所述相互串接的所述第一放电回路16及第二放电回路18与构成对应像素单元20的其中一条公共电极线12相连接。所述信号线10可以是显示面板内传递选中信号的扫描线，也可以是用于传递显示信号的数据线。在本实施例中，所述像素单元20为虚拟像素单元(Dummy Pixel)。
所述第一放电回路16及第二放电回路18分别包括两个薄膜晶体管15(Thin Film Transistor，TFT)。所述每一个所述TFT 15包括栅极150、源极152及漏极154。每一个TFT 15的栅极150与漏极154相连接。所述第一放电回路16及第二放电回路18中的其中一个TFT 15的源极152及漏极154分别与另一个TFT 15的漏极154及源极152相连接以构成一个闭合回路。所述第一放电回路16中其中一个TFT 15的栅极150与所述信号线10相连接。所述第一放电回路16中的其中一个漏极154与源极152的连接点A与所述第二放电回路18中的其中一个漏极154与源极152连接点B相连接。所述第二放电回路18与第一放电回路16相对的另一个漏极154与源极152的连接点与公共电极线12相连接。所述像素电极14连接至所述第一放电回路16与第二放电回路18相互连接线之间的连接点上。在本实施例中，所述像素电极14为开设有多条狭缝的垂直配向型像素电极14。
本发明所提供的显示面板线路结构1通过虚拟像素中TFT 15组成的放电回路形成放电途径以起到静电防护的作用，同时虚拟像素中的像素电极14可以保持显示面板周边像素单元20的负载与显示面板内的像素单元20的负载一致。所以，显示面板的外围不需要再设置独立的静电防护电路，有利于显示面板的边框空间以实现窄边框设计。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (10)

  1. 一种显示面板线路结构，其包括沿第一方向延伸的信号线、沿第二方向延伸的公共电极线、像素电极、第一放电回路及第二放电回路，每个信号线通过相互串接的所述第一放电回路及第二放电回路与公共电极线连接，所述像素电极连接至所述第一放电回路与第二放电回路之间的相交点。
  2. 如权利要求1所述的显示面板线路结构，其中，所述第一方向与第二方向相互垂直。
  3. 如权利要求1所述的显示面板线路结构，其中，相邻的两条平行的信号线与相邻的两条公共电极线相交定义出多个呈矩阵排列的所述像素单元，所述每个像素单元内对应设置有一个所述像素电极。
  4. 如权利要求1所述的显示面板线路结构，其中，所述像素单元为虚拟像素单元。
  5. 如权利要求1所述的显示面板线路结构，其中，所述第一放电回路及第二放电回路分别包括两个薄膜晶体管，所述每一个所述薄膜晶体管包括栅极、源极及漏极，每一个薄膜晶体管的栅极与漏极相连接，所述第一放电回路及第二放电回路中的其中一个薄膜晶体管的源极及漏极分别与另一个薄膜晶体管的漏极及源极相连接以构成一个闭合回路。
  6. 如权利要求5所述的显示面板线路结构，其中，所述第一放电回路中的其中一个漏极与源极的连接点与所述第二放电回路中的其中一个漏极与源极连接点相连接。
  7. 如权利要求5所述的显示面板线路结构，其中，所述第二放电回路与第一放电回路相对的另一个漏极与源极的连接点与公共电极线相连接。
  8. 如权利要求5所述的显示面板线路结构，其中，所述第二放电回路与第一放电回路相对的另一个漏极与源极的连接点与公共电极线相连接。
  9. 如权利要求1所述的显示面板线路结构，其中，所述信号线选自用于传递选中信号的扫描线及用于传递显示信号的数据线中的一种。
  10. 如权利要求1所述的显示面板线路结构，其中，所述像素电极为开设有多条狭缝的垂直配向型像素电极。
PCT/CN2015/071299 2014-01-23 2015-01-22 显示面板线路结构 Ceased WO2015110032A1 (zh)

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CN103794606A (zh) 2014-01-23 2014-05-14 深圳市华星光电技术有限公司 显示面板线路结构
CN107402464B (zh) * 2017-07-21 2019-12-24 惠科股份有限公司 一种静电放电电路和显示面板
CN107993579B (zh) * 2017-11-29 2019-11-12 武汉天马微电子有限公司 一种显示面板及其驱动方法、显示装置
CN108803173B (zh) * 2018-07-02 2021-08-10 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
TWI667780B (zh) * 2018-08-02 2019-08-01 友達光電股份有限公司 顯示面板

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